STD7N60DM2

STD7N60DM2 N-channel 600 V, 0.78 Ω typ., 6 A MDmesh™ DM2 Power MOSFET in a DPAK package Datasheet - production data Features Order code VDS RDS(on) max. ID PTOT STD7N60DM2 600 V 0.90 Ω 6A 60 W   Figure 1: Internal schematic diagram     Fast-recovery body diode Extremely low gate charge and input capacitance Low on-resistance 100% avalanche tested Extremely high dv/dt ruggedness Zener-protected Applications  Switching applications Description This high voltage N-channel Power MOSFET is part of the MDmesh™ DM2 fast recovery diode series. It offers very low recovery charge (Qrr) and time (trr) combined with low RDS(on), rendering it suitable for the most demanding high efficiency converters and ideal for bridge topologies and ZVS phase-shift converters. Table 1: Device summary Order code Marking Package Packing STD7N60DM2 7N60DM2 DPAK Tape and reel June 2017 DocID030755 Rev 1 This is information on a product in full production. 1/15 www.st.com Contents STD7N60DM2 Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 5 2/15 4.1 DPAK (TO-252) type A package information..................................... 9 4.2 DPAK (TO-252) packing information ............................................... 12 Revision history ............................................................................ 14 DocID030755 Rev 1 STD7N60DM2 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol VGS Parameter Gate-source voltage Value Unit ±25 V Drain current (continuous) at Tcase = 25 °C 6 Drain current (continuous) at Tcase = 100 °C 3.8 IDM(1) Drain current (pulsed) 24 A PTOT W ID Total dissipation at Tcase = 25 °C 60 dv/dt(2) Peak diode recovery voltage slope 50 dv/dt(3) MOSFET dv/dt ruggedness 50 Tstg Storage temperature range Tj Operating junction temperature range A V/ns -55 to 150 °C Value Unit Notes: (1) Pulse width is limited by safe operating area. (2) ISD ≤ 6 A, di/dt=900 A/μs; VDS peak < V(BR)DSS, VDD = 480 V. (3) VDS ≤ 480 V. Table 3: Thermal data Symbol Rthj-case Rthj-pcb (1) Parameter Thermal resistance junction-case 2.08 Thermal resistance junction-pcb 50 °C/W Notes: (1) When mounted on a 1-inch² FR-4, 2 Oz copper board. Table 4: Avalanche characteristics Symbol Parameter Value Unit IAR(1) Avalanche current, repetitive or not repetitive 1.5 A EAS(2) Single pulse avalanche energy 160 mJ Notes: (1) Pulse width limited by Tjmax. (2) Starting Tj = 25 °C, ID = IAR, VDD = 50 V. DocID030755 Rev 1 3/15 Electrical characteristics 2 STD7N60DM2 Electrical characteristics (Tcase = 25 °C unless otherwise specified) Table 5: Static Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS = 0 V, ID = 1 mA Min. Typ. Max. 600 Unit V VGS = 0 V, VDS = 600 V 1 VGS = 0 V, VDS = 600 V, Tcase = 125 °C (1) 100 Gate-body leakage current VDS = 0 V, VGS = ±25 V ±5 µA VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA 4 4.75 V RDS(on) Static drain-source onresistance VGS = 10 V, ID = 3 A 0.78 0.90 Ω Min. Typ. Max. Unit - 324 - - 18 - - 2 - IDSS Zero gate voltage drain current IGSS 3.25 µA Notes: (1)Defined by design, not subject to production test. Table 6: Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Coss Test conditions VDS = 100 V, f = 1 MHz, VGS = 0 V pF Equivalent output capacitance VDS = 0 to 480 V, VGS = 0 V - 25 - pF RG Intrinsic gate resistance f = 1 MHz, ID = 0 A - 6 - Ω Qg Total gate charge - 7.5 - Qgs Gate-source charge - 2.2 - Qgd Gate-drain charge VDD = 480 V, ID = 6 A, VGS = 0 to 10 V (see Figure 15: "Test circuit for gate charge behavior") - 3.2 - eq. (1) nC Notes: (1) Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. Table 7: Switching times Symbol td(on) tr td(off) tf 4/15 Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions Min. Typ. Max. VDD = 300 V, ID = 3 A RG = 4.7 Ω, VGS = 10 V (see Figure 14: "Test circuit for resistive load switching times" and Figure 19: "Switching time waveform") - 10 - - 6 - - 12.6 - - 22.6 - DocID030755 Rev 1 Unit ns STD7N60DM2 Electrical characteristics Table 8: Source-drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit ISD Source-drain current - 6 A ISDM(1) Source-drain current (pulsed) - 24 A VSD(2) Forward on voltage VGS = 0 V, ISD = 6 A - 1.6 V trr Reverse recovery time - 69 ns Qrr Reverse recovery charge - 164 nC IRRM Reverse recovery current ISD = 6 A, di/dt = 100 A/µs, VDD = 60 V (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 4.8 A ISD = 6 A, di/dt = 100 A/µs, VDD = 60 V, Tj = 150 °C (see Figure 16: "Test circuit for inductive load switching and diode recovery times") - 144 ns - 492 nC - 6.8 A trr Reverse recovery time Qrr Reverse recovery charge IRRM Reverse recovery current Notes: (1) Pulse width is limited by safe operating area. (2) Pulse test: pulse duration = 300 µs, duty cycle 1.5%. DocID030755 Rev 1 5/15 Electrical characteristics 2.1 STD7N60DM2 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance 6/15 DocID030755 Rev 1 STD7N60DM2 Electrical characteristics Figure 8: Capacitance variations Figure 9: Output capacitance stored energy Figure 10: Normalized gate threshold voltage vs temperature Figure 11: Normalized on-resistance vs temperature Figure 12: Source-drain diode forward characteristics Figure 13: Normalized V(BR)DSS vs temperature DocID030755 Rev 1 7/15 Test circuits 3 8/15 STD7N60DM2 Test circuits Figure 14: Test circuit for resistive load switching times Figure 15: Test circuit for gate charge behavior Figure 16: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive load test circuit Figure 18: Unclamped inductive waveform Figure 19: Switching time waveform DocID030755 Rev 1 STD7N60DM2 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK ® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. 4.1 DPAK (TO-252) type A package information Figure 20: DPAK (TO-252) type A package outline DocID030755 Rev 1 9/15 Package information STD7N60DM2 Table 9: DPAK (TO-252) type A mechanical data mm Dim. Min. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 4.95 E 6.40 E1 4.60 4.70 4.80 e 2.16 2.28 2.40 e1 4.40 4.60 H 9.35 10.10 L 1.00 1.50 (L1) 2.60 2.80 3.00 L2 0.65 0.80 0.95 L4 0.60 R V2 10/15 Typ. 5.10 5.25 6.60 1.00 0.20 0° DocID030755 Rev 1 8° STD7N60DM2 Package information Figure 21: DPAK (TO-252) type A recommended footprint (dimensions are in mm) DocID030755 Rev 1 11/15 Package information 4.2 STD7N60DM2 DPAK (TO-252) packing information Figure 22: DPAK (TO-252) tape outline 12/15 DocID030755 Rev 1 STD7N60DM2 Package information Figure 23: DPAK (TO-252) reel outline Table 10: DPAK (TO-252) tape and reel mechanical data Tape Reel mm mm Dim. Dim. Min. Max. A0 6.8 7 A B0 10.4 10.6 B 1.5 12.1 C 12.8 B1 D 1.5 D1 1.5 E 1.65 F 1.6 Min. Max. 330 13.2 D 20.2 G 16.4 1.85 N 50 7.4 7.6 T K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 DocID030755 Rev 1 18.4 22.4 13/15 Revision history 5 STD7N60DM2 Revision history Table 11: Document revision history 14/15 Date Revision 20-Jun-2017 1 DocID030755 Rev 1 Changes First release. STD7N60DM2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2017 STMicroelectronics – All rights reserved DocID030755 Rev 1 15/15