STD8N60DM2

STD8N60DM2 Datasheet N-channel 600 V, 550 mΩ typ., 8 A, MDmesh™ DM2 Power MOSFET in a DPAK package Features TAB 2 3 1 • • • • • • DPAK D(2, TAB) Order code VDS RDS(on) max. ID PTOT STD8N60DM2 600 V 600 mΩ 8A 85 W Fast-recovery body diode Extremely low gate charge and input capacitance Low on-resistance 100% avalanche tested Extremely high dv/dt ruggedness Zener-protected G(1) Applications • S(3) Switching applications AM01475V1 Description This high-voltage N-channel Power MOSFET is part of the MDmesh™ DM2 fastrecovery diode series. It offers very low recovery charge (Qrr) and time (trr) combined with low RDS(on), rendering it suitable for the most demanding high-efficiency converters and ideal for bridge topologies and ZVS phase-shift converters. Product status link STD8N60DM2 Product summary Order code STD8N60DM2 Marking 8N60DM2 Package DPAK Packing Tape and reel DS11054 - Rev 3 - September 2018 For further information contact your local STMicroelectronics sales office. www.st.com STD8N60DM2 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol VGS Parameter Gate-source voltage Value Unit ±25 V Drain current (continuous) at Tcase = 25 °C 8 Drain current (continuous) at Tcase = 100 °C 5 IDM (1) Drain current (pulsed) 32 A PTOT Total dissipation at Tcase = 25 °C 85 W dv/dt(2) Peak diode recovery voltage slope 50 dv/dt(3) MOSFET dv/dt ruggedness 50 Tstg Storage temperature range ID Tj Operating junction temperature range A V/ns –55 to 150 °C Value Unit 1. Pulse width is limited by safe operating area. 2. ISD ≤ 8 A, di/dt = 900 A/μs, VDS peak < V(BR)DSS, VDD = 400 V 3. VDS ≤ 480 V Table 2. Thermal data Symbol Rthj-case Rthj-pcb (1) Parameter Thermal resistance junction-case 1.47 Thermal resistance junction-pcb 50 °C/W 1. When mounted on a 1-inch² FR-4, 2 Oz copper board. Table 3. Avalanche characteristics Symbol IAR(1) (2) EAS Parameter Value Unit Avalanche current, repetitive or not repetitive 2.5 A Single pulse avalanche energy 430 mJ 1. Pulse width limited by Tjmax. 2. Starting Tj = 25 °C, ID = IAR, VDD = 50 V. DS11054 - Rev 3 page 2/17 STD8N60DM2 Electrical characteristics 2 Electrical characteristics (Tcase = 25 °C unless otherwise specified) Table 4. Static Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS = 0 V, ID = 1 mA Min. Typ. 600 Zero gate voltage drain current IGSS 1 VGS = 0 V, VDS = 600 V, Tcase = 125 100 °C(1) Gate-body leakage current VDS = 0 V, VGS = ±25 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source on-resistance VGS = 10 V, ID = 4 A Unit V VGS = 0 V, VDS = 600 V IDSS Max. µA ±5 µA 4 5 V 550 600 mΩ Min. Typ. Max. Unit - 449 - - 24 - - 0.89 - 3 1. Defined by design, not subject to production test. Table 5. Dynamic Symbol Parameter Test conditions Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Coss eq. (1) Equivalent output capacitance VDS = 0 to 480 V, VGS = 0 V - 42 - pF RG Intrinsic gate resistance f = 1 MHz, ID = 0 A - 6.5 - Ω Qg Total gate charge VDD = 480 V, ID = 8 A, - 13.5 - Qgs Gate-source charge VGS = 10 V - 3 - Gate-drain charge (see Figure 14. Test circuit for gate charge behavior) - 7.7 - Qgd VDS = 100 V, f = 1 MHz, VGS = 0 V pF nC 1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. Table 6. Switching times Symbol td(on) tr td(off) tf DS11054 - Rev 3 Parameter Test conditions Min. Typ. Max. Turn-on delay time VDD = 300 V, ID = 4 A, - 10 - Rise time RG = 4.7 Ω, VGS = 10 V - 6 - Turn-off delay time (see Figure 13. Test circuit for resistive load switching times and Figure 18. Switching time waveform) - 25.4 - - 9.5 - Fall time Unit ns page 3/17 STD8N60DM2 Electrical characteristics Table 7. Source-drain diode Symbol ISD ISDM (1) (2) Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 8 A Source-drain current (pulsed) - 32 A 1.6 V Forward on voltage VGS = 0 V, ISD = 8 A - trr Reverse recovery time ISD = 8 A, di/dt = 100 A/µs, - 80 ns Qrr Reverse recovery charge VDD = 60 V - 188 nC Reverse recovery current (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 4.7 A trr Reverse recovery time ISD = 8 A, di/dt = 100 A/µs, - 160 ns Qrr Reverse recovery charge VDD = 60 V, Tj = 150 °C - 640 nC IRRM Reverse recovery current (see Figure 15. Test circuit for inductive load switching and diode recovery times) - 8 A VSD IRRM 1. Pulse width is limited by safe operating area. 2. Pulse test: pulse duration = 300 µs, duty cycle 1.5%. DS11054 - Rev 3 page 4/17 STD8N60DM2 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 2. Thermal impedance Figure 1. Safe operating area GADG220720160851SOA ID (A) Operation in this area is limited by R DS(on) GC20460 K tp = 10µs 10 1 100 tp = 100µs 10 0 tp = 1ms 10 -1 10 -1 T j ≤150 °C T c = 25°C single pulse 10 0 10 1 10-1 tp = 10ms 10 2 10 3 VDS (V) 10-2 10-5 Figure 3. Output characteristics ID (A) 10-4 10-3 10-2 10-1 tp (s) Figure 4. Transfer characteristics ID (A) GADG260720160958OCH VGS = 8, 9, 10 V 15 GADG260720160958TCH VDS = 20 V 15 7V 12 12 9 9 6 6 6V 3 3 0 0 4 8 12 16 VDS (V) Figure 5. Gate charge vs gate-source voltage VGS (V) GIPG260720161231QVG VDS (V) VDD = 480 V ID = 8 A 12 10 600 VDS 500 0 0 2 4 6 8 VGS (V) Figure 6. Static drain-source on resistance RDS(on) (Ω) GADG210720161757RON VGS = 10 V 0.58 0.57 8 400 6 300 4 200 2 100 0.54 0 Qg (nC) 0.53 0 0.56 0 0 DS11054 - Rev 3 3 6 9 12 15 0.55 2 4 6 8 Tj (°C) page 5/17 STD8N60DM2 Electrical characteristics (curves) Figure 8. Normalized gate threshold voltage vs temperature Figure 7. Capacitance variations C (pF) GADG210720161759CVR VGS(th) (norm.) 103 CISS GADG210720161803VTH ID = 250 µA 1.1 1 102 101 f= 1 MHz COSS 0.9 CRSS 0.8 100 0.7 10-1 10-1 100 101 VDS (V) 102 Figure 9. Normalized on-resistance vs temperature RDS(on) (norm.) GADG210720161806RON VGS = 10 V 2.2 0.6 -75 1 1 0.96 0.6 0.92 75 125 Tj (°C) Figure 11. Source-drain diode forward characteristics VSD (V) GADG210720161810SDF Tj = -50 °C 1.1 125 Tj (°C) GADG210720161808BDV ID = 1 mA 1.08 1.4 25 75 V(BR)DSS (norm.) 1.04 -25 25 Figure 10. Normalized V(BR)DSS vs temperature 1.8 0.2 -75 -25 0.88 -75 -25 25 75 125 Tj (°C) Figure 12. Output capacitance stored energy EOSS (µJ) GADG210720161815EOS 3 1 Tj = 25 °C 0.9 2 0.8 Tj = 150 °C 0.7 1 0.6 0.5 0 DS11054 - Rev 3 2 4 6 8 ISD (A) 0 0 100 200 300 400 500 600 VDS (V) page 6/17 STD8N60DM2 Test circuits 3 Test circuits Figure 13. Test circuit for resistive load switching times Figure 14. Test circuit for gate charge behavior VDD 12 V 2200 + μF 3.3 μF VDD VD VGS 1 kΩ 100 nF RL IG= CONST VGS RG 47 kΩ + pulse width D.U.T. 2.7 kΩ 2200 μF pulse width D.U.T. 100 Ω VG 47 kΩ 1 kΩ AM01469v1 AM01468v1 Figure 15. Test circuit for inductive load switching and diode recovery times D G A D.U.T. S 25 Ω A L A B B 3.3 µF D G + VD 100 µH fast diode B Figure 16. Unclamped inductive load test circuit RG 1000 + µF 2200 + µF VDD 3.3 µF VDD ID D.U.T. S D.U.T. Vi _ pulse width AM01471v1 AM01470v1 Figure 18. Switching time waveform Figure 17. Unclamped inductive waveform ton V(BR)DSS td(on) VD toff td(off) tr tf 90% 90% IDM VDD 10% 0 ID VDD AM01472v1 VGS 0 VDS 10% 90% 10% AM01473v1 DS11054 - Rev 3 page 7/17 STD8N60DM2 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. DS11054 - Rev 3 page 8/17 STD8N60DM2 DPAK (TO-252) type A package information 4.1 DPAK (TO-252) type A package information Figure 19. DPAK (TO-252) type A package outline 0068772_A_25 DS11054 - Rev 3 page 9/17 STD8N60DM2 DPAK (TO-252) type A package information Table 8. DPAK (TO-252) type A mechanical data Dim. mm Min. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 4.95 E 6.40 E1 4.60 4.70 4.80 e 2.159 2.286 2.413 e1 4.445 4.572 4.699 H 9.35 10.10 L 1.00 1.50 (L1) 2.60 2.80 3.00 L2 0.65 0.80 0.95 L4 0.60 R V2 DS11054 - Rev 3 Typ. 5.10 5.25 6.60 1.00 0.20 0° 8° page 10/17 STD8N60DM2 DPAK (TO-252) type E package information 4.2 DPAK (TO-252) type E package information Figure 20. DPAK (TO-252) type E package outline 0068772_type-E_rev.25 DS11054 - Rev 3 page 11/17 STD8N60DM2 DPAK (TO-252) type E package information Table 9. DPAK (TO-252) type E mechanical data Dim. A mm Min. Typ. Max. 2.18 2.39 A2 0.13 b 0.65 0.884 b4 4.95 5.46 c 0.46 0.61 c2 0.46 0.60 D 5.97 6.22 D1 5.21 E 6.35 E1 4.32 6.73 e 2.286 e1 4.572 H 9.94 10.34 L 1.50 1.78 L1 L2 2.74 0.89 L4 1.27 1.02 Figure 21. DPAK (TO-252) recommended footprint (dimensions are in mm) FP_0068772_25 DS11054 - Rev 3 page 12/17 STD8N60DM2 DPAK (TO-252) packing information 4.3 DPAK (TO-252) packing information Figure 22. DPAK (TO-252) tape outline 10 pitches cumulative tolerance on tape +/- 0.2 mm T P0 Top cover tape P2 D E F B1 K0 For machine ref. only including draft and radii concentric around B0 W B0 A0 P1 D1 User direction of feed R Bending radius User direction of feed AM08852v1 DS11054 - Rev 3 page 13/17 STD8N60DM2 DPAK (TO-252) packing information Figure 23. DPAK (TO-252) reel outline T 40mm min. access hole at slot location B D C N A G measured at hub Tape slot in core for tape start 2.5mm min.width Full radius AM06038v1 Table 10. DPAK (TO-252) tape and reel mechanical data Tape Dim. mm mm Dim. Min. Max. A0 6.8 7 A B0 10.4 10.6 B 1.5 12.1 C 12.8 1.6 D 20.2 G 16.4 50 B1 DS11054 - Rev 3 Reel Min. Max. 330 13.2 D 1.5 D1 1.5 E 1.65 1.85 N F 7.4 7.6 T K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 18.4 22.4 page 14/17 STD8N60DM2 Revision history Table 11. Document revision history Date Revision 12-May-2015 1 Changes First release. Document status promoted from preliminary to production data. 24-Nov-2016 2 Updated title in cover page, Section 1: "Electrical ratings" and Section 2: "Electrical characteristics". Added Section 2.1: "Electrical characteristics (curves)". Removed maturity status indication from cover page. 07-Sep-2018 3 Added Section 4.2 DPAK (TO-252) type E package information. Minor text changes DS11054 - Rev 3 page 15/17 STD8N60DM2 Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2 2 Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.1 Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 3 Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 4 Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 4.1 DPAK (TO-252) type A package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 4.2 DPAK (TO-252) type E package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.3 DPAK (TO-252) packing information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 DS11054 - Rev 3 page 16/17 STD8N60DM2 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2018 STMicroelectronics – All rights reserved DS11054 - Rev 3 page 17/17