STD64N4F6AG

STD64N4F6AG Automotive-grade N-channel 40 V, 7 mΩ typ., 54 A STripFET™ F6 Power MOSFET in a DPAK package Datasheet - production data Features Order code VDS RDS(on) max. ID PTOT STD64N4F6AG 40 V 8.2 mΩ 54 A 60 W • Figure 1: Internal schematic diagram • • • • Designed for automotive applications and AEC-Q101 qualified Very low on-resistance Very low gate charge High avalanche ruggedness Low gate drive power loss Applications • Switching applications Description This device is an N-channel Power MOSFET developed using the STripFET™ F6 technology with a new trench gate structure. The resulting Power MOSFET exhibits very low RDS(on) in all packages. Table 1: Device summary Order code Marking Package Packing STD64N4F6AG 64N4F6 DPAK Tape and reel June 2015 DocID027883 Rev 1 This is information on a product in full production. 1/15 www.st.com Contents STD64N4F6AG Contents 1 Electrical ratings ............................................................................. 3 2 Electrical characteristics ................................................................ 4 2.1 Electrical characteristics (curves) ...................................................... 6 3 Test circuits ..................................................................................... 8 4 Package information ....................................................................... 9 5 2/15 4.1 DPAK (TO-252) type A package information..................................... 9 4.2 DPAK (TO-252) packing information ............................................... 12 Revision history ............................................................................ 14 DocID027883 Rev 1 STD64N4F6AG 1 Electrical ratings Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit VDS Drain-source voltage 40 V VGS Gate-source voltage ±20 V (1) Drain current (continuous) at Tcase = 25 °C 54 Drain current (continuous) at Tcase = 100 °C 46 IDM Drain current (pulsed) 216 A PTOT Total dissipation at Tcase = 25 °C 60 W Tstg Storage temperature -55 to 175 °C Value Unit ID (2) Tj Operating junction temperature A Notes: (1) (2) Current is limited by package. Pulse width is limited by safe operating area. Table 3: Thermal data Symbol Parameter Rthj-case Thermal resistance junction-case 2.5 Thermal resistance junction-pcb 35 Rthj-pcb (1) °C/W Notes: (1) When mounted on a 1-inch² FR-4, 2 Oz copper board. Table 4: Avalanche characteristics Symbol (1) IAS (2) EAS Parameter Value Unit Avalanche current, repetitive or not repetitive 54 A Single pulse avalanche energy 180 mJ Notes: (1) (2) Pulse width limited by Tjmax. starting Tj = 25 °C, ID = IAS, VDD = 25 V. DocID027883 Rev 1 3/15 Electrical characteristics 2 STD64N4F6AG Electrical characteristics (Tcase = 25 °C unless otherwise specified) Table 5: Static Symbol V(BR)DSS Parameter Test conditions Drain-source breakdown voltage VGS = 0 V, ID = 250 µA Min. Typ. Max. 40 Unit V VGS = 0 V, VDS = 40 V 1 VGS = 0 V, VDS = 40 V, Tcase = 125 °C 10 ±100 nA 4.5 V 7 8.2 mΩ Min. Typ. Max. Unit - 2415 - - 232 - - 170 - - 44 - - 15 - - 12 - Test conditions Min. Typ. Max. VDD = 20 V, ID = 27 A RG = 4.7 Ω, VGS = 10 V (see Figure 13: "Switching times test circuit for resistive load" and Figure 18: "Switching time waveform") - 21.2 - - 113 - - 40.4 - - 25.2 - IDSS Zero gate voltage drain current IGSS Gate-body leakage current VDS = 0 V, VGS = ±20 V VGS(th) Gate threshold voltage VDS = VGS, ID = 250 µA RDS(on) Static drain-source onresistance VGS = 10 V, ID = 27 A 2 µA Table 6: Dynamic Symbol Parameter Ciss Input capacitance Coss Output capacitance Crss Reverse transfer capacitance Qg Total gate charge Qgs Gate-source charge Qgd Gate-drain charge Test conditions VDS = 25 V, f = 1 MHz, VGS = 0 V VDD = 20 V, ID = 54 A, VGS = 10 V (see Figure 14: "Gate charge test circuit") pF nC Table 7: Switching times Symbol td(on) tr td(off) tf 4/15 Parameter Turn-on delay time Rise time Turn-off delay time Fall time DocID027883 Rev 1 Unit ns STD64N4F6AG Electrical characteristics Table 8: Source-drain diode Symbol ISD Parameter Test conditions Min. Typ. Max. Unit Source-drain current - 54 A (1) Source-drain current (pulsed) - 216 A (2) Forward on voltage VGS = 0 V, ISD = 27 A - 1.3 V trr Reverse recovery time - 29.4 ns Qrr Reverse recovery charge - 31.3 nC IRRM Reverse recovery current ISD = 54 A, di/dt = 100 A/µs, VDD = 32 V (see Figure 15: "Test circuit for inductive load switching and diode recovery times") - 2.1 A ISDM VSD Notes: (1) (2) Pulse width is limited by safe operating area. Pulse test: pulse duration = 300 µs, duty cycle 1.5%. DocID027883 Rev 1 5/15 Electrical characteristics 2.1 6/15 STD64N4F6AG Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance DocID027883 Rev 1 STD64N4F6AG Electrical characteristics Figure 8: Capacitance variations Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V(BR)DSS vs temperature Figure 12: Source-drain diode forward characteristics DocID027883 Rev 1 7/15 Test circuits 3 STD64N4F6AG Test circuits Figure 13: Switching times test circuit for resistive load Figure 14: Gate charge test circuit Figure 15: Test circuit for inductive load switching and diode recovery times Figure 16: Unclamped inductive load test circuit Figure 17: Unclamped inductive waveform 8/15 Figure 18: Switching time waveform DocID027883 Rev 1 STD64N4F6AG 4 Package information Package information In order to meet environmental requirements, ST offers these devices in different grades of ® ® ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: www.st.com. ® ECOPACK is an ST trademark. 4.1 DPAK (TO-252) type A package information Figure 19: DPAK (TO-252) type A package outline DocID027883 Rev 1 9/15 Package information STD64N4F6AG Table 9: DPAK (TO-252) type A mechanical data mm Dim. Min. Max. A 2.20 2.40 A1 0.90 1.10 A2 0.03 0.23 b 0.64 0.90 b4 5.20 5.40 c 0.45 0.60 c2 0.48 0.60 D 6.00 6.20 D1 4.95 E 6.40 E1 4.60 4.70 4.80 e 2.16 2.28 2.40 e1 4.40 4.60 H 9.35 10.10 L 1.00 1.50 (L1) 2.60 2.80 3.00 L2 0.65 0.80 0.95 L4 0.60 R V2 10/15 Typ. 5.10 5.25 6.60 1.00 0.20 0° DocID027883 Rev 1 8° STD64N4F6AG Package information Figure 20: DPAK (TO-252) recommended footprint (dimensions are in mm) DocID027883 Rev 1 11/15 Package information 4.2 STD64N4F6AG DPAK (TO-252) packing information Figure 21: DPAK (TO-252) tape outline 10 pitches cumulative tolerance on tape +/- 0.2 mm T P0 Top cover tape P2 D E F B1 K0 For machine ref. only including draft and radii concentric around B0 W B0 A0 P1 D1 User direction of feed R Bending radius User direction of feed AM08852v1 12/15 DocID027883 Rev 1 STD64N4F6AG Package information Figure 22: DPAK (TO-252) reel outline T 40mm min. access hole at slot location B D C N A G measured at hub Tape slot in core for tape start 2.5mm min.width Full radius AM06038v1 Table 10: DPAK (TO-252) tape and reel mechanical data Tape Reel mm mm Dim. Dim. Min. Max. A0 6.8 7 A B0 10.4 10.6 B 1.5 12.1 C 12.8 B1 D 1.5 D1 1.5 E 1.65 F 1.6 Min. Max. 330 13.2 D 20.2 G 16.4 1.85 N 50 7.4 7.6 T K0 2.55 2.75 P0 3.9 4.1 Base qty. 2500 P1 7.9 8.1 Bulk qty. 2500 P2 1.9 2.1 R 40 T 0.25 0.35 W 15.7 16.3 DocID027883 Rev 1 18.4 22.4 13/15 Revision history 5 STD64N4F6AG Revision history Table 11: Document revision history 14/15 Date Revision 10-Jun-2015 1 DocID027883 Rev 1 Changes First release. STD64N4F6AG IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2015 STMicroelectronics – All rights reserved DocID027883 Rev 1 15/15