STM708S

STM706T/S/R, STM706P, STM708T/S/R 3 V supervisor Features ■ Precision VCC monitor – STM706/708 T: 3.00 V ≤ VRST ≤ 3.15 V S: 2.88 V ≤ VRST ≤ 3.00 V R: STM706P: 2.59 V ≤ VRST ≤ 2.70 V RST and RST outputs 200 ms (typ.) trec Watchdog timer - 1.6 s (typ.) Manual reset input (MR) Power-fail comparator (PFI/PFO) Low supply current - 40 µA (typ.) Guaranteed RST (RST) assertion down to VCC = 1.0 V Operating temperature: –40 °C to 85 °C (industrial grade) RoHS compliance – Lead-free components are compliant with the RoHS directive 8 1 SO8 (M) ■ ■ ■ ■ ■ ■ ■ ■ ■ TSSOP8 3x3 (DS)(1) 1. Contact local ST sales office for availability. Table 1. Device summary Watchdog input Watchdog output(1) ✓ ✓ ✓ Active-low RST(1) ✓ ✓ ✓ Active-high RST(1) Manual reset input ✓ ✓ ✓ Power-fail comparator ✓ ✓ ✓ STM706T/S/R STM706P (2) ✓ ✓ STM708T/S/R 1. Push-pull output. 2. The STM706P is identical to the STM706R, except its reset output is active-high. August 2010 Doc ID 10518 Rev 10 1/33 www.st.com 1 Contents STM706T/S/R, STM706P, STM708T/S/R Contents 1 2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 2.2 2.3 2.4 2.5 2.6 2.7 MR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 WDI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 WDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 RST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 RST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 PFI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 PFO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 3 Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 3.2 3.3 3.4 3.5 3.6 3.7 Reset output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Push-button reset input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Watchdog input (STM706T/S/R and STM706P) . . . . . . . . . . . . . . . . . . . 11 Watchdog output (STM706T/S/R and STM706P) . . . . . . . . . . . . . . . . . . 11 Power-fail input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Ensuring a valid reset output down to VCC = 0 V . . . . . . . . . . . . . . . . . . . 12 Interfacing to microprocessors with bi-directional reset pins . . . . . . . . . . 13 4 5 6 7 8 9 Typical operating characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 2/33 Doc ID 10518 Rev 10 STM706T/S/R, STM706P, STM708T/S/R List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 DC and AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 SO8 - 8-lead plastic small outline, 150 mils body width, package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 TSSOP8 - 8-lead, thin shrink small outline, 3 x 3 mm body size, mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Marking description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Doc ID 10518 Rev 10 3/33 List of figures STM706T/S/R, STM706P, STM708T/S/R List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Logic diagram (STM706T/S/R and STM706P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Logic diagram (STM708T/S/R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 STM706T/S/R and STM706P SO8 connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 STM706T/S/R and STM706P TSSOP8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 STM708T/S/R SO8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 STM708T/S/R TSSOP8 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Block diagram (STM706T/S/R and STM706P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Block diagram (STM708T/S/R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Hardware hookup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Reset output valid to ground circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Interfacing to microprocessors with bi-directional reset I/O . . . . . . . . . . . . . . . . . . . . . . . . 13 Supply current vs. temperature (no load) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 VPFI threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Reset comparator propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Power-up trec vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Normalized reset threshold vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Watchdog timeout period vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 PFI to PFO propagation delay vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Output voltage vs. load current (VCC = 5 V; TA = 25 °C) . . . . . . . . . . . . . . . . . . . . . . . . . . 18 RST output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 RST output voltage vs. supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Power-fail comparator response time (assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Power-fail comparator response time (de-assertion) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Maximum transient duration vs. reset threshold overdrive . . . . . . . . . . . . . . . . . . . . . . . . . 21 AC testing input/output waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Power-fail comparator waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 MR timing waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Watchdog timing (STM706T/S/R and STM706P) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 SO8 – 8-lead plastic small outline, 150 mils body width, package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 TSSOP8 – 8-lead, thin shrink small outline, 3 x 3 mm body size, outline. . . . . . . . . . . . . . 29 4/33 Doc ID 10518 Rev 10 STM706T/S/R, STM706P, STM708T/S/R Description 1 Description The STM70x supervisors are self-contained devices which provide microprocessor supervisory functions. A precision voltage reference and comparator monitors the VCC input for an out-of-tolerance condition. When an invalid VCC condition occurs, the reset output (RST) is forced low (or high in the case of RST). These devices also offer a watchdog timer (except for STM708T/S/R) as well as a power-fail comparator to provide the system with an early warning of impending power failure. The STM706P is identical to the STM706R, except its reset output is active-high. These devices are available in a standard 8-pin SOIC package or a space-saving 8-pin TSSOP package. Figure 1. Logic diagram (STM706T/S/R and STM706P) VCC WDI MR PFI WDO STM706T/S/R, STM706P RST (RST)(1) PFO VSS AI08841 1. For STM706P only. Figure 2. Logic diagram (STM708T/S/R) VCC RST MR STM708T/S/R PFI RST PFO VSS AI08842 Doc ID 10518 Rev 10 5/33 Description Table 2. Symbol MR WDI WDO RST RST (1) STM706T/S/R, STM706P, STM708T/S/R Signal names Name Push-button reset input Watchdog input Watchdog output Active-low reset output Active-high reset output Supply voltage Power-fail input Power-fail output Ground No connect VCC PFI PFO VSS NC 1. For STM706P and STM708T/S/R only. Figure 3. STM706T/S/R and STM706P SO8 connections SO8 MR VCC VSS PFI 1 2 3 4 8 7 6 5 WDO RST(RST)(1) WDI PFO AI08837 1. For STM706P reset output is active-high. Figure 4. STM706T/S/R and STM706P TSSOP8 connections TSSOP8 (1) RST(RST) WDO MR VCC 1 2 3 4 8 7 6 5 WDI PFO PFI VSS AI08838 1. For STM706P reset output is active-high. 6/33 Doc ID 10518 Rev 10 STM706T/S/R, STM706P, STM708T/S/R Description Figure 5. STM708T/S/R SO8 connections SO8 MR VCC VSS PFI 1 2 3 4 8 7 6 5 RST RST NC PFO AI08839 Figure 6. STM708T/S/R TSSOP8 connections TSSOP8 RST RST MR VCC 1 2 3 4 8 7 6 5 NC PFO PFI VSS AI08840 Doc ID 10518 Rev 10 7/33 Pin descriptions STM706T/S/R, STM706P, STM708T/S/R 2 2.1 Pin descriptions MR A logic low on MR asserts the reset output. Reset remains asserted as long as MR is low and for trec after MR returns high. This active-low input has an internal pull-up. It can be driven from a TTL or CMOS logic line, or shorted to ground with a switch. Leave open if unused. 2.2 WDI If WDI remains high or low for 1.6 s, the internal watchdog timer runs out and reset (or WDO) is triggered. The internal watchdog timer clears while reset is asserted or when WDI sees a rising or falling edge. The watchdog function cannot be disabled by allowing the WDI pin to float. 2.3 WDO WDO goes low when a transition does not occur on WDI within 1.6 s, and remains low until a transition occurs on WDI (indicating the watchdog interrupt has been serviced). WDO also goes low when VCC falls below the reset threshold; however, unlike the reset output, WDO goes high as soon as VCC exceeds the reset threshold. Output type is push-pull. Note: For those devices with a WDO output, a watchdog timeout will not trigger reset unless WDO is connected to MR. 2.4 RST Pulses low for trec when triggered, and stays low whenever VCC is below the reset threshold or when MR is a logic low. It remains low for trec after either VCC rises above the reset threshold, the watchdog triggers a reset, or MR goes from low to high. 2.5 RST Pulses high for trec when triggered, and stays high whenever VCC is above the reset threshold or when MR is a logic high. It remains high for trec after either VCC falls below the reset threshold, the watchdog triggers a reset, or MR goes from high to low. 2.6 PFI When PFI is less than VPFI, PFO goes low; otherwise, PFO remains high. Connect to ground if unused. 8/33 Doc ID 10518 Rev 10 STM706T/S/R, STM706P, STM708T/S/R Pin descriptions 2.7 PFO When PFI is less than VPFI, PFO goes low; otherwise, PFO remains high. Leave open if unused. Output type is push-pull. Table 3. Pin description Pin Name Function STM706P SO8 1 6 8 — 7 2 4 5 3 — TSSOP8 3 8 2 — 1 4 6 7 5 — STM706T/S/R SO8 1 6 8 7 — 2 4 5 3 — TSSOP8 3 8 2 1 — 4 6 7 5 — STM708T/S/R SO8 1 — — 7 8 2 4 5 3 6 TSSOP8 3 — — 1 2 4 6 7 5 8 MR WDI WDO RST RST VCC PFI PFO VSS NC Push-button reset input Watchdog input Watchdog output (push-pull) Active-low reset output Active-high reset output Supply voltage Power-fail input Power-fail output (push-pull) Ground No connect Figure 7. Block diagram (STM706T/S/R and STM706P) WDI WDI transitional detector WATCHDOG TIMER WDO VCC VCC VRST COMPARE MR trec generator RST (RST)(1) PFI VPFI COMPARE PFO AI08829 1. For STM706P only. Doc ID 10518 Rev 10 9/33 Pin descriptions Figure 8. Block diagram (STM708T/S/R) STM706T/S/R, STM706P, STM708T/S/R VCC VRST COMPARE RST VCC trec generator RST MR PFI VPFI COMPARE PFO AI08830 Figure 9. Hardware hookup Regulator Unregulated voltage VIN VCC VCC 0.1 μF STM706T/S/R; STM706P; STM708T/S/R WDI(1) R1 From microprocessor PFI R2 Push-button MR WDO(1) To microprocessor IRQ PFO RST RST(2) To microprocessor NMI To microprocessor reset AI08843 1. For STM706T/S/R and STM706P. 2. For STM706P and STM708T/S/R. 10/33 Doc ID 10518 Rev 10 STM706T/S/R, STM706P, STM708T/S/R Operation 3 3.1 Operation Reset output The STM70x supervisor asserts a reset signal to the MCU whenever VCC goes below the reset threshold (VRST), a watchdog timeout occurs (if WDO is connected to MR), or when the push-button reset input (MR) is taken low. RST is guaranteed to be a logic low (logic high for STM706P and STM708T/S/R) for VCC < VRST down to VCC =1 V for TA = 0 °C to 85 °C. During power-up, once VCC exceeds the reset threshold an internal timer keeps RST low for the reset timeout period, trec. After this interval RST returns high. If VCC drops below the reset threshold, RST goes low. Each time RST is asserted, it stays low for at least the reset timeout period (trec). Any time VCC goes below the reset threshold the internal timer clears. The reset timer starts when VCC returns above the reset threshold. 3.2 Push-button reset input A logic low on MR asserts reset. Reset remains asserted while MR is low, and for trec (see Figure 27) after it returns high. The MR input has an internal 40 kΩ pull-up resistor, allowing it to be left open if not used. This input can be driven with TTL/CMOS-logic levels or with open-drain / collector outputs. Connect a normally open momentary switch from MR to GND to create a manual reset function; external debounce circuitry is not required. If MR is driven from long cables or the device is used in a noisy environment, connect a 0.1 µF capacitor from MR to GND to provide additional noise immunity. MR may float, or be tied to VCC when not used. 3.3 Watchdog input (STM706T/S/R and STM706P) The watchdog timer can be used to detect an out-of-control MCU. If the MCU does not toggle the watchdog input (WDI) within tWD (1.6 s), the watchdog output pin (WDO) is asserted. The internal 1.6s timer is cleared by either: 1. 2. a reset pulse, or by toggling WDI (high-to-low or low-to-high), which can detect pulses as short as 50 ns. See Figure 28 for STM706T/S/R and STM706P. The timer remains cleared and does not count for as long as reset is asserted. As soon as reset is released, the timer starts counting. 3.4 Watchdog output (STM706T/S/R and STM706P) When VCC drops below the reset threshold, WDO will go low even if the watchdog timer has not yet timed out. However, unlike the reset output, WDO goes high as soon as VCC exceeds the reset threshold. WDO may be used to generate a reset pulse by connecting it to the MR input. Doc ID 10518 Rev 10 11/33 Operation STM706T/S/R, STM706P, STM708T/S/R 3.5 Power-fail input/output The power-fail input (PFI) is compared to an internal reference voltage (independent from the VRST comparator). If PFI is less than the power-fail threshold (VPFI), the power-fail output (PFO) will go low. This function is intended for use as an undervoltage detector to signal a failing power supply. Typically PFI is connected through an external voltage divider (see Figure 9) to either the unregulated DC input (if it is available) or the regulated output of the VCC regulator. The voltage divider can be set up such that the voltage at PFI falls below VPFI several milliseconds before the regulated VCC input to the STM70x or the microprocessor drops below the minimum operating voltage. If the comparator is unused, PFI should be connected to VSS and PFO left unconnected. PFO may be connected to MR on the STM70x so that a low voltage on PFI will generate a reset output. 3.6 Ensuring a valid reset output down to VCC = 0 V When VCC falls below 1 V, the state of the RST output can no longer be guaranteed, and becomes essentially an open circuit. If a high value pulldown resistor is added to the RST pin, the output will be held low during this condition. A resistor value of approximately 100 kΩ will be large enough to not load the output under operating conditions, but still sufficient to pull RST to ground during this low voltage condition (see Figure 10). Figure 10. Reset output valid to ground circuit STM70x RST R1 AI08844 12/33 Doc ID 10518 Rev 10 STM706T/S/R, STM706P, STM708T/S/R Operation 3.7 Interfacing to microprocessors with bi-directional reset pins Microprocessors with bi-directional reset pins can contend with the STM70x reset output. For example, if the reset output is driven high and the micro wants to pull it low, signal contention will result. To prevent this from occurring, connect a 4.7kΩ resistor between the reset output and the micro's reset I/O as in Figure 11. Figure 11. Interfacing to microprocessors with bi-directional reset I/O Buffered reset to other system components VCC VCC Microprocessor 4.7 kΩ RST RST STM70x GND GND AI08845 Doc ID 10518 Rev 10 13/33 Typical operating characteristics STM706T/S/R, STM706P, STM708T/S/R 4 Typical operating characteristics Typical values are at TA = 25 °C. Figure 12. Supply current vs. temperature (no load) 30 25 20 Supply current (µA) 15 VCC = 2.7 V VCC = 3.0 V VCC = 3.6 V VCC = 4.5 V VCC = 5.5 V 10 5 0 –40 –20 0 20 40 Temperature (°C) 60 80 100 120 AI09141b 14/33 Doc ID 10518 Rev 10 STM706T/S/R, STM706P, STM708T/S/R Figure 13. VPFI threshold vs. temperature 1.270 1.265 1.260 1.255 1.250 1.245 1.240 1.235 1.230 1.225 –40 VCC = 2.5 V VCC = 3.0 V VCC = 3.3 V VCC = 3.6 V Typical operating characteristics V PFI threshold (V) –20 0 20 40 Temperature (°C) 60 80 100 120 AI09142b Figure 14. Reset comparator propagation delay vs. temperature 30 28 26 Propagation delay (µs) 24 22 20 18 16 14 12 10 –40 –20 0 20 40 Temperature (°C) 60 80 100 120 AI09143b Doc ID 10518 Rev 10 15/33 Typical operating characteristics Figure 15. Power-up trec vs. temperature 240 STM706T/S/R, STM706P, STM708T/S/R 235 230 t rec (ms) VCC = 3.0 V 225 VCC = 4.5 V VCC = 5.5 V 220 215 210 –40 –20 0 20 40 60 Temperature (°C) 80 100 120 AI09144b Figure 16. Normalized reset threshold vs. temperature 1.004 Normalized reset threshold 1.002 1.000 0.998 0.996 –40 –20 0 20 40 Temperature (°C) 60 80 100 120 AI09145b 16/33 Doc ID 10518 Rev 10 STM706T/S/R, STM706P, STM708T/S/R Figure 17. Watchdog timeout period vs. temperature 1.90 Typical operating characteristics 1.85 Watchdog timeout period (s) 1.80 1.75 VCC = 3.0 V VCC = 4.5 V VCC = 5.5 V 1.70 1.65 1.60 –40 –20 0 20 40 Temperature (˚ C) 60 80 100 120 AI09146b Figure 18. PFI to PFO propagation delay vs. temperature 4.0 VCC = 3.0 V 3.0 PFI to PFO propagation dela VCC = 3.6 V VCC = 4.5 V VCC = 5.5 V 2.0 1.0 0.0 –40 –20 0 20 40 Temperature (˚C) 60 80 100 120 AI09148b Doc ID 10518 Rev 10 17/33 Typical operating characteristics STM706T/S/R, STM706P, STM708T/S/R Figure 19. Output voltage vs. load current (VCC = 5 V; TA = 25 °C) 5.00 4.98 V OUT (V) 4.96 4.94 0 10 20 I OUT (mA) 30 40 50 AI10496 18/33 Doc ID 10518 Rev 10 STM706T/S/R, STM706P, STM708T/S/R Figure 20. RST output voltage vs. supply voltage Typical operating characteristics 5 VRST VCC 4 5 4 V RST (V) 3 3 V CC (V) 2 2 1 1 0 500 ms / div 0 AI09149b Figure 21. RST output voltage vs. supply voltage 5 V RST VCC 5 4 4 V RST (V) 3 3 V CC (V) 2 2 1 1 0 500 ms / div 0 AI09150b Doc ID 10518 Rev 10 19/33 Typical operating characteristics STM706T/S/R, STM706P, STM708T/S/R Figure 22. Power-fail comparator response time (assertion) 5V PFO 1 V / div 0V 1.3 V PFI 500 mV / div 0V 500 ns / div AI09153b Figure 23. Power-fail comparator response time (de-assertion) 5V PFO 1 V / div 0V 1.3 V PFI 500 mV / div 0V 500 ns / div AI09154b 20/33 Doc ID 10518 Rev 10 STM706T/S/R, STM706P, STM708T/S/R Typical operating characteristics Figure 24. Maximum transient duration vs. reset threshold overdrive 6000 5000 Transient duration (µs) 4000 Reset occurs above the curve 3000 2000 1000 0 0.001 0.01 0.1 1 10 AI09156b Reset comparator overdrive, V RST – V CC (V) Doc ID 10518 Rev 10 21/33 Maximum ratings STM706T/S/R, STM706P, STM708T/S/R 5 Maximum ratings Stressing the device above the rating listed in the “absolute maximum ratings” table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Table 4. Symbol TSTG TSLD(1) VIO(2) VCC IO PD Absolute maximum ratings Parameter Storage temperature (VCC Off) Lead solder temperature for 10 seconds Input or output voltage Supply voltage Output current Power dissipation Value –55 to 150 260 –0.3 to VCC +0.3 –0.3 to 7.0 20 320 Unit °C °C V V mA mW 1. Reflow at peak temperature of 260 °C. The time above 255 °C must not exceed 30 seconds. 2. Negative undershoot of –1.5 V for up to 10 ns or positive overshoot of VCC + 1.5 V for up to 10 ns is allowable on the WDI and MR input pins. 22/33 Doc ID 10518 Rev 10 STM706T/S/R, STM706P, STM708T/S/R DC and AC parameters 6 DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics tables that follow, are derived from tests performed under the measurement conditions summarized in Table 5, operating and AC measurement conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 5. Operating and AC measurement conditions Parameter VCC supply voltage Ambient operating temperature (TA) Input rise and fall times Input pulse voltages Input and output timing ref. voltages STM70x 1.0 to 5.5 –40 to 85 ≤5 0.2 to 0.8 VCC 0.3 to 0.7 VCC Unit V °C ns V V Figure 25. AC testing input/output waveforms 0.8 V CC 0.7 V CC 0.3 V CC AI02568 0.2 V CC Figure 26. Power-fail comparator waveform VCC VRST trec PFO RST AI08860a Doc ID 10518 Rev 10 23/33 DC and AC parameters STM706T/S/R, STM706P, STM708T/S/R Figure 27. MR timing waveform MR tMLRL RST (1) tMLMH trec AI07837a 1. RST for STM706P and STM708T/S/R. Figure 28. Watchdog timing (STM706T/S/R and STM706P) VCC RST trec tWD WDI WDO AI08833 24/33 Doc ID 10518 Rev 10 STM706T/S/R, STM706P, STM708T/S/R DC and AC parameters Table 6. Symbol VCC ICC DC and AC characteristics Description Operating voltage VCC supply current Input leakage current (WDI) VCC < 3.6 V VCC < 5.5 V 0 V < VIN < VCC 0 V < VIN < VCC VRST (max) < VCC < 3.6 V 4.5 V < VCC < 5.5 V 4.5 V < VCC < 5.5 V VRST (max) < VCC < 3.6 V Input high voltage (WDI) Input low voltage (MR) Input low voltage (WDI) Output low voltage (PFO, RST, RST, WDO) VRST (max) < VCC < 5.5 V 4.5 V < VCC < 5.5 V VRST (max) < VCC < 3.6 V VRST (max) < VCC < 5.5 V VCC = VRST (max), ISINK = 3.2 mA ISINK = 50 µA, VCC = 1.0 V, TA = 0 °C to 85 °C ISINK = 100 µA, VCC = 1.2 V Output high voltage (RST, RST, WDO) Output high voltage (PFO) ISOURCE = 1 mA, VCC = VRST (max) ISOURCE = 75 µA, VCC = VRST (max) 2.4 0.8 VCC –1 –25 25 75 2.0 0.7 VCC 0.7 VCC 0.8 0.6 0.3 VCC 0.3 0.3 0.3 2 80 125 Test condition(1) Min. 1.2(2) 35 40 Typ. Max. 5.5 50 60 +1 +25 250 300 Unit V µA µA µA nA µA µA V V V V V V V V V V V ILI Input leakage current (PFI) Input leakage current (MR) VIH VIH VIL VIL VOL Input high voltage (MR) VOL Output low voltage (RST) VOH Power-fail comparator PFI falling (STM70xP/R, VCC = 3.0 V; STM70xS/T, VCC = 3.3 V) VPFI PFI input threshold PFI to PFO propagation delay 1.20 1.25 1.30 V tPFD 2 µs Doc ID 10518 Rev 10 25/33 DC and AC parameters Table 6. Symbol Reset thresholds STM706T/S/R, STM706P, STM708T/S/R DC and AC characteristics (continued) Description Test condition(1) Min. Typ. Max. Unit STM706P/70xR VRST Reset threshold(3) STM70xS STM70xT Reset threshold hysteresis Blank (see Table 9) trec RST pulse width A(4) (see Table 9) 2.55 2.85 3.00 2.63 2.93 3.08 20 2.70 3.00 3.15 V V V mV 140 160 200 200 280 ms 280 Push-button reset input tMLMH (or tMR) MR pulse width VRST (max) < VCC < 3.6 V 4.5 V < VCC < 5.5 V VRST (max) < VCC < 3.6 V 4.5 V < VCC < 5.5 V 500 150 750 250 ns ns ns ns tMLRL MR to RST output delay (or tMRD) Watchdog timer (STM706T/S/R and STM706P) tWD Watchdog timeout period STM706P/70xR, VCC = 3.0 V STM70xS/70XT, VCC = 3.3 V 1.12 1.60 2.24 s WDI pulse width 4.5 V < VCC < 5.5 V VRST (max) < VCC < 3.6 V 50 100 ns ns 1. Valid for ambient operating temperature: TA = –40 to 85 °C; VCC = VRST (max) to 5.5 V (except where noted). 2. VCC (min) = 1.0 V for TA = 0 °C to +85 °C. 3. For VCC falling. 4. STM706P/STM70xR, VCC = 3 V; STM706xS/STM70xT, VCC = 3.3 V. 26/33 Doc ID 10518 Rev 10 STM706T/S/R, STM706P, STM708T/S/R Package mechanical data 7 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Doc ID 10518 Rev 10 27/33 Package mechanical data STM706T/S/R, STM706P, STM708T/S/R Figure 29. SO8 – 8-lead plastic small outline, 150 mils body width, package mechanical A2 B e D A C ddd 8 E 1 H A1 L SO-A Note: Drawing is not to scale. Table 7. SO8 - 8-lead plastic small outline, 150 mils body width, package mechanical data mm Symbol Typ. A A1 B C D ddd E e H h L α N — — — — — — — 1.27 — — — — 8 Min. 1.35 0.10 0.33 0.19 4.80 — 3.80 — 5.80 0.25 0.40 0° 8 Max. 1.75 0.25 0.51 0.25 5.00 0.10 4.00 — 6.20 0.50 0.90 8° Typ. — — — — — — — 0.050 — — — — Min. 0.053 0.004 0.013 0.007 0.189 — 0.150 — 0.228 0.010 0.016 0° Max. 0.069 0.010 0.020 0.010 0.197 0.004 0.157 — 0.244 0.020 0.035 8° inches 28/33 Doc ID 10518 Rev 10 STM706T/S/R, STM706P, STM708T/S/R Package mechanical data Figure 30. TSSOP8 – 8-lead, thin shrink small outline, 3 x 3 mm body size, outline D 8 5 E1 E c 1 4 A1 A CP b e A2 L L1 TSSOP8BM Note: Drawing is not to scale. Table 8. TSSOP8 - 8-lead, thin shrink small outline, 3 x 3 mm body size, mechanical data mm Symbol Typ. A A1 A2 b c CP D e E E1 L L1 α N — — 0.85 — — — 3.00 0.65 4.90 3.00 0.55 0.95 — 8 Min. — 0.05 0.75 0.25 0.13 — 2.90 — 4.65 2.90 0.40 — 0° 8 Max. 1.10 0.15 0.95 0.40 0.23 0.10 3.10 — 5.15 3.10 0.70 — 6° Typ. — — 0.034 — — — 0.118 0.026 0.193 0.118 0.022 0.037 — Min. — 0.002 0.030 0.010 0.005 — 0.114 — 0.183 0.114 0.016 — 0° Max. 0.043 0.006 0.037 0.016 0.009 0.004 0.122 — 0.203 0.122 0.030 — 6° inches Doc ID 10518 Rev 10 29/33 Part numbering STM706T/S/R, STM706P, STM708T/S/R 8 Part numbering Table 9. Example: Device type STM706 STM708 Ordering information scheme STM706 T M 6 E Reset threshold voltage T: 3.00 V ≤ VRST ≤ 3.15 V S: 2.88 V ≤ VRST ≤ 3.00 V R, STM706P: 2.59 V ≤ VRST ≤ 2.70 V RST pulse width Blank = 140 to 280 ms A(1) = 160 to 280 ms Package M = SO8 DS(2) = TSSOP8 Temperature range 6 = –40 to 85 °C Shipping method E = ECOPACK® packages, tubes F = ECOPACK® packages, tape and reel 1. Available in SO8 (M) package only. 2. Contact local ST sales office for availability. For other options, or for more information on any aspect of this device, please contact the ST sales office nearest you. 30/33 Doc ID 10518 Rev 10 STM706T/S/R, STM706P, STM708T/S/R Table 10. Marking description Reset threshold 2.63 V TSSOP8 SO8 STM706T 3.08 V TSSOP8 SO8 STM706S 2.93 V TSSOP8 SO8 STM706R 2.63 V TSSOP8 SO8 STM708T 3.08 V TSSOP8 SO8 STM708S 2.93 V TSSOP8 SO8 STM708R 2.63 V TSSOP8 Package SO8 STM706P Part numbering Part number Topside marking 706P 706T 706S 706R 708T 708S 708R Doc ID 10518 Rev 10 31/33 Revision history STM706T/S/R, STM706P, STM708T/S/R 9 Revision history Table 11. Date Oct-2003 12-Dec-2003 16-Jan-2004 09-Apr-2004 25-May-2004 02-Jul-2004 21-Sep-2004 25-Feb-2005 02-Nov-2009 30-Apr-2010 06-Aug-2010 Document revision history Revision 1 2 2.1 3 4 5 6 7 8 9 10 Initial release. Reformatted; update characteristics (Figure 2, 3, 8 to 10, 27 to 29; Table 6 to 9). Add Typical operating characteristics (Figure 13, to 19, 21, to 25). Reformatted; update characteristics (Figure 15, 19, 21, 22, 25; Table 8). Update characteristics (Table 3, Table 6). Datasheet promoted; waveform corrected (Table 27). Clarify root part numbers; (Figure 2, to 10, 29; Table 1, 3, 6, 9). Update typical characteristics (Figure 13 to 25). Updated Table 1, Table 3, Table 4, Table 6, Table 9, Section 2.3, Section 2.7, text in Section 7; reformatted document. Updated Table 4, corrected typo in Table 2, Section 2.3, Section 3, Section 5 and Section 6, Figure 17, Table 7 and Table 8. Updated Features, Section 4: Typical operating characteristics; Table 9. Changes 32/33 Doc ID 10518 Rev 10 STM706T/S/R, STM706P, STM708T/S/R Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. 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