STP22N60M6
Datasheet
N-channel 600 V, 196 mΩ typ., 15 A, MDmesh™ M6 Power MOSFET
in a TO-220 package
Features
TAB
1
2
3
TO-220
Order code
VDS
RDS(on) max.
ID
STP22N60M6
600 V
230 mΩ
15 A
•
•
Reduced switching losses
Lower RDS(on) per area vs previous generation
•
•
•
Low gate input resistance
100% avalanche tested
Zener-protected
D(2, TAB)
Applications
•
•
•
G(1)
S(3)
AM01475V1
Switching applications
LLC converters
Boost PFC converters
Description
The new MDmesh™ M6 technology incorporates the most recent advancements to
the well-known and consolidated MDmesh family of SJ MOSFETs.
STMicroelectronics builds on the previous generation of MDmesh devices through its
new M6 technology, which combines excellent RDS(on) per area improvement with
one of the most effective switching behaviors available, as well as a user-friendly
experience for maximum end-application efficiency.
Product status link
STP22N60M6
Product summary
Order code
STP22N60M6
Marking
22N60M6
Package
TO-220
Packing
Tube
DS12818 - Rev 1 - November 2018
For further information contact your local STMicroelectronics sales office.
www.st.com
STP22N60M6
Electrical ratings
1
Electrical ratings
Table 1. Absolute maximum ratings
Symbol
Value
Unit
Gate-source voltage
±25
V
Drain current (continuous) at Tcase = 25 °C
15
Drain current (continuous) at Tcase = 100 °C
9.5
IDM(1)
Drain current (pulsed)
42
A
PTOT
Total power dissipation at Tcase = 25 °C
130
W
dv/dt(2)
Peak diode recovery voltage slope
15
dv/dt(3)
MOSFET dv/dt ruggedness
100
Tstg
Storage temperature range
VGS
ID
Tj
Parameter
Operating junction temperature range
A
V/ns
-55 to 150
°C
Value
Unit
1. Pulse width is limited by safe operating area.
2. ISD ≤ 15 A, di/dt = 400 A/μs, VDS < V(BR)DSS, VDD = 400 V
3. VDS ≤ 480 V
Table 2. Thermal data
Symbol
Parameter
Rthj-case
Thermal resistance junction-case
0.96
°C/W
Rthj-amb
Thermal resistance junction-ambient
62.5
°C/W
Value
Unit
2.9
A
230
mJ
Table 3. Avalanche characteristics
Symbol
IAR
EAS
DS12818 - Rev 1
Parameter
Avalanche current, repetitive or non-repetitive
(pulse width limited by TJmax)
Single pulse avalanche energy
(starting Tj = 25 °C, ID = IAR, VDD = 50 V)
page 2/13
STP22N60M6
Electrical characteristics
2
Electrical characteristics
(Tcase = 25 °C unless otherwise specified).
Table 4. On/off states
Symbol
V(BR)DSS
Parameter
Test conditions
Drain-source breakdown voltage
VGS = 0 V, ID = 1 mA
Min.
Typ.
600
Zero gate voltage drain current
IGSS
1
VGS = 0 V, VDS = 600 V,
Tcase = 125
100
°C(1)
Gate-body leakage current
VDS = 0 V, VGS = ±25 V
VGS(th)
Gate threshold voltage
VDS = VGS, ID = 250 µA
RDS(on)
Static drain-source on-resistance
ID = 7.5 A, VGS = 10 V
Unit
V
VGS = 0 V, VDS = 600 V
IDSS
Max.
µA
±5
µA
4
4.75
V
196
230
mΩ
Min.
Typ.
Max.
Unit
-
800
-
-
52.6
-
-
4.3
-
3.25
1. Defined by design, not subject to production test.
Table 5. Dynamic
Symbol
Parameter
Test conditions
Ciss
Input capacitance
Coss
Output capacitance
Crss
Reverse transfer capacitance
Coss eq.(1)
Equivalent output capacitance
VDS = 0 to 480 V, VGS = 0 V
-
181
-
pF
RG
Intrinsic gate resistance
f = 1 MHz, ID = 0 A
-
4.7
-
Ω
Qg
Total gate charge
VDD = 480 V, ID = 15 A,
-
20
-
Qgs
Gate-source charge
VGS = 0 to 10 V
-
5.6
-
Gate-drain charge
(see Figure 14. Test circuit for gate
charge behavior)
-
9.5
-
Qgd
VDS = 100 V, f = 1 MHz, VGS = 0 V
pF
nC
1. Coss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0
to 80% VDSS.
Table 6. Switching times
Symbol
td(on)
tr
td(off)
tf
DS12818 - Rev 1
Parameter
Test conditions
Min.
Typ.
Max.
Turn-on delay time
VDD = 300 V, ID = 7.5 A,
-
13.6
-
Rise time
RG = 4.7 Ω, VGS = 10 V
-
6.3
-
Turn-off delay time
(see Figure 13. Test circuit for
resistive load switching times and
Figure 18. Switching time
waveform)
-
32
-
-
8.7
-
Fall time
Unit
ns
page 3/13
STP22N60M6
Electrical characteristics
Table 7. Source-drain diode
Symbol
ISD
ISDM(1)
(2)
Parameter
Test conditions
Min.
Typ.
Max.
Unit
Source-drain current
-
15
A
Source-drain current (pulsed)
-
42
A
1.6
V
Forward on voltage
ISD = 15 A, VGS = 0 V
-
trr
Reverse recovery time
ISD = 15 A, di/dt = 100 A/µs,
-
217
ns
Qrr
Reverse recovery charge
VDD = 60 V
-
1.99
µC
Reverse recovery current
(see Figure 15. Test circuit for
inductive load switching and diode
recovery times)
-
18.3
A
-
299
ns
-
2.95
μC
-
19.7
A
VSD
IRRM
trr
Reverse recovery time
Qrr
Reverse recovery charge
IRRM
Reverse recovery current
ISD = 15 A, di/dt = 100 A/µs,
VDD = 60 V, Tj = 150 °C
(see Figure 15. Test circuit for
inductive load switching and diode
recovery times)
1. Pulse width is limited by safe operating area.
2. Pulsed: pulse duration = 300 µs, duty cycle 1.5%
DS12818 - Rev 1
page 4/13
STP22N60M6
Electrical characteristics (curves)
2.1
Electrical characteristics (curves)
Figure 2. Thermal impedance
Figure 1. Safe operating area
ID
(A)
GIPG061120181053SOA
Operation in this area
is limited by R DS(on)
tp =1 µs
10 1
tp =10 µs
tp =100 µs
tp =1 ms
TJ≤150 °C
TC=25 °C
VGS=10 V
single pulse
10 0
10 -1
10 -1
10 0
tp =10 ms
10 1
VDS (V)
10 2
Figure 3. Output characteristics
ID
(A)
Figure 4. Transfer characteristics
GIPG061120181052OCH
VGS =10 V
VGS =9 V
42
36
24
42
VDS = 14 V
30
24
18
VGS =7 V
12
18
12
6
VGS =6 V
2
4
6
8
10
12
14
VDS (V)
Figure 5. Gate charge vs gate-source voltage
VDS
(V) VDD = 480 V
ID = 15 A
600
500
400
GIPG061120181052TCH
36
VGS =8 V
30
0
0
ID
(A)
Qgd
Qgs
12
212
8
5
6
7
8
9
VGS (V)
Figure 6. Static drain-source on-resistance
RDS(on)
(mΩ)
10
VDS
0
4
(V)
GIPG061120181050QVG VGS
Qg
6
GIPG061120181210RID
VGS = 10 V
208
204
200
300
6
200
4
100
2
0
0
DS12818 - Rev 1
4
8
12
16
20
0
Qg (nC)
196
192
188
184
0
2
4
6
8
10
12
14
ID (A)
page 5/13
STP22N60M6
Electrical characteristics (curves)
Figure 7. Capacitance variations
C
(pF)
EOSS
(µJ)
8
GIPG061120181052CVR
10 3
CISS
GADG061120181125EOS
7
6
5
10 2
10 1
Figure 8. Output capacitance stored energy
4
f = 1 MHz
COSS
3
CRSS
2
1
10 0
10 -1
10 0
10 1
10 2
VDS (V)
Figure 9. Normalized gate threshold voltage vs
temperature
VGS(th)
(norm.)
GADG190720181456VTH
200
300
400
500
600
VDS (V)
Figure 10. Normalized on-resistance vs temperature
RDS(on)
(norm.)
GADG190720181456RON
VGS = 10 V
1.8
1.0
1.4
0.9
1
0.8
0.6
0.7
0.6
-75
100
2.2
ID = 250 µA
1.1
0
0
-25
25
75
125
Tj (°C)
Figure 11. Normalized V(BR)DSS vs temperature
V(BR)DSS
(norm.)
GADG190720181457BDV
-25
25
75
125
Tj (°C)
Figure 12. Source-drain diode forward characteristics
VSD
(V)
GIPG061120181205SDF
1.1
ID = 1 mA
1.08
0.2
-75
Tj = -50 °C
1.0
1.04
0.9
Tj = 25 °C
1.00
0.8
0.96
0.92
0.88
-75
DS12818 - Rev 1
Tj = 150 °C
0.7
0.6
-25
25
75
125
Tj (°C)
0.5
0
2
4
6
8
10
12
14
ISD (A)
page 6/13
STP22N60M6
Test circuits
3
Test circuits
Figure 13. Test circuit for resistive load switching times
Figure 14. Test circuit for gate charge behavior
VDD
RL
RL
2200
+ μF
3.3
μF
VDD
VD
RG
VGS
IG= CONST
VGS
+
pulse width
D.U.T.
2.7 kΩ
2200
μF
pulse width
D.U.T.
100 Ω
VG
47 kΩ
1 kΩ
AM01469v10
AM01468v1
Figure 15. Test circuit for inductive load switching and
diode recovery times
D
G
A
D.U.T.
S
25 Ω
A
L
A
VD
100 µH
fast
diode
B
B
B
3.3
µF
D
G
+
Figure 16. Unclamped inductive load test circuit
RG
1000
+ µF
2200
+ µF
VDD
3.3
µF
VDD
ID
D.U.T.
S
D.U.T.
Vi
_
pulse width
AM01471v1
AM01470v1
Figure 18. Switching time waveform
Figure 17. Unclamped inductive waveform
ton
V(BR)DSS
td(on)
toff
td(off)
tr
tf
VD
90%
90%
IDM
VDD
10%
0
ID
VDD
AM01472v1
VGS
0
VDS
10%
90%
10%
AM01473v1
DS12818 - Rev 1
page 7/13
STP22N60M6
Package information
4
Package information
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK®
packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions
and product status are available at: www.st.com. ECOPACK® is an ST trademark.
DS12818 - Rev 1
page 8/13
STP22N60M6
TO-220 type A package information
4.1
TO-220 package information
Figure 19. TO-220 type A package outline
0015988_typeA_Rev_22
DS12818 - Rev 1
page 9/13
STP22N60M6
TO-220 type A package information
Table 8. TO-220 type A package mechanical data
Dim.
mm
Min.
Max.
A
4.40
4.60
b
0.61
0.88
b1
1.14
1.55
c
0.48
0.70
D
15.25
15.75
D1
DS12818 - Rev 1
Typ.
1.27
E
10.00
10.40
e
2.40
2.70
e1
4.95
5.15
F
1.23
1.32
H1
6.20
6.60
J1
2.40
2.72
L
13.00
14.00
L1
3.50
3.93
L20
16.40
L30
28.90
øP
3.75
3.85
Q
2.65
2.95
page 10/13
STP22N60M6
Revision history
Table 9. Document revision history
DS12818 - Rev 1
Date
Version
16-Nov-2018
1
Changes
First release.
page 11/13
STP22N60M6
Contents
Contents
1
Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
2
Electrical characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.1
Electrical characteristics (curves) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3
Test circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
4
Package information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4.1
TO-220 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
DS12818 - Rev 1
page 12/13
STP22N60M6
IMPORTANT NOTICE – PLEASE READ CAREFULLY
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Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of
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No license, express or implied, to any intellectual property right is granted by ST herein.
Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.
ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.
Information in this document supersedes and replaces information previously supplied in any prior versions of this document.
© 2018 STMicroelectronics – All rights reserved
DS12818 - Rev 1
page 13/13