U2752M-AFLG3

U2752M Digital I/Q-Generator Chip for DAB Description Electrostatic sensitive device. Observe precautions for handling. The U2752M is an integrated circuit in CMOS technology for splitting a digital DAB signal into its quadrature components. The device is designed for DAB (ETS 300 401) applications. Features D U2752M splits a digital DAB input signal into its D D D quadrature components Quadrature matching: 0 dB in magnitude, ≤ 1.6° in phase Clock frequency: 4.096 MHz Input signal – Center frequency: 3.072 MHz – Bandwidth: 1.536 MHz – Data format: 8 bit, 4.096 MHz in 2’s complement representation D Output signal Block Diagram om po ne 2 AP–I MUX 2 AP–Q 96 12265 nt s – Select pin for baseband or 1.024-MHz center frequency – I-, Q- components in time multiplex – Data format: 8 bit, 4.096 MHz in 2’s complement representation 8 DATA_IN RESET CLOCK Ad ro nic C VDD VSS Figure 1. Block diagram Ordering Information Extended Type Number U2752M-AFL U2752M-AFLG3 Package SO24 SO24 Taping according to IEC-286-3 Rev. A1, 29-Jun-98 Gm bH IQDATA 7 DATA_RI MIX_OFF Remarks 1 (6) Preliminary Information U2752M Pin Description MIX_OFF 1 RESET VSS DATA_IN0 2 3 4 5 6 7 8 9 24 23 22 21 20 19 DATA_IN1 DATA_IN2 DATA_IN3 DATA_IN4 DATA_IN5 Ad ro nic C 18 17 16 DATA_IN6 10 15 14 13 DATA_IN7 11 VSS 12 96 12266 Figure 2. Pinning 2 (6) om po ne VDD IQDATA0 IQDATA1 IQDATA2 IQDATA3 IQDATA4 IQDATA5 IQDATA6 IQDATA7 VDD DATA_RI CLOCK ÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ Á Á Á Á ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ ÁÁÁÁ Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Signal MIX_OFF RESET VSS DATA_IN0 DATA_IN1 DATA_IN2 DATA_IN3 DATA_IN4 DATA_IN5 DATA_IN6 DATA_IN7 VSS CLOCK DATA_RI VDD IQDATA7 IQDATA6 IQDATA5 IQDATA4 IQDATA3 IQDATA2 IQDATA1 IQDATA0 VDD Description Low: I/Q in baseband representation, High. I/Q in IF representation Reset signal, high active Ground Data input (LSB) Data input Data input Data input Data input Data input Data input Data input (MSB) Ground System clock 4.096 MHz Internal data_ri signal Power supply Data_output, I and Q multiplex (MSB) Data_output, I and Q multiplex Data_output, I and Q multiplex Data_output, I and Q multiplex Data_output, I and Q multiplex Data_output, I and Q multiplex Data_output, I and Q multiplex Data_output, I and Q multiplex (LSB) Power supply PAD Type BUFINCDN BUFINCDN nt s Functional Description The U2752M generates the in-phase and quadrature components of the DAB input signal with a quadrature matching of 0 dB in magnitude and a maximum value of 1.6° in phase. The clock of the device is 4.096 MHz. The data format of the input signal DATA_IN is 8 bits, sampled with 4.096 MHz in 2’s complement representation. Its center frequency is 3.072 MHz with a bandwidth of 1536 MHz. The U2752M uses decimation and common filter techniques to generate the quadrature components. The output interface consists of the split signal IQDATA with a data format of 8 bits, 4.096 MHz in 2’s complement representation. The in-phase (I) and quadrature (Q) components are represented in time division multiplex format with a selection signal DATA_RI of 4.096 MHz. The output representation in baseband or 1.024-MHz center frequency is selected by the MIX_OFF signal. For utilization together with TEMIC’s U2752M device, the baseband representation (MIX_OFF = ‘0’) must be selected. Preliminary Information Gm bH BUFINMOS BUFINMOS BUFINMOS BUFINMOS BUFINMOS BUFINMOS BUFINMOS BUFINMOS BUFTGMOS BU2OUT BU2OUT BU2OUT BU2OUT BU2OUT BU2OUT BU2OUT BU2OUT BU2OUT Rev. A1, 29-Jun-98 U2752M Absolute Maximum Ratings Parameters DC supply voltage Input / output voltage Storage temperature Symbol VDD Vin/Vout Tstg Min. –0.5 –0.5 –65 Typ. Max. +7 VDD + 0.5 +150 Unit V V °C Operating Range Parameters DC supply voltage Input / output voltage Ambient temperature Power dissipation (static) Power dissipation (dynamic) Symbol VDD Vin/Vout Tamb Pstat Pdyn Gm bH Min. 4.5 0 –40 Typ. Max. 5.5 VDD +85 0.25 15 Value 80 Min. 3.5 1.61 2.47 ±1 +40 2.4 0.4 Typ. Max. 1.5 2.60 3.52 ±5 +100 Parameters Junction ambient SO24 om po ne Thermal Resistance nt s Symbol RthJA Symbol VIH VIL VT+ VT– IL VOH VOL Unit V V °C mW mW Unit K/W Electrical Characteristics Parameters Input HIGH voltage Input LOW voltage Positive threshold Negative threshold Input leakage Test conditions: VDD = 5 V, Tamb = 25°C Ad ro nic C Test Conditions / Pins Pins 1, 2, 4 to 11 Pins 1, 2, 4 to 11 Pin 13 Unit V V V V Output HIGH voltage Output LOW voltage VIN = VDD or VSS VIN = VDD Pins 1, 2, 4 to 11 and 13 IOH = +6.4 mA Pins 14, 16 to 23 IOH = –6.4 mA Pins 14, 16 to 23 µA µA V V Rev. A1, 29-Jun-98 3 (6) Preliminary Information U2752M Input Interface Description CLOCK Internal RI selection signal DATA_IN tsu_din Figure 3. Input interface signals (tsu_din ≥ 10 ns) om po ne 80 60 40 20 Phase deviation from 90 degree 0 –20 –40 –60 –80 –100 0 96 12047 For verification purposes, it can be helpful to know how the U2752M selects the input samples for real and imaginary data processing. The U2752M generates an internal real and imaginary selection signal, which depends on the first recognized rising CLOCK edge as shown in figure 3. Due to this selection signal, the data input DATA_IN will be used for the real or imaginary process path of the IC. The setup time of DATA_IN tsu_din must be ≥ 10 ns. Results The phase deviation from 90° of the I- and Q- parts over the normalized frequency is shown in figure 4. Ad ro nic C The DAB-relevant frequency range is from 1/8 to 7/8 on the normalized frequency axis. For the DAB frequency range, the maximum phase mismatch is 1.6° and the amplitude mismatch is 0 dB. 4 (6) nt s 100 max. phase mismatch = 1.6 deg max. amplitude mismatch = 0 dB 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 Normalized frequency Figure 4. Phase deviation of the I- and Q–parts Preliminary Information Gm bH R I R I 96 12267 RESET Rev. A1, 29-Jun-98 U2752M Package Information Package SO24 Dimensions in mm 15.55 15.30 9.15 8.65 2.35 0.25 0.10 13.97 24 13 0.4 1.27 om po ne nt s technical drawings according to DIN specifications 13037 1 12 Rev. A1, 29-Jun-98 Ad ro nic C Gm bH 10.50 10.20 7.5 7.3 0.25 5 (6) Preliminary Information U2752M Ozone Depleting Substances Policy Statement It is the policy of TEMIC Semiconductor GmbH to 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances ( ODSs). The Montreal Protocol ( 1987) and its London Amendments ( 1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. TEMIC Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2 . Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency ( EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C ( transitional substances ) respectively. TEMIC Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances. We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC products for any unintended or unauthorized application, the buyer shall indemnify TEMIC against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. TEMIC Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 ( 0 ) 7131 67 2831, Fax number: 49 ( 0 ) 7131 67 2423 6 (6) Ad ro nic C om po ne nt s Preliminary Information Gm bH 1. Meet all present and future national and international statutory requirements. Rev. A1, 29-Jun-98