DG884DN

DG884 Vishay Siliconix 8 x 4 Wideband Video Crosspoint Array DESCRIPTION FEATURES The DG884 contains a matrix of 32 T-switches configured in an 8 x 4 crosspoint array. Any of the IN/OUT pins may be used as an input or output. Any of the IN pins may be switched to any or simultaneously to all OUT pins. • • • • The DG884 is built on a proprietary D/CMOS process that combines low capacitance switching DMOS FETs with low power CMOS control logic and drivers. The ground lines between adjacent signal input pins help to reduce crosstalk. The low on-resistance and low on-capacitance of the DG884 make it ideal for video and wideband signal routing. Routes Any Input to Any Output Wide Bandwidth: 300 MHz Low Crosstalk: - 85 dB at 5 MHz Double Buffered TTL-Compatible Latches with Readback • Low rDS(on): 45 Ω • Optional Negative Supply RoHS* COMPLIANT BENEFITS • • • • • • • Control data is loaded individually into four Next Event latches. When all Next Event latches have been programmed, data is transferred into the Current Event latches via a SALVO command. Current Event latch data readback is available to poll array status. Output disable capabilities make it possible to parallel multiple DG884s to form larger switch arrays. DIS outputs provide control signals used to place external buffers in a power saving mode. Pb-free Available Reduced Board Space Improved System Bandwidth Improved Channel Off-Isolation Simplified Logic Interfacing Allows Bipolar Signal Swings Reduced Insertion Loss High Reliability APPLICATIONS • • • • • For additional information see applications note AN504 (FaxBack document number 70610). Wideband Signal Routing and Multiplexing High-End Video Systems NTSC, PAL, SECAM Switchers Digital Video Routing ATE Systems FUNCTIONAL BLOCK DIAGRAM IN1 IN2 IN3 IN4 IN5 IN6 IN7 IN8 OUT1 OUT2 8 4 Switch Matrix OUT3 OUT4 Decode Logic, Switch Drivers Current Event Latches WR CS B1 4 Disable Outputs RS SALVO I/O Control Logic Next Event Latches B0 I/O A3 A2 A1 A0 * Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 70071 S-71241–Rev. H, 25-Jun-07 www.vishay.com 1 DG884 Vishay Siliconix GND OUT4 OUT1 5 4 3 2 1 44 43 42 41 40 GND GND OUT3 GND 6 GND IN 1 OUT2 GND PIN CONFIGURATION AND ORDERING INFORMATION IN2 7 39 DGND GND 8 38 VL IN3 9 37 RS GND 10 36 SALVO IN4 11 35 WR GND 12 PLCC and CLCC 34 A3 IN5 13 Top View 33 A2 GND 14 32 A1 IN6 15 31 A0 GND 16 30 CS IN7 17 29 I/O ORDERING INFORMATION Temp Range Package Part Number - 40 to 85 °C 44-Pin PLCC DG884DN DG884DN-E3 B1 B0 V+ DIS 4 DIS 3 DIS 2 DIS 1 V GND IN8 GND 18 19 20 21 22 23 24 25 26 27 28 TRUTH TABLE I RS I/O CS WR 1 0 1 1 No change to Next Event latches 1 0 0 1 Next Event latches loaded as defined in table below 1 0 0 1 Next Event latches are transparent 1 0 0 1 Next Event data latched-in 1 0 X 1 1 0 0 X 1 0 X 1 1 0 0 0 0 Both next and Current Event latches are transparent 1 1 1 1 1 A0, A1, A2, A3 - High impedance 1 1 0 1 1 A0, A1, A2, A3 become outputs and reflect the contents of the Current Event latches B0, B1 determine which Current Event latches are being read 0 X X 1 1 All crosspoints opened (but data in Next Event latches is preserved) 0 SALVO Actions Data in all Next Event latches is simultaneously loaded into the Current Event latches, i.e., all new crosspoint addresses change simultaneously when SALVO goes low 0 Current Event latches are transparent Current Event data latched-in All other states are not recommended. www.vishay.com 2 Document Number: 70071 S-71241–Rev. H, 25-Jun-07 DG884 Vishay Siliconix TRUTH TABLE II WR B1 B0 A3 0 0 1 0 0 1 1 0 0 1 0 1 0 1 1 1 A2 0 0 0 0 1 1 1 1 X 0 0 0 0 1 1 1 1 X 0 0 0 0 1 1 1 1 X 0 0 0 0 1 1 1 1 X A1 0 0 1 1 0 0 1 1 X 0 0 1 1 0 0 1 1 X 0 0 1 1 0 0 1 1 X 0 0 1 1 0 0 1 1 X A0 0 1 0 1 0 1 0 1 X 0 1 0 1 0 1 0 1 X 0 1 0 1 0 1 0 1 X 0 1 0 1 0 1 0 1 X Next Event Latches IN1 to OUT1 Loaded IN2 to OUT1 Loaded IN3 to OUT1 Loaded IN4 to OUT1 Loaded IN5 to OUT1 Loaded IN6 to OUT1 Loaded IN7 to OUT1 Loaded IN8 to OUT1 Loaded Turn Off OUT1 Loaded IN1 to OUT2 Loaded IN2 to OUT2 Loaded IN3 to OUT2 Loaded IN4 to OUT2 Loaded IN5 to OUT2 Loaded IN6 to OUT2 Loaded IN7 to OUT2 Loaded IN8 to OUT2 Loaded Turn Off OUT2 Loaded IN1 to OUT3 Loaded IN2 to OUT3 Loaded IN3 to OUT3 Loaded IN4 to OUT3 Loaded IN5 to OUT3 Loaded IN6 to OUT3 Loaded IN7 to OUT3 Loaded IN8 to OUT3 Loaded Turn Off OUT3 Loaded IN1 to OUT4 Loaded IN2 to OUT4 Loaded IN3 to OUT4 Loaded IN4 to OUT4 Loaded IN5 to OUT4 Loaded IN6 to OUT4 Loaded IN7 to OUT4 Loaded IN8 to OUT4 Loaded Turn Off OUT4 Loaded 0 Notes: When WR = 0 Next Event latches are transparent. Each crosspoint is addressed individually, e.g., to connect IN1 to OUT1 thru OUT4 requires A0, A1, A2 = 0 to be latched with each combination of B0, B1. When RS = 0, all four DIS outputs pull low simultaneously. ABSOLUTE MAXIMUM RATINGS Parameter V+ to GND V+ to VV- to GND VL to GND Digital Inputs VS, VD Current (any terminal) Continuous Current (S or D) Pulsed 1 ms 10 % Duty (A Suffix) Storage Temperature (D Suffix) (A Suffix) Operating Temperature (D Suffix) 44-Pin Quad J Lead PLCCb a Power Dissipation (Package) 44-Pin Quad J Lead Hermetic CLCCc Notes: a. All leads soldered or welded to PC Board. b. Derate 6 mW/°C above 75 °C c. Derate 16 mW/°C above 75 °C. Document Number: 70071 S-71241–Rev. H, 25-Jun-07 Limit - 0.3 to 21 - 0.3 to 21 - 10 to 0.3 0 to (V+) + 0.3 (V-) - 0.3 to (VL) + 0.3 or 20 mA, whichever occurs first (V-) - 0.3 to (V-) + 14 or 20 mA, whichever occurs first 20 40 - 65 to 150 - 65 to 125 - 55 to 125 - 40 to 85 450 1200 Unit V mA °C mW www.vishay.com 3 DG884 Vishay Siliconix SPECIFICATIONSa Parameter Analog Switch Symbol Test Conditions Unless Specified V+ = 15 V, V- = - 3 V VL = 5 V, RS = 2.0 V SALVO, CS, WR, I/O = 0.8 V Analog Signal Rangee Drain-Source On-Resistance Resistance Match Between Channels VANALOG V- = - 5 V ΔrDS(on) IS = - 10 mA, VD = 0 V VAIH = 2.0 V, VAIL = 0.8 V Sequence Each Switch On Source Off Leakage Current IS(off) VS = 8 V, VD = 0 V, RS = 0.8 V Drain Off Leakage Current ID(off) VD = 0 V, VS = 8 V, RS = 0.8 V ID(on) VS = VD = 8 V Total Switch On Leakage Current Digital Input/Output rDS(on) Tempb Typc Full Unit 8 -5 8 V 3 9 9 Room Full Room Full Room Full - 20 - 200 - 20 - 200 - 20 - 2000 2 VAO = 2.7 V, See Truth Table - 600 VAO = 0.4 V, See Truth Table Room 1500 Room 1.5 DIS Pin Sink Current Maxd Room Full Room Full Room IDIS Mind 90 120 Full IAO Maxd 90 120 VAIL Address Output Current Mind -5 VAIH VAI = 0 V or 2 V or 5 V Unit 45 Input Voltage High IAI D Suffix - 40 to 85 °C Room Full Input Voltage Low Address Input Current A Suffix - 55 to 125 °C 0.1 -1 - 10 20 200 20 200 20 2000 - 20 - 200 - 20 - 200 - 20 - 200 20 200 20 200 20 200 2 0.8 1 10 - 200 500 -1 - 10 0.8 1 10 - 200 Ω nA V µA 500 mA Dynamic Characteristics On State Input Capacitancee CS(on) Off State Input Capacitancee Off State Output Capacitancee Transition Time CS(off) tTRANS Break-Before-Make Interval tOPEN SALVO, WR Turn On Time tON SALVO, WR Turn Off Time tOFF Charge Injection CD(off) Q Matrix Disabled Crosstalk XTALK(DIS) Adjacent Input Crosstalk XTALK(AI) All Hostile Crosstalk XTALK(AH) Bandwidth www.vishay.com 4 BW 1 In to 1 Out, See Figure 11 Room 30 40 1 In to 4 Out, See Figure 11 Room 120 160 Room 8 20 20 Room 10 20 20 See Figure 11 See Figure 5 RL = 1 kΩ, CL = 35 pF 50 % Control to 90 % Output See Figure 3 See Figure 6 RIN = RL = 75 Ω f = 5 MHz, See Figure 10 RIN = 10 Ω, RL = 10 kΩ f = 5 MHz, See Figure 9 RIN = 10 Ω, RL = 10 kΩ f = 5 MHz, See Figure 8 RL = 50 Ω, See Figure 7 Room pF 300 Full Room Full Room Full Room 10 300 500 175 300 - 100 Room - 82 Room - 85 Room - 66 Room 300 10 300 ns 175 pC dB MHz Document Number: 70071 S-71241–Rev. H, 25-Jun-07 DG884 Vishay Siliconix SPECIFICATIONSa Parameter Test Conditions Unless Specified V+ = 15 V, V- = - 3 V VL = 5 V, RS = 2.0 V SALVO, CS, WR, I/O = 0.8 V A Suffix - 55 to 125 °C D Suffix - 40 to 85 °C Unit Mind Mind Unit Tempb Typc Room Full 1.5 Room Full - 1.5 -3 -5 -3 -5 IDG Full - 275 - 750 - 750 IL Full 200 Symbol Maxd Maxd Power Supplies Positive Supply Current I+ Negative Supply Current I- Digital GND Supply Current Logic Supply Current Functional Operating Supply Voltage Rangee V+ to VV- to GND V+ to GND All Inputs at GND or 2 V RS = 2 V See Operating Voltage Range (Typical Characteristics) page 6 3 6 3 6 500 mA μA 500 Full 13 20 13 Full - 5.5 0 - 5.5 20 0 Full 10 20 10 20 V Minimum Input Timing Requirements Address Write Time tAW Full 20 50 50 Minimum WR Pulse Width tWP Full 50 100 100 Write Address Time tWA Full - 10 10 10 Chip Select Write Time tCW Full 50 100 100 Write Chip Select Time tWC Full 25 75 75 Minimum SALVO Pulse Width tSP Full 50 100 100 SALVO Write Time tSW Full - 10 10 10 Write SALVOTime tWS Room 20 Input Output Time tIO Room 150 200 200 Address Output Time tAO Room 150 200 200 Chip Select Output Time tCO Room 150 200 Chip Select Address Time tCA Room 60 Reset to SALVO tRS Full I/O Address Input Time tIA Room See Figure 1 ns 50 200 100 50 50 50 Notes: a. Refer to PROCESS OPTION FLOWCHART. b. Room = 25 °C, Full = as determined by the operating temperature suffix. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. e. Guaranteed by design, not subject to production test. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Document Number: 70071 S-71241–Rev. H, 25-Jun-07 www.vishay.com 5 DG884 Vishay Siliconix 120 120 100 100 X TALK(DIS) (– dB) X TALK(AI) (– dB) TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 80 60 80 60 40 40 20 20 1 10 1 100 10 Adjacent Input Crosstalk Matrix Disabled Crosstalk 100 21 19 V+ – Positive Supply (V) 80 X TALK(AH) (– dB) 100 f - Frequency (MHz) f - Frequency (MHz) 60 40 20 17 15 Operating Voltage Area 13 11 0 9 1 10 f – Frequency (MHz) All Hostile Crosstalk www.vishay.com 6 100 0 -1 - 2 - 3 - 4 - 5 - 6 V- – Negative Supply (V) Operating Voltage Area Document Number: 70071 S-71241–Rev. H, 25-Jun-07 DG884 Vishay Siliconix TIMING DIAGRAMS CS for Device A Presetting Device A Donít Care CS for Device B Donít Care Presetting Device B tCA Address B0 B1 Select Output 1 Address A0 A3 Input Select Output 2 Output N Select Input Input Select Input tAW WR tIA tWA tWP tWA tAW tAW tWS SALVO tCW tWA tSW tWC tSP tSW tWS tCW I/O tSP RS Reset Occuring at Any Time Results In All Current Event Latches Being Cleared tRS Figure 1. Input Timing Requirements CS for Device A Interrogating Device A CS for Device B Interrogating Device B tC O Address B0 B1 Address A0 A3 tC Select Current Event Latch 1 tAO Output Latch N tAO Address Output 1 tCA Out N O tC Select Current Event Latch A tAO t AO Address Output WR SALVO tIO tIA I/O RS Reset Occuring at Any Time Results In All Current Event Latches Being Cleared Figure 2. Output Timing Requirements PARAMETER DEFINITIONS Symbol Parameter TAW Address to Write Minimum time address must be valid before WR goes high TWA Write to Address Minimum time address must remain valid after WR pulse goes high TWP WR Pulse TCW Chip Select to WR Minimum time chip select must be valid before a WR pulse TWC WR to Chip Select Minimum time chip select must remain valid after WR pulse TSP SALVO Pulse Minimum time of SALVO pulse width TWS WR to SALVO Minimum time from WR pulse to SALVOto load new address TSW SALVO to WR Minimum time from SALVO pulse to WR to load current address TIA I/O to Address In TRS RS to SALVO TIO I/O to Output TAO Address to Output TCO CS to Output TCA CS to Address In Document Number: 70071 S-71241–Rev. H, 25-Jun-07 Description Minimum time of WR pulse width to write address into Next Event latches Minimum time I/O must be valid before address applied Minimum time RS must be valid before SALVO pulse Minimum time I/O must be valid before address output valid Minimum time address BX must be valid until address AX output valid Minimum time CS must be valid until AX output is valid Minimum time CS must be valid before address applied if I/O is high www.vishay.com 7 DG884 Vishay Siliconix TEST CIRCUITS -3V VL V 1V 5V 15 V V+ VO IN1 3V OUT1 GND DGND 1 kΩ DG884 A0, A1, A2 0V SALVO 3V 50 % 35 pF 50 % 0V IN2 – IN8 1V 90 % 90 % VO SALVO A0, A1, A2 B0 B1 I/O CS WR A3 RS tOFF tON 3V Figure 3. SALVO Turn On/Off Time -3V VL V 1V 5V 15 V V+ 3V VO IN1 OUT1 GND A0, A1, A2 0V WR 3V 50 % DGND 1 kΩ DG884 50 % 35 pF IN2 – IN8 0V WR A0, A1, A2 B0 B1 I/O CS SALVO VO 90 % 90 % 1V A3 RS tON tOFF 3V Figure 4. WR Turn On/Off Time -3V 1V V IN1 5V VL 15 V V+ 3V VO OUT1 A0, A1, A2 0V 50 % GND VO 90 % DGND IN8 1 kΩ DG884 IN2 – IN7 tTRANS WR A0, A1, A2 B0 B1 I/O CS SALVO tBBM A3 RS 3V Figure 5. Transition Time and Break-Before-Make Interval www.vishay.com 8 Document Number: 70071 S-71241–Rev. H, 25-Jun-07 DG884 Vishay Siliconix TEST CIRCUITS -3V 5V VL V IN1 -3V 15 V V+ VO OUT1 Signal Generator 50 Ω GND DGND 35 pF DG884 A3 5V 15 V VL V IN8 V+ VO OUT1 GND 50 Ω DG884 DGND WR WR A0, A1, A2 B B I/O CS SALVO RS 0 1 A0 A3 B0 B1 I/O CS SALVO WR RS A3 ΔV O 5V 5V Q = ΔV0 CL Figure 6. Charge Injection Any one input to any one output - all remaining inputs connected to remaining outputs Figure 7. -3 dB Bandwidth VO Any input or output pin to adjacent input or output pin Outputs RL 10 kΩ 10 kΩ RL 10 kΩ RIN 10 Ω Vn – 1 Vn RIN 10 Ω Inputs Signal Generator 75 Ω V Signal Generator 75 Ω X TA LK(AH) = 20 log 10 Vn + 1 V OUT V X TALK(AI) = 20 log10 Vn – 1 Vn or 20 log10 Vn + 1 Vn Figure 9. Adjacent Input Crosstalk Figure 8. All Hostile Crosstalk All crosspoints open RIN 10 Ω VO Outputs IN3 DG884 IN 8 -3V 15 V CS "0" = Off-State "1" = On-State V OUT V Figure 10. Matrix Disabled Crosstalk Document Number: 70071 S-71241–Rev. H, 25-Jun-07 V+ X TALK(DIS) = 20 log10 I/O V– Signal Generator 75 Ω IN7 5V VL RS IN5 V GND DGND IN4 IN6 OUT 4 OUT 3 OUT 2 IN2 OUT 1 Meter HP4192A Impedance Analyzer or Equivalent Inputs IN 1 RL 75 Ω Figure 11. On-State and Off-State Capacitances www.vishay.com 9 DG884 Vishay Siliconix PIN DESCRIPTION Pin Symbol 1, 3, 4, 6, 8, 10, 12, 14, 16, 18, 20, 41, 43 GND 39 DGND 26 V+ Positive Supply Voltage 21 V- Negative Supply Voltage 38 VL Logic Supply Voltage - generally 5 V 5, 7, 9, 11, 13, 15, 17, 19 IN1 to IN8 2, 40, 42, 44 OUT1 to OUT4 29 I/O Determines whether data is being written into the Next Event latches or read from the Current Event latches 30 CS Chip Select - a logic input 31, 32, 33, 34 A0, A1, A2, A3 27, 28 B 0, B 1 35 WR 36 SALVO 37 RS 22, 23, 24, 25 DIS1 to DIS4 Description Analog Signal Ground Digital Ground 8 Analog Input Channels 4 Analog Output Channels IN Address - logic inputs or outputs as defined by I/O pin, select one of eight IN channels OUT Address - logic inputs, select one of four OUT channels Write command that latches A0, A1, A2, A3 into the Next Event latches Master write command, that in one action, transfers all the data from Next Event latches into Current Event latches Reset - a low will clear the Current Event latches Open drain disable outputs - these outputs pull low when the corresponding OUT channel is off DEVICE DESCRIPTION The DG884 is the world’s first monolithic wideband crosspoint array that operates from dc to > 100 MHz. The DG884 offers the ability to route any one of eight input signals to any one of four OUT pins. Any input can be routed to one, two, three or four OUTs simultaneously with no risk of shorting inputs together (guaranteed by design). Each crosspoint is configured as a “T” switch in which DMOS FETs are used due to their excellent low resistance and low capacitance characteristics. Each OUT line has a series switch that minimizes capacitive loading when the OUT is off. Interfacing The DG884 was designed to allow complex matrices to be developed while maintaining a simple control interface. The status of the I/O pin determines whether the DG884 is being written to or read from (see Figures 1 and 2). In order to WRITE to an individual latch, CS and I/O need to be low, while RS, WR and SALVO must be high. The IN to OUT path is selected by using address A0 through A3 to define the IN line and address B0 and B1 to define the OUT line. That is, The IN defined by A0 through A3 is electrically connected to the OUT defined by B0, B1. This chosen path is loaded into the Next Event latches when WR goes low and returns high again. This operation is repeated up to three more times if other crosspoint connections need to be changed. www.vishay.com 10 Upon completing all crosspoint connections that are to be changed in a single device, other DG884s can be similarly preset by taking the CS pin low on the appropriate device. When all DG884s are preset, the Current Event latches are simultaneously changed by a single SALVO command applied to all devices. In this manner the crosspoint configuration of any number of devices can be simultaneously updated. DIS Outputs Four open drain disable OUTs are provided to control external line drivers or to provide visual or electrical signaling. For example, any or all of the DIS OUTs can directly interface with a CLC410 Video Amplifier to place it into a high impedance, low-power standby mode when the corresponding OUT is not being used. (See Figure 15). The DIS outputs are low and sink to V- when corresponding OUT is open or RS is low. Reset The reset function (RS) allows the resetting of all crosspoints to a known state (open). At power up, the reset facility may be used to guarantee that all switches are open. It should be noted that RS clears the Current Event latches, but the Next Event latches remain unchanged. This useful facility allows the user to return the matrix to its previous state (prior to reset) by simply applying the SALVO command. Alternatively, the user can reprogram the Next Event latches, and then apply the SALVO command to reconfigure the matrix to a new state. Document Number: 70071 S-71241–Rev. H, 25-Jun-07 DG884 Vishay Siliconix DEVICE DESCRIPTION Readback The I/O facility enables the user to write data to the Next Event latches or to read the contents of the Current Event latches. This feature permits the central controller to periodically monitor the state of the matrix. If a power loss to the controller occurs, the readback feature helps the matrix to recover rapidly. It also offers a means to perform PC board diagnostics both in production and in system operation. 8 Analog Inputs EN OUT1 CMOS Output Buffers Mux 1 8 4 / Data Buffers OUT2 Mux 2 EN / I/O 4 8 Q0 4 / Q3 7 / Latch 3 Next Event Latch 3 A0 A1 A2 A3 Current Event RS Decoders/ Drivers 9 / 8 T-Switches 1 Series Switch OUT3 8 B0 B1 CS OUT4 Mux 4 WR DIS3 Open Drain Output Mux 3 Decoder SALVO One of Four Blocks of Logic/Latches Shown Figure 12. Control Circuitry APPLICATIONS WR Two-Si584 Quad Unity-Gain Buffers IN1 SALVO CLC410 75 Ω x1 75 Ω IN2 x2 OUT1 x2 OUT2 x2 OUT3 x2 OUT4 DIS1 x1 DIS2 DG884 DIS3 DIS4 IN8 x1 RS Note: DIS outputs are used to power down the Si582 amplifiers. RESET B0 B1 A0 A1 A2 A3 Figure 13. Fully Buffered 8 x 4 Crosspoint Document Number: 70071 S-71241–Rev. H, 25-Jun-07 www.vishay.com 11 DG884 Vishay Siliconix APPLICATIONS +5V + 15 V 51 Ω 51 Ω 6 + C1 VL C2 5 V+ V th – Logic Threshold (V) C2 + C1 DG884 V C1 C2 0 Rules: A useful feature of the DG884 is its power supply flexibility. It can be operated from dual supplies, or a single positive supply (V- connected to 0 V) if required. Allowable operating voltage ranges are shown in Operating Voltage Range (Typical Characteristics) graph, page 6. 1) 3) It allows flexibility in analog signal handling, i.e. with V- = - 5 V and V+ = 15 V, up to ± 5 V ac signals can be accepted. The value of on-capacitance [CS(on)] may be reduced by increasing the value of V-. It is useful to note that optimum video differential phase and gain occur when V- is - 3 V. Note that V+ has no effect on CS(on). V- eliminates the need to bias an ac analog signal using potential dividers and large decoupling capacitors. 4 6 8 10 12 14 16 18 Figure 15. Switching Threshold Voltage vs. VL Power Supplies and Decoupling Note that the analog signal must not go below V- by more than 0.3 V (see absolute maximum ratings). However, the addition of a V- pin has a number of advantages: 2 VL – Logic Supply (V) Figure 14. DG884 Power Supply Decoupling 2) 2 0 C1 = 1 µF Tantalum C2 = 100 nF Ceramic 3V 1) 3 1 + 51 Ω 4 2) 3) Decoupling capacitors should be incorporated on all power supply pins (V+, V-, VL). They should be mounted as close as possible to the device pins. Capacitors should have good high frequency characteristics - tantalum bead and/or monolithic ceramic disc types are suitable. Recommended decoupling capacitors are 1 to 10 µF tantalum bead, in parallel with 100 nF monolithic ceramic. 4) Additional high frequency protection may be provided by 51 Ω carbon film resistors connected in series with the power supply pins (see Figure 14). The VL pin permits interface to various logic types. The device is primarily designed to be TTL or CMOS logic compatible with + 5 V applied to VL. The actual logic threshold can be raised simply by increasing VL. It is established RF design practice to incorporate sufficient bypass capacitors in the circuit to decouple the power supplies to all active devices in the circuit. The dynamic performance of the DG884 is adversely affected by poor decoupling of power supply pins. Also, since the substrate of the device is connected to the negative supply, proper decoupling of this pin is essential. www.vishay.com 12 Document Number: 70071 S-71241–Rev. H, 25-Jun-07 DG884 Vishay Siliconix APPLICATIONS A typical switching threshold versus VL is shown in Figure 15. Layout These devices feature an address readback facility whereby the last address written to the device may be read by the system. This allows improved status monitoring and hand shaking without additional external components. The PLCC package pinout is optimized so that large crosspoint arrays can be easily implemented with a minimum number of PCB layers (see Figure 16). Crosstalk is minimized and off-isolation is optimized by having ground pins located adjacent to each input and output signal pins. Optimum off-isolation and low crosstalk performance can only be achieved by the proper use of RF layout techniques: avoid sockets, use ground planes, avoid ground loops, bypass the power supplies with high frequency type capacitors (low ESR, low ESL), use striplines to maintain transmission line impedance matching. When the I/O assigns the address output condition, the AX address pins can sink or source current for logic low and high, respectively. Note that VL is the logic high output condition. This point must be respected if VL is varied for input logic threshold shifting. Video Out Bus Address Bus Video Out Bus Address Bus Note: Even though these devices are designed to be latchup resistant, VL must not exceed V+ by more than 0.3 V in operation or during power supply on/off sequencing. Video In Bus Video In Bus Video In Bus Video In Bus Video Out Bus Video Out Bus Figure 16. 16 X 8 Expandable Crosspoint Matrix Using DG884 Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?70071. Document Number: 70071 S-71241–Rev. H, 25-Jun-07 www.vishay.com 13 Legal Disclaimer Notice Vishay Disclaimer All product specifications and data are subject to change without notice. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay’s terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. Product names and markings noted herein may be trademarks of their respective owners. Document Number: 91000 Revision: 18-Jul-08 www.vishay.com 1