IRF840ASTRR

IRF840AS, SiHF840AS, IRF840AL, SiHF840AL www.vishay.com Vishay Siliconix Power MOSFET G G D S D FEATURES D D2PAK (TO-263) I2PAK (TO-262) • Low gate charge Qg results in simple drive requirement • Improved gate, avalanche, and dynamic dV/dt Available ruggedness • Fully characterized capacitance and avalanche Available voltage and current • Effective Coss specified • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 G S S N-Channel MOSFET Note * This datasheet provides information about parts that are RoHS-compliant and / or parts that are non RoHS-compliant. For example, parts with lead (Pb) terminations are not RoHS-compliant. Please see the information / tables in this datasheet for details PRODUCT SUMMARY VDS (V) RDS(on) (Ω) 500 VGS = 10 V 0.85 Qg max. (nC) 38 APPLICATIONS Qgs (nC) 9.0 Qgd (nC) 18 • Switch mode power supply (SMPS) • Uninterruptible power supply • High speed power switching Configuration Single TYPICAL SMPS TOPOLOGIES • Two transistor forward • Half bridge • Full bridge ORDERING INFORMATION Package D2PAK (TO-263) D2PAK (TO-263) Lead (Pb)-free and Halogen-free SiHF840AS-GE3 SiHF840ASTRL-GE3 Lead (Pb)-free IRF840ASPbF IRF840ASTRLPbF a D2PAK (TO-263) a I2PAK (TO-262) SiHF840ASTRR-GE3 a IRF840ASTRRPbF a SiHF840AL-GE3 a IRF840ALPbF Note a. See device orientation ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted) PARAMETER SYMBOL LIMIT Drain-Source Voltage VDS 500 Gate-Source Voltage VGS ± 30 Continuous Drain Current VGS at 10 V TC = 25 °C TC = 100 °C Pulsed Drain Current a ID UNIT V 8.0 5.1 A IDM 32 1.0 W/°C Single Pulse Avalanche Energy b EAS 510 mJ Repetitive Avalanche Current a IAR 8.0 A Repetitive Avalanche Energy a EAR 13 mJ Linear Derating Factor Maximum Power Dissipation TC = 25 °C TA = 25 °C Peak Diode Recovery dV/dt c, e Operating Junction and Storage Temperature Range Soldering Temperature d for 10 s PD 125 3.1 dV/dt 5.0 TJ, Tstg -55 to +150 300 W V/ns °C Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11) b. Starting TJ = 25 °C, L = 16 mH, Rg = 25 Ω, IAS = 8.0 A (see fig. 12) c. ISD ≤ 8.0 A, dI/dt ≤ 100 A/μs, VDD ≤ VDS, TJ ≤ 150 °C d. 1.6 mm from case e. Uses IRF840A, SiH840A data and test conditions S21-0901-Rev. E, 30-Aug-2021 Document Number: 91066 1 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF840AS, SiHF840AS, IRF840AL, SiHF840AL www.vishay.com Vishay Siliconix THERMAL RESISTANCE RATINGS PARAMETER SYMBOL MIN. TYP. MAX. Maximum Junction-to-Ambient (PCB mount)a RthJA - - 40 Maximum Junction-to-Case (Drain) RthJC - - 1.0 UNIT °C/W Note a. When mounted on 1" square PCB (FR-4 or G-10 material) SPECIFICATIONS (TJ = 25 °C, unless otherwise noted) PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage VDS Temperature Coefficient Gate-Source Threshold Voltage Gate-Source Leakage Zero Gate Voltage Drain Current VDS VGS = 0, ID = 250 μA 500 - - V ΔVDS/TJ Reference to 25 °C, ID = 1 mA d - 0.58 - V/°C VGS(th) VDS = VGS, ID = 250 μA 2.0 - 4.0 V nA IGSS IDSS VGS = ± 30 V - - ± 100 VDS = 500 V, VGS = 0 V - - 25 VDS = 400 V, VGS = 0 V, TJ = 125 °C - - 250 μA - - 0.85 Ω gfs VDS = 50 V, ID = 4.8 A 3.7 - - S Input Capacitance Ciss 1018 - Coss VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5 - Output Capacitance - 155 - 8.0 - Drain-Source On-State Resistance Forward Transconductance RDS(on) ID = 4.8 A b VGS = 10 V Dynamic Reverse Transfer Capacitance Crss Output Capacitance Coss Output Capacitance Effective Output Capacitance Coss Qg Gate-Source Charge Qgs Gate-Drain Charge Turn-On Delay Time Rise Time 1490 VDS = 400 V, f = 1.0 MHz 42 VDS = 0 V to 480 V c, d Coss eff. Total Gate Charge Turn-Off Delay Time VGS = 0 V - VDS = 1.0 V, f = 1.0 MHz 56 - - 38 - - 9.0 Qgd - - 18 td(on) - 11 - tr td(off) Fall Time tf Gate Input Resistance Rg VGS = 10 V ID = 8.0 A, VDS = 400 V, see fig. 6 and 13 b, d pF nC VDD = 250 V, ID = 8.0 A, Rg = 9.1 Ω, RD = 31 Ω, see fig. 10 b, d - 23 - - 26 - - 19 - f = 1 MHz, open drain 0.7 - 3.7 - - 8.0 S - - 32 Vb - - 2.0 V - 422 633 ns - 2.0 3.0 μC ns Ω Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current Pulsed Diode Forward Current a Body Diode Voltage IS ISM VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Forward Turn-On Time ton MOSFET symbol showing the integral reverse p - n junction diode D A G TJ = 25 °C, IS = 8.0 A, VGS = 0 TJ = 25 °C, IF = 8.0 A, dI/dt = 100 A/μs b Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11) b. Pulse width ≤ 300 μs; duty cycle ≤ 2 % c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 %to 80 % VDS d. Uses IRF840A, SiHF840A data and test conditions S21-0901-Rev. E, 30-Aug-2021 Document Number: 91066 2 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF840AS, SiHF840AS, IRF840AL, SiHF840AL www.vishay.com Vishay Siliconix ID, Drain-to-Source Current (A) 102 VGS 15 V 10 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V Bottom 4.5 V Top 10 1 4.5 V 20 µs Pulse Width TJ = 25 °C 0.1 0.1 102 10 1 VDS, Drain-to-Source Voltage (V) 91066_01 C, Capacitance (pF) ID, Drain-to-Source Current (A) 1 2.0 1.5 1.0 0.5 0.0 - 60 - 40 - 20 0 20 40 60 80 100 120 140 160 TJ, Junction Temperature (°C) VGS = 0 V, f = 1 MHz Ciss = Cgs + Cgd, Cds Shorted Crss = Cgd Coss = Cds + Cgd 104 Ciss 103 Coss 102 10 20 µs Pulse Width TJ = 150 °C 0.1 1 VDS, Drain-to-Source Voltage (V) 20 TJ = 25 °C 1 20 µs Pulse Width VDS = 50 V 5.0 6.0 7.0 8.0 VGS, Gate-to-Source Voltage (V) Fig. 3 - Typical Transfer Characteristics S21-0901-Rev. E, 30-Aug-2021 VGS, Gate-to-Source Voltage (V) TJ = 150 °C 4.0 103 Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage 102 0.1 102 10 91066_05 Fig. 2 - Typical Output Characteristics 10 Crss 1 102 10 1 VDS, Drain-to-Source Voltage (V) 91066_02 ID, Drain-to-Source Current (A) 2.5 Fig. 4 - Normalized On-Resistance vs. Temperature 4.5 V 0.1 91066_03 ID = 8.0 A VGS = 10 V 105 VGS Top 15 V 10 V 8.0 V 7.0 V 6.0 V 5.5 V 5.0 V Bottom 4.5 V 10 3.0 91066_04 Fig. 1 - Typical Output Characteristics 102 RDS(on), Drain-to-Source On Resistance (Normalized) TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted) ID = 8.0 A VDS = 400 V 16 VDS = 250 V VDS = 100 V 12 8 4 For test circuit see figure 13 0 0 9.0 91066_06 10 20 30 40 QG, Total Gate Charge (nC) Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Document Number: 91066 3 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF840AS, SiHF840AS, IRF840AL, SiHF840AL www.vishay.com Vishay Siliconix 8.0 10 TJ = 150 °C TJ = 25 °C 1 4.0 2.0 VGS = 0 V 0.1 0.2 0.5 0.8 1.1 0.0 25 1.4 VSD, Source-to-Drain Voltage (V) 91066_07 50 75 125 150 Fig. 9 - Maximum Drain Current vs. Case Temperature RD VDS 102 100 TC, Case Temperature (°C) 91066_09 Fig. 7 - Typical Source-Drain Diode Forward Voltage ID, Drain Current (A) 6.0 ID, Drain Current (A) ISD, Reverse Drain Current (A) 102 Operation in this area limited by RDS(on) VGS D.U.T. Rg 10 µs + - VDD 10 100 µs 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % 1 ms 1 Fig. 10a - Switching Time Test Circuit 10 ms TC = 25 °C TJ = 150 °C Single Pulse 0.1 102 10 103 VDS 90 % 104 VDS, Drain-to-Source Voltage (V) 91066_08 10 % VGS Fig. 8 - Maximum Safe Operating Area td(on) td(off) tf tr Fig. 10b - Switching Time Waveforms Thermal Response (ZthJC) 10 1 D = 0.50 PDM 0.20 0.1 0.10 t1 0.05 t2 0.02 0.01 10-2 10-5 91066_11 Notes: 1. Duty Factor, D = t1/t2 2. Peak Tj = PDM x ZthJC + TC Single Pulse (Thermal Response) 10-4 10-3 10-2 0.1 1 t1, Rectangular Pulse Duration (s) Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case S21-0901-Rev. E, 30-Aug-2021 Document Number: 91066 4 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF840AS, SiHF840AS, IRF840AL, SiHF840AL www.vishay.com Vishay Siliconix 610 Driver L VDS Rg D.U.T. + A - VDD IAS 20 V VDSav, Avalanche Voltage (V) 15 V 0.01 Ω tp Fig. 12a - Unclamped Inductive Test Circuit 600 590 580 570 560 550 540 0.0 1.0 2.0 5.0 6.0 Fig. 12d - Typical Drain-to-Source Voltage vs. Avalanche Current VDS tp QG 10 V IAS QGS QGD VG Fig. 12b - Unclamped Inductive Waveforms EAS, Single Pulse Avalanche Energy (mJ) 4.0 IAV, Avalanche Current (A) 91066_12d 1200 3.0 ID 3.6 A 5.1 A Bottom 8.0 A Charge Top 1000 Fig. 13a - Basic Gate Charge Waveform 800 Current regulator Same type as D.U.T. 600 400 50 kΩ 12 V 200 91066_12c 0.2 µF 0.3 µF + 0 D.U.T. 25 50 75 100 125 - VDS 150 Starting TJ, Junction Temperature (°C) VGS 3 mA Fig. 12c - Maximum Avalanche Energy vs. Drain Current IG ID Current sampling resistors Fig. 13b - Gate Charge Test Circuit S21-0901-Rev. E, 30-Aug-2021 Document Number: 91066 5 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 IRF840AS, SiHF840AS, IRF840AL, SiHF840AL www.vishay.com Vishay Siliconix Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - Rg • • • • + dV/dt controlled by Rg Driver same type as D.U.T. ISD controlled by duty factor “D” D.U.T. - device under test + - VDD Driver gate drive P.W. Period D= P.W. Period VGS = 10 Va D.U.T. lSD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage Inductor current VDD Body diode forward drop Ripple ≤ 5 % ISD Note a. VGS = 5 V for logic level devices Fig. 14 - For N-Channel Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?91066. S21-0901-Rev. E, 30-Aug-2021 Document Number: 91066 6 For technical questions, contact: hvm@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 Package Information Vishay Siliconix TO-263AB (HIGH VOLTAGE) A (Datum A) 3 A 4 4 L1 B A E c2 H Gauge plane 4 0° to 8° 5 D B Detail A Seating plane H 1 2 C 3 C L L3 L4 Detail “A” Rotated 90° CW scale 8:1 L2 B A1 B A 2 x b2 c 2xb E 0.010 M A M B ± 0.004 M B 2xe Plating 5 b1, b3 Base metal c1 (c) D1 4 5 (b, b2) Lead tip MILLIMETERS DIM. MIN. MAX. View A - A INCHES MIN. 4 E1 Section B - B and C - C Scale: none MILLIMETERS MAX. DIM. MIN. INCHES MAX. MIN. MAX. A 4.06 4.83 0.160 0.190 D1 6.86 - 0.270 - A1 0.00 0.25 0.000 0.010 E 9.65 10.67 0.380 0.420 6.22 - 0.245 - b 0.51 0.99 0.020 0.039 E1 b1 0.51 0.89 0.020 0.035 e b2 1.14 1.78 0.045 0.070 H 14.61 15.88 0.575 0.625 b3 1.14 1.73 0.045 0.068 L 1.78 2.79 0.070 0.110 2.54 BSC 0.100 BSC c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.066 c1 0.38 0.58 0.015 0.023 L2 - 1.78 - 0.070 c2 1.14 1.65 0.045 0.065 L3 D 8.38 9.65 0.330 0.380 L4 0.25 BSC 4.78 5.28 0.010 BSC 0.188 0.208 ECN: S-82110-Rev. A, 15-Sep-08 DWG: 5970 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimensions are shown in millimeters (inches). 3. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm (0.005") per side. These dimensions are measured at the outmost extremes of the plastic body at datum A. 4. Thermal PAD contour optional within dimension E, L1, D1 and E1. 5. Dimension b1 and c1 apply to base metal only. 6. Datum A and B to be determined at datum plane H. 7. Outline conforms to JEDEC outline to TO-263AB. Document Number: 91364 Revision: 15-Sep-08 www.vishay.com 1 Package Information Vishay Siliconix I2PAK (TO-262) (HIGH VOLTAGE) A (Datum A) E B c2 A E A L1 Seating plane D1 D C L2 C B B L A c 3 x b2 E1 A1 3xb Section A - A Base metal 2xe b1, b3 Plating 0.010 M A M B c1 c (b, b2) Lead tip Section B - B and C - C Scale: None MILLIMETERS INCHES MILLIMETERS INCHES DIM. MIN. MAX. MIN. MAX. DIM. MIN. MAX. MIN. MAX. A 4.06 4.83 0.160 0.190 D 8.38 9.65 0.330 0.380 A1 2.03 3.02 0.080 0.119 D1 6.86 - 0.270 - b 0.51 0.99 0.020 0.039 E 9.65 10.67 0.380 0.420 b1 0.51 0.89 0.020 0.035 E1 6.22 - 0.245 - b2 1.14 1.78 0.045 0.070 e b3 1.14 1.73 0.045 0.068 L 13.46 14.10 0.530 0.555 c 0.38 0.74 0.015 0.029 L1 - 1.65 - 0.065 c1 0.38 0.58 0.015 0.023 L2 3.56 3.71 0.140 0.146 c2 1.14 1.65 0.045 0.065 2.54 BSC 0.100 BSC ECN: S-82442-Rev. A, 27-Oct-08 DWG: 5977 Notes 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Dimension D and E do not include mold flash. Mold flash shall not exceed 0.127 mm per side. These dimensions are measured at the outmost extremes of the plastic body. 3. Thermal pad contour optional within dimension E, L1, D1, and E1. 4. Dimension b1 and c1 apply to base metal only. Document Number: 91367 Revision: 27-Oct-08 www.vishay.com 1 AN826 Vishay Siliconix RECOMMENDED MINIMUM PADS FOR D2PAK: 3-Lead 0.420 0.355 0.635 (16.129) (9.017) (10.668) 0.145 (3.683) 0.135 (3.429) 0.200 0.050 (5.080) (1.257) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Document Number: 73397 11-Apr-05 www.vishay.com 1 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. 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