IRFR430A, IRFU430A, SiHFR430A, SiHFU430A
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Power MOSFET
FEATURES
D
DPAK
(TO-252)
• Low gate charge Qg results in simple drive
requirement
IPAK
(TO-251)
• Improved gate, avalanche, and dynamic
dV/dt ruggedness
D
D
G
G
S
G
• Fully
characterized
capacitance
avalanche voltage and current
D S
• Effective Coss specified
S
• Material categorization: for definitions of compliance
please see www.vishay.com/doc?99912
N-Channel MOSFET
PRODUCT SUMMARY
APPLICATIONS
VDS (V)
500
RDS(on) (Ω)
Available
and
VGS = 10 V
• Switch mode power supply (SMPS)
1.7
Qg (Max.) (nC)
24
Qgs (nC)
6.5
Qgd (nC)
• Uninterruptible power supply
• High speed power switching
13
Configuration
Single
ORDERING INFORMATION
Package
DPAK (TO-252)
DPAK (TO-252)
DPAK (TO-252)
DPAK (TO-252)
IPAK (TO-251)
Lead (Pb)-free and
halogen-free
SiHFR430A-GE3
SiHFR430ATR-GE3 a
SiHFR430ATRL-GE3 a
SiHFR430ATRR-GE3 a
SiHFU430A-GE3
IRFR430APbF
IRFR430ATRPbFa
IRFR430ATRLPbFa
-
IRFU430APbF
Lead (Pb)-free
Note
a. See device orientation
ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
LIMIT
Drain-source voltage
VDS
500
Gate-source voltage
VGS
± 30
VGS at 10 V
Continuous drain current
TC = 25 °C
TC = 100 °C
Pulsed drain current a
ID
IDM
Linear derating factor
UNIT
V
5.0
3.2
A
20
0.91
W/°C
Single pulse avalanche energy b
EAS
130
mJ
Repetitive avalanche current a
IAR
5.0
A
Repetitive avalanche energy a
EAR
11
mJ
PD
110
W
dV/dt
3.0
V/ns
TJ, Tstg
-55 to +150
Maximum power dissipation
Peak diode recovery dV/dt
TC = 25 °C
c
Operating junction and storage temperature range
Soldering recommendations (peak temperature) d
For 10 s
300
°C
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Starting TJ = 25 °C, L = 11 mH, Rg = 25 Ω, IAS = 5.0 A (see fig. 12)
c. ISD ≤ 5.0 A, dI/dt ≤ 320 A/μs, VDD ≤ VDS, TJ ≤ 150 °C
d. 1.6 mm from case
S21-0373-Rev. E, 19-Apr-2021
Document Number: 91276
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THERMAL RESISTANCE RATINGS
PARAMETER
SYMBOL
TYP.
MAX.
Maximum junction-to-ambient
RthJA
-
62
Case-to-sink, flat, greased surface
RthCS
0.50
-
Maximum junction-to-case (drain)
RthJC
-
1.1
UNIT
°C/W
SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)
PARAMETER
SYMBOL
TEST CONDITIONS
MIN.
TYP.
MAX.
UNIT
VDS
VGS = 0 V, ID = 250 μA
500
-
-
V
ΔVDS/TJ
Reference to 25 °C, ID = 1 mA
-
0.60
-
V/°C
Static
Drain-source breakdown voltage
VDS temperature coefficient
Gate-source threshold voltage
VGS(th)
VDS = VGS, ID = 250 μA
2.0
-
4.5
V
Gate-source leakage
IGSS
VGS = ± 30 V
-
-
± 100
nA
Zero gate voltage drain current
IDSS
VDS = 500 V, VGS = 0 V
-
-
25
VDS = 400 V, VGS = 0 V, TJ = 125 °C
-
-
250
Drain-source on-state resistance
Forward transconductance
RDS(on)
gfs
ID = 3.0 Ab
VGS = 10 V
VDS = 50 V, ID = 3.0 A
μA
-
-
1.7
Ω
2.3
-
-
S
-
490
-
Dynamic
Input capacitance
Ciss
Output capacitance
Coss
Reverse transfer capacitance
Crss
Output capacitance
Coss
Effective output capacitance
VGS = 0 V,
VDS = 25 V,
f = 1.0 MHz, see fig. 5
VDS = 1.0 V, f = 1.0 MHz
VGS = 10 V
Coss eff.
Total gate charge
Qg
Gate-source charge
Qgs
VGS = 10 V
-
75
-
-
4.5
-
-
750
-
VDS = 400 V, f = 1.0 MHz
-
25
-
VDS = 0 V to 400 Vc
-
51
-
-
-
24
-
-
6.5
ID = 5.0 A, VDS = 400 V,
see fig. 6 and 13b
Gate-drain charge
Qgd
-
-
13
Turn-on delay time
td(on)
-
8.7
-
Rise time
Turn-off delay time
Fall time
tr
td(off)
VDD = 250 V, ID = 5.0 A,
Rg = 15 Ω, RD = 50 Ω, see fig. 10b
tf
pF
pF
nC
-
27
-
-
17
-
-
16
-
-
-
5.0
-
-
20
-
-
1.5
-
410
620
ns
-
1.4
2.1
μC
ns
Drain-Source Body Diode Characteristics
Continuous source-drain diode current
IS
Pulsed diode forward current a
ISM
Body diode voltage
VSD
Body diode reverse recovery time
trr
Body diode reverse recovery charge
Qrr
Forward turn-on time
ton
MOSFET symbol
showing the
integral reverse
p - n junction diode
D
A
G
S
TJ = 25 °C, IS = 5.0 A, VGS = 0 Vb
TJ = 25 °C, IF = 5.0 A, dI/dt = 100 A/μsb
V
Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Pulse width ≤ 300 μs; duty cycle ≤ 2 %
c. Coss eff. is a fixed capacitance that gives the same charging time as Coss while VDS is rising from 0 to 80 % VDS
S21-0373-Rev. E, 19-Apr-2021
Document Number: 91276
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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)
100
100.00
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
10
ID, Drain-to-Source Current (Α )
ID, Drain-to-Source Current (A)
TOP
1
0.1
4.5V
0.01
10.00
T J = 150°C
1.00
T J = 25°C
0.10
20μs PULSE WIDTH
Tj = 25°C
VDS = 100V
20μs PULSE WIDTH
0.01
0.001
0.1
1
10
100
4.0
6.0
Fig. 1 - Typical Output Characteristics
100
3.0
VGS
15V
10V
8.0V
7.0V
6.0V
5.5V
5.0V
BOTTOM 4.5V
14.0
16.0
I D = 5.0A
4.5V
0.1
20μs PULSE WIDTH
Tj = 150°C
0.01
1
10
VDS, Drain-to-Source Voltage (V)
Fig. 1 - Typical Output Characteristics
S21-0373-Rev. E, 19-Apr-2021
100
2.0
(Normalized)
RDS(on) , Drain-to-Source On Resistance
ID, Drain-to-Source Current (A)
12.0
2.5
1
0.1
10.0
Fig. 2 - Typical Transfer Characteristics
TOP
10
8.0
VGS, Gate-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
1.5
1.0
0.5
V GS = 10V
0.0
-60
-40
-20
0
20
40
60
TJ , Junction Temperature
80
100
120
140
160
( ° C)
Fig. 3 - Normalized On-Resistance vs. Temperature
Document Number: 91276
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10000
100
VGS = 0V,
f = 1 MHZ
Ciss = Cgs + Cgd, Cds SHORTED
Crss = Cgd
Coss = Cds + Cgd
1000
Ciss
I SD , Reverse Drain Current (A)
C, Capacitance(pF)
Vishay Siliconix
100
Coss
10
Crss
10
TJ = 25 ° C
TJ = 150 ° C
1
1
1
10
100
V GS= 0 V
1000
0.1
0.2
VDS, Drain-to-Source Voltage (V)
Fig. 4 - Typical Capacitance vs. Drain-to-Source Voltage
1.4
OPERATION IN THIS AREA
LIMITED BY R DS(on)
VDS = 400V
VDS = 250V
VDS = 100V
10
VGS , Gate-to-Source Voltage (V)
1.1
100
I D = 5.0A
7
5
2
10
100μsec
1
1msec
0.1
0
0
0.8
Fig. 6 - Typical Source-Drain Diode Forward Voltage
ID , Drain-to-Source Current (A)
12
0.5
V SD,Source-to-Drain Voltage (V)
4
8
12
16
20
QG , Total Gate Charge (nC)
Fig. 5 - Typical Gate Charge vs. Gate-to-Source Voltage
S21-0373-Rev. E, 19-Apr-2021
Tc = 25°C
Tj = 150°C
Single Pulse
10
10msec
100
1000
10000
VDS , Drain-toSource Voltage (V)
Fig. 7 - Maximum Safe Operating Area
Document Number: 91276
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Vishay Siliconix
5.5
RD
VDS
VGS
ID , Drain Current (A)
4.4
D.U.T.
Rg
+
- VDD
10 V
3.3
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %
2.2
Fig. 10a - Switching Time Test Circuit
1.1
90 %
VDS
0.0
25
50
75
100
125
150
10 %
VGS
( ° C)
TC , Case Temperature
td(on)
Fig. 8 - Maximum Drain Current vs. Case Temperature
td(off) tf
tr
Fig. 10b - Switching Time Waveforms
(Z thJC )
10
1
Thermal Response
D = 0.50
0.20
P DM
0.10
0.1
0.05
t1
SINGLE PULSE
(THERMAL RESPONSE)
0.02
0.01
t2
Notes:
1. Duty factor D =
2. Peak T
0.01
0.00001
0.0001
0.001
0.01
t1/ t 2
J = P DM x Z thJC
+TC
0.1
1
t1, Rectangular Pulse Duration (sec)
Fig. 9 - Maximum Effective Transient Thermal Impedance, Junction-to-Case
VDS
15 V
tp
L
VDS
D.U.T
Rg
IAS
20 V
tp
Driver
+
A
- VDD
IAS
0.01 Ω
Fig. 12a - Unclamped Inductive Test Circuit
S21-0373-Rev. E, 19-Apr-2021
Fig. 12b - Unclamped Inductive Waveforms
Document Number: 91276
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5.0
250
EAS , Single Pulse Avalanche Energy (mJ)
200
TOP
2.2A
3.2A
BOTTOM
5.0A
VGS(th) Gate threshold Voltage (V)
ID
150
100
50
4.5
ID = 250μA
4.0
3.5
3.0
2.5
-75
0
25
50
75
100
Starting Tj, Junction Temperature
125
-50
-25
0
25
50
75
100 125
150
150
T J , Temperature ( °C )
( ° C)
Fig. 12c - Maximum Avalanche Energy vs. Drain Current
Fig. 12d - Threshold Voltage vs. Temperature
Current regulator
Same type as D.U.T.
50 kΩ
QG
VGS
12 V
0.2 µF
0.3 µF
QGS
QGD
+
D.U.T.
VG
-
VDS
VGS
3 mA
Charge
IG
ID
Current sampling resistors
Fig. 13a - Basic Gate Charge Waveform
S21-0373-Rev. E, 19-Apr-2021
Fig. 13b - Gate Charge Test Circuit
Document Number: 91276
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Peak Diode Recovery dV/dt Test Circuit
+
D.U.T.
Circuit layout considerations
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
+
+
-
-
Rg
•
•
•
•
dV/dt controlled by Rg
Driver same type as D.U.T.
ISD controlled by duty factor “D”
D.U.T. - device under test
+
-
VDD
Driver gate drive
P.W.
Period
D=
P.W.
Period
VGS = 10 Va
D.U.T. lSD waveform
Reverse
recovery
current
Body diode forward
current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
Re-applied
voltage
Inductor current
VDD
Body diode forward drop
Ripple ≤ 5 %
ISD
Note
a. VGS = 5 V for logic level devices
Fig. 10 - For N-Channel
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91276.
S21-0373-Rev. E, 19-Apr-2021
Document Number: 91276
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Package Information
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TO-252AA Case Outline
VERSION 1: FACILITY CODE = Y
E
A
C2
H
D
D1
L3
b3
e
b2
e1
L
gage plane height (0.5 mm)
L4
b
L5
E1
C
A1
MILLIMETERS
DIM.
MIN.
A
2.18
MAX.
2.38
A1
-
0.127
b
0.64
0.88
b2
0.76
1.14
b3
4.95
5.46
C
0.46
0.61
C2
0.46
0.89
D
5.97
6.22
D1
4.10
-
E
6.35
6.73
E1
4.32
-
H
9.40
10.41
e
2.28 BSC
e1
4.56 BSC
L
1.40
1.78
L3
0.89
1.27
L4
-
1.02
L5
1.01
1.52
Note
• Dimension L3 is for reference only
Revision: 03-Oct-2022
Document Number: 71197
1
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
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VERSION 2: FACILITY CODE = N
E
e
A
b3
E1
E1/2
c2
θ
e
L4
L5
L6
H
D
L3
D1
θ
0.25
(3°)
DETAIL "B"
C A B
(3°)
DETAIL "B"
A1
C
L
(L1)
b1
SEATING
C
PLANE
θ
L2
GAUGE
PLANE
H
C
(b)
c1
3x b
2x e
c
2x b2
MILLIMETERS
MILLIMETERS
DIM.
A
MIN.
2.18
MAX.
DIM.
MIN.
2.39
L
1.50
A1
-
0.13
L1
b
0.65
0.89
L2
MAX.
1.78
2.74 ref.
0.51 BSC
b1
0.64
0.79
L3
b2
0.76
1.13
L4
-
1.02
b3
4.95
5.46
L5
1.14
1.49
c
0.46
0.61
L6
0.65
0.85
c1
0.41
0.56
0°
10°
1
0°
15°
2
25°
35°
c2
0.46
0.60
D
5.97
6.22
D1
5.21
-
E
6.35
6.73
E1
4.32
e
H
2.29 BSC
9.94
0.89
1.27
Notes
• Dimensioning and tolerance confirm to ASME Y14.5M-1994
• All dimensions are in millimeters. Angles are in degrees
• Heat sink side flash is max. 0.8 mm
• Radius on terminal is optional
10.34
ECN: E22-0399-Rev. R, 03-Oct-2022
DWG: 5347
Revision: 03-Oct-2022
Document Number: 71197
2
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Package Information
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Vishay Siliconix
Case Outline for TO-251AA (High Voltage)
OPTION 1:
4
E1
3
E
Thermal PAD
4
b4
θ2
4
A
0.010 0.25 M C A B
L2 4
c2
A
θ1
B
D
D1
A
C
3
Seating
plane
5
C
L1 L3
(Datum A)
C
L
B
B
A
A1
3 x b2
View A - A
2xe
c
3xb
0.010 0.25 M C A B
Plating
5
b1, b3
Base
metal
Lead tip
5
c1
(c)
(b, b2)
Section B - B and C - C
MILLIMETERS
INCHES
MILLIMETERS
INCHES
DIM.
MIN.
MAX.
MIN.
MAX.
DIM.
MIN.
MAX.
MIN.
A
2.18
2.39
0.086
0.094
D1
5.21
-
0.205
MAX.
-
A1
0.89
1.14
0.035
0.045
E
6.35
6.73
0.250
0.265
4.32
-
0.170
-
b
0.64
0.89
0.025
0.035
E1
b1
0.65
0.79
0.026
0.031
e
b2
0.76
1.14
0.030
0.045
L
8.89
9.65
0.350
0.380
b3
0.76
1.04
0.030
0.041
L1
1.91
2.29
0.075
0.090
b4
4.95
5.46
0.195
0.215
L2
0.89
1.27
0.035
0.050
c
0.46
0.61
0.018
0.024
L3
1.14
1.52
0.045
0.060
c1
0.41
0.56
0.016
0.022
1
0'
15'
0'
15'
c2
0.46
0.86
0.018
0.034
2
25'
35'
25'
35'
D
5.97
6.22
0.235
0.245
2.29 BSC
2.29 BSC
ECN: E21-0682-Rev. C, 27-Dec-2021
DWG: 5968
Notes
• Dimensioning and tolerancing per ASME Y14.5M-1994
• Dimension are shown in inches and millimeters
• Dimension D and E do not include mold flash. Mold flash shall not exceed 0.13 mm (0.005") per side. These dimensions are measured at
the outermost extremes of the plastic body
• Thermal pad contour optional with dimensions b4, L2, E1 and D1
• Lead dimension uncontrolled in L3
• Dimension b1, b3 and c1 apply to base metal only
• Outline conforms to JEDEC® outline TO-251AA
Revision: 27-Dec-2021
Document Number: 91362
1
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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Package Information
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OPTION 2: FACILITY CODE = N
E
A
L2
b4
c2
E1
D2
θ1
CL
L4
θ1
D
D1
Ø 1.00
x 0.10 deep
C
B
B
L
L3
L1
C
b2
A1
b
b1, b3
c
c
e
c1
θ2
Third angle
projection
b, b2
Section “B-B” and “C-C”
DIM.
MIN.
NOM.
MAX.
DIM.
MIN.
NOM.
A
2.180
2.285
2.390
D2
5.380
-
MAX.
-
A1
0.890
1.015
1.140
E
6.350
6.540
6.730
4.32
-
-
b
0.640
0.765
0.890
E1
b1
0.640
0.715
0.790
e
b2
0.760
0.950
1.140
L
8.890
9.270
9.650
b3
0.760
0.900
1.040
L1
1.910
2.100
2.290
b4
4.950
5.205
5.460
L2
0.890
1.080
1.270
c
0.460
-
0.610
L3
1.140
1.330
1.520
c1
0.410
-
0.560
L4
1.300
1.400
1.500
c2
0.460
-
0.610
1
0°
7.5°
15°
D
5.970
6.095
6.220
2
4°
-
-
D1
4.300
-
-
2.29 BSC
ECN: E21-0682-Rev. C, 27-Dec-2021
DWG: 5968
Notes
• Dimensioning and tolerancing per ASME Y14.5M-1994
• All dimension are in millimeters, angles are in degrees
• Heat sink side flash is max. 0.8 mm
Revision: 27-Dec-2021
Document Number: 91362
2
For technical questions, contact: hvmos.techsupport@vishay.com
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
Application Note 826
Vishay Siliconix
RECOMMENDED MINIMUM PADS FOR DPAK (TO-252)
0.224
0.243
0.087
(2.202)
0.090
(2.286)
(10.668)
0.420
(6.180)
(5.690)
0.180
0.055
(4.572)
(1.397)
Recommended Minimum Pads
Dimensions in Inches/(mm)
Return to Index
Return to Index
APPLICATION NOTE
Document Number: 72594
Revision: 21-Jan-08
www.vishay.com
3
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