SI2312BDS-T1-E3

Si2312BDS Vishay Siliconix N-Channel 20 V (D-S) MOSFET FEATURES PRODUCT SUMMARY VDS (V) 20 RDS(on) (Ω) ID (A) 0.031 at VGS = 4.5 V 5.0 0.037 at VGS = 2.5 V 4.6 0.047 at VGS = 1.8 V 4.1 • Halogen-free According to IEC 61249-2-21 Definition • TrenchFET® Power MOSFET • 100 % Rg Tested • Compliant to RoHS Directive 2002/95/EC Qg (Typ.) 7.5 TO-236 (SOT-23) G 1 3 S D 2 Top View Si2312BDS (M2)* * Marking Code Ordering Information: Si2312BDS-T1-E3 (Lead (Pb)-free) Si2312BDS-T1-GE3 (Lead (Pb)-free and Halogen-free) ABSOLUTE MAXIMUM RATINGS TA = 25 °C, unless otherwise noted Parameter Symbol 5s Steady State Drain-Source Voltage VDS 20 Gate-Source Voltage VGS ±8 TA = 25 °C Continuous Drain Current (TJ = 150 °C)a TA = 70 °C Pulsed Drain Currentb ID L = 0.1 mH Single Avalanche Energy a 5.0 3.9 3.1 Power Dissipationa TA = 25 °C TA = 70 °C 15 IAS 13 EAS 8.45 IS Continuous Source Current (Diode Conduction) PD A mJ 1.0 0.63 1.25 0.75 0.80 0.48 TJ, Tstg Operating Junction and Storage Temperature Range V 4.0 IDM Avalanche Currentb Unit - 55 to 150 A W °C THERMAL RESISTANCE RATINGS Parameter Maximum Junction-to-Ambienta Maximum Junction-to-Foot Symbol t≤5s Steady State Steady State RthJA RthJF Typical Maximum 80 100 120 166 50 60 Unit °C/W Notes: a. Surface mounted on 1" x 1" FR4 board. b. Pulse width limited by maximum junction temperature. Document Number: 73235 S10-0791-Rev. D, 05-Apr-10 www.vishay.com 1 Si2312BDS Vishay Siliconix SPECIFICATIONS TA = 25 °C, unless otherwise noted Limits Parameter Symbol Test Conditions Min. Typ. Max. Unit Static VDS VGS = 0 V, ID = 250 µA 20 VGS(th) VDS = VGS, ID = 250 µA 0.45 Gate-Body Leakage IGSS VDS = 0 V, VGS = ± 8 V Zero Gate Voltage Drain Current IDSS On-State Drain Currenta ID(on) Drain-Source Breakdown Voltage Gate-Threshold Voltage Drain-Source On-Resistancea Forward Transconductancea Diode Forward Voltage ± 100 VDS = 20 V, VGS = 0 V 1 VDS = 20 V, VGS = 0 V, TJ = 70 °C 75 VDS ≥ 10 V, VGS = 4.5 V RDS(on) V 0.85 nA µA 15 A VGS = 4.5 V, ID = 5.0 A 0.025 0.031 VGS = 2.5 V, ID = 4.6 A 0.030 0.037 0.047 VGS = 1.8 V, ID = 4.1 A 0.036 gfs VDS = 15 V, ID = 5.0 A 30 VSD IS = 1.0 A, VGS = 0 V 0.8 1.2 7.5 12 Ω S V Dynamicb Total Gate Charge Qg Gate-Source Charge Qgs Gate-Drain Charge Qgd Gate Resistance Rg VDS = 10 V, VGS = 4.5 V, ID = 5.0 A 1.4 nC 1.2 f = 1.0 MHz 1.1 2.2 3.3 9 15 Ω Switching Turn-On Delay Time td(on) Rise Time tr Turn-Off Delay Time td(off) VDD = 10 V, RL = 10 Ω ID ≅ 1.0 A, VGEN = 4.5 V, Rg = 6 Ω 30 45 35 55 Fall Time tf 10 15 Source-Drain Reverse Recovery Time trr 13 25 Body Diode Reverse Recovery Charge Qrr 4.5 7 IF = 1.0 A, dI/dt = 100 A/µs ns nC Notes: a. Pulse test: Pulse width ≤ 300 µs, duty cycle ≤ 2 %. b. Guaranteed by design, not subject to production testing. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 15 15 VGS = 4.5 V thru 2 V 1.5 V 12 I D - Drain Current (A) I D - Drain Current (A) 12 9 6 9 6 TC = 125 °C 3 3 25 °C 1V - 55 °C 0 0 0 1 2 3 VDS - Drain-to-Source Voltage (V) Output Characteristics www.vishay.com 2 4 0 0.25 0.5 0.75 1.0 1.25 1.5 VGS - Gate-to-Source Voltage (V) 1.75 2.0 Transfer Characteristics Document Number: 73235 S10-0791-Rev. D, 05-Apr-10 Si2312BDS Vishay Siliconix 0.06 1200 0.05 1000 0.04 VGS = 1.8 V 0.03 Ciss C - Capacitance (pF) R DS(on) - On-Resistance (Ω) TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted VGS = 2.5 V 0.02 800 600 400 VGS = 4.5 V Coss 0.01 200 0.00 0 Crss 0 3 6 9 12 15 0 4 ID - Drain Current (A) 8 16 20 VDS - Drain-to-Source Voltage (V) Capacitance On-Resistance vs. Drain Current 1.6 5 VGS = 4.5 V ID = 5.0 A VDS = 10 V ID = 5.0 A 1.4 3 2 (Normalized) 4 R DS(on) - On-Resistance VGS - Gate-to-Source Voltage (V) 12 1.2 1.0 0.8 1 0.6 - 50 0 0 1 2 3 4 5 6 7 8 - 25 0 25 50 75 100 125 Qg - Total Gate Charge (nC) TJ - Junction Temperature (°C) Gate Charge On-Resistance vs. Junction Temperature 150 0.20 20 10 RDS(on) - On-Resistance (Ω) I S - Source Current (A) TJ = 150 °C 1 TJ = 25 °C 0.1 0.01 0.001 0.0 ID = 5.0 A 0.15 0.10 0.05 0.00 0.2 0.4 0.6 0.8 1.0 VSD - Source-to-Drain Voltage (V) Source-Drain Diode Forward Voltage Document Number: 73235 S10-0791-Rev. D, 05-Apr-10 1.2 0 1 2 3 4 5 6 7 8 VGS - Gate-to-Source Voltage (V) On-Resistance vs. Gate-to-Source Voltage www.vishay.com 3 Si2312BDS Vishay Siliconix TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted 0.3 8 0.2 7 6 ID = 250 µA 0.0 Power (W) VGS(th) Variance (V) 0.1 - 0.1 5 TA = 25 °C 4 - 0.2 3 - 0.3 2 - 0.4 1 - 0.5 - 50 - 25 0 25 50 75 100 TJ - Temperature (°C) 125 150 0 0.01 1 0.1 10 100 600 Time (s) Threshold Voltage Single Pulse Power 100 Limited by R DS(on)* 10 µs I D - Drain Current (A) 10 100 µs 1 1 ms 10 ms 100 ms 0.1 TA = 25 °C Single Pulse 1s 10 s 100 s, DC Only valid when VGS = or > 1.8 V 0.01 0.1 1 10 100 VDS - Drain-to-Source Voltage (V) * VGS > minimum V GS at which R DS(on) is specified Safe Operating Area 2 Normalized Effective Transient Thermal Impedance 1 Duty Cycle = 0.5 0.2 Notes: 0.1 PDM 0.1 0.05 t1 t2 1. Duty Cycle, D = 0.02 t1 t2 2. Per Unit Base = R thJA = 166 °C/W 3. T JM - TA = PDMZthJA(t) Single Pulse 0.01 10- 4 10- 3 4. Surface Mounted 10- 2 10- 1 1 Square Wave Pulse Duration (s) 10 100 600 Normalized Thermal Transient Impedance, Junction-to-Ambient Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?73235. www.vishay.com 4 Document Number: 73235 S10-0791-Rev. D, 05-Apr-10 Package Information Vishay Siliconix SOT-23 (TO-236): 3-LEAD b 3 E1 1 E 2 e S e1 D 0.10 mm C 0.004" A2 A C q Gauge Plane Seating Plane Seating Plane C A1 Dim 0.25 mm L L1 MILLIMETERS Min INCHES Max Min Max 0.044 A 0.89 1.12 0.035 A1 0.01 0.10 0.0004 0.004 A2 0.88 1.02 0.0346 0.040 b 0.35 0.50 0.014 0.020 c 0.085 0.18 0.003 0.007 D 2.80 3.04 0.110 0.120 E 2.10 2.64 0.083 0.104 E1 1.20 1.40 0.047 e 0.95 BSC e1 L 1.90 BSC 0.40 L1 q 0.0748 Ref 0.60 0.016 0.64 Ref S 0.024 0.025 Ref 0.50 Ref 3° 0.055 0.0374 Ref 0.020 Ref 8° 3° 8° ECN: S-03946-Rev. K, 09-Jul-01 DWG: 5479 Document Number: 71196 09-Jul-01 www.vishay.com 1 AN807 Vishay Siliconix Mounting LITTLE FOOTR SOT-23 Power MOSFETs Wharton McDaniel Surface-mounted LITTLE FOOT power MOSFETs use integrated circuit and small-signal packages which have been been modified to provide the heat transfer capabilities required by power devices. Leadframe materials and design, molding compounds, and die attach materials have been changed, while the footprint of the packages remains the same. See Application Note 826, Recommended Minimum Pad Patterns With Outline Drawing Access for Vishay Siliconix MOSFETs, (http://www.vishay.com/doc?72286), for the basis of the pad design for a LITTLE FOOT SOT-23 power MOSFET footprint . In converting this footprint to the pad set for a power device, designers must make two connections: an electrical connection and a thermal connection, to draw heat away from the package. ambient air. This pattern uses all the available area underneath the body for this purpose. 0.114 2.9 0.081 2.05 0.150 3.8 0.059 1.5 0.0394 1.0 0.037 0.95 FIGURE 1. Footprint With Copper Spreading The electrical connections for the SOT-23 are very simple. Pin 1 is the gate, pin 2 is the source, and pin 3 is the drain. As in the other LITTLE FOOT packages, the drain pin serves the additional function of providing the thermal connection from the package to the PC board. The total cross section of a copper trace connected to the drain may be adequate to carry the current required for the application, but it may be inadequate thermally. Also, heat spreads in a circular fashion from the heat source. In this case the drain pin is the heat source when looking at heat spread on the PC board. Figure 1 shows the footprint with copper spreading for the SOT-23 package. This pattern shows the starting point for utilizing the board area available for the heat spreading copper. To create this pattern, a plane of copper overlies the drain pin and provides planar copper to draw heat from the drain lead and start the process of spreading the heat so it can be dissipated into the Document Number: 70739 26-Nov-03 Since surface-mounted packages are small, and reflow soldering is the most common way in which these are affixed to the PC board, “thermal” connections from the planar copper to the pads have not been used. Even if additional planar copper area is used, there should be no problems in the soldering process. The actual solder connections are defined by the solder mask openings. By combining the basic footprint with the copper plane on the drain pins, the solder mask generation occurs automatically. A final item to keep in mind is the width of the power traces. The absolute minimum power trace width must be determined by the amount of current it has to carry. For thermal reasons, this minimum width should be at least 0.020 inches. The use of wide traces connected to the drain plane provides a low-impedance path for heat to move away from the device. www.vishay.com 1 Application Note 826 Vishay Siliconix 0.049 (1.245) 0.029 0.022 (0.559) (0.724) 0.037 (0.950) (2.692) 0.106 RECOMMENDED MINIMUM PADS FOR SOT-23 0.053 (1.341) 0.097 (2.459) Recommended Minimum Pads Dimensions in Inches/(mm) Return to Index Return to Index APPLICATION NOTE Document Number: 72609 Revision: 21-Jan-08 www.vishay.com 25 Legal Disclaimer Notice www.vishay.com Vishay Disclaimer  ALL PRODUCT, PRODUCT SPECIFICATIONS AND DATA ARE SUBJECT TO CHANGE WITHOUT NOTICE TO IMPROVE RELIABILITY, FUNCTION OR DESIGN OR OTHERWISE. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, “Vishay”), disclaim any and all liability for any errors, inaccuracies or incompleteness contained in any datasheet or in any other disclosure relating to any product. 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Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. Product names and markings noted herein may be trademarks of their respective owners. © 2017 VISHAY INTERTECHNOLOGY, INC. ALL RIGHTS RESERVED Revision: 08-Feb-17 1 Document Number: 91000