VESD12A1C-HD1-GS08

VESD12A1C-HD1 www.vishay.com Vishay Semiconductors ESD Protection Diode in LLP1006-2L FEATURES • Ultra compact LLP1006-2L package • Low package height < 0.4 mm • 1-line ESD protection 1 2 • Low leakage current < 0.01 μA 20856 • Low load capacitance CD = 12.5 pF (VR = 6 V; f = 1 MHz) 20855 • ESD immunity acc. IEC 61000-4-2 ± 30 kV contact discharge ± 30 kV air discharge MARKING (example only) • High surge current acc. IEC 61000-4-5 IPP > 4 A XY • Soldering can be checked by standard vision inspection. No X-ray necessary 21121 Bar = cathode marking X = date code Y = type code (see table below) • Pin plating NiPdAu (e4) no whisker growth • PATENT(S): www.vishay.com/patents DESIGN SUPPORT TOOLS • Material categorization: for definitions of compliance please see www.vishay.com/doc?99912 click logo to get started Models Available ORDERING INFORMATION ORDERING CODE TAPED UNITS PER REEL (8 mm TAPE ON 7" REEL) MINIMUM ORDER QUANTITY VESD12A1C-HD1-GS08 8000 8000 DEVICE NAME VESD12A1C-HD1 PACKAGE DATA DEVICE NAME PACKAGE NAME TYPE CODE WEIGHT MOLDING COMPOUND FLAMMABILITY RATING VESD12A1C-HD1 LLP1006-2L G 0.72 mg UL 94 V-0 MOISTURE SENSITIVITY LEVEL SOLDERING CONDITIONS MSL level 1 Peak temperature max. 260 °C (according J-STD-020) ABSOLUTE MAXIMUM RATINGS VESD12A1C-HD1 PARAMETER TEST CONDITIONS SYMBOL Peak pulse current Acc. IEC 61000-4-5; tp = 8/20 μs; single shot IPPM 4 A Peak pulse power Acc. IEC 61000-4-5; tp = 8/20 μs; single shot PPP 92 W Contact discharge, acc. IEC 61000-4-2; 10 pulses VESD ± 30 kV Air discharge, acc. IEC 61000-4-2; 10 pulses VESD ± 30 kVp TJ -40 to +125 °C TSTG -55 to +150 °C ESD immunity Operating temperature Storage temperature Junction temperature VALUE UNIT PATENT(S): www.vishay.com/patents This Vishay product is protected by one or more United States and international patents. Rev. 1.9, 03-Jan-2019 Document Number: 81799 1 For technical questions, contact: ESDprotection@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VESD12A1C-HD1 www.vishay.com Vishay Semiconductors BiAs-MODE (Bidirectional asymmetrical protection mode) With the VESD12A1C-HD1 one signal- or data-lines (L1) can be protected against voltage transients. With pin 1 connected to ground and pin 2 connected to a signal- or data-line which has to be protected. As long as the voltage level on the data- or signal-line is between 0 V (ground level) and the specified maximum reverse working voltage (VRWM) the protection diode between data line and ground offers a high isolation to the ground line. The protection device behaves like an open switch. As soon as any positive transient voltage signal exceeds the break through voltage level of the protection diode, the diode becomes conductive and shorts the transient current to ground. Now the protection device behaves like a closed switch. The clamping voltage (VC) is defined by the breakthrough voltage (VBR) level plus the voltage drop at the series impedance (resistance and inductance) of the protection device. Any negative transient signal will be clamped accordingly. The negative transient current is flowing in the forward direction of the protection diode. The low forward voltage (VF) clamps the negative transient close to the ground level. Due to the different clamping levels in forward and reverse direction the VESD12A1C-HD1 clamping behavior is bidirectional and asymmetrical (BiAs). 2 L1 1 BiAs Ground 20925 ELECTRICAL CHARACTERISTICS VESD12A1C-HD1 BiAs mode (between pin 1 and pin 2) (Tamb = 25 °C, unless otherwise specified) PARAMETER TEST CONDITIONS/REMARKS SYMBOL MIN. TYP. Number of lines which can be protected Nchannel - Max. reverse working voltage VRWM - Reverse voltage At IR = 0.1 μA VR 12 - - V Reverse current At VRWM = 12 V IR - < 0.01 0.1 μA At IR = 1 mA VBR 13.5 14 16 V At IPP = 1 A VC - 15.8 17 V At IPP = IPPM = 4 A VC - 20 23 V Protection paths Reverse stand-off voltage Reverse breakdown voltage Reverse clamping voltage Forward clamping voltage Capacitance Rev. 1.9, 03-Jan-2019 MAX. UNIT - 1 lines - 12 V At IPP = 0.2 A VF 0.9 1.2 V At IPP = 1 A VF 1.1 1.5 V At IPP = IPPM = 4 A VF 1.7 2.1 V At VR = 0 V; f = 1 MHz CD - 30 36 pF At VR = 6 V; f = 1 MHz CD - 12.5 - pF Document Number: 81799 2 For technical questions, contact: ESDprotection@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VESD12A1C-HD1 www.vishay.com Vishay Semiconductors TYPICAL CHARACTERISTICS (Tamb = 25 °C, unless otherwise specified) Axis Title 100 10000 120 Rise time = 0.7 ns to 1 ns 100 10 1000 60 53 40 1 IF (mA) 1st line 2nd line 2nd line IESD (%) 80 0.1 100 27 0.01 20 0 10 -10 0 0.001 10 20 30 40 50 60 70 80 90 100 0.5 t (ns) 2nd line 20557 0.6 0.7 Fig. 1 - ESD Discharge Current Wave Form acc. IEC 61000-4-2 (330 /150 pF) 0.8 0.9 VF (V) 20679 Fig. 4 - Typical Forward Current IF vs. Forward Voltage VF Axis Title 10000 100 16 8 µs to 100 % 14 12 80 20 µs to 50 % 40 VR (V) 60 1st line 2nd line 2nd line IPPM (%) 1000 10 8 6 100 4 20 2 0 10 0 10 20 30 0 0.01 40 t (µs) 2nd line 20548 Fig. 2 - 8/20 μs Peak Pulse Current Wave Form (acc. IEC 61000-4-5) 0.1 1 10 100 1000 10 000 IR (µA) 20680 Fig. 5 - Typical Reverse Voltage VR vs. Reverse Current IR 35 25 f = 1 MHz Measured acc. IEC 61000-4-5 (8/20 µs - wave form) 30 20 Reverse VF/VC (V) CD (pF) 25 20 15 15 10 10 5 5 Forward 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 20678 VR (V) Fig. 3 - Typical Capacitance CD vs. Reverse Voltage VR Rev. 1.9, 03-Jan-2019 0 20681 1 2 3 4 5 IPP (A) Fig. 6 - Typical Clamping Voltage vs. Peak Pulse Current IPP Document Number: 81799 3 For technical questions, contact: ESDprotection@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VESD12A1C-HD1 www.vishay.com Vishay Semiconductors 60 Acc. IEC 61000-4-2 +8 kV contact discharge Reverse 50 VC-ESD (V) 40 30 20 10 0 -10 -20 -10 0 10 20 30 40 50 60 70 80 90 20683 t (ns) Fig. 7 - Typical Clamping Performance at + 8 kV Contact Discharge (acc. IEC 61000-4-2) 20 Acc. IEC 61000-4-2 -8 kV contact discharge Forward 10 VC-ESD (V) 0 -10 -20 -30 -40 -50 -10 0 10 20 30 40 50 60 70 80 90 t (ns) 20682 Fig. 8 - Typical Clamping Performance at - 8 kV Contact Discharge (acc. IEC 61000-4-2) 200 Acc. IEC 61000-4-2 contact discharge 150 Positive discharge (pin 2 to pin 1) VC-ESD (V) 100 50 VC-ESD 0 -50 Negative discharge (pin 1 to pin 2) -100 -150 0 20684 5 10 15 20 VESD (kV) Fig. 9 - Typical Clamping Voltage at ± ESD Contact Discharge Fig. 10 - (acc. IEC 61000-4-2) Rev. 1.9, 03-Jan-2019 Document Number: 81799 4 For technical questions, contact: ESDprotection@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000 VESD12A1C-HD1 www.vishay.com Vishay Semiconductors 0.25 [0.010] 0.15 [0.006] PACKAGE DIMENSIONS in millimeters (inches): LLP1006-2L 0.65 [0.026] 0.55 [0.022] Orientation identification 0.05 [0.002] 0 [0.000] 0.4 [0.016] 0.33 [0.013] 0.45 [0.018] 0.35 [0.014] 0.125 [0.005] ref. 0.55 [0.022] 0.45 [0.018] 0.3 [0.012] 0.2 [0.008] 1.05 [0.041] 0.95 [0.037] 1 [0.039] Solder resist mask 0.2 [0.008] 0.5 [0.020] 0.6 [0.024] Foot print recommendation: Solder pad 0.5 [0.020] 0.05 [0.002] 0.25 [0.010] Pad Design Patented: ( P US 9.018.537 B2) Document no.: S8-V-3906.04-005 (4) Rev. 7 - Date: 11.May 2016 20812 Unreeling direction LLP1006-2X Orientation identification Top view S8-V-3906.04-017 (4) 02.05.2017 22965 Rev. 1.9, 03-Jan-2019 Pad layout - view from top seen at bottom side Document Number: 81799 5 For technical questions, contact: ESDprotection@vishay.com THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. 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