TB62777FNG,EL

TB62777FNG/FG TOSHIBA Bi-CMOS Integrated Circuit Silicon Monolithic TB62777FNG, TB62777FG 8-Channel Constant-Current LED Driver of the 3.3-V and 5-V Power Supply Voltage Operation The TB62777FNG/FG is comprised of constant-current drivers designed for LEDs and LED panel displays. The regulated current sources are designed to provide a constant current, which is adjustable through one external resistor. The TB62777FNG/FG incorporates eight channels of shift registers, latches, AND gates and constant-current outputs. Fabricated using the Bi-CMOS process, the TB62777FNG/FG is capable of high-speed data transfers. The TB62777FNG/FG is RoHS. TB62777FNG TB62777FG Features • Power supply voltages: VDD = 3.3 V/5 V • Output drive capability and output count: 50 mA × 8 channels • Constant-current output range: 5 to 40 mA • Voltage applied to constant-current output terminals: 0.4 V (min, IOUT = 5 to 40 mA) • Designed for common-anode LEDs • Thermal shutdown (TSD)（min: 150℃） • Power on reset (POR) • Logical input signal voltage level: 3.3-V and 5-V CMOS interfaces (Schmitt trigger input) • Maximum output voltage: 25V • Serial data transfer rate: 25 MHz (max) @cascade connection • Operating temperature range: Topr = −40 to 85°C • Package: SSOP16-P-225-0.65B/ SSOP16-P-225-1.00A • Constant-current accuracy Weight: SSOP16-P-225-0.65B 0.07 g (typ.) SSOP16-P-225-1.00A 0.14 g (typ.) Output Voltage Current accuracy Between Channels Current Accuracy Between ICs Output Current 0.4 V to 4 V ±3% ±6% 15 mA 1 2010-03-08 TB62777FNG/FG Pin Assignment (top view) GND SERIAL-IN CLOCK LATCH VDD R-EXT SERIAL-OUT ENABLE OUT7 OUT6 OUT5 OUT4 OUT0 OUT1 OUT2 OUT3 Block Diagram OUT1 OUT0 R-EXT OUT7 I-REG TSD VDD POR ENABLE Q Q Q ST R D ST R D ST R D GND LATCH D0 SERIAL-IN Q0 Q1 Q7 8-bit shift register D0 to D7 R CLOCK D Q SERIAL-OUT CK R Truth Table CLOCK Note 1: LATCH ENABLE SERIAL-IN OUT0 … OUT5 … OUT7 SERIAL-OUT H L Dn Dn … Dn − 5 … Dn − 7 No change L L Dn + 1 No Change No change H L Dn + 2 Dn + 2 … Dn − 3 … Dn − 5 No change X H Dn + 3 OFF No change X H Dn + 3 OFF Dn －4 OUT0 to OUT7 = On when Dn = H; OUT0 to OUT7 = Off when Dn = L. 2 2010-03-08 TB62777FNG/FG Timing Diagram n=0 1 2 3 4 5 6 7 H CLOCK L H SERIAL-IN L H LATCH L H ENABLE L ON OUT0 OFF ON OUT1 OFF ON OUT 2 OFF ON OUT7 OFF H Data applied when n = 0 SERIAL-OUT L Note 1: Latches are level-sensitive, not edge-triggered. Note 2: The TB62777FNG can be used at 3.3 V or 5.0 V. However, the VDD supply voltage must be equal to the input voltage. Note 3: Serial data is shifted out of SERIAL-OUT on the falling edge of CLOCK. Marks: The latches hold data while the LATCH terminal is held Low. When the LATCH terminal is High, the latches do not hold data and pass it transparently. When the ENABLE terminal is Low, OUT0 to OUT7 toggle between ON and OFF according to the data. When the ENABLE terminal is High, OUT0 to OUT7 are forced OFF. 3 2010-03-08 TB62777FNG/FG Terminal Description Pin No. Pin Name Function 1 GND 2 SERIAL-IN Serial data input terminal 3 CLOCK Serial clock input terminal 4 LATCH Latch input terminal 5 OUT0 Constant-current output terminal (Open collector) 6 OUT1 Constant-current output terminal (Open collector) 7 OUT2 Constant-current output terminal (Open collector) 8 OUT3 Constant-current output terminal (Open collector) 9 OUT4 Constant-current output terminal (Open collector) 10 OUT5 Constant-current output terminal (Open collector) 11 OUT6 Constant-current output terminal (Open collector) 12 OUT7 Constant-current output terminal (Open collector) 13 ENABLE 14 SERIAL-OUT 15 R-EXT 16 VDD GND terminal Output enable input terminal All outputs ( OUT0 to OUT7 ) are disabled when the ENABLE terminal is driven High, and enabled when it is driven Low. Serial data output terminal. Serial data is clocked out on the falling edge of CLOCK. An external resistor is connected between this terminal and ground. OUT0 to OUT7 are adjusted to the same current value. Power supply terminal Equivalent Circuits for Inputs and Outputs SERIAL-OUT Terminal CLOCK, SERIAL-IN ， ENABLE ， LATCH Terminals VDD VDD CLOCK SERIAL-IN SERIAL-OUT ENABLE LATCH GND GND OUT0 to OUT7 Constant-current Output Terminals OUT0 ~ OUT7 GND 4 2010-03-08 TB62777FNG/FG Absolute Maximum Ratings (Ta = 25°C) Characteristics Symbol Rating Unit Supply voltage VDD 6.0 V Input voltage VIN −0.3 to VDD + 0.3 (Note 1) V Output current IOUT 55 mA/ch Output voltage VOUT Power dissipation Thermal resistance Pd −0.3 to 25 1.19(FG TYPE) / 1.02(FNG TYPE) V (Notes 2 and 3) 105(FG TYPE) / 122(FNG TYPE) Rth (j-a) (Note 2) W °C/W Operating temperature range Topr −40 to 85 °C Storage temperature range Tstg −55 to 150 °C Tj 150 °C Maximum junction temperature Note 1: However, do not exceed 6.0 V. Note 2: When mounted on a PCB (76.2 × 114.3 × 1.6 mm; Cu = 30%; 35-μm-thick; SEMI-compliant) Note 3: Power dissipation is reduced by 1/Rth (j-a) for each °C above 25°C ambient. Operating Ranges (unless otherwise specified, Ta = −40°C to 85°C) Characteristics Symbol Test Condition Min Typ. Max Unit Supply voltage VDD ⎯ 3 ⎯ 5.5 V Output voltage VOUT OUT0 to OUT 7 0.4 ⎯ 4 V IOUT OUT0 to OUT 7 5 ⎯ 40 mA/ch IOH SERIAL-OUT ⎯ ⎯ −5 IOL SERIAL-OUT ⎯ ⎯ 5 0.7 × VDD ⎯ VDD GND ⎯ 0.3 × VDD ⎯ ⎯ 25 Output current VIH Input voltage VIL SERIAL-IN/CLOCK/ LATCH / ENABLE Clock frequency fCLK LATCH pulse width twLAT (Note 2) 20 ⎯ ⎯ CLOCK pulse width twCLK (Note 2) 20 ⎯ ⎯ (Note 2) 2 ⎯ ⎯ twENA IOUT ≥ 20 mA ENABLE pulse width 5 mA ≤ IOUT ≤ 20 mA (Note 2) 3 ⎯ ⎯ 5 ⎯ ⎯ Setup time Cascade connection mA tSETUP1 5 ⎯ ⎯ tHOLD1 5 ⎯ ⎯ tHOLD2 5 ⎯ ⎯ ⎯ ⎯ 5 ⎯ ⎯ 5 tSETUP2 Hold time Maximum clock rise time Maximum clock fall time tr (Note 2) Single operation tf (Notes 1 and 2) V MHz ns μs ns μs Note 1: For cascade operation, the CLOCK waveform might become ambiguous, causing the tr and tf values to be large. Then it may not be possible to meet the timing requirement for data transfer. Please consider the timing carefully. Note 2: Please see the timing waveform on page 9. 5 2010-03-08 TB62777FNG/FG Electrical Characteristics (Unless otherwise specified, Ta = 25°C, VDD = 4.5 to 5.5 V) Symbol Test Circuit IOUT1 5 Output current error between ICs ΔIOUT1 Output current error between channels Characteristics Output current Output leakage current Test Condition Min Typ. Max Unit VOUT = 0.4 V, R-EXT = 1.2 kΩ VDD = 5 V, ― 15 ― mA 5 VOUT = 0.4 V, R-EXT = 1.2 kΩ All channels ON VDD = 5 V, ― ±3 ±6 ％ ΔIOUT2 5 VOUT = 0.4 V, R-EXT = 1.2 kΩ All channels ON VDD = 5 V ⎯ ±1 ±3 % IOZ 5 VOUT = 25 V ⎯ ⎯ 1 μA VIH ⎯ SERIAL-IN/CLOCK/ LATCH / 0.7 × VDD ⎯ VDD VIL ⎯ SERIAL-IN/CLOCK/ LATCH / GND ⎯ 0.3 × VDD IIH 2 ― ― 1 ENABLE Input voltage V Input current IIL 3 ENABLE VIN = VDD CLOCK/SERIAL-IN / LATCH / ENABLE μA VIN = GND CLOCK/SERIAL-IN/ LATCH / ― ― −1 ENABLE VOL 1 IOL = 5.0 mA, VDD = 5 V ⎯ ⎯ 0.3 VOH 1 IOH = −5.0 mA, VDD = 5 V 4.7 ⎯ ⎯ %/VDD 5 VDD = 3 V to 5.5 V ⎯ 1 2 IDD (OFF) 1 4 R-EXT = OPEN, VOUT = 25.0 V ⎯ ⎯ 1 IDD (OFF) 2 4 R-EXT = 1.2 kΩ, VOUT = 25.0 V, All channels OFF ⎯ ⎯ 5 IDD (ON) 4 R-EXT = 1.2 kΩ, VOUT = 0.4 V, All channels ON ⎯ ⎯ 9 SERIAL-OUT output voltage Changes in constant output current dependent on VDD Supply current V % mA Switching Characteristics (Unless otherwise specified, Ta = 25°C, VDD = 4.5 to 5.5V) Characteristics Propagation delay time Symbol Test Circuit tpLH1 6 tpLH2 6 tpLH3 6 tpLH 6 tpHL1 6 Test Condition (Note 1) CLK- OUTn , LATCH = “H”, ENABLE = “L” LATCH − OUTn , ENABLE = “L” ENABLE − OUTn , LATCH = “H” CLK-SERIAL OUT CLK- OUTn , LATCH = “H”, ENABLE = “L” LATCH − OUTn , Min Typ. Max ⎯ 20 300 ⎯ 20 300 ⎯ 20 300 2 10 14 ⎯ 30 340 ns ⎯ 70 340 ⎯ 70 340 CLK-SERIAL OUT 2 10 14 6 10% to 90% points of OUT0 to OUT7 voltage waveforms ― 20 150 6 90% to 10% points of OUT0 to OUT7 voltage waveforms ― 125. 300 tpHL2 6 tpHL3 6 tpHL 6 Output rise time tor Output fall time tof ENABLE = “L” ENABLE − OUTn , LATCH = “H” Unit Note 1: Topr = 25°C, VDD = VIH = 5 V, VIL = 0 V, REXT = 1.2 kΩ, IOUT = 15 mA, VL = 5.0 V, CL = 10.5 pF (see test circuit 6.) 6 2010-03-08 TB62777FNG/FG Electrical Characteristics (Unless otherwise specified, Ta = 25°C, VDD = 3 to 3.6 V) Symbol Test Circuit IOUT1 5 Output current error between ICs ΔIOUT1 Output current error between channels Characteristics Output current Output leakage current Test Condition Min Typ. Max Unit VOUT = 0.4 V, R-EXT = 1.2 kΩ VDD = 3.3 V ― 15 ― mA 5 VOUT = 0.4 V, R-EXT = 1.2 kΩ All channels ON VDD = 3.3 V ― ±3 ±6 % ΔIOUT2 5 VOUT = 0.4 V, R-EXT = 1.2 kΩ All channels ON VDD = 3.3 V ⎯ ±1 ±3 % IOZ 5 VOUT = 25 V ⎯ ⎯ 1 μA VIH ⎯ SERIAL-IN/CLOCK/ LATCH / 0.7 × VDD ⎯ VDD VIL ⎯ SERIAL-IN/CLOCK/ LATCH / GND ⎯ 0.3 × VDD IIH 2 ― ― 1 ENABLE Input voltage V ENABLE VIN = VDD CLOCK/SERIAL-IN/ LATCH / ENABLE Input current IIL 3 μA VIN = GND CLOCK/SERIAL-IN/ LATCH / ― ― −1 ENABLE VOL 1 IOL = 5.0 mA, VDD = 3.3 V ⎯ ⎯ 0.3 VOH 1 IOH = −5.0 mA, VDD = 3.3 V 3.0 ⎯ ⎯ %/VDD 5 VDD = 3 V to 5.5 V ⎯ 1 2 IDD (OFF) 1 4 R-EXT = OPEN, VOUT = 25.0 V ⎯ ⎯ 1 IDD (OFF) 2 4 R-EXT = 1.2 kΩ, VOUT = 25.0 V, All channels OFF ⎯ ⎯ 5 IDD (ON) 4 R-EXT = 1.2 kΩ, VOUT = 0.4 V, All channels ON ⎯ ⎯ 9 SERIAL-OUT output voltage Changes in constant output current dependent on VDD Supply current V % mA Switching Characteristics (Unless otherwise specified, Ta = 25°C, VDD = 3 to 3.6 V) Characteristics Propagation delay time Symbol Test Circuit tpLH1 6 tpLH2 6 LATCH - OUTn , tpLH3 6 ENABLE - OUTn , tpLH 6 CLK-SERIAL OUT tpHL1 6 Test Condition (Note 1) CLK- OUTn , LATCH = “H”, ENABLE = “L” ENABLE = “L” LATCH = “H” CLK- OUTn , LATCH = “H”, ENABLE = “L” tpHL2 6 LATCH - OUTn , tpHL3 6 ENABLE - OUTn , tpHL 6 Output rise time tor Output fall time tof Min Typ. Max ⎯ ⎯ 300 ⎯ ⎯ 300 ⎯ ⎯ 300 2 ⎯ 14 ⎯ ⎯ 340 ns ⎯ ⎯ 340 ⎯ ⎯ 340 CLK-SERIAL OUT 2 ⎯ 14 6 10% to 90% points of OUT0 to OUT7 voltage waveforms ⎯ ⎯ 150 6 90% to 10% points of OUT0 to OUT7 voltage waveforms ⎯ ⎯ 300 ENABLE = “L” LATCH = “H” Unit Note 1: Topr = 25°C, VDD = VIH = 3.3 V, VIL = 0 V, REXT = 1.2 kΩ, IOUT = 15 mA, VL = 5.0 V, CL = 10.5 pF (see test circuit 6.) 7 2010-03-08 TB62777FNG/FG Test Circuits Test Circuit 1: SERIAL-OUT output voltage (VOH/VOL) ENABLE VDD OUT0 CLOCK F.G LATCH GND SERIAL-OUT REXT IO = −5 mA to 5 mA R-EXT CL = 10.5 pF VIH = VDD VIL = 0 V tr = tf = 10 ns (10 to 90%) V VDD = 5 V、3.3V OUT7 SERIAL-IN Test Circuit 2: Input Current (IIH) VIN = VDD A A A ENABLE VDD OUT0 CLOCK LATCH GND SERIAL-OUT REXT R-EXT CL = 10.5 pF A VDD = 4.5 to 5.5 V、3 to 3.6V OUT7 SERIAL-IN Test Circuit 3: Input Current (IIL) OUT0 CLOCK LATCH OUT7 SERIAL-IN R-EXT GND SERIAL-OUT 8 VDD = 4.5 to 5.5 V、3 to 3.6V A VDD CL = 10.5 pF A A ENABLE REXT A 2010-03-08 TB62777FNG/FG Test Circuit 4: Supply Current ENABLE LATCH OUT7 SERIAL-IN R-EXT GND SERIAL-OUT CL = 10.5 pF REXT = 1.2 kΩ VIH = VDD VIL = 0 V tr = tf = 10 ns (10 to 90%) VDD = 4.5 to 5.5 V、3 to 3.6V F.G OUT0 CLOCK A Note: The output terminal is based on the power supply current conditions on page 6 and 7. Test Circuit 5: Output Current (IOUT1), Output Leakage Current (IOZ), Output Current Error Margin (ΔIOUT1/ΔIOUT2), Current Variation with VDD (%/VDD) ENABLE VDD OUT0 A OUT7 A CLOCK LATCH SERIAL-IN R-EXT GND SERIAL-OUT CL = 10.5 pF REXT = 1.2 kΩ VIH = VDD VIL = 0 V tr = tf = 10 ns (10 to 90%) VOUT = 0.4 V, 25 V A VDD = 4.5 to 5.5 V、3 to 3.6V F.G Theoretical output current = 1.13 V/REXT × 16 9 2010-03-08 TB62777FNG/FG Test Circuit 6: Switching Characteristics ENABLE RL=300Ω VDD OUT0 CLOCK F.G CL LATCH IOUT SERIAL-IN R-EXT GND SERIAL-OUT CL = 10.5 pF REXT = 1.2 kΩ VIH = VDD VIL = 0 V tr = tf = 10 ns (10 to 90%) 10 VDD = 4.5 to 5.5 V、3 to 3.6V CL = 10.5 pF VL = 5 V OUT7 2010-03-08 TB62777FNG/FG Timing Waveforms 1. CLOCK, SERIAL-IN, SERIAL-OUT twCLK CLOCK 50% 90% 50% 10% tSETUP1 SERIAL-IN 90% 10% tr 50% tf 50% tHOLD1 SERIAL-OUT 50% tpLH/tpHL 2. CLOCK, SERIAL-IN, LATCH , ENABLE , OUTn CLOCK 50% 50% SERIAL-IN LATCH tHOLD2 tSETUP2 50% 50% twLAT twENA 50% ENABLE OUTn twENA 50% 50% 50% 50% tpHL1/LH1 tpHL2/LH2 tpHL3/LH3 3. OUTn 90% 90% OFF OUTn 10% 10% tof ON tor Note: Timing chart waveforms are presented to describe functions and operations and may be simplified. Adequate consideration should be given to timing conditions. 11 2010-03-08 TB62777FNG/FG Output Current vs. Derating (lighting rate) Graph PCB Conditions: 76.2 × 114.3 × 1.6 mm, Cu = 30%, 35-μm Thick, SEMI-Compliant TB62777FNG IOUT − Duty ON PCB Pd-Ta 1.4 100 90 1.2 70 1.0 60 0.8 Pd(W) IOUT (mA) 80 50 40 0.6 ON PCB 30 All outputs ON 0.4 Ta = 85°C 20 VDD = 5.0 V 10 0.2 VOUT = 1.0 V 0.0 0 0 20 40 60 80 0 100 50 100 150 Ta (°C) Duty − Turn-ON rate (%) Output Current vs. External Resistor (typ.) IOUT −R IOUT - EXT REXT 50 Theoretical value 45 IOUT (A) = 1.13 (V) ÷ REXT (Ω)) × 16 40 IOUT (mA) IOUT (mA) 35 30 25 20 15 10 5 All outputs ON Ta = 25°C VOUT = 0.7 V 0 100 1000 REXT (Ω) 10000 The above graphs are presented merely as a guide and do not constitute any guarantee as to the performance or characteristics of the device. Each product design should be fully evaluated in a real-world environment. 12 2010-03-08 TB62777FNG/FG Application Circuit 1: General Composition for Static Lighting of LEDs In the following diagram, it is recommended that the LED supply voltage (VLED) be equal to or greater than the sum of Vf (max) of all LEDs plus 0.7 V. VLED O0 O1 O2 O5 O6 O7 SERIAL-IN C.U. ENABLE LATCH O0 SERIAL-OUT ENABLE TB62777FNG/FG LATCH CLOCK O1 O2 O5 O6 O7 SERIAL-OUT SERIAL-IN TB62777FNG/FG CLOCK R-EXT GND R-EXT 13 GND 2010-03-08 TB62777FNG/FG Application Circuit 2: General Composition for Dynamic Lighting of LEDs In the following diagram, it is recommended that the LED supply voltage (VLED) be equal to or greater than the sum of Vf (max) of all LEDs plus 0.7 V. Example) TD62M8600FG 8 bit multichip PNP transistor array. It is not necessary when lighting statically. VLED O0 O6 O1 O7 C.U. ENABLE LATCH O0 SERIAL-OUT SERIAL-IN ENABLE TB62777FNG/FG LATCH CLOCK O6 O1 O7 SERIAL-OUT SERIAL-IN TB62777FNG/FG CLOCK R-EXT R-EXT GND 14 GND 2010-03-08 TB62777FNG/FG Package Dimensions Weight: 0.07 g (typ.) 15 2010-03-08 TB62777FNG/FG Package Dimensions Weight: 0.14 g (typ.) 16 2010-03-08 TB62777FNG/FG Notes on Contents 1. Block Diagrams Some of the functional blocks, circuits, or constants in the block diagram may be omitted or simplified for explanatory purposes. 2. Equivalent Circuits The equivalent circuit diagrams may be simplified or some parts of them may be omitted for explanatory purposes. 3. Timing Charts Timing charts may be simplified for explanatory purposes. 4. Application Circuits The application circuits shown in this document are provided for reference purposes only. Thorough evaluation is required, especially at the mass production design stage. Toshiba does not grant any license to any industrial property rights by providing these examples of application circuits. 5. Test Circuits Components in the test circuits are used only to obtain and confirm the device characteristics. These components and circuits are not guaranteed to prevent malfunction or failure from occurring in the application equipment. IC Usage Considerations Notes on handling of ICs (1) The absolute maximum ratings of a semiconductor device are a set of ratings that must not be exceeded, even for a moment. Do not exceed any of these ratings. Exceeding the rating(s) may cause breakdown, damage or deterioration of the device, and may result in injury by explosion or combustion. (2) Use an appropriate power supply fuse to ensure that a large current does not continuously flow in the event of over current and/or IC failure. The IC will fully break down when used under conditions that exceed its absolute maximum ratings, when the wiring is routed improperly or when an abnormal pulse noise occurs from the wiring or load, causing a large current to continuously flow. Such a breakdown can lead to smoke or ignition. To minimize the effects of a large current flow in the event of breakdown, fuse capacity, fusing time, insertion circuit location, and other such suitable settings are required. (3) If your design includes an inductive load such as a motor coil, incorporate a protection circuit into the design to prevent device malfunction or breakdown caused by the current resulting from the inrush current at power ON or the negative current resulting from the back electromotive force at power OFF. IC breakdown may cause injury, smoke or ignition. For ICs with built-in protection functions, use a stable power supply with. An unstable power supply may cause the protection function to not operate, causing IC breakdown. IC breakdown may cause injury, smoke or ignition. (4) Do not insert devices incorrectly or in the wrong orientation. Make sure that the positive and negative terminals of power supplies are connected properly. Otherwise, the current or power consumption may exceed the absolute maximum rating, and exceeding the rating(s) may cause breakdown, damage or deterioration of the device, which may result in injury by explosion or combustion. In addition, do not use any device that has had current applied to it while inserted incorrectly or in the wrong orientation even once. 17 2010-03-08 TB62777FNG/FG (5) Carefully select power amp, regulator, or other external components (such as inputs and negative feedback capacitors) and load components (such as speakers). If there is a large amount of leakage current such as input or negative feedback capacitors, the IC output DC voltage will increase. If this output voltage is connected to a speaker with low input withstand voltage, overcurrent or IC failure can cause smoke or ignition. (The over current can cause smoke or ignition from the IC itself.) In particular, please pay attention when using a Bridge Tied Load (BTL) connection type IC that inputs output DC voltage to a speaker directly. Points to remember on handling of ICs (1) Heat Dissipation Design In using an IC with large current flow such as a power amp, regulator or driver, please design the device so that heat is appropriately dissipated, not to exceed the specified junction temperature (Tj) at any time or under any condition. These ICs generate heat even during normal use. An inadequate IC heat dissipation design can lead to decrease in IC life, deterioration of IC characteristics or IC breakdown. In addition, please design the device taking into consideration the effect of IC heat dissipation on peripheral components.. (2) Back-EMF When a motor rotates in the reverse direction, stops, or slows down abruptly, a current flow back to the motor’s power supply due to the effect of back-EMF. If the current sink capability of the power supply is small, the device’s motor power supply and output pins might be exposed to conditions beyond maximum ratings. To avoid this problem, take the effect of back-EMF into consideration in your system design. 18 2010-03-08 TB62777FNG/FG About solderability, following conditions were confirmed • Solderability (1) Use of Sn-37Pb solder Bath · solder bath temperature = 230°C · dipping time = 5 seconds · the number of times = once · use of R-type flux (2) Use of Sn-3.0Ag-0.5Cu solder Bath · solder bath temperature = 245°C · dipping time = 5 seconds · the number of times = once · use of R-type flux 19 2010-03-08 TB62777FNG/FG RESTRICTIONS ON PRODUCT USE • Toshiba Corporation, and its subsidiaries and affiliates (collectively “TOSHIBA”), reserve the right to make changes to the information in this document, and related hardware, software and systems (collectively “Product”) without notice. • This document and any information herein may not be reproduced without prior written permission from TOSHIBA. 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Product and related software and technology may be controlled under the Japanese Foreign Exchange and Foreign Trade Law and the U.S. Export Administration Regulations. Export and re-export of Product or related software or technology are strictly prohibited except in compliance with all applicable export laws and regulations. • Please contact your TOSHIBA sales representative for details as to environmental matters such as the RoHS compatibility of Product. Please use Product in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances, including without limitation, the EU RoHS Directive. TOSHIBA assumes no liability for damages or losses occurring as a result of noncompliance with applicable laws and regulations. 20 2010-03-08