TB62777FNGEL

DISCONTINUED MAR 2009 TB62705CPG/CFG/CFNG TOSHIBA Bi−CMOS INTEGRATED CIRCUIT SILICON MONOLITHIC TB62705CPG, TB62705CFG, TB62705CFNG 8-BIT SHIFT REGISTER, LATCHES & CONSTANT-CURRENT DRIVERS The TB62705CPG / CFG / CFNG are specifically designed for LED and LED DISPLAY constant-current drivers. These constant-current output circuits can support the set-up of an external resistor (IOUT = 5~90mA). This IC is a monolithic integrated circuit designed to be used together with Bi-CMOS process. The devices consist of an 8-bit shift register, latch, AND-GATE and constant-current drivers. This devices are a product for the Pb free(Sn-Ag). TB62705CPG FEATURES Constant-current Output : current with one resistor for 5 to 90mA. TB62705CFG Maximum Clock Frequency : fCLK = 15 (MHz) (Cascade Connecte Operate, Topr = 25°C) 5V C−MOS Compatible Input Package : DIP16−P−300−2.54A (TB62705CPG) SSOP16−P−225−1.00A (TB62705CFG) SSOP16−P−225−0.65B (TB62705CFNG) TB62705CFNG Constant Output Current Matching: OUTPUT-GND VOLTAGE ≥ 0.4 V ≥ 0.7 V CURRENT MATCHING ±6.0% ±6.0% OUTPUT CURRENT 5~40 mA 5~90 mA PIN CONNECTION (Top view) Weight DIP16−P−300−2.54A : 1.11 g (typ.) SSOP16−P−225−1.00A : 0.14 g (typ.) SSOP16−P−225−0.65B : 0.07 g (typ.) VDD R-EXT SERIAL-OUT GND SERIAL-IN CLOCK LATCH OUTn OUTn OUTn OUTn 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ENABLE OUTn OUTn OUTn OUTn Company Headquarters 3 Northway Lane North Latham, New York 12110 Toll Free: 800.984.5337 Fax: 518.785.4725 Web: www.marktechopto.com | Email: info@marktechopto.com4 TB62705CPG/CFG/CFNG BLOCK DIAGRAM OUTn OUTn OUTn TIMING DIAGRAM CLOCK 5V 0V 5V 0V 5V 0V 5V 0V Off On Off On Off On Off 5V 0V SERIAL-IN LATCH ENABLE OUT0 OUT1 OUT3 OUT7 SERIAL-OUT Note: Latches are level-sensitive, not rising edge-sensitive, and are not synchronized with the CLOCK signal. The data will pass through the latch circuit if the latch input is set at “H” level, and will be retained if the input is set at “L”. 2 2005-10-06 TB62705CPG/CFG/CFNG PIN DESCRIPTION PIN No. 1 2 3 4 5~12 13 14 15 16 PIN NAME GND SERIAL−IN CLOCK LATCH OUTn ENABLE SERIAL−OUT R−EXT VDD GND terminal for control logic Input pin for shift register serial data Clock input terminal for data shift to up-edge. Data strobe input terminal. Latches pass LATCH data with “H” level input and retain data with “L” level input. Output terminals Input terminal for output enable. All outputs ( OUTn ) go off with ENABLE data input at "H" level and go on with data input at "L" level. Output terminal for serial data for the next SERIAL-IN terminal. Input terminal for connecting a resistor to regulate all output currents. 5-V supply pin of the IC FUNCTION TRUTH TABLE CLOCK UP UP UP DOWN DOWN LATCH H L H X X ENABLE L L L L H SERIAL−IN Dn Dn+1 Dn+2 Dn+3 Dn+3 OUTn Dn ··· Dn−5 ··· Dn−7 No change Dn+2 ··· Dn−3 ··· Dn−5 Dn+2 ··· Dn−3 ··· Dn−5 Off SERIAL−OUT Dn − 7 Dn−6 Dn − 5 Dn − 5 Dn − 5 Note: OUTn = on if Dn = H level, and OUTn = off if Dn = L level. An external resistor is connected with R−EXT and GND. Be sure to administer the correct power supply voltage. INPUT/OUTPUT EQUIVALENT CIRCUITS 1. ENABLE terminal 2. LATCH terminal 3. CLOCK, SERIAL−IN terminal 4. SERIAL−OUT terminal 3 2005-10-06 TB62705CPG/CFG/CFNG MAXIMUM RATINGS (Ta = 25°C) CHARACTERISTIC Supply Voltage Input Voltage Output Current Output Voltage Clock Frequency GND Terminal Current Power Dissipation SYMBOL VDD VIN IOUT VCE fCK IGND PD RATING 0~7.0 −0.4~VDD + 0.4 90 −0.5~17.0 15 720 1.47 (CPG−type : FREE AIR, Ta = 25°C) 0.78 (CFG / CFNG−type : ON PCB, Ta = 25°C) 85 (CPG−type : FREE AIR, Ta = 25°C) 160 (CFG / CFNG−type : ON PCB, Ta = 25°C) −40~85 −55~150 UNIT V V mA V MHz mA W Thermal Resistance Operating Temperature Storage Temperature Rth (j−a) Topr Tstg °C / W °C °C Note: CPG type: For an ambient temperature above 25°C, the derating is 11.8 mW/°C. CFG and CFNG type: For an ambient temperature above 25°C, the derating is 6.3 mW/°C. RECOMMENDED OPERATING CONDITION (Ta = −40~85°C unless otherwise stated) CHARACTERISTIC Supply Voltage Output Voltage SYMBOL VDD VOUT IO Output Current IOH IOL VIH Input Voltage VIL LATCH Pulse Width CLOCK Pulse Width ENABLE Pulse Width Set-up Time for DATA Hold Time for DATA Set-up Time for LATCH Hold Time for LATCH Clock Frequency tw LAT tw CLK tw EN tsetup (D) thold (D) tsetup (L) thold (L) fCK Cascade operation Ta = 85°C (CPG−type FREE AIR) Ta = 85°C (CFG / CFNG−type ON PCB) VDD = 4.5~5.5 V ― CONDITION ― ― OUTn , DC 1 circuit SERIAL−OUT SERIAL−OUT ― MIN 4.5 ― 5 ― ― 0.7 VDD −0.3 100 50 4500 60 20 100 60 10.0 ― ― TYP. 5.0 ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― MAX 5.5 15.0 88 1.0 −1.0 VDD +0.3 0.3 VDD ― ― ― ― ― ― ― ― 0.82 W 0.40 mA UNIT V V V ns ns ns ns ns ns ns MHz Power Dissipation PD 4 2005-10-06 TB62705CPG/CFG/CFNG ELECTRICAL CHARACTERISTICS (VDD = 5.0 V, Ta = 25°C unless otherwise stated) CHARACTERISTIC "H" Level Input Voltage "L" Level Output Leakage Current Output Voltage S−OUT VIL IOH VOL VOH IOL1 IOL2 Current Skew Output Current 2 Current Skew Supply Voltage Regulation Pull−Up Resistor Pull−Down Resistor ∆IOL1 IOL3 IOL4 ∆IOL2 % / VDD RIN (up) RIN (down) IDD (off) 1 "OFF" Supply Current "ON" IDD (off) 2 IDD (off) 3 IDD (on) 1 IDD (on) 2 ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― VOH = 15.0 V IOL = 1.0 mA IOH = −1.0 mA VCE = 0.7 V VCE = 0.4 V IO = 40 mA, VCE = 0.4 V VCE = 1.0 V VCE = 0.7 V IO = 75 mA, VCE = 0.7 V REXT = 470 Ω (Include skew) REXT = 470 Ω REXT = 250 Ω (Include skew) REXT = 250 Ω ― SYMBOL VIH TEST CIR− CUIT ― CONDITION ― MIN 0.7 VDD GND ― ― 4.6 34.1 33.7 ― 64.2 63.8 ― ― 150 100 ― 3.5 6.5 7.0 10.0 TYP. ― ― ― ― ― 40.0 39.5 ±1.5 75.5 75.0 ±1.5 1.5 300 200 0.6 5.8 10.7 12.0 22.0 MAX VDD 0.3 VDD 10 0.4 ― 45.9 45.3 ±6.0 86.8 86.2 ±6.0 5.0 600 400 1.2 8.0 15.0 18.0 32.0 mA V UNIT µA V Output Current 1 mA % mA % %/V kΩ kΩ REXT = 470 Ω, Ta = −40~85°C ― ― REXT = OPEN, OUT0 ~ 7 = off REXT = 470 Ω, OUT0 ~ 7 = off REXT = 250 Ω, OUT0 ~ 7 = off REXT = 470 Ω, OUT0 ~ 7 = on REXT = 250 Ω, OUT0 ~ 7 = on 5 2005-10-06 TB62705CPG/CFG/CFNG SWITCHING CHARACTERISTICS (Ta = 25°C unless otherwise stated) CHARACTERISTIC SIN− OUTn Propagation Delay Time (“L” to “H”) LATCH − OUTn ENABLE − OUTn CLK−SOUT SIN − OUTn Propagation Delay Time (“H” to “L”) LATCH − OUTn ENABLE − OUTn CLK−SOUT Pulse Width Set−up Time for LATCH Hold Time for LATCH CK LATCH L−H H− L L−H H− L tw CLK tw LAT tsetup ― ― ― tpHL ― VDD = 5.0 V VCE = 0.4 V VIH = VDD VIL = GND REXT = 470 Ω IOUT = 40 mA VL = 3.0 V R L = 65 Ω CL = 10.5 pF tpLH ― SYMBOL TEST CIR− CUIT CONDITION MIN ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― ― 300 150 TYP. 1200 1200 1200 30 700 700 700 30 20 10 25 25 0 0 ― ― 600 300 MAX 1500 1500 1500 70 1000 1000 1000 70 30 25 50 50 30 30 10 10 1000 600 ns ns ns UNIT ns thold tr tf tor tof ― ― ― ― ― ns µs µs ns ns Maximum CLOCK Rise Time Maximum CLOCK Fall Time Output Rise Time Output Fall Time 6 2005-10-06 TB62705CPG/CFG/CFNG TEST CIRCUIT DC characteristics OUTn OUTn AC characteristics OUTn OUTn Precaution on Use Utmost care is necessary in the design of the output line, VCC (VDD) and GND line since the IC may be damaged due to short-circuits between outputs, air contamination faults, or faults caused by improper grounding. 7 2005-10-06 TB62705CPG/CFG/CFNG TIMING WAVEFORM 1. CLOCK−SERIAL OUT, OUTn OUTn (current) 2. CLOCK− LATCH 3. ENABLE − OUTn OUTn 8 2005-10-06 TB62705CPG/CFG/CFNG Iout-Duty Cycle(TB62705CFG/CFNG) Iout-Duty Cycle(TB62705CFG/CFNG) Iout-Duty Cycle(TB62705CFG/CFNG) Iout-Duty Cycle(TB62705CPG) Iout-Duty Cycle(TB62705CPG) Iout-Duty Cycle(TB62705CPG) 9 2005-10-06 TB62705CPG/CFG/CFNG LED DRIVER TB6270X SERIES APPLICATION NOTE 1:CFG/CFNG ON PCB 2:CFG/CFNG FREE AIR 3:CPG FREE AIR 10 2005-10-06 TB62705CPG/CFG/CFNG [1] [2] Output current (IOUT) IOUT is set by the external resistor (R−EXT), as shown in Fig. 1. Total supply voltage (VLED) This device can operate on 0.4~0.7 V (VO). When a higher voltage is input to the device, the excess voltage is consumed inside the device, which leads to power dissipation. To minimize power dissipation and loss, we recommend that the total supply voltage be set as follows: VLED (total supply voltage) = VCE (Tr Vsat) + Vf (LED forward voltage) + VO (IC supply voltage). When the total supply is too high in the light of the power dissipation of this device, an additional resistor (R) can be used to decrease the supply voltage (VO). PATTERN LAYOUT OUTn OUTn OUTn OUTn [3] Pattern layout This device has only one ground pin, i.e., the combined signal ground pin and power ground pin. If the ground pattern layout contains a large amount of inductance and impedance, and the voltage between the ground and LATCH or CLOCK terminals exceeds 2.5 V due to switching noise, the device may not operate correctly. Be sure to pay attention to pattern layout to minimize inductance. 11 2005-10-06 TB62705CPG/CFG/CFNG PACKAGE DIMENSIONS Weight: 1.11 g (Typ.) 12 2005-10-06 TB62705CPG/CFG/CFNG PACKAGE DIMENSIONS Weight: 0.14 g (Typ.) 13 2005-10-06 TB62705CPG/CFG/CFNG PACKAGE DIMENSIONS Weight: 0.07 g (Typ.) 14 2005-10-06 TB62705CPG/CFG/CFNG 15 2005-10-06