IS6605A

IS6605A 4V to 16V Input, 6A Sync Step-Down Converter W/ Light Load Mode, Programmable Switching Frequency and Over Current Limit Rev2.0 6/2020 Part Number IS6605A Input Voltage 4V~16V Description IS6606 uses proprietary Turbo Constant-OnTime (TCOTTM) control with internal compensation to provide fast transient response and simplified loop stability. The switching frequency can be easily set to 600kHz, 1.1MHz, 1.5MHz or 2MHz. The switching frequency of IS6605A remains constant regardless of input and output voltages. The soft start process is controlled by an internal 1.5msec timer, which can be increased by adding a capacitor from TRK / REF to GND. The open-drain power good (PGOOD) signal indicates whether the output is within its nominal voltage range. When the input power fails to power the IS6605A, PGOOD is clamped at about 0.7V by an external pull-up voltage. The IS6605A is equipped with full suites of protection functions which includes overcurrent protection (OCP), over-voltage protection (OVP), under-voltage protection (UVP), and over-temperature protection (OTP). The IS6605A is available in a 14-pin QFN (2mmx3mm) package. Production Datasheet Current Rating 6A Features The IS6605A is a fully integrated, highfrequency, synchronous, step-down converter. It provides a very compact solution that achieves up to 6A output current with excellent load and line regulation over wide input voltage range. IS6605A has high working efficiency over its output current load range. Moisture Sensitivity Leve 3. Output Voltage 0.6V~5.5V Turbo Constant-On-Time (TCOTTM) Control with Fast Transient Response. • VIN Input Voltage Range: 2.7 V to 16V with External Bias VCC voltage, or 4V to 16V with Internal Bias VCC. • Output Voltage Range: 0.6V to 5.5V, and 90% max duty cycle. • 6A Continuous Output Current. • • Excellent Load and Line Regulations with 0.5% Voltage Accuracy. • Up to 90% Efficiency at VIN=12V, VOUT=1.8V Mode Selection between Pulse Skip and CCM at Light Load • PGOOD Active Clamp at Low Level during a Power Outage • Programmable Soft-Start time • 1.0µA Current into VIN Pin during Shutdown • Programmable Switch Valley Current Limit • Adjustable Switching Frequency: 600kHz, 1.1MHz, 1.5MHz and 2MHz • OCP, NOCP, OVP, UVLO and OTP • QFN 2mm x 3mm Package with 14-Pin • Applications • • • • Telecom/Datacom Computing and Servers Point of Load Module Computing and Servers Innovision Semiconductor 1 IS6605A Rev2.0 6/2020 Typical Application Circuit R6 C4 BS T L1 VI N C1 VO PHAS E VI N R4 C2 C8 VCC R1 C3 C7 C5 PG D PGOOD IS6605A R7 FB ON EN OFF R5 C6 MODE PGND AGND CS R2 REF R3 Production Datasheet Innovision Semiconductor 2 IS6605A Rev2.0 6/2020 Order Information TOP MARKING (IS6605A) Part Number Package Shipping Method Package Marking IS6605A QFN-14(2mm x 3mm) 5000u Tape & Reel 6605A 6605A 8A653 YYWW 6605A: First five digits of the part number 8A653: Lot ID YY: Year code W:W Week code Package Reference PGND VCC 14 13 PGND 1 12 MODE PHASE 2 11 PHASE VIN 3 10 BST CS 4 9 PGOOD EN 5 8 REF 6 7 FB AGND Top View Production Datasheet Innovision Semiconductor 3 IS6605A Rev2.0 6/2020 Absolute Maximum Ratings Thermal Ratings Supply Voltage (Vin)……………………...-0.3V to 18V Vcc Voltage (Vcc)………………………….-0.3V to 5.5V Switch Node Voltage (VPH) DC……….-0.3V to 18.3V Switch Node Voltage (VPH) 25ns ……….-5V to 20V BST Pin (Vbst-sw) 25ns………………….-0.3V to 5.5V All other pins……………………………..-0.3V to 5.5V Junction Temperature (Tj)………………………150°C Storage Temperature…………………-65°C to 150°C ΘJC Max………………………………………17.5°C/W Θ JBTyp (Still Air, No Heatsink)……………7°C/W Recommended Operating Conditions Supply Voltage (Vin)………………………2.7V to 16V Vcc Voltage (Vcc)………………………3.15V to 3.6V Output Voltage (Vo)………………………0.6V to 5.5V Max Output Current (Io_max)…………………………6A Junction Temperature (Tj)……………-40°C to 125°C Note 1. Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only; functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. ESD Ratings Electrostatic Discharge Standard Value Human Body Mode (HBM) Charge Device Mode (CDM) JEDEC EIA/JESD22-A114 JEDEC EIA/JESD22-C101F 1500V 2000V 1). JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. 2). JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Production Datasheet Innovision Semiconductor 4 IS6605A Rev2.0 6/2020 Pin Out and Package IS6605A(QFN-14) Pin Number Name Description 1,14 PGND System Ground. Power ground of the power stage. 2,11 PHASE Switch Output. Switch node of power stage. 3 VIN Supply voltage. Input to the power stage and internal LDO. 4 CS Current limit and inductor current report. Connect a resistor to AGND to set the valley current limit trip point. A voltage indicating the inductor current during operating. 5 EN Enable pin. An input signal turns the regulator on or off. Connect EN to VIN through a pull-up resistor. Do not float this pin. 6 FB An external resistor divider from output to AGND is tapped to FB to set the output voltage. It is recommended to place the resistor divider as close as possible to FB. Avoid vias on FB traces. 7 AGND 8 REF External tracking voltage input. The output voltage tracks this input signal. REF is decoupled as close as possible to the ceramic capacitor 9 PGOOD Power good output with open drain. If the output voltage is within the regulation range, a pull-up resistor connected to the DC voltage is required to indicate a logic high signal. 10 BST Bootstrap connection. A capacitor connected between PHASE and BST is required to form a floating supply across the high-side switch driver. 12 MODE 13 VCC Production Datasheet Signal logic ground. A Kelvin connection to PGND is required. Operation mode selection. Connect a resistor to AGND to set switching frequency and select PLUSE SKIP/FCCM Mode. Internal 3.3V LDO output. The driver and control circuit are powered by VCC. Decouple VCC with a minimum 1uF ceramic capacitor as close as possible. Innovision Semiconductor 5 IS6605A Rev2.0 6/2020 FUNCTIONAL BLOCK DIAGRAM VIN MODE VCC MODE Select LDO BST REG BST Off Timer EN Reference System Monitor HS Driver xS OV_TH UV_TH REF + -Error Amplifier FB Q HSG LSG xR + PWM Comparator On Timer PHASE Logic Control HSG Ramp LSG LS Driver + - OV_TH + PGOOD PGOOD Comparator UV_TH OV Detect Comparator + ZCD UV Detect Comparator xLIM Valley Current Limit& ZCD PGND FAULT CS AGND Production Datasheet Innovision Semiconductor 6 IS6605A Rev2.0 6/2020 ELECTRICAL CHARACTERISTICS Vin = 12V, T = −40°C to 125°C, unless otherwise noted. Definition/Datasheet Parameters Min Typ Units Max Supply Voltage & Current VIN Supply Voltage (with internal LDO) 4.0 16 V VIN Supply Voltage (with external bias) 2.85 16 V VIN Supply Current (Quiescent) EN=2V, VFB = 0.62V VIN Shutdown Current EN="Lo" 1500 µA 0 2 µA 3.3 3.42 V VCC Supply VCC Output Voltage (6V 8 × 2 × where • • • COUT(min) is the minimum output capacitance needed to meet the stability requirement of the design tON is the on-time information based on the switching frequency and duty cycle (in this design, 100 ns) τ is the ramp compensation time constant of the design based on the switching frequency and duty cycle (in this design, 1 sec) • • LOUT is the output inductance (in the design, 0.39 µH) • VREF is the reference voltage level (in this design, 0.6 V) VOUT is the output voltage (1 V) The stability is ensured when the amount of the output capacitance is greater than the minimum required value. And when all MLCCs (multi-layer ceramic capacitors) are used, both DC and AC derating effects must be considered to ensure that the minimum output capacitance requirement is met with sufficient margin. For Constant on time topology, the minimum capacitance required by the stability is much smaller than that is required by the load transient. Response to a Load Transient Production Datasheet In general applications where the overall output voltage tolerance is +/-5%, the allowed transient voltage deviation during the worst case load release can be set at around 3% depending on how much output voltage setpoint accuracy (1% in this design) and the ripple voltage requirement (1% in this design). The minimum output capacitance to meet the overshoot requirement can be calculated using the above equation. This example uses a combination of POSCAP and MLCC capacitors to meet the overshoot requirement. • POSCAP bank #1: 1 x 330 µF, 2.5 V, 6 mΩ per capacitor • MLCC bank #2: 1 × 10 µF, 2.5 V, 1 mΩ per capacitor (7) with DC+AC derating factor of 50% Recalculating the worst case overshoot using the described capacitor bank design, the overshoot needs to be 30 mV or less which meets the 3% overshoot transient specification requirement. Output Voltage Ripple The output voltage ripple is another important design consideration. The following equation calculates the minimum output capacitance required to meet the output voltage ripple specification. This criterion is the requirement Innovision Semiconductor 17 IS6605A Rev2.0 6/2020 when the impedance of the output capacitance 9.4 mΩ. For this example, four 22 μF, 25 V lowESR polymer capacitors in parallel were is dominated by ESR. selected for the power stage. _ = 8× × Bootstrap Capacitor Selection _ In this example, the maximum output voltage ripple is 9 mV. Because this capacitance value is significantly lower compared to that of transient load release, determining the output capacitance bank using the worst case load release requirement is generally adequate. Because the output capacitor bank consists of both POSCAP and MLCC type capacitors, it is important to consider the ripple effect at the switching frequency due to effective ESR. A ceramic capacitor with a value of 0.1 μF must be connected between the BOOT and SW pins for proper operation. It is recommended to use a ceramic capacitor with X5R or better grade dielectric. Use a capacitor with a voltage rating of 25 V or higher. 5. R-C Snubber and VIN Pin High-Frequency Bypass Though it is possible to operate the IS6605A within absolute maximum ratings without ringing For detailed calculations, please contact the reduction techniques, some designs may require factory to obtain a user-friendly Excel based external components to further reduce ringing design tool. levels. This example uses two approaches: a high frequency power stage bypass capacitor on 4. Input Capacitor Selection the VIN pins, and an R-C snubber between the The IS6605A devices require a high-quality, PHASE area and GND. ceramic, type X5R or X7R, input decoupling capacitor with a value of at least 1 μF of The high-frequency VIN bypass capacitor is a effective capacitance on the VCC pin, relative to lossless ringing reduction technique which helps AGND. The power stage input decoupling minimizes the outboard parasitic inductances in capacitance (effective capacitance at the VIN and PGND pins) must be sufficient to supply the the power stage, which store energy during the high switching currents demanded when the low-side MOSFET on-time, and discharge once high-side MOSFET switches on, while providing the high-side MOSFET is turned on. For this minimal input voltage ripple as a result. This design twin 2.2 nF, 25 V, 0603 sized higheffective capacitance includes any DC bias frequency capacitors are used. The placement effects. The voltage rating of the input capacitor of these capacitors is critical to its effectiveness. must be greater than the maximum input It’s ideal placement is shown in PCB layout voltage. The capacitor must also have a ripple guidelines. current rating greater than the maximum input current ripple to the device during full load. The input ripple current can be calculated using the equation below. The value of a ceramic capacitor varies significantly over temperature and the amount of DC bias applied to the capacitor. The capacitance variations due to temperature can be minimized by selecting a dielectric material that is stable over temperature. X5R and X7R ceramic dielectrics are usually selected for power regulator capacitors because they have a high capacitance to volume ratio and are fairly stable over temperature. The input capacitor must also be selected with the DC bias taken into consideration. For this design example, a ceramic capacitor with at least a 25 V voltage rating is required to support the maximum input voltage. For this design, allow 0.1 V input ripple for VRIPPLE(cap), and 0.3 V input ripple for VRIPPLE(esr). the minimum input capacitance for this design is 38.5 µF, and the maximum ESR is Production Datasheet Innovision Semiconductor 18 IS6605A Rev2.0 6/2020 4. VCC capacitor should be placed as close to the IS6605A as possible. Connecting AGND Efficient PCB layout is crucial to the stable and PGND at VCC capacitor's grounding point is strongly recommended. operation of the circuit. For best PCB Layout Guidelines performance, follow the recommendations below. PCB layout 1.The input MLCC capacitors shall be placed as close as possible to the VIN and PGND pins of IS6605A. The MLCC capacitor shall be placed on the same side as that of IS6605A. The copper plane of VIN and PGND shall be maximized to minimize the parasitic impedance. 3. Place as many PGND vias as possible nearest to the PGND pin to minimize parasitic impedance and thermal resistance. Production Datasheet 5. Place the BST capacitor as close as possible to BST and PH pins. Routing width should be greater than 20mil. It is recommended to use a 0.1 µF to 1 µF bootstrap capacitance value Place BST resistance between the IC and the BST capacitor to achieve damping effect by limiting the speed of the FET being turned on. It is recommended to use a 3.3 Ω resistor for bootstrapping purpose. 6. Place the REF capacitor close to AGND pin. It is recommended to use a 22 nF to 220 nF capacitor. Innovision Semiconductor 19 IS6605A Rev2.0 6/2020 Typical Application Circuits Production Datasheet Innovision Semiconductor 20 IS6605A Rev2.0 6/2020 PCB Layout TOP Layer Production Datasheet Innovision Semiconductor 21 IS6605A Rev2.0 6/2020 Layer 2 Layer 3 Production Datasheet Innovision Semiconductor 22 IS6605A Rev2.0 6/2020 Bottom Layer Production Datasheet Innovision Semiconductor 23 IS6605A Rev2.0 6/2020 Package Dimension Production Datasheet Innovision Semiconductor 24 IS6605A Rev2.0 6/2020 Reflow Specification Qualification Reflow: The IS6606 was qualified in accordance with IPC/JEDEC J-STD-020D.01. This standard classifies proper packaging, storage, and handling in order to avoid subsequent thermal and mechanical damage during the solder reflow attachment phase of PCB assembly. The qualification preconditioning process specifies a sequence consisting of a bake cycle, moisture soak cycle (in a temperature humidity oven), and three consecutive solder reflow cycles, followed by functional device testing. SUPPLIER TP≥TC USER TP≤TC TC TC -5℃ SUPPLIER tp USER tp TP tp MAXIMUM RAMP UP RATE = 3℃/s MAXIMUM RAMP DOWM RATE = 6℃/s TL TSMAX PREHEAT AREA TC -5℃ tL TMEPERATURE[℃] TSMIN ts 25 TIME 25℃ TO PEAK TIME Production Reflow: PROFILE FEATURE SN - PB EUTECTIC ASSEMBLY PB-FREE ASSEMBLY Peak package body temperature (TP) For users, TP must not exceed For users, TP must not exceed TC(235℃).For suppliers, TP must TC(260℃).For suppliers, TP must equal or exceed TC(235℃). equal or exceed TC(260℃). Storage Specifications The storage specification of the IS6606 conforms to IPC/JEDEC J-STD-020D.01 Moisture Sensitivity Level (MSL) 3. After opening moisture-sealed bag Production Datasheet 168 hours -- Storage conditions: ambient ≤30°C at 60%RH Innovision Semiconductor 25 IS6605A Rev2.0 6/2020 TAPE AND REEL INFORMATION REEL DIMENSIONS TAPE DIMENSIONS E Discharging direction P1 P0 D0 P2 W F B0 . . . . T K0 . Pin1 A0 Reel Width NOTE: 1、CARRIER TAPE COLOR:BLACK. KEY PARAMETER LIST OF TAPE AND REEL 2、COVER TAPE WIDTH : 5.5±0.10. 3、COVER TAPE COLOR : TRANSPARENT. Package Type Reel Diameter (inch) Reel Width （mm） 13″ 9.5 13..00 QFN-14(2 x 3) 4、10 SPROCKET HOLE PITCH CUMULATIVE TOLERANCE ± 0.20MAX. 5、CAMBER NOT TO EXCEED 1MM IN 100MM. 6、MOLD#2X3X0.75/0.85. 7、BAN TO USE THE LEVEL 1 ENVIRONMENT-RELATED SUBSTANCES OF JCET PRESCRIBING. Unit(mm) ITEM DIM W A0 B0 K0 P0 P1 P2 F S E D0 T 8.00 3.30 ±0.10 2.30 ±0.10 1.1 ±0.10 4.00 ±0.10 4.00 ±0.10 2.00 ±0.05 3.50 ±0.05 0.00 ±0.10 1.75 ±0.10 1.50 0.20 ±0.02 +0.30 - 0.10 Production Datasheet Innovision Semiconductor +0.10 - 0.00 26