HFA1405
TM
Data Sheet
August 2000
Quad, 675MHz, Low Power, Video
Operational Amplifier
File Number
3604.6
Features
• Low Supply Current . . . . . . . . . . . . . . . . . 5.8mA/Op Amp
The HFA1405 is a quad, high speed, low power current
feedback amplifier built with Intersil’s proprietary
complementary bipolar UHF-1 process.
• High Input Impedance . . . . . . . . . . . . . . . . . . . . . . . 1MΩ
• Wide -3dB Bandwidth (AV = +2) . . . . . . . . . . . . . . 675MHz
These amplifiers deliver up to 675MHz bandwidth and
2500V/µs slew rate, on only 58mW of quiescent power. They
are specifically designed to meet the performance, power,
and cost requirements of high volume video applications.
The excellent gain flatness and differential gain/phase
performance make these amplifiers well suited for
component or composite video applications. Video
performance is maintained even when driving a back
terminated cable (RL = 150Ω), and degrades only slightly
when driving two back terminated cables (RL = 75Ω). RGB
applications will benefit from the high slew rates, and high
full power bandwidth.
• Very Fast Slew Rate . . . . . . . . . . . . . . . . . . . . . . 2500V/µs
The HFA1405 is a pin compatible, low power, high
performance upgrade for the popular Intersil HA5025, and
for the CLC414 and CLC415.
• Professional Video Processing
• Gain Flatness (to 50MHz) . . . . . . . . . . . . . . . . . . . . ±0.03dB
• Differential Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.02%
• Differential Phase . . . . . . . . . . . . . . . . . . . . 0.03 Degrees
• All Hostile Crosstalk (5MHz). . . . . . . . . . . . . . . . . . -60dB
• Pin Compatible Upgrade to HA5025, CLC414, and
CLC415
Applications
• Flash A/D Drivers
• Video Digitizing Boards/Systems
• Multimedia Systems
Ordering Information
PART NUMBER
• RGB Preamps
TEMP.
RANGE (oC)
PACKAGE
PKG. NO.
HFA1405IB
-40 to 85
14 Ld SOIC
M14.15
HFA1405IP
-40 to 85
14 Ld PDIP
E14.3
HFA1405IA
-40 to 85
16 Ld SSOP
M16.15A
HA5025EVAL
High Speed Op Amp DIP Evaluation Board
OPAMPSSOPEVAL1 High Speed Op Amp SSOP Evaluation Board
• Medical Imaging
• Hand Held and Miniaturized RF Equipment
• Battery Powered Communications
• High Speed Oscilloscopes and Analyzers
Related Literature
• Technical Brief TB363 “Guidelines for Handling and
Processing Moisture Sensitive Surface Mount Devices
(SMDs)”
Pinouts
OUT 1 1
-
+
+IN 1 3
12 +IN 4
V+ 4
-
10 +IN 3
9 -IN 3
8 OUT 3
OUT 2 7
-
+IN 1 3
+IN 2 5
-IN 2 6
OUT 2 7
15 -IN 4
14 +IN 4
V+ 4
NC 8
1
-
13 V+
-
-IN 1 2
16 OUT 4
+
+
-IN 2 6
11 V+
+IN 2 5
13 -IN 4
+
-
OUT 1 1
+
-IN 1 2
14 OUT 4
HFA1405 (SSOP)
TOP VIEW
+
HFA1405 (PDIP, SOIC)
TOP VIEW
-
-
12 +IN 3
11 -IN 3
10 OUT 3
9 NC
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Corporation. | Copyright © Intersil Corporation 2000
HFA1405
Absolute Maximum Ratings
TA = 25oC
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA (oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
90
PDIP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
100
SSOP Package . . . . . . . . . . . . . . . . . . . . . . . . . . . .
140
Moisture Sensitivity (see Technical Brief TB363)
All Packages. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Level 1
Maximum Junction Temperature (Die) . . . . . . . . . . . . . . . . . . . 175oC
Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC
Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC
(SOIC and SSOP - Lead Tips Only)
Voltage Between V+ and V- . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11V
DC Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VSUPPLY
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5V
Output Current (Note 2) . . . . . . . . . . . . . . . . .Short Circuit Protected
30mA Continuous
60mA ≤ 50% Duty Cycle
ESD Rating
Human Body Model (Per MIL-STD-883 Method 3015.7) . . . 600V
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . . -40oC to 85oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTES:
1. θJA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
2. Output is short circuit protected to ground. Brief short circuits to ground will not degrade reliability, however continuous (100% duty cycle) output
current must not exceed 30mA for maximum reliability.
Electrical Specifications
PARAMETER
VSUPPLY = ±5V, AV = +1, RF = 510Ω , RL = 100Ω , Unless Otherwise Specified
TEST
CONDITIONS
(NOTE 4)
TEST
TEMP
LEVEL
(oC)
HFA1405IB (SOIC)
HFA1405IP (PDIP)
HFA1405IA (SSOP)
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
5
-
2
5
-
2
5
mV
INPUT CHARACTERISTICS
Input Offset Voltage
A
25
-
2
A
Full
-
3
8
-
3
8
-
3
8
mV
B
Full
-
1
10
-
1
10
-
1
10
µV/oC
∆VCM = ±1.8V
A
25
45
48
-
45
48
-
45
48
-
dB
Average Input Offset
Voltage Drift
Input Offset Voltage
Common-Mode Rejection
Ratio
Input Offset Voltage
Power Supply Rejection
Ratio
∆VCM = ±1.8V
A
85
43
46
-
43
46
-
43
46
-
dB
∆VCM = ±1.2V
A
-40
43
46
-
43
46
-
43
46
-
dB
∆VPS = ±1.8V
A
25
48
52
-
48
52
-
48
52
-
dB
∆VPS = ±1.8V
A
85
46
48
-
46
48
-
46
48
-
dB
∆VPS = ±1.2V
A
-40
46
48
-
46
48
-
46
48
-
dB
Non-Inverting Input Bias
Current
A
25
-
6
15
-
6
15
-
6
15
µA
A
Full
-
10
25
-
10
25
-
10
25
µA
Non-Inverting Input Bias
Current Drift
B
Full
-
5
60
-
5
60
-
5
60
nA/oC
∆VPS = ±1.8V
A
25
-
0.5
1
-
0.5
1
-
0.5
1
µA/V
∆VPS = ±1.8V
A
85
-
0.8
3
-
0.8
3
-
0.8
3
µA/V
∆VPS = ±1.2V
A
-40
-
0.8
3
-
0.8
3
-
0.8
3
µA/V
∆VCM = ±1.8V
A
25
0.8
1.2
-
0.8
1.2
-
0.8
1.2
-
MΩ
∆VCM = ±1.8V
A
85
0.5
0.8
-
0.5
0.8
-
0.5
0.8
-
MΩ
Non-Inverting Input Bias
Current Power Supply
Sensitivity
Non-Inverting Input
Resistance
∆VCM = ±1.2V
A
-40
0.5
0.8
-
0.5
0.8
-
0.5
0.8
-
MΩ
A
25
-
2
7.5
-
2
7.5
-
2
7.5
µA
A
Full
-
5
15
-
5
15
-
5
15
µA
B
Full
-
60
200
-
60
200
-
60
200
nA/oC
∆VCM = ±1.8V
A
25
-
3
6
-
3
6
-
3
6
µA/V
∆VCM = ±1.8V
A
85
-
4
8
-
4
8
-
4
8
µA/V
∆VCM = ±1.2V
A
-40
-
4
8
-
4
8
-
4
8
µA/V
Inverting Input Bias Current
Inverting Input Bias Current
Drift
Inverting Input Bias Current
Common-Mode Sensitivity
2
HFA1405
Electrical Specifications
PARAMETER
Inverting Input Bias Current
Power Supply Sensitivity
VSUPPLY = ±5V, AV = +1, RF = 510Ω , RL = 100Ω , Unless Otherwise Specified (Continued)
TEST
CONDITIONS
(NOTE 4)
TEST
TEMP
LEVEL
(oC)
HFA1405IB (SOIC)
HFA1405IP (PDIP)
HFA1405IA (SSOP)
MIN
TYP
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
∆VPS = ±1.8V
A
25
-
2
5
-
2
5
-
2
5
µA/V
∆VPS = ±1.8V
A
85
-
4
8
-
4
8
-
4
8
µA/V
A
-40
-
4
8
-
4
8
-
4
8
µA/V
Inverting Input Resistance
∆VPS = ±1.2V
C
25
-
60
-
-
60
-
-
60
-
Ω
Input Capacitance
B
25
-
1.4
-
-
2.2
-
-
1.2
-
pF
Input Voltage Common
Mode Range (Implied by
VIO CMRR, +RIN, and
-IB-IAS CMS Tests)
A
25, 85
±1.8
±2.4
-
±1.8
±2.4
-
±1.8
±2.4
-
V
A
-40
±1.2
±1.7
-
±1.2
±1.7
-
±1.2
±1.7
-
V
Input Noise Voltage Density f = 100kHz
B
25
-
3.5
-
-
3.5
-
-
3.5
-
nV/√Hz
Non-Inverting Input Noise
Current Density
f = 100kHz
B
25
-
2.5
-
-
2.5
-
-
2.5
-
pA/√Hz
Inverting Input Noise Current f = 100kHz
Density
B
25
-
20
-
-
20
-
-
20
-
pA/√Hz
C
25
-
500
-
-
500
-
-
500
-
kΩ
TRANSFER CHARACTERISTICS
Open Loop
Transimpedance Gain
AV = -1
AC CHARACTERISTICS (Note 3)
-3dB Bandwidth
(VOUT = 0.2VP-P,
Notes 3, 5)
Full Power Bandwidth
(VOUT = 5VP-P,
Notes 3, 5)
Gain Flatness
(VOUT = 0.2VP-P,
Notes 3, 5)
AV = -1
B
25
-
420
-
-
360
-
-
450
-
MHz
AV = +2
B
25
-
560
-
-
400
-
-
675
-
MHz
AV = +6
B
25
-
140
-
-
100
-
-
-
-
MHz
AV = -1
B
25
-
260
-
-
260
-
-
290
-
MHz
AV = +2
B
25
-
165
-
-
165
-
-
190
-
MHz
AV = +6
B
25
-
140
-
-
100
-
-
-
-
MHz
AV = -1, 25MHz
B
25
-
±0.03
-
-
±0.04
-
-
±0.03
-
dB
AV = -1, 50MHz
B
25
-
±0.04
-
-
±0.04
-
-
±0.06
-
dB
AV = -1, 100MHz
B
25
-
±0.09
-
-
±0.06
-
-
±0.07
-
dB
AV = +2, 25MHz
B
25
-
±0.03
-
-
±0.04
-
-
±0.04
-
dB
AV = +2, 50MHz
B
25
-
±0.03
-
-
±0.04
-
-
±0.08
-
dB
AV = +2, 100MHz
B
25
-
±0.07
-
-
±0.06
-
-
±0.09
-
dB
AV = +6, 15MHz
B
25
-
±0.08
-
-
±0.08
-
-
−
-
dB
AV = +6, 30MHz
B
25
-
±0.19
-
-
±0.27
-
-
−
-
dB
Minimum Stable Gain
Crosstalk
(AV = +1, All Channels
Hostile, Note 5)
A
Full
-
1
-
-
1
-
-
1
-
V/V
5MHz
B
25
-
-60
-
-
-55
-
-
-59
-
dB
10MHz
B
25
-
-56
-
-
-52
-
-
-56
-
dB
±3.4
-
±3
±3.4
-
±3
±3.4
-
V
OUTPUT CHARACTERISTICS AV = +2 (Note 3), Unless Otherwise Specified
Output Voltage Swing
(Note 5)
AV = -1,
RL = 100Ω
Output Current
(Note 5)
AV = -1,
RL = 50Ω
25
±3
A
Full
±2.8
±3
-
±2.8
±3
-
±2.8
±3
-
V
A
25, 85
50
60
-
50
60
-
50
60
-
mA
A
A
-40
28
42
-
28
42
-
28
42
-
mA
Output Short Circuit Current
B
25
-
90
-
-
90
-
-
90
-
mA
Closed Loop Output
Impedance
B
25
-
0.2
-
-
0.2
-
-
0.2
-
Ω
Second Harmonic Distortion 10MHz
(VOUT = 2VP-P, Note 5)
20MHz
B
25
-
-51
-
-
-51
-
-
-51
-
dBc
B
25
-
-46
-
-
-46
-
-
-46
-
dBc
Third Harmonic Distortion
(VOUT = 2VP-P, Note 5)
10MHz
B
25
-
-63
-
-
-63
-
-
-63
-
dBc
20MHz
B
25
-
-56
-
-
-56
-
-
-56
-
dBc
3
HFA1405
Electrical Specifications
PARAMETER
VSUPPLY = ±5V, AV = +1, RF = 510Ω , RL = 100Ω , Unless Otherwise Specified (Continued)
TEST
CONDITIONS
(NOTE 4)
TEST
TEMP
LEVEL
(oC)
HFA1405IB (SOIC)
HFA1405IP (PDIP)
HFA1405IA (SSOP)
MIN
MAX
MIN
TYP
MAX
MIN
TYP
MAX
UNITS
0.6
-
ns
TYP
TRANSIENT CHARACTERISTICS AV = +2 (Note 3), Unless Otherwise Specified
Rise and Fall Times
(VOUT = 0.5VP-P, Note 3)
AV = +2
Overshoot
(VOUT = 0.5VP-P, VIN
tRISE = 1ns, Notes 3, 6)
Slew Rate
(VOUT = 5VP-P,
Notes 3, 5)
Settling Time
(VOUT = +2V to 0V Step,
Note 5)
Overdrive Recovery Time
VIDEO CHARACTERISTICS
Differential Gain
(f = 3.58MHz)
B
25
-
0.8
-
-
0.9
-
-
AV = +6
B
25
-
2.9
-
-
4
-
-
-
-
ns
AV = -1, +OS
B
25
-
7
-
-
3
-
-
2
-
%
AV = -1, -OS
B
25
-
8
-
-
13
-
-
8
-
%
AV = +2, +OS
B
25
-
5
-
-
7
-
-
5
-
%
AV = +2, -OS
B
25
-
10
-
-
11
-
-
5
-
%
AV = +6, +OS
B
25
-
2
-
-
2
-
-
-
-
%
AV = +6, -OS
B
25
-
2
-
-
2
-
-
-
-
%
AV = -1, +SR
B
25
-
2500
-
-
2500
-
-
2900
-
V/µs
AV = -1, -SR
B
25
-
1900
-
-
1900
-
-
2500
-
V/µs
AV = +2, +SR
B
25
-
1700
-
-
1600
-
-
2100
-
V/µs
AV = +2, -SR
B
25
-
1700
-
-
1400
-
-
1900
-
V/µs
AV = +6, +SR
B
25
-
1500
-
-
1000
-
-
-
-
V/µs
AV = +6, -SR
B
25
-
1100
-
-
1000
-
-
-
-
V/µs
To 0.1%
B
25
-
23
-
-
23
-
-
30
-
ns
To 0.05%
B
25
-
30
-
-
30
-
-
33
-
ns
To 0.025%
B
25
-
37
-
-
40
-
-
50
-
ns
VIN = ±2V
B
25
-
8.5
-
-
8.5
-
-
8.5
-
ns
AV = +2 (Note 3), Unless Otherwise Specified
RL = 150Ω
B
25
-
0.02
-
-
0.03
-
-
0.02
-
%
RL = 75Ω
B
25
-
0.03
-
-
0.06
-
-
0.03
-
%
RL = 150Ω
B
25
-
0.03
-
-
0.03
-
-
0.03
-
Degrees
RL = 75Ω
B
25
-
0.06
-
-
0.06
-
-
0.06
-
Degrees
Power Supply Range
C
25
±4.5
-
±5.5
±4.5
-
±5.5
±4.5
-
±5.5
V
Power Supply Current
(Note 5)
A
25
-
5.8
6.1
-
5.8
6.1
-
5.8
6.1
mA/Op
Amp
A
Full
-
5.9
6.3
-
5.9
6.3
-
5.9
6.3
mA/Op
Amp
Differential Phase
(f = 3.58MHz)
POWER SUPPLY CHARACTERISTICS
NOTES:
3. The optimum feedback resistor depends on closed loop gain and package type. See the “Optimum Feedback Resistor” table in the Application
Information section for details.
4. Test Level: A. Production Tested; B. Typical or Guaranteed Limit Based on Characterization; C. Design Typical for Information Only.
5. See Typical Performance Curves for more information.
6. Undershoot dominates for output signal swings below GND (e.g., 2VP-P), yielding a higher overshoot limit compared to the VOUT = 0V to 2V
condition. See the “Application Information” section for details.
Application Information
Performance Differences Between Packages
The amplifiers comprising the HFA1405 are high frequency
current feedback amplifiers. As such, they are sensitive to
feedback capacitance which destabilizes the op amp and
causes overshoot and peaking. Unfortunately, the standard
quad op amp pinout places the amplifier’s output next to its
inverting input, thus making the package capacitance an
unavoidable parasitic feedback capacitor. The larger
4
parasitic capacitance of the PDIP requires an inherently
more stable amplifier, which yields a PDIP device with lower
performance than the SOIC and SSOP devices - see
Electrical Specification tables for details.
Because of these performance differences, designers
should evaluate and breadboard with the same package
style to be used in production.
Note that the “Typical Performance Curves” section has
separate pulse and frequency response graphs for each
HFA1405
package type. Graphs not labeled with a specific package
type are applicable to all packages.
Optimum Feedback Resistor
Although a current feedback amplifier’s bandwidth
dependency on closed loop gain isn’t as severe as that of a
voltage feedback amplifier, there can be an appreciable
decrease in bandwidth at higher gains. This decrease may
be minimized by taking advantage of the current feedback
amplifier’s unique relationship between bandwidth and RF.
All current feedback amplifiers require a feedback resistor,
even for unity gain applications, and RF, in conjunction with
the internal compensation capacitor, sets the dominant pole
of the frequency response. Thus, the amplifier’s bandwidth is
inversely proportional to RF. The HFA1405 design is
optimized for RF = 402Ω/510Ω/681Ω (PDIP/SOIC/SSOP) at
a gain of +2. Decreasing RF decreases stability, resulting in
excessive peaking and overshoot (Note: Capacitive
feedback causes the same problems due to the feedback
impedance decrease at higher frequencies). However, at
higher gains the amplifier is more stable so RF can be
decreased in a trade-off of stability for bandwidth.
The table below lists recommended RF values for various
gains, and the expected bandwidth. For good channel-tochannel gain matching, it is recommended that all resistors
(termination as well as gain setting) be ±1% tolerance or
better.
TABLE 1. OPTIMUM FEEDBACK RESISTOR
GAIN
(ACL)
RF (Ω)
PDIP/SOIC/SSOP
BANDWIDTH (MHz)
PDIP/SOIC/SSOP
-1
310/360/432
360/420/450
+1
510 (+RS = 510)/
464 (+RS = 649)/
681 (+RS = 806)
300/375/330
+2
402/510/681
400/560/675
+5
NA/200/649
NA/330/200
+6
500/500/NA (Note)
100/140/NA
+10
NA/180/681
NA/140/120
NOTE: RF = 500Ω is not the optimum value. It was chosen to
match the RF of the CLC414 and CLC415, for performance
comparison purposes. Performance at AV = +6 may be increased by
reducing RF below 500Ω.
Non-inverting Input Source Impedance
For best operation, the DC source impedance seen by the
non-inverting input should be ≥ 50Ω. This is especially
important in inverting gain configurations where the noninverting input would normally be connected directly to GND.
Pulse Undershoot
The HFA1405 utilizes a quasi-complementary output stage
to achieve high output current while minimizing quiescent
supply current. In this approach, a composite device
replaces the traditional PNP pulldown transistor. The
5
composite device switches modes after crossing 0V,
resulting in added distortion for signals swinging below
ground, and an increased undershoot on the negative
portion of the output waveform (see Figure 8 and Figure 11).
This undershoot isn’t present for small bipolar signals, or
large positive signals (see Figure 6 and Figure 7).
PC Board Layout
The frequency response of this amplifier depends greatly on
the amount of care taken in designing the PC board. The
use of low inductance components such as chip
resistors and chip capacitors is strongly recommended,
while a solid ground plane is a must!
Attention should be given to decoupling the power supplies.
A large value (10µF) tantalum in parallel with a small value
(0.1µF) chip capacitor works well in most cases.
Terminated microstrip signal lines are recommended at the
input and output of the device. Capacitance, parasitic or
planned, connected to the output must be minimized, or
isolated as discussed in the next section.
Care must also be taken to minimize the capacitance to
ground at the amplifier’s inverting input (-IN). The larger this
capacitance, the worse the gain peaking, resulting in pulse
overshoot and eventual instability. To reduce this
capacitance the designer should remove the ground plane
under traces connected to -IN, and keep connections to -IN
as short as possible.
An example of a good high frequency layout is the
Evaluation Boards shown in Figures 3 and 5.
Driving Capacitive Loads
Capacitive loads, such as an A/D input, or an improperly
terminated transmission line will degrade the amplifier’s
phase margin resulting in frequency response peaking and
possible oscillations. In most cases, the oscillation can be
avoided by placing a resistor (RS) in series with the output
prior to the capacitance.
Figure 1 details starting points for the selection of this
resistor. The points on the curve indicate the RS and CL
combinations for the optimum bandwidth, stability, and
settling time, but experimental fine tuning is recommended.
Picking a point above or to the right of the curve yields an
overdamped response, while points below or left of the curve
indicate areas of underdamped performance.
RS and CL form a low pass network at the output, thus limiting
system bandwidth well below the amplifier bandwidth of
560MHz. By decreasing RS as CL increases (as illustrated in
the curve), the maximum bandwidth is obtained without
HFA1405
sacrificing stability. In spite of this, bandwidth still decreases
as the load capacitance increases.
TOP LAYOUT
SERIES OUTPUT RESISTANCE (Ω)
50
40
30
20
AV = +2
10
0
0
50
100
150
200
250
300
350
400
LOAD CAPACITANCE (pF)
BOTTOM LAYOUT
FIGURE 1. RECOMMENDED SERIES OUTPUT RESISTOR vs
LOAD CAPACITANCE
Evaluation Board
The performance of the HFA1405 PDIP or SOIC can be
evaluated using the HA5025 Evaluation Board. The
HFA1405IB (SOIC) requires a SOIC to DIP adaptor like the
Aries Electronics Part Number 14-350000-10. The SSOP
version can be evaluated using the OPAMPSSOPEVAL
board.
The schematic for the PDIP/SOIC amplifier 1 and the
HA5025EVAL board layout are shown in Figure 2 and
Figure 3. Resistors RF, RG , and +RS may require a
change to values applicable to the HFA1405.
FIGURE 3. EVALUATION BOARD LAYOUT FOR PDIP/SOIC
The schematic for the SSOP amplifier 1 and the
OPAMPSSOPEVAL board layout are shown in Figure 4 and
Figure 5. Resistors RF, RG , and +RS may require a change
to values applicable to the HFA1405IA.
To order evaluation boards (part number HA5025EVAL or
OPAMPSSOPEVAL), please contact your local sales office.
49.9Ω
OUT
RF
2
RG
IN
49.9Ω
3
RG
RF
1
2
IN
50Ω
+RS
3
14
10µF
12
4
10
0.1µF 6
9
7
8
10µF
GND
GND
FIGURE 2. EVALUATION BOARD SCHEMATIC FOR PDIP/SOIC
6
12
0Ω
4
11
5
10
0.1µF 6
9
7
8
0.1µF
-5V
10µF
0Ω
GND
-5V
0.1µF
+5V
10µF
13
GND
11
5
+
+5V
13
+
14
+RS
50Ω
OUT
1
FIGURE 4. EVALUATION BOARD SCHEMATIC FOR SSOP
HFA1405
TOP LAYOUT
BOTTOM LAYOUT
FIGURE 5. EVALUATION BOARD LAYOUT FOR SSOP
Typical Performance Curves
VSUPPLY = ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table,
RL = 100Ω, Unless Otherwise Specified
160
1.6
AV = +2
SOIC
1.2
80
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (mV)
AV = +2
120 SOIC
40
0
-40
-80
0.8
0.4
0
-0.4
-0.8
-120
-1.2
-160
-1.6
TIME (5ns/DIV.)
TIME (5ns/DIV.)
FIGURE 6. SMALL SIGNAL PULSE RESPONSE
FIGURE 7. LARGE SIGNAL POSITIVE PULSE RESPONSE
1.6
120
OUTPUT VOLTAGE (mV)
OUTPUT VOLTAGE (V)
1.2
160
AV = +2
SOIC
0.8
0.4
0
-0.4
-0.8
-1.2
AV = -1
SOIC
80
40
0
-40
-80
-120
-1.6
TIME (5ns/DIV.)
FIGURE 8. LARGE SIGNAL BIPOLAR PULSE RESPONSE
7
-160
TIME (5ns/DIV.)
FIGURE 9. SMALL SIGNAL PULSE RESPONSE
HFA1405
Typical Performance Curves
VSUPPLY = ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table,
RL = 100Ω, Unless Otherwise Specified (Continued)
1.6
1.2
OUTPUT VOLTAGE (V)
0.8
0.4
0
-0.4
AV = -1
SOIC
0.8
0.4
0
-0.4
-0.8
-0.8
-1.2
-1.2
-1.6
-1.6
TIME (5ns/DIV.)
TIME (5ns/DIV.)
FIGURE 10. LARGE SIGNAL POSITIVE PULSE RESPONSE
FIGURE 11. LARGE SIGNAL BIPOLAR PULSE RESPONSE
1.6
160
1.2
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (mV)
120
AV = +6
SOIC
80
40
0
-40
-80
AV = +6
SOIC
0.8
0.4
0
-0.4
-0.8
-120
-1.2
-160
-1.6
TIME (5ns/DIV.)
TIME (5ns/DIV.)
VOUT = 200mVP-P
6
SOIC
3
AV = +2
GAIN
0
AV = -1
-3
AV = +6
PHASE
0
90
AV = +6
180
AV = -1
AV = +2
270
360
0.3
1
10
100
FREQUENCY (MHz)
FIGURE 14. FREQUENCY RESPONSE
8
800
NORMALIZED GAIN (dB)
FIGURE 13. LARGE SIGNAL PULSE RESPONSE
NORMALIZED PHASE (DEGREES)
NORMALIZED GAIN (dB)
FIGURE 12. SMALL SIGNAL PULSE RESPONSE
2
AV = +2
VOUT = 200mVP-P
1
SOIC
0
RF = 500Ω
RF = 683Ω
RF = 750Ω
GAIN
-1
RF = 1kΩ
RF = 1.5kΩ
-2
-3
RF = 1.5kΩ
PHASE
0
90
180
270
RF = 500Ω
1
10
100
FREQUENCY (MHz)
PHASE (DEGREES)
OUTPUT VOLTAGE (V)
1.2
1.6
AV = -1
SOIC
360
800
FIGURE 15. FREQUENCY RESPONSE vs FEEDBACK RESISTOR
HFA1405
Typical Performance Curves
VSUPPLY = ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table,
RL = 100Ω, Unless Otherwise Specified (Continued)
0.3
0.2
AV = +2, SOIC
VOUT = 200mVP-P
0.1
SOIC
0.1
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
0.2
VOUT = 200mVP-P
AV = -1
0
-0.1
AV = +2
-0.2
-0.3
-0.4
AV = +6
-0.5
RF = 500Ω
0
-0.1
RF = 683Ω
-0.2
-0.3
RF = 750Ω
-0.4
RF = 1kΩ
-0.5
RF = 1.5kΩ
-0.6
-0.6
-0.7
-0.7
1
10
FREQUENCY (MHz)
-0.8
100
FIGURE 16. GAIN FLATNESS
1
10
FREQUENCY (MHz)
100
FIGURE 17. GAIN FLATNESS vs FEEDBACK RESISTOR
-10
0.2
-30
0.15
SETTLING ERROR (%)
CROSSTALK (dB)
SOIC
-20
RL = 100Ω
-40
-50
-60
RL =
∞
-70
-80
0.1
-0.1
-90
-100
-0.2
1
10
FREQUENCY (MHz)
100
0
200
15
20
25
30
TIME (ns)
35
40
45
50
80
40
0
-40
-80
-120
AV = +2
SSOP
1.2
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (mV)
10
1.6
AV = +2
SSOP
120
5
FIGURE 19. SETTLING RESPONSE
FIGURE 18. ALL HOSTILE CROSSTALK
160
SOIC
0.05
0.025
0
-0.025
-0.05
-0.15
-110
0.3
AV = +2
VOUT = 2V
0.8
0.4
0
-0.4
-0.8
-1.2
-160
-1.6
TIME (5ns/DIV.)
FIGURE 20. SMALL SIGNAL PULSE RESPONSE
9
TIME (5ns/DIV.)
FIGURE 21. LARGE SIGNAL POSITIVE PULSE RESPONSE
HFA1405
Typical Performance Curves
VSUPPLY = ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table,
RL = 100Ω, Unless Otherwise Specified (Continued)
1.6
160
AV = +2
SSOP
1.2
120
80
OUTPUT VOLTAGE (mV)
OUTPUT VOLTAGE (V)
0.8
0.4
0
-0.4
-0.8
-1.2
40
0
-40
-80
-120
-1.6
-160
TIME (5ns/DIV.)
TIME (5ns/DIV.)
FIGURE 22. LARGE SIGNAL BIPOLAR PULSE RESPONSE
FIGURE 23. SMALL SIGNAL PULSE RESPONSE
1.6
1.6
1.2
AV = -1
SSOP
1.2
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (V)
AV = -1
SSOP
0.8
0.8
0.4
0
-0.4
-0.8
0.4
0
-0.4
-0.8
-1.2
-1.2
-1.6
-1.6
TIME (5ns/DIV.)
TIME (5ns/DIV.)
FIGURE 24. LARGE SIGNAL POSITIVE PULSE RESPONSE
FIGURE 25. LARGE SIGNAL BIPOLAR PULSE RESPONSE
1.6
160
AV = +1
SSOP
120
AV = +1
SSOP
1.2
0.8
80
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (mV)
AV = -1
SSOP
40
0
-40
-80
0.4
0
-0.4
-0.8
-1.2
-120
-1.6
-160
TIME (5ns/DIV.)
FIGURE 26. SMALL SIGNAL PULSE RESPONSE
10
TIME (5ns/DIV.)
FIGURE 27. LARGE SIGNAL BIPOLAR PULSE RESPONSE
HFA1405
Typical Performance Curves
VSUPPLY = ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table,
RL = 100Ω, Unless Otherwise Specified (Continued)
1.6
160
AV = +5
SSOP
1.2
0.8
80
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (mV)
AV = +5
SSOP
120
40
0
-40
-80
0.4
0
-0.4
-0.8
-1.2
-120
-1.6
-160
TIME (5ns/DIV.)
TIME (5ns/DIV.)
FIGURE 28. SMALL SIGNAL PULSE RESPONSE
1.6
160
AV = +10
AV = +10
SSOP
120
SSOP
1.2
0.8
80
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (mV)
FIGURE 29. LARGE SIGNAL BIPOLAR PULSE RESPONSE
40
0
-40
-80
0.4
0
-0.4
-0.8
-1.2
-120
-1.6
-160
TIME (10ns/DIV.)
TIME (10ns/DIV.)
VOUT = 200mVP-P
SSOP
AV = +2
0
GAIN
AV = -1
-3
-6
AV = +1
0
AV = +2
PHASE
90
180
AV = -1
AV = +1
1
10
100
FREQUENCY (MHz)
FIGURE 32. FREQUENCY RESPONSE
11
VOUT = 200mVP-P
SSOP
4
270
360
1000
NORMALIZED GAIN (dB)
3
FIGURE 31. LARGE SIGNAL BIPOLAR PULSE RESPONSE
NORMALIZED PHASE (DEGREES)
NORMALIZED GAIN (dB)
FIGURE 30. SMALL SIGNAL PULSE RESPONSE
3
2
1
0
-1
AV = +10
-2
AV = +5
-3
-4
1
10
100
FREQUENCY (MHz)
FIGURE 33. FREQUENCY RESPONSE
1000
HFA1405
Typical Performance Curves
VSUPPLY = ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table,
RL = 100Ω, Unless Otherwise Specified (Continued)
VOUT = 5VP-P
4
0.3
SSOP
3
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
AV = -1
VOUT = 200mVP-P
SSOP
0.4
0.2
0.1
AV = +1
0
-0.1
-0.2
AV = +2
-0.3
2
1
AV = -1
0
AV = +1
-1
-2
-3
-0.4
-4
AV = +2
1
10
FREQUENCY (MHz)
100
200
1
10
100
FREQUENCY (MHz)
1000
FIGURE 35. FULL POWER BANDWIDTH
FIGURE 34. GAIN FLATNESS
-10
AV = +2
VOUT = 2V
SSOP
-20
0.1
SSOP
SETTLING ERROR (%)
CROSSTALK (dB)
-30
-40
-50
RL = 100Ω
-60
-70
RL = ∞
-80
-90
0.05
0.025
0
-0.025
-0.05
-0.1
-100
-110
0.3
1
10
FREQUENCY (MHz)
10
100
1.6
AV = +2
PDIP
1.2
80
40
0
-40
-80
-120
40
50
60
70
80
90
FIGURE 37. SETTLING RESPONSE
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (mV)
120
30
TIME (ns)
FIGURE 36. ALL HOSTILE CROSSTALK
160
20
AV = +2
PDIP
0.8
0.4
0
-0.4
-0.8
-1.2
-160
-1.6
TIME (5ns/DIV.)
FIGURE 38. SMALL SIGNAL PULSE RESPONSE
12
TIME (5ns/DIV.)
FIGURE 39. LARGE SIGNAL PULSE RESPONSE
100
HFA1405
Typical Performance Curves
VSUPPLY = ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table,
RL = 100Ω, Unless Otherwise Specified (Continued)
160
PDIP
1.2
80
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (mV)
120
1.6
AV = -1
40
0
-40
AV = -1
PDIP
0.8
0.4
0
-0.4
-80
-0.8
-120
-1.2
-1.6
-160
TIME (5ns/DIV.)
TIME (5ns/DIV.)
FIGURE 40. SMALL SIGNAL PULSE RESPONSE
160
1.6
AV = +1
PDIP
1.2
80
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (mV)
120
FIGURE 41. LARGE SIGNAL PULSE RESPONSE
40
0
-40
AV = +1
PDIP
0.8
0.4
0
-0.4
-80
-0.8
-120
-1.2
-1.6
-160
TIME (5ns/DIV.)
TIME (5ns/DIV.)
FIGURE 42. SMALL SIGNAL PULSE RESPONSE
160
1.6
+6
AA
VV==+2
PDIP
PDIP
RF = 150Ω
1.2
80
OUTPUT VOLTAGE (V)
OUTPUT VOLTAGE (mV)
120
FIGURE 43. LARGE SIGNAL PULSE RESPONSE
40
0
-40
-80
-120
AV = +6
PDIP
RF = 150Ω
0.8
0.4
0
-0.4
-0.8
-1.2
-160
-1.6
TIME (5ns/DIV.)
FIGURE 44. SMALL SIGNAL PULSE RESPONSE
13
TIME (5ns/DIV.)
FIGURE 45. LARGE SIGNAL PULSE RESPONSE
HFA1405
Typical Performance Curves
VSUPPLY = ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table,
RL = 100Ω, Unless Otherwise Specified (Continued)
1.6
160
AV = +6
PDIP
RF = 500Ω
1.2
OUTPUT VOLTAGE (V)
80
40
0
-40
0.8
0.4
0
-0.4
-80
-0.8
-120
-1.2
-160
AV = +6
PDIP
RF = 500Ω
-1.6
TIME (5ns/DIV.)
TIME (5ns/DIV.)
VOUT = 200mVP-P
PDIP
3
AV = +2
GAIN
0
-3
PHASE
AV = -1
AV = +1 (RF = +RS = 510Ω)
0
-6
90
AV = +2
AV = -1
AV = +1
180
270
360
0.3
1
10
100
NORMALIZED GAIN (dB)
FIGURE 47. LARGE SIGNAL PULSE RESPONSE
NORMALIZED PHASE (DEGREES)
NORMALIZED GAIN (dB)
FIGURE 46. SMALL SIGNAL PULSE RESPONSE
AV = +6
VOUT = 200mVP-P
3
PDIP
0
GAIN
RF = 150Ω
RF = 500Ω
-3
0
-6
PHASE
90
RF = 500Ω
RF = 150Ω
180
270
360
0.3
800
1
10
100
PHASE (DEGREES)
OUTPUT VOLTAGE (mV)
120
800
FREQUENCY (MHz)
FREQUENCY (MHz)
FIGURE 48. FREQUENCY RESPONSE
FIGURE 49. FREQUENCY RESPONSE
2
VOUT = 5VP-P
NORMALIZED GAIN (dB)
NORMALIZED GAIN (dB)
3
AV = -1
PDIP
1
0
AV = +2
-1
-2
-3
-4
AV = +2
2
RF = 390Ω
VOUT = 200mVP-P
1
RF = 365Ω
PDIP
0
-1
RF = 422Ω
-2
RF = 510Ω
-3
AV = +6 (RF = 500Ω)
AV = +6
(RF = 150Ω)
0.3
1
10
100
FREQUENCY (MHz)
FIGURE 50. FULL POWER BANDWIDTH
14
800
1
10
100
800
FREQUENCY (MHz)
FIGURE 51. FREQUENCY RESPONSE vs FEEDBACK RESISTOR
HFA1405
Typical Performance Curves
VSUPPLY = ±5V, TA = 25oC, RF = Value From the Optimum Feedback Resistor Table,
PDIP
VOUT = 200mVP-P
0.2
PDIP
AV = +1 (RF = +RS = 510Ω)
0.1
-10
AV = +2
-20
0
-30
CROSSTALK (dB)
NORMALIZED GAIN (dB)
RL = 100Ω, Unless Otherwise Specified (Continued)
-0.1
-0.2
AV = -1
AV = +6
(RF = 150Ω)
-0.3
-40
RL = 100Ω
-50
RL = ∞
-60
-70
-80
-90
1
10
-100
0.3
100
1
10
FREQUENCY (MHz)
FREQUENCY (MHz)
100
FIGURE 53. ALL HOSTILE CROSSTALK
FIGURE 52. GAIN FLATNESS
3.6
0.2
PDIP
3.4
OUTPUT VOLTAGE (V)
3.5
0.1
0.05
0.025
0
-0.025
-0.05
-0.1
3.3
AV = -1
+VOUT (RL= 100Ω)
|-VOUT| (RL= 100Ω)
|-VOUT| (RL= 50Ω)
3.2
3.1
+VOUT (RL= 50Ω)
3.0
2.9
2.8
-0.15
2.7
-0.2
0
5
10
15
20
25
30
TIME (ns)
35
40
45
2.6
-50
50
-25
0
25
6.5
6.4
6.3
6.2
6.1
6.0
5.9
5.8
5.7
5.6
5
5.5
6
6.5
SUPPLY VOLTAGE (±V)
FIGURE 56. SUPPLY CURRENT vs SUPPLY VOLTAGE
15
75
100
FIGURE 55. OUTPUT VOLTAGE vs TEMPERATURE
6.6
5.5
4.5
50
TEMPERATURE (oC)
FIGURE 54. SETTLING RESPONSE
SUPPLY CURRENT (mA/AMPLIFIER)
SETTLING ERROR (%)
0.15
AV = +2
VOUT = 2V
7
125
HFA1405
Die Characteristics
DIE DIMENSIONS:
SUBSTRATE POTENTIAL (POWERED UP):
79 mils x 118 mils
Floating (Recommend Connection to V-)
2000µm x 3000µm
PASSIVATION:
Type: Nitride
Thickness: 4kÅ ± 0.5kÅ
METALLIZATION:
Type: Metal 1: AICu (2%)/TiW
Thickness: Metal 1: 8kÅ ± 0.4kÅ
TRANSISTOR COUNT:
320
Type: Metal 2: AICu (2%)
Thickness: Metal 2: 16kÅ ± 0.8kÅ
Metallization Mask Layout
HFA1405
-IN1
OUT1
OUT4
-IN4
+IN4
+IN1
V+
V-
+IN3
+IN2
-IN2
16
OUT2
V-
OUT3
-IN3
HFA1405
Small Outline Plastic Packages (SOIC)
M14.15 (JEDEC MS-012-AB ISSUE C)
N
INDEX
AREA
H
0.25(0.010) M
14 LEAD NARROW BODY SMALL OUTLINE PLASTIC
PACKAGE
B M
E
INCHES
-B-
1
2
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
α
e
A1
B
0.25(0.010) M
C A M
C
B S
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch).
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
17
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.0040
0.0098
0.10
0.25
-
B
0.013
0.020
0.33
0.51
9
C
0.0075
0.0098
0.19
0.25
-
D
0.3367
0.3444
8.55
8.75
3
E
0.1497
0.1574
3.80
4.00
4
e
0.10(0.004)
MILLIMETERS
0.050 BSC
1.27 BSC
-
H
0.2284
0.2440
5.80
6.20
-
h
0.0099
0.0196
0.25
0.50
5
L
0.016
0.050
0.40
1.27
6
N
α
14
0o
14
8o
0o
7
8o
Rev. 0 12/93
HFA1405
Dual-In-Line Plastic Packages (PDIP)
E14.3 (JEDEC MS-001-AA ISSUE D)
N
14 LEAD DUAL-IN-LINE PLASTIC PACKAGE
E1
INDEX
AREA
1 2 3
INCHES
N/2
-B-
-AE
D
BASE
PLANE
-C-
A2
SEATING
PLANE
A
L
D1
e
B1
D1
A1
eC
B
0.010 (0.25) M
C A B S
SYMBOL
MIN
MAX
MIN
MAX
NOTES
A
-
0.210
-
5.33
4
A1
0.015
-
0.39
-
4
A2
0.115
0.195
2.93
4.95
-
B
0.014
0.022
0.356
0.558
-
C
L
B1
0.045
0.070
1.15
1.77
8
eA
C
0.008
0.014
C
D
0.735
0.775
D1
0.005
-
0.13
-
5
E
0.300
0.325
7.62
8.25
6
E1
0.240
0.280
6.10
7.11
5
eB
NOTES:
1. Controlling Dimensions: INCH. In case of conflict between English
and Metric dimensions, the inch dimensions control.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication No. 95.
4. Dimensions A, A1 and L are measured with the package seated in
JEDEC seating plane gauge GS-3.
5. D, D1, and E1 dimensions do not include mold flash or protrusions.
Mold flash or protrusions shall not exceed 0.010 inch (0.25mm).
6. E and eA are measured with the leads constrained to be perpendicular to datum -C- .
7. eB and eC are measured at the lead tips with the leads unconstrained. eC must be zero or greater.
8. B1 maximum dimensions do not include dambar protrusions. Dambar
protrusions shall not exceed 0.010 inch (0.25mm).
9. N is the maximum number of terminal positions.
10. Corner leads (1, N, N/2 and N/2 + 1) for E8.3, E16.3, E18.3, E28.3,
E42.6 will have a B1 dimension of 0.030 - 0.045 inch (0.76 1.14mm).
18
MILLIMETERS
e
0.100 BSC
eA
0.300 BSC
eB
-
L
0.115
N
0.204
14
0.355
18.66
19.68
5
2.54 BSC
-
7.62 BSC
6
0.430
-
0.150
2.93
14
10.92
7
3.81
4
9
Rev. 0 12/93
HFA1405
Shrink Small Outline Plastic Packages (SSOP)
M16.15A
N
INDEX
AREA
H
0.25(0.010) M
16 LEAD SHRINK NARROW BODY SMALL OUTLINE
PLASTIC PACKAGE
B M
E
GAUGE
PLANE
-B-
INCHES
SYMBOL
1
2
3
L
0.25
0.010
SEATING PLANE
-A-
h x 45o
A
D
-C-
α
e
B
0.17(0.007) M
A2
A1
C
0.10(0.004)
C A M
B S
NOTES:
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. Dimension “B” does not include dambar protrusion. Allowable dambar
protrusion shall be 0.10mm (0.004 inch) total in excess of “B” dimension at maximum material condition.
10. Controlling dimension: INCHES. Converted millimeter dimensions are
not necessarily exact.
MIN
MAX
MILLIMETERS
MIN
MAX
NOTES
A
0.053
0.069
1.35
1.75
-
A1
0.004
0.010
0.10
0.25
-
A2
-
0.061
-
1.54
-
B
0.008
0.012
0.20
0.30
9
C
0.007
0.010
0.18
0.25
-
D
0.189
0.196
4.80
4.98
3
E
0.150
0.157
3.81
3.98
4
e
0.025 BSC
0.635 BSC
-
H
0.228
0.244
5.80
6.19
-
h
0.0099
0.0196
0.26
0.49
5
L
0.016
0.050
0.41
1.27
6
N
α
16
0o
16
8o
0o
7
8o
Rev. 0 5/96
All Intersil semiconductor products are manufactured, assembled and tested under ISO9000 quality systems certification.
Intersil semiconductor products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
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19
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