74LVC573ABXX

74LVC573A Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state Rev. 8 — 27 August 2021 Product data sheet 1. General description The 74LVC573A is an 8-bit D-type transparent latch with 3-state outputs. The device features latch enable (LE) and output enable (OE) inputs. When LE is HIGH, data at the inputs enter the latches. In this condition the latches are transparent, a latch output will change each time its corresponding D-input changes. When LE is LOW the latches store the information that was present at the inputs a set-up time preceding the HIGH-to-LOW transition of LE. A HIGH on OE causes the outputs to assume a high-impedance OFF-state. Operation of the OE input does not affect the state of the latches. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V environments. Schmitt-trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. This device is fully specified for partial power down applications using IOFF. The IOFF circuitry disables the output, preventing the potentially damaging backflow current through the device when it is powered down. 2. Features and benefits • • • • • • • • • • Wide supply voltage range from 1.2 to 3.6 V Overvoltage tolerant inputs to 5.5 V CMOS low power consumption Direct interface with TTL levels IOFF circuitry provides partial Power-down mode operation High-impedance when VCC = 0 V Flow-through pinout architecture Complies with JEDEC standard: • JESD8-7A (1.65 V to 1.95 V) • JESD8-5A (2.3 V to 2.7 V) • JESD8-C/JESD36 (2.7 V to 3.6 V) ESD protection: • HBM JESD22-A114F exceeds 2000 V • MM JESD22-A115-B exceeds 200 V • CDM JESD22-C101E exceeds 1000 V Specified from -40 °C to +85 °C and -40 °C to +125 °C 74LVC573A Nexperia Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name Description Version 74LVC573AD -40 °C to +125 °C SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 74LVC573APW -40 °C to +125 °C TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1 74LVC573ABQ -40 °C to +125 °C DHVQFN20 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 × 4.5 × 0.85 mm SOT764-1 4. Functional diagram 11 1 1 2 3 4 5 6 7 8 9 D0 OE Q0 D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 LE 11 Fig. 1. 2 19 C1 EN1 19 1D 3 18 4 17 16 5 16 15 6 15 14 7 14 8 13 9 12 18 17 13 12 mna807 mna808 Logic symbol Fig. 2. IEC logic symbol 2 D0 Q0 19 3 D1 Q1 18 4 D2 Q2 17 5 D3 6 D4 7 D5 Q5 14 8 D6 Q6 13 9 D7 Q7 12 LATCH 1 to 8 3-STATE OUTPUTS Q3 16 Q4 15 11 LE 1 OE mna809 Fig. 3. Functional diagram 74LVC573A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 August 2021 © Nexperia B.V. 2021. All rights reserved 2 / 16 74LVC573A Nexperia Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state D0 D1 D Q D2 D Q D3 D Q D4 D Q D5 D Q D6 D Q D7 D Q D Q LATCH 1 LATCH 2 LATCH 3 LATCH 4 LATCH 5 LATCH 6 LATCH 7 LATCH 8 LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE LE OE Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 mna810 Fig. 4. Logic diagram 5. Pinning information 5.1. Pinning 74LVC573A 74LVC573A OE 1 1 2 20 VCC 19 Q0 OE D0 D0 2 20 VCC 19 Q0 D1 3 18 Q1 D1 3 18 Q1 D2 4 17 Q2 D2 4 17 Q2 D3 5 16 Q3 D3 5 16 Q3 D4 6 15 Q4 D4 6 15 Q4 D5 7 14 Q5 D5 7 14 Q5 D6 8 13 Q6 D6 8 13 Q6 D7 9 12 Q7 D7 9 12 Q7 GND 10 11 LE GND 10 11 LE aaa-029011 aaa-029010 Fig. 5. Pin configuration SOT163-1 (SO20) 74LVC573A Product data sheet Fig. 6. Pin configuration SOT360-1 (TSSOP20) All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 August 2021 © Nexperia B.V. 2021. All rights reserved 3 / 16 74LVC573A Nexperia Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state 1 OE terminal 1 index area 20 VCC 74LVC573A D0 2 19 Q0 D1 3 18 Q1 D2 4 17 Q2 D3 5 16 Q3 D4 6 15 Q4 D5 7 D6 8 D7 9 14 Q5 GND(1) 13 Q6 LE 11 GND 10 12 Q7 aaa-029012 Transparent top view (1) This is not a ground pin. There is no electrical or mechanical requirement to solder the pad. In case soldered, the solder land should remain floating or connected to GND. Fig. 7. Pin configuration SOT764-1 (DHVQFN20) 5.2. Pin description Table 2. Pin description Symbol Pin Description OE 1 output enable input (active LOW) LE 11 latch enable input (active HIGH) D0, D1, D2, D3, D4, D5, D6, D7 2, 3, 4, 5, 6, 7, 8, 9 data input Q0, Q1, Q2, Q3, Q4, Q5, Q6, Q7 19, 18, 17, 16, 15, 14, 13, 12 data output GND 10 ground (0 V) VCC 20 supply voltage 6. Functional description Table 3. Functional table H = HIGH voltage level; h = HIGH voltage level one set-up time prior to the HIGH-to-LOW LE transition L = LOW voltage level; l = LOW voltage level one set-up time prior to the HIGH-to-LOW LE transition Z = high-impedance OFF-state Operating modes Input Internal latch Output OE LE Dn Enable and read register (transparent mode) L H L L L L H H H H Latch and read register L L l L L L L h H H Latch register and disable outputs H L l L Z H L h H Z 74LVC573A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 August 2021 Qn © Nexperia B.V. 2021. All rights reserved 4 / 16 74LVC573A Nexperia Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state 7. Limiting values Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter Conditions Min Max Unit -0.5 +6.5 V -50 - -0.5 +6.5 V - ±50 mA -0.5 VCC + 0.5 - ±50 mA 100 mA VCC supply voltage IIK input clamping current VI input voltage IOK output clamping current VO output voltage IO output current ICC supply current - IGND ground current -100 - mA Tstg storage temperature -65 +150 °C Ptot total power dissipation - 500 mW [1] [2] [3] VI < 0 [1] VO > VCC or VO < 0 [2] VO = 0 V to VCC Tamb = -40 °C to +125 °C [3] mA V The minimum input voltage ratings may be exceeded if the input current ratings are observed. The output voltage ratings may be exceeded if the output current ratings are observed. For SOT163-1 (SO20) package: Ptot derates linearly with 12.3 mW/K above 109 °C. For SOT360-1 (TSSOP20) package: Ptot derates linearly with 10.0 mW/K above 100 °C. For SOT764-1 (DHVQFN20) package: Ptot derates linearly with 12.9 mW/K above 111 °C. 8. Recommended operating conditions Table 5. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit VCC 1.65 - 3.6 V 1.2 - - V 0 - 5.5 V 0 - VCC V supply voltage functional VI input voltage VO output voltage Tamb ambient temperature in free air Δt/ΔV input transition rise and fall rate output HIGH- or LOW-state output 3-state 74LVC573A Product data sheet 0 - 5.5 V -40 - +125 °C VCC = 1.65 V to 2.7 V 0 - 20 ns/V VCC = 2.7 V to 3.6 V 0 - 10 ns/V All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 August 2021 © Nexperia B.V. 2021. All rights reserved 5 / 16 74LVC573A Nexperia Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state 9. Static characteristics Table 6. Static characteristics At recommended operating conditions. Voltages are referenced to GND (ground = 0 V). Symbol Parameter VIH HIGH-level input voltage VIL LOW-level input voltage VOH VOL HIGH-level output voltage LOW-level output voltage Conditions -40 °C to +85 °C VCC = 1.2 V VCC = 1.65 V to 1.95 V -40 °C to +125 °C Unit Min Typ [1] Max Min Max 1.08 - - 1.08 - V 0.65VCC - - 0.65VCC - V VCC = 2.3 V to 2.7 V 1.7 - - 1.7 - V VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V VCC = 1.2 V - - 0.12 - 0.12 V VCC = 1.65 V to 1.95 V - - 0.35VCC - VCC = 2.3 V to 2.7 V - - 0.7 - 0.7 V VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V VCC - 0.2 - - VCC - 0.3 - V IO = -4 mA; VCC = 1.65 V 1.2 - - 1.05 - V IO = -8 mA; VCC = 2.3 V 1.8 - - 1.65 - V IO = -12 mA; VCC = 2.7 V 2.2 - - 2.05 - V IO = -18 mA; VCC = 3.0 V 2.4 - - 2.25 - V IO = -24 mA; VCC = 3.0 V 2.2 - - 2.0 - V IO = 100 μA; VCC = 1.65 V to 3.6 V - - 0.2 - 0.3 V IO = 4 mA; VCC = 1.65 V - - 0.45 - 0.65 V IO = 8 mA; VCC = 2.3 V - - 0.6 - 0.8 V IO = 12 mA; VCC = 2.7 V - - 0.4 - 0.6 V IO = 24 mA; VCC = 3.0 V - - 0.55 - 0.8 V 0.35VCC V VI = VIH or VIL IO = -100 μA; VCC = 1.65 V to 3.6 V VI = VIH or VIL II input leakage current VCC = 3.6 V; VI = 5.5 V or GND - ±0.1 ±5 - ±20 μA IOZ OFF-state output current VI = VIH or VIL; VCC = 3.6 V; VO = 5.5 V or GND - 0.1 ±5 - ±20 μA IOFF power-off VCC = 0 V; VI or VO = 5.5 V leakage current - 0.1 ±10 - ±20 μA ICC supply current VCC = 3.6 V; VI = VCC or GND; IO = 0 A - 0.1 10 - 40 μA ΔICC additional supply current per input pin; VCC = 2.7 V to 3.6 V; VI = VCC - 0.6 V; IO = 0 A - 5 500 - 5000 μA CI input capacitance VCC = 0 V to 3.6 V; VI = GND to VCC - 5.0 - - - pF [1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb = 25 °C. 74LVC573A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 August 2021 © Nexperia B.V. 2021. All rights reserved 6 / 16 74LVC573A Nexperia Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state 10. Dynamic characteristics Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Fig. 12. Symbol Parameter tpd propagation delay Conditions -40 °C to +85 °C Dn to Qn; see Fig. 8 16.0 - - - ns 7.8 16.3 2.1 18.8 ns VCC = 2.3 V to 2.7 V 1.5 4.1 8.0 1.5 9.2 ns VCC = 2.7 V 1.5 4.1 7.2 1.5 9.0 ns VCC = 3.0 V to 3.6 V 1.5 3.4 6.2 1.5 8.0 ns - 16.0 - - - ns VCC = 1.65 V to 1.95 V 2.0 7.7 16.0 2.0 18.4 ns VCC = 2.3 V to 2.7 V 1.5 4.1 7.8 1.5 9.1 ns VCC = 2.7 V 1.5 3.7 7.5 1.5 9.5 ns 1.5 3.4 6.5 1.5 8.5 ns - 18.0 - - - ns VCC = 1.65 V to 1.95 V 1.7 7.5 17.5 1.7 20.2 ns VCC = 2.3 V to 2.7 V 1.5 4.2 9.2 1.5 10.6 ns VCC = 2.7 V 1.5 4.2 8.5 1.5 11.0 ns VCC = 3.0 V to 3.6 V 1.5 3.4 7.5 1.5 9.5 ns - 8.0 - - - ns VCC = 1.65 V to 1.95 V 1.0 3.3 10.1 1.0 11.6 ns VCC = 2.3 V to 2.7 V 0.3 1.8 5.7 0.3 6.6 ns VCC = 2.7 V 1.5 3.0 6.5 1.5 8.5 ns VCC = 3.0 V to 3.6 V 1.5 2.5 6.0 1.5 7.5 ns VCC = 1.65 V to 1.95 V 5.0 - - 5.0 - ns VCC = 2.3 V to 2.7 V 4.0 - - 4.0 - ns VCC = 2.7 V 3.2 - - 3.2 - ns VCC = 3.0 V to 3.6 V 3.2 1.6 - 3.2 - ns VCC = 1.65 V to 1.95 V 4.0 - - 4.0 - ns VCC = 2.3 V to 2.7 V 2.5 - - 2.5 - ns VCC = 2.7 V 1.7 - - 1.7 - ns VCC = 3.0 V to 3.6 V 1.7 - - 1.7 - ns VCC = 1.65 V to 1.95 V 3.0 - - 3.0 - ns VCC = 2.3 V to 2.7 V 1.9 - - 1.9 - ns VCC = 2.7 V 1.5 - - 1.5 - ns VCC = 3.0 V to 3.6 V 1.4 - - 1.4 - ns [2] OE to Qn; see Fig. 10 [2] VCC = 1.2 V OE to Qn; see Fig. 10 VCC = 1.2 V tW tsu th pulse width set-up time hold time 74LVC573A Product data sheet Max - VCC = 3.0 V to 3.6 V disable time Min 2.1 VCC = 1.2 V tdis Max VCC = 1.65 V to 1.95 V LE to Qn; see Fig. 9 enable time Typ [1] [2] VCC = 1.2 V ten Min -40 °C to +125 °C Unit [2] LE HIGH; see Fig. 9 Dn to LE; see Fig. 11 Dn to LE; see Fig. 11 All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 August 2021 © Nexperia B.V. 2021. All rights reserved 7 / 16 74LVC573A Nexperia Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state Symbol Parameter Conditions -40 °C to +85 °C Min Typ [1] Max Min Max - - 1.0 - 1.5 ns VCC = 1.65 V to 1.95 V - 7.1 - - - pF VCC = 2.3 V to 2.7 V - 10.3 - - - pF VCC = 3.0 V to 3.6 V - 13.2 - - - pF tsk(0) output skew time VCC = 3.0 V to 3.6 V [3] CPD power dissipation capacitance per latch; VI = GND to VCC [4] [1] [2] [3] [4] -40 °C to +125 °C Unit Typical values are measured at Tamb = 25 °C and VCC = 1.2 V, 1.8 V, 2.5 V, 2.7 V and 3.3 V respectively. tpd is the same as tPLH and tPHL. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design. CPD is used to determine the dynamic power dissipation (PD in μW). 2 2 PD = CPD × VCC × fi × N + Σ(CL × VCC × fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = number of inputs switching 2 Σ(CL × VCC × fo) = sum of the outputs 10.1. Waveforms and test circuit VI VM Dn input GND tPLH tPHL VOH VM Qn output mna811 VOL Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 8. Input (Dn) to output (Qn) propagation delays 1/fmax VI LE input VM GND tW t PHL t PLH VOH VM Qn output VOL mna812 Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 9. Latch Enable input (LE) pulse width, the latch enable input to output (Qn) propagation delays 74LVC573A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 August 2021 © Nexperia B.V. 2021. All rights reserved 8 / 16 74LVC573A Nexperia Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state VI OE input VM GND t PLZ Qn output LOW-to-OFF OFF-to-LOW t PZL VCC VM VX VOL t PZH t PHZ Qn output HIGH-to-OFF OFF-to-HIGH VOH VY VM GND outputs enabled outputs enabled outputs disabled mna813 Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig. 10. 3-state enable and disable times VI VM Dn input GND th t su t su th VI LE input VM GND mna814 Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. Fig. 11. Data set-up and hold times for the Dn input to the LE input Table 8. Measurement points Supply voltage Input Output VCC VI VM VM VX VY 1.2 V VCC 0.5 × VCC 0.5 × VCC VOL + 0.15 V VOH - 0.15 V 1.65 V to 1.95 V VCC 0.5 × VCC 0.5 × VCC VOL + 0.15 V VOH - 0.15 V 2.3 V to 2.7 V VCC 0.5 × VCC 0.5 × VCC VOL + 0.15 V VOH - 0.15 V 2.7 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V 3.0 V to 3.6 V 2.7 V 1.5 V 1.5 V VOL + 0.3 V VOH - 0.3 V 74LVC573A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 August 2021 © Nexperia B.V. 2021. All rights reserved 9 / 16 74LVC573A Nexperia Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state tW VI 90 % negative pulse VM VM 10 % 0V VI tf tr tr tf 90 % positive pulse VM VM 10 % 0V tW VEXT VCC G VI RL VO DUT RT CL RL 001aae331 Test data is given in Table 9. Definitions for test circuit: RL = Load resistance. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Fig. 12. Test circuit for measuring switching times Table 9. Test data Supply voltage Input Load VEXT VI tr, tf CL RL tPLH, tPHL tPLZ, tPZL tPHZ, tPZH 1.2 V VCC ≤ 2 ns 30 pF 1 kΩ open 2 × VCC GND 1.65 V to 1.95 V VCC ≤ 2 ns 30 pF 1 kΩ open 2 × VCC GND 2.3 V to 2.7 V VCC ≤ 2 ns 30 pF 500 Ω open 2 × VCC GND 2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 2 × VCC GND 3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω open 2 × VCC GND 74LVC573A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 August 2021 © Nexperia B.V. 2021. All rights reserved 10 / 16 74LVC573A Nexperia Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state 11. Package outline SO20: plastic small outline package; 20 leads; body width 7.5 mm SOT163-1 D E A X c y HE v M A Z 20 11 Q A2 A (A 3 ) A1 pin 1 index θ Lp L 1 10 e detail X w M bp 0 5 10 mm scale DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (1) e HE L Lp Q v w y mm 2.65 0.3 0.1 2.45 2.25 0.25 0.49 0.36 0.32 0.23 13.0 12.6 7.6 7.4 1.27 10.65 10.00 1.4 1.1 0.4 1.1 1.0 0.25 0.25 0.1 0.9 0.4 inches 0.1 0.012 0.096 0.004 0.089 0.01 0.019 0.013 0.014 0.009 0.51 0.49 0.30 0.29 0.05 0.419 0.043 0.055 0.394 0.016 0.043 0.039 0.01 0.01 0.004 0.035 0.016 Z (1) θ o 8 o 0 Note 1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. REFERENCES OUTLINE VERSION IEC JEDEC SOT163-1 075E04 MS-013 JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 Fig. 13. Package outline SOT163-1 (SO20) 74LVC573A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 August 2021 © Nexperia B.V. 2021. All rights reserved 11 / 16 74LVC573A Nexperia Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state TSSOP20: plastic thin shrink small outline package; 20 leads; body width 4.4 mm D SOT360-1 E A X c HE y v M A Z 11 20 Q A2 pin 1 index (A 3 ) A1 A θ Lp 1 L 10 detail X w M bp e 0 2.5 5 mm scale DIMENSIONS (mm are the original dimensions) UNIT A max. A1 A2 A3 bp c D (1) E (2) e HE L Lp Q v w y Z (1) θ mm 1.1 0.15 0.05 0.95 0.80 0.25 0.30 0.19 0.2 0.1 6.6 6.4 4.5 4.3 0.65 6.6 6.2 1 0.75 0.50 0.4 0.3 0.2 0.13 0.1 0.5 0.2 8o 0o Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT360-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE 99-12-27 03-02-19 MO-153 Fig. 14. Package outline SOT360-1 (TSSOP20) 74LVC573A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 August 2021 © Nexperia B.V. 2021. All rights reserved 12 / 16 74LVC573A Nexperia Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state DHVQFN20: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 20 terminals; body 2.5 x 4.5 x 0.85 mm B D SOT764-1 A A A1 E c detail X terminal 1 index area terminal 1 index area e1 C e b 2 9 v w C A B C y1 C y L 1 10 Eh e 20 11 19 12 X Dh 0 2.5 5 mm scale Dimensions (mm are the original dimensions) Unit mm A(1) A1 b max 1.00 0.05 0.30 nom 0.90 0.02 0.25 min 0.80 0.00 0.18 c D(1) Dh E(1) Eh e e1 L v 0.2 4.6 4.5 4.4 3.15 3.00 2.85 2.6 2.5 2.4 1.15 1.00 0.85 0.5 3.5 0.5 0.4 0.3 0.1 w y 0.05 0.05 y1 0.1 Note 1. Plastic or metal protrusions of 0.075 mm maximum per side are not included. References Outline version IEC JEDEC JEITA SOT764-1 --- MO-241 --- sot764-1_po European projection Issue date 03-01-27 14-12-12 Fig. 15. Package outline SOT764-1 (DHVQFN20) 74LVC573A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 August 2021 © Nexperia B.V. 2021. All rights reserved 13 / 16 74LVC573A Nexperia Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state 12. Abbreviations Table 10. Abbreviations Acronym Description CDM Charged Device Model CMOS Complementary Metal-Oxide Semiconductor DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model TTL Transistor-Transistor Logic 13. Revision history Table 11. Revision history Document ID Release date Data sheet status Change notice Supersedes 74LVC573A v.8 20210827 Product data sheet - Modifications: • • 74LVC573A v.7 20200330 Modifications: • 74LVC573A v.6 20180926 Modifications: • • • • Section 1 and Section 2 updated. Type number 74LVC573ADB (SOT339-1/SSOP20) removed. Product data sheet - 74LVC573A v.6 Table 4: Derating values for Ptot total power dissipation updated. Product data sheet - 74LVC573A v.5 The format of this data sheet has been redesigned to comply with the identity guidelines of Nexperia. Legal texts have been adapted to the new company name where appropriate. Type number 74LVC573ABX (SOT1045-2) removed. Fig. 15: Package outline drawing SOT764-1 updated 74LVC573A v.5 20130219 Modifications: • 74LVC573A v.4 20121129 Modifications: • • • 74LVC573A v.7 Product data sheet - 74LVC573A v.4 - 74LVC573A v.3 74LVC573ABX added. Product data sheet The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. Legal texts have been adapted to the new company name where appropriate. Table 4, Table 5, Table 6, Table 7, Table 8 and Table 9: values added for lower voltage ranges. 74LVC573A v.3 20031003 Product specification - 74LVC573A v.2 74LVC573A v.2 20030526 Product specification - 74LVC573A v.1 74LVC573A v.1 19980729 Product specification - - 74LVC573A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 August 2021 © Nexperia B.V. 2021. All rights reserved 14 / 16 74LVC573A Nexperia Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state 14. Legal information injury, death or severe property or environmental damage. Nexperia and its suppliers accept no liability for inclusion and/or use of Nexperia products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. 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In no event shall Nexperia be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, Nexperia’s aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of Nexperia. Right to make changes — Nexperia reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — Nexperia products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an Nexperia product can reasonably be expected to result in personal 74LVC573A Product data sheet Applications — Applications that are described herein for any of these products are for illustrative purposes only. Nexperia makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Customers are responsible for the design and operation of their applications and products using Nexperia products, and Nexperia accepts no liability for any assistance with applications or customer product design. It is customer’s sole responsibility to determine whether the Nexperia product is suitable and fit for the customer’s applications and products planned, as well as for the planned application and use of customer’s third party customer(s). Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. Nexperia does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’s applications and products using Nexperia products in order to avoid a default of the applications and the products or of the application or use by customer’s third party customer(s). Nexperia does not accept any liability in this respect. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale — Nexperia products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nexperia.com/profile/terms, unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. Nexperia hereby expressly objects to applying the customer’s general terms and conditions with regard to the purchase of Nexperia products by customer. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from competent authorities. Non-automotive qualified products — Unless this data sheet expressly states that this specific Nexperia product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. Nexperia accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without Nexperia’s warranty of the product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond Nexperia’s specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies Nexperia for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond Nexperia’s standard warranty and Nexperia’s product specifications. Translations — A non-English (translated) version of a document is for reference only. The English version shall prevail in case of any discrepancy between the translated and English versions. Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 August 2021 © Nexperia B.V. 2021. All rights reserved 15 / 16 74LVC573A Nexperia Octal D-type transparent latch with 5 V tolerant inputs/outputs; 3-state Contents 1. General description...................................................... 1 2. Features and benefits.................................................. 1 3. Ordering information....................................................2 4. Functional diagram.......................................................2 5. Pinning information......................................................3 5.1. Pinning.........................................................................3 5.2. Pin description............................................................. 4 6. Functional description................................................. 4 7. Limiting values............................................................. 5 8. Recommended operating conditions..........................5 9. Static characteristics....................................................6 10. Dynamic characteristics............................................ 7 10.1. Waveforms and test circuit........................................ 8 11. Package outline........................................................ 11 12. Abbreviations............................................................ 14 13. Revision history........................................................14 14. Legal information......................................................15 © Nexperia B.V. 2021. All rights reserved For more information, please visit: http://www.nexperia.com For sales office addresses, please send an email to: salesaddresses@nexperia.com Date of release: 27 August 2021 74LVC573A Product data sheet All information provided in this document is subject to legal disclaimers. Rev. 8 — 27 August 2021 © Nexperia B.V. 2021. All rights reserved 16 / 16