24LC1025T-E/SN

24AA1025/24LC1025/24FC1025 1024-Kbit I2C Serial EEPROM Device Selection Table Part Number VCC Range Maximum Clock Frequency Temperature Ranges Packages 24AA1025 1.7V-5.5V 400 kHz(1) I P, SN, SM 24LC1025 2.5V-5.5V 400 kHz(2) I, E P, SN, SM I P, SN, SM 24FC1025 Note 1: 2: 3: 1.8V-5.5V (3) 1 MHz 100 kHz for VCC < 2.5V 100 kHz for VCC < 4.5V, E-temp 400 kHz for VCC < 2.5V Features Description • Low-Power CMOS Technology: - Read current 450 µA, maximum - Standby current 5 µA, maximum • Two-Wire Serial Interface, I2C Compatible • Cascadable up to Four Devices • Schmitt Trigger Inputs for Noise Suppression • Output Slope Control to Eliminate Ground Bounce • 100 KHz and 400 KHz Clock Compatibility • 1 MHz Clock for FC Versions • Page Write Time: 5 ms, Maximum • Self-Timed Erase/Write Cycle • 128-Byte Page Write Buffer • Hardware Write-Protect • ESD Protection >4000V • More than 1 Million Erase/Write Cycles • Data Retention >200 Years • Factory Programming Available • RoHS Compliant • Temperature Ranges: - Industrial (I): -40C to +85C - Extended (E): -40C to +125C • Automotive AEC-Q100 Qualified The Microchip Technology Inc. 24XX1025(1) is a 1024-Kbit Electrically Erasable PROM (EEPROM). The device is organized as two block of 64K x 8 bit memory with a two-wire serial interface. Its low-voltage design permits operation down to 1.7V, with standby and active currents of 5 µA and 5 mA, respectively. The 24XX1025 also has a page write capability for up to 128 bytes of data. Packages • 8-Lead PDIP, 8-Lead SOIC and 8-Lead SOIJ This device is capable of both random and sequential reads. Reads may be sequential within address boundaries 0000h to FFFFh and 10000h to 1FFFFh. Functional address lines allow up to four devices on the same data bus. This allows for up to 4 Mbits total system EEPROM memory. Note 1: 24XX1025 is used in this document as a generic part number for the 24AA1025/24LC1025/24FC1025 devices. Package Type PDIP A0 1 8 VCC A1 2 7 WP A2(1) 3 6 VSS 4 5 Note 1:  2005-2021 Microchip Technology Inc. and its subsidiaries SOIC/SOIJ A0 1 8 VCC A1 2 7 WP SCL A2(1) 3 6 SCL SDA VSS 4 5 SDA A2 must be tied to VCC. DS20001941M-page 1 24AA1025/24LC1025/24FC1025 Block Diagram A0 A1 I/O Control Logic WP Memory Control Logic HV Generator XDEC EEPROM Array Page Latches I/O SCL YDEC SDA VCC VSS DS20001941M-page 2 Sense AMP R/W Control  2005-2021 Microchip Technology Inc. and its subsidiaries 24AA1025/24LC1025/24FC1025 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) VCC.............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS ...........................................................................................................-0.6V to VCC+1.0V Storage temperature ............................................................................................................................... -65°C to +150°C Ambient temperature with power applied................................................................................................ -40°C to +125°C ESD protection on all pins  4 kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. TABLE 1-1: DC CHARACTERISTICS DC CHARACTERISTICS Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C Extended (E): VCC = +2.5V to 5.5V TA = -40°C to +125°C Param. Symbol No. Minimum Maximum Units — — — 0.7 VCC — V Characteristic A1, A2, SCL, SDA and WP Pins: D1 VIH High-level Input Voltage D2 VIL Low-level Input Voltage D3 VHYS Hysteresis of Schmitt Trigger inputs (SDA, SCL pins) D4 VOL D5 Conditions — 0.3 VCC V VCC 2.5V — 0.2 VCC V VCC < 2.5V 0.05 VCC — V VCC  2.5V (Note 1) Low-level Output Voltage — 0.40 V IOL = 3.0 mA @ VCC = 4.5V IOL = 2.1 mA @ VCC = 2.5V ILI Input Leakage Current — ±1 µA VIN = VSS or VCC VIN = VSS or VCC D6 ILO Output Leakage Current — ±1 µA VOUT = VSS or VCC D7 CIN, COUT Pin Capacitance (all inputs/outputs) — 10 pF VCC = 5.0V (Note 1) TA = 25°C, FCLK = 1 MHz — 450 µA VCC = 5.5V, SCL = 400 kHz — 5 mA VCC = 5.5V — 5 µA SCL, SDA, VCC = 5.5V A1, A2, WP = VSS D8 D9 Note 1: ICC Read ICC Write ICCS Operating Current Standby current This parameter is periodically sampled and not 100% tested.  2005-2021 Microchip Technology Inc. and its subsidiaries DS20001941M-page 3 24AA1025/24LC1025/24FC1025 TABLE 1-2: AC CHARACTERISTICS AC CHARACTERISTICS Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C Extended (E): Vcc = +2.5V to 5.5V TA = -40°C to +125°C Param. No. Minimum Maximum 1 Symbol FCLK 2 THIGH 3 TLOW 4 TR 5 TF 6 Characteristic Clock Frequency Clock High Time Clock Low Time SDA and SCL Rise Time SDA and SCL Fall Time THD:STA Start Condition Hold Time 7 TSU:STA Start Condition Setup Time THD:DAT Data Input Hold Time 8 9 TSU:DAT Data Input Setup Time Note 1: 2: 3: 4: Units Conditions — 100 kHz 1.7V  VCC  2.5V — 100 kHz 2.5V  VCC  4.5V, E-temp — 400 kHz 2.5V  VCC  5.5V — 400 kHz 1.8V  VCC  2.5V (24FC1025) — 1000 kHz 2.5V  VCC  5.5V (24FC1025) 4000 — ns 1.7V  VCC  2.5V 4000 — ns 2.5V  VCC  4.5V, E-temp 600 — ns 2.5V  VCC  5.5V 600 — ns 1.8V  VCC  2.5V (24FC1025) 500 — ns 2.5V  VCC  5.5V (24FC1025) 4700 — ns 1.7V  VCC  2.5V 4700 — ns 2.5V  VCC  4.5V, E-temp 1300 — ns 2.5V  VCC  5.5V 1300 — ns 1.8V  VCC  2.5V (24FC1025) 500 — ns 2.5V  VCC  5.5V (24FC1025) — 1000 ns 1.7V  VCC  2.5V (Note 1) — 1000 ns 2.5V  VCC  4.5V, E-temp (Note 1) — 300 ns 2.5V  VCC  5.5V (Note 1) — 300 ns 1.8V  VCC  2.5V (24FC1025) (Note 1) — 300 ns 2.5V  VCC  5.5V (24FC1025) (Note 1) — 300 ns All except 24FC1025 (Note 1) — 100 ns 1.8V  VCC  5.5V (24FC1025) (Note 1) 4000 — ns 1.7V  VCC  2.5V 4000 — ns 2.5V  VCC  4.5V, E-temp 600 — ns 2.5V  VCC  5.5V 600 — ns 1.8V  VCC  2.5V (24FC1025) 250 — ns 2.5V  VCC  5.5V (24FC1025) 4700 — ns 1.7V  VCC  2.5V 4700 — ns 2.5V  VCC  4.5V, E-temp 600 — ns 2.5V  VCC  5.5V 600 — ns 1.8V  VCC  2.5V (24FC1025) 250 — ns 2.5V  VCC  5.5V (24FC1025) 0 — ns Note 2 250 — ns 1.7V  VCC  2.5V 250 — ns 2.5V  VCC  4.5V, E-temp 100 — ns 2.5V  VCC  5.5V 100 — ns 1.8V  VCC  2.5V (24FC1025) 100 — ns 2.5V  VCC  5.5V (24FC1025) Not 100% tested. CB = total capacitance of one bus line in pF. As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. This parameter is not tested but established by characterization. DS20001941M-page 4  2005-2021 Microchip Technology Inc. and its subsidiaries 24AA1025/24LC1025/24FC1025 TABLE 1-2: AC CHARACTERISTICS AC CHARACTERISTICS (Continued) Industrial (I): VCC = +1.7V to 5.5V TA = -40°C to +85°C Extended (E): Vcc = +2.5V to 5.5V TA = -40°C to +125°C Param. No. Minimum Maximum 10 Symbol Characteristic TSU:WP 12 THD:WP 13 TAA 14 TBUF ns — ns 2.5V  VCC  4.5V, E-temp 600 — ns 2.5V  VCC  5.5V 600 — ns 1.8V  VCC  2.5V (24FC1025) 15 TSP 16 TWC 17 3: 4: — ns 2.5V  VCC  5.5V (24FC1025) — ns 1.7V  VCC  2.5V 4000 — ns 2.5V  VCC  4.5V, E-temp 600 — ns 2.5V  VCC  5.5V 600 — ns 1.8V  VCC  2.5V (24FC1025) 600 — ns 2.5V  VCC  5.5V (24FC1025) 4700 — ns 1.7V  VCC  2.5V 4700 — ns 2.5V  VCC  4.5V, E-temp 1300 — ns 2.5V  VCC  5.5V 1300 — ns 1.8V  VCC  2.5V (24FC1025) 1300 — ns 2.5V  VCC  5.5V (24FC1025) — 3500 ns 1.7V  VCC  2.5V (Note 2) — 3500 ns 2.5V  VCC  4.5V, E-temp (Note 2) — 900 ns 2.5V  VCC  5.5V (Note 2) — 900 ns 1.8V  VCC  2.5V (24FC1025) (Note 2) — 400 ns 2.5V  VCC  5.5V (24FC1025) (Note 2) 4700 — ns 1.7V  VCC  2.5V 4700 — ns 2.5V  VCC  4.5V, E-temp 1300 — ns 2.5V  VCC  5.5V 1300 — ns 1.8V  VCC  2.5V (24FC1025) 500 — ns 2.5V  VCC  5.5V (24FC1025) — 50 ns All except 24FC1025 (Note 1 and Note 3) Input filter spike suppression (SDA and SCL pins) Write cycle time (byte or page) Endurance Note 1: 2: 250 4000 Output Valid From Clock Bus Free Time: Time The Bus Must Be Free Before a New Transmission Can Start 1.7V  VCC  2.5V — 4000 WP Setup Time WP Hold Time Conditions 4000 TSU:STO Stop Condition Setup Time 11 Units — 5 1,000,000 — ms cycles +25°C, 5.5V, Page Mode (Note 4) Not 100% tested. CB = total capacitance of one bus line in pF. As a transmitter, the device must provide an internal minimum delay time to bridge the undefined region (minimum 300 ns) of the falling edge of SCL to avoid unintended generation of Start or Stop conditions. The combined TSP and VHYS specifications are due to new Schmitt Trigger inputs which provide improved noise spike suppression. This eliminates the need for a TI specification for standard operation. This parameter is not tested but established by characterization.  2005-2021 Microchip Technology Inc. and its subsidiaries DS20001941M-page 5 24AA1025/24LC1025/24FC1025 FIGURE 1-1: BUS TIMING DATA 5 SCL 7 SDA IN 3 4 D3 2 8 10 9 6 15 14 13 SDA OUT WP DS20001941M-page 6 (protected) (unprotected) 11 12  2005-2021 Microchip Technology Inc. and its subsidiaries 24AA1025/24LC1025/24FC1025 2.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 2-1. TABLE 2-1: Name PIN FUNCTION TABLE PDIP SOIJ SOIC Function A0 1 1 1 User Configurable Chip Select A1 2 2 2 User Configurable Chip Select A2 3 3 3 Non-Configurable Chip Select. This pin must be hard-wired to logical ‘1’ state (VCC). Operation will be undefined with this pin left floating or held to logical ‘0’ (VSS). VSS 4 4 4 Ground SDA 5 5 5 Serial Address/Data I/O SCL 6 6 6 Serial Clock WP 7 7 7 Write-Protect Input VCC 8 8 8 Power Supply 2.1 A0, A1 Chip Address Inputs The A0 and A1 inputs are used by the 24XX1025 for multiple device operations. The levels on these inputs are compared with the corresponding bits in the client address. The chip is selected if the comparison is true. Up to four devices may be connected to the same bus by using different Chip Select bit combinations. In most applications, the chip address inputs A0 and A1 are hard-wired to logic ‘0’ or logic ‘1’. For applications in which these pins are controlled by a microcontroller or other programmable device, the chip address pins must be driven to logic ‘0’ or logic ‘1’ before normal device operation can proceed. 2.2 A2 Chip Address Input The A2 input is non-configurable Chip Select. This pin must be tied to VCC in order for this device to operate. If left floating or tied to VSS, device operation will be undefined. 2.3 Serial Address/Data Input/Output (SDA) This is a bidirectional pin used to transfer addresses and data into and data out of the device. It is an open-drain terminal, therefore, the SDA bus requires a pull-up resistor to VCC (typical 10 k for 100 kHz, 2 k for 400 kHz and 1 MHz). For normal data transfer SDA is allowed to change only during SCL low. Changes during SCL high are reserved for indicating the Start and Stop conditions. 2.4 Serial Clock (SCL) This input is used to synchronize the data transfer from and to the device. 2.5 Write-Protect (WP) This pin must be connected to either VSS or VCC. If tied to VSS, normal memory operation is enabled (read/write the entire memory 00000h to 1FFFFh). If tied to VCC, write operations are inhibited. The entire memory will be write-protected. Read operations are not affected.  2005-2021 Microchip Technology Inc. and its subsidiaries DS20001941M-page 7 24AA1025/24LC1025/24FC1025 3.0 FUNCTIONAL DESCRIPTION The 24XX1025 supports a bidirectional two-wire bus and data transmission protocol. A device that sends data onto the bus is defined as a transmitter and a device receiving data as a receiver. The bus must be controlled by a host device which generates the Serial Clock (SCL), controls the bus access, and generates the Start and Stop conditions while the 24XX1025 works as a client. Both host and client can operate as a transmitter or receiver, but the host device determines which mode is activated. 4.0 BUS CHARACTERISTICS The following bus protocol has been defined: • Data transfer may be initiated only when the bus is not busy. • During data transfer, the data line must remain stable whenever the clock line is high. Changes in the data line while the clock line is high will be interpreted as a Start or Stop condition. Accordingly, the following bus conditions have been defined (Figure 4-1). 4.1 Start Data Transfer (B) A high-to-low transition of the SDA line while the clock (SCL) is high determines a Start condition. All commands must be preceded by a Start condition. 4.3 Stop Data Transfer (C) Data Valid (D) The state of the data line represents valid data when, after a Start condition, the data line is stable for the duration of the high period of the clock signal. The data on the line must be changed during the low period of the clock signal. There is one bit of data per clock pulse. Each data transfer is initiated with a Start condition and terminated with a Stop condition. The number of the data bytes transferred between the Start and Stop conditions is determined by the host device and is, theoretically, unlimited (although only the last 128 will be stored when doing a write operation). When an overwrite does occur, it will replace data in a First-In First-Out (FIFO) principle. 4.5 Acknowledge Each receiving device, when addressed, is obliged to generate an Acknowledge after the reception of each byte. The host device must generate an extra clock pulse which is associated with this Acknowledge bit. Note: Bus Not Busy (A) Both data and clock lines remain high. 4.2 4.4 The 24XX1025 does not generate any Acknowledge bits if an internal programming cycle is in progress. A device that acknowledges must pull-down the SDA line during the Acknowledge clock pulse in such a way that the SDA line is stable-low during the high period of the Acknowledge-related clock pulse. Moreover, setup and hold times must be taken into account. During reads, a host must signal an end of data to the client by NOT generating an Acknowledge bit on the last byte that has been clocked out of the client. In this case, the client (24XX1025) will leave the data line high to enable the host to generate the Stop condition. A low-to-high transition of the SDA line while the clock (SCL) is high determines a Stop condition. All operations must end with a Stop condition. FIGURE 4-1: (A) DATA TRANSFER SEQUENCE ON THE SERIAL BUS (B) (D) Start Condition Address or Acknowledge Valid (D) (C) (A) SCL SDA DS20001941M-page 8 Data Allowed To Change Stop Condition  2005-2021 Microchip Technology Inc. and its subsidiaries 24AA1025/24LC1025/24FC1025 FIGURE 4-2: ACKNOWLEDGE TIMING Acknowledge Bit SCL SDA 1 2 3 4 5 6 7 Data from transmitter The transmitter must release the SDA line at this point allowing the receiver to pull the SDA line low to acknowledge the previous eight bits of data.  2005-2021 Microchip Technology Inc. and its subsidiaries 8 9 1 2 3 Data from transmitter The receiver must release the SDA line at this point so the transmitter can continue sending data. DS20001941M-page 9 24AA1025/24LC1025/24FC1025 5.0 DEVICE ADDRESSING FIGURE 5-1: A control byte is the first byte received following the Start condition from the host device (Figure 5-1). The control byte consists of a 4-bit control code; for the 24XX1025, this is set as ‘1010’ binary for read and write operations. The next bit of the control byte is the block select bit (B0). This bit acts as the A16 address bit for accessing the entire array. The next two bits of the control byte are the Chip Select bits (A1, A0). The Chip Select bits allow the use of up to four 24XX1025 devices on the same bus and are used to select which device is accessed. The Chip Select bits in the control byte must correspond to the logic levels on the corresponding A1 and A0 pins for the device to respond. These bits are in effect the two Most Significant bits (MSb) of the word address. The combination of the 4-bit control code and the next three bits are called the client address. The last bit of the control byte is the Read/Write (R/W) bit and it defines the operation to be performed. When set to a ‘1’, a read operation is selected. When set to a ‘0’, a write operation is selected. The next two bytes received define the address of the first data byte (Figure 5-2). The upper address bits are transferred first, followed by the Least Significant bits (LSb). Following the Start condition, the 24XX1025 monitors the SDA bus checking the device type identifier being transmitted. Upon receiving a valid client address and the R/W bit, the client device outputs an Acknowledge signal on the SDA line. Depending on the state of the R/W bit, the 24XX1025 will select a read or write operation. CONTROL BYTE FORMAT Read/Write Bit Block Select Bits Control Code S 1 0 1 0 B0 Chip Select Bits A1 A0 R/W ACK Client Address Start Bit 5.1 Acknowledge Bit Contiguous Addressing Across Multiple Devices The Chip Select bits A1 and A0 can be used to expand the contiguous address space for up to 4 Mbit by adding up to four 24XX1025’s on the same bus. In this case, software can use A0 of the control byte as address bit A17 and A1 as address bit A18. It is not possible to sequentially read across device boundaries. Each device has internal addressing boundary limitations. This divides each part into two segments of 512-Kbits. The block select bit ‘B0’ controls access to each “half”. Sequential read operations are limited to 512-Kbit blocks. To read through four devices on the same bus, eight random Read commands must be given. This device has an internal addressing boundary limitation that is divided into two segments of 512-Kbits. Block select bit ‘B0’ to control access to each segment. FIGURE 5-2: ADDRESS SEQUENCE BIT ASSIGNMENTS Control Byte 1 0 1 Control Code 0 B 0 A 1 Address High Byte A 0 R/W A A A A A A 15 14 13 12 11 10 Address Low Byte A 9 A 8 A 7 • • • • • • A 0 Block Chip Select Select Bits Bit DS20001941M-page 10  2005-2021 Microchip Technology Inc. and its subsidiaries 24AA1025/24LC1025/24FC1025 6.0 WRITE OPERATIONS 6.1 Byte Write Following the Start condition from the host, the control code (four bits), the block select (one bit), the Chip Select (two bits), and the R/W bit (which is a logic low) are clocked onto the bus by the host transmitter. This indicates to the addressed client receiver that the address high byte will follow after it has generated an Acknowledge bit during the ninth clock cycle. Therefore, the next byte transmitted by the host is the high-order byte of the word address and will be written into the Address Pointer of the 24XX1025. The next byte is the Least Significant Address Byte. After receiving another Acknowledge signal from the 24XX1025, the host device will transmit the data word to be written into the addressed memory location. The 24XX1025 acknowledges again and the host generates a Stop condition. This initiates the internal write cycle and during this time, the 24XX1025 will not generate Acknowledge signals as long as the control byte being polled matches the control byte that was used to initiate the write (Figure 6-1). If an attempt is made to write to the array with the WP pin held high, the device will acknowledge the command, but no write cycle will occur, no data will be written and the device will immediately accept a new command. After a byte Write command, the internal Address Pointer will point to the address location following the one that was just written. Note: 6.2 Page Write The write control byte, word address and the first data byte are transmitted to the 24XX1025 in the same way as in a byte write. But instead of generating a Stop condition, the host transmits up to 127 additional bytes, which are temporarily stored in the on-chip page buffer and will be written into memory after the host has transmitted a Stop condition. After receipt of each word, the seven lower Address Pointer bits, which form the byte counter, are internally incremented by one. The higher-order 9 bits of the word address remain constant. If the host should transmit more than 128 bytes prior to generating the Stop condition, the Address Pointer will roll over and the previously received data will be overwritten. As with the byte write operation, once the Stop condition is received, an internal write cycle will begin (Figure 6-2). If an attempt is made to write to the array with the WP pin held high, the device will acknowledge the command, but no write cycle will occur, no data will be written and the device will immediately accept a new command. Note: When doing a write of less than 128 bytes the data in the rest of the page are refreshed along with the data bytes being written. This will force the entire page to endure a write cycle, for this reason endurance is specified per page. 6.3 Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or ‘page size’) and end at addresses that are integer multiples of page size – 1. If a page write command attempts to write across a physical page boundary, the result is that the data wrap around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. Write Protection The WP pin allows the user to write-protect the entire array (00000-1FFFF) when the pin is tied to VCC. If tied to VSS the write protection is disabled. The WP pin is sampled at the Stop bit for every Write command (Figure 1-1). Toggling the WP pin after the Stop bit will have no effect on the execution of the write cycle.  2005-2021 Microchip Technology Inc. and its subsidiaries DS20001941M-page 11 24AA1025/24LC1025/24FC1025 FIGURE 6-1: BYTE WRITE S T A R T Bus Activity Host Control Byte Address High Byte Data P A C K Bus Activity FIGURE 6-2: SDA Line S T O P AA S1 010B 010 0 SDA Line Bus Activity Host Address Low Byte A C K A C K A C K PAGE WRITE S T A R T Control Byte Address High Byte Address Low Byte Data Byte 0 S T O P Data Byte 127 BAA S10100100 Bus Activity DS20001941M-page 12 P A C K A C K A C K A C K A C K  2005-2021 Microchip Technology Inc. and its subsidiaries 24AA1025/24LC1025/24FC1025 7.0 ACKNOWLEDGE POLLING Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete. (This feature can be used to maximize bus throughput.) Once the Stop condition for a write command has been issued from the host, the device initiates the internally timed write cycle. ACK polling can be initiated immediately. This involves the host sending a Start condition, followed by the control byte for a write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If no ACK is returned, then the Start bit and control byte must be resent. If the cycle is complete, then the device will return the ACK and the host can then proceed with the next read or write operation. See Figure 7-1 for flow diagram. Note: Care must be taken when polling the 24XX1025. The control byte that was used to initiate the write needs to match the control byte used for polling. FIGURE 7-1: ACKNOWLEDGE POLLING FLOW Send Write Command Send Stop Condition to Initiate Write Cycle Send Start Send Control Byte with R/W = 0 Did Device Acknowledge (ACK = 0)? No Yes Next Operation  2005-2021 Microchip Technology Inc. and its subsidiaries DS20001941M-page 13 24AA1025/24LC1025/24FC1025 8.0 READ OPERATION 8.2 Read operations are initiated in the same way as write operations with the exception that the R/W bit of the control byte is set to one. There are three basic types of read operations: current address read, random read and sequential read. 8.1 Current Address Read The 24XX1025 contains an Address Pointer that maintains the address of the last word accessed, internally incremented by one. Therefore, if the previous read access was to address n (n is any legal address), the next current address read operation would access data from address n + 1. Upon receipt of the control byte with R/W bit set to one, the 24XX1025 issues an Acknowledge and transmits the 8-bit data word. The host will not acknowledge the transfer, but does generate a Stop condition and the 24XX1025 discontinues transmission (Figure 8-1). FIGURE 8-1: CURRENT ADDRESS READ Bus Activity Host S T A R T SDA Line S 1 0 1 0 B AA 1 0 1 0 Control Byte Bus Activity DS20001941M-page 14 S T O P Data Byte P A C K N O A C K Random Read Random read operations allow the host to access any memory location in a random manner. To perform this type of read operation, first the word address must be set. This is done by sending the word address to the 24XX1025 as part of a write operation (R/W bit set to 0). After the word address is sent, the host generates a Start condition following the Acknowledge. This terminates the write operation, but not before the internal Address Pointer is set. Then, the host issues the control byte again, but with the R/W bit set to a one. The 24XX1025 will then issue an Acknowledge and transmit the 8-bit data word. The host will not acknowledge the transfer, but does generate a Stop condition which causes the 24XX1025 to discontinue transmission (Figure 8-2). After a random Read command, the internal Address Pointer will point to the address location following the one that was just read. 8.3 Sequential Read Sequential reads are initiated in the same way as a random read except that after the 24XX1025 transmits the first data byte, the host issues an Acknowledge as opposed to the Stop condition used in a random read. This Acknowledge directs the 24XX1025 to transmit the next sequentially addressed 8-bit word (Figure 8-3). Following the final byte transmitted to the host, the host will NOT generate an Acknowledge, but will generate a Stop condition. To provide sequential reads, the 24XX1025 contains an internal Address Pointer which is incremented by one at the completion of each operation. This Address Pointer allows half the memory contents to be serially read during one operation. Sequential read address boundaries are 00000h to 0FFFFh and 10000h to 1FFFFh. The internal Address Pointer will automatically roll over from address 0FFFFh to address 00000h if the host acknowledges the byte received from the array address 0FFFFh. The internal Address Pointer will automatically roll over from address 1FFFFh to address 10000h if the host acknowledges the byte received from the array address 1FFFFh.  2005-2021 Microchip Technology Inc. and its subsidiaries 24AA1025/24LC1025/24FC1025 FIGURE 8-2: Bus Activity Host SDA Line RANDOM READ S T A R T Control Byte S 1 0 1 0 Bus Activity Host S T A R T Address Low Byte B A A 0 0 1 0 Control Byte S 1 0 1 0 A C K A C K Bus Activity FIGURE 8-3: Address High Byte A C K S T O P Data Byte B A A 1 0 1 0 P N O A C K A C K SEQUENTIAL READ Control Byte Data n Data n + 1 S T O P Data n + X Data n + 2 P SDA Line Bus Activity A C K A C K  2005-2021 Microchip Technology Inc. and its subsidiaries A C K A C K N O A C K DS20001941M-page 15 24AA1025/24LC1025/24FC1025 9.0 PACKAGING INFORMATION 9.1 Package Marking Information 8-Lead PDIP (300 mil) XXXXXXXX TXXXXNNN YYWW 8-Lead SOIC (3.90 mm) XXXXXXXT XXXXYYWW NNN 8-Lead SOIJ (5.28 mm) XXXXXXXX TXXXXXXX YYWWNNN DS20001941M-page 16 Example 24LC1025 I/P e3 13F 2132 Example 24L1025I SN e3 2132 13F Example 24LC1025 I/SM e3 2132 13F  2005-2021 Microchip Technology Inc. and its subsidiaries 24AA1025/24LC1025/24FC1025 Part Number 1st Line Marking PDIP SOIJ SOIC 24AA1025 24AA1025 24AA1025 24A1025T(1) 24LC1025 24LC1025 24LC1025 24L1025T(1) 24FC1025 24FC1025 24FC1025 24F1025T(1) Note 1: T = Temperature grade (I, E) Legend: XX...X T Y YY WW NNN * Part number or part number code Temperature (I, E) Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code (2 characters for small packages) JEDEC® designator for Matte Tin (Sn) Standard OTP marking consists of Microchip part number, year code, week code, and traceability code. Note: For very small packages with no room for the JEDEC® designator e3 , the marking will only appear on the outer carton or reel label. Note: In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information.  2005-2021 Microchip Technology Inc. and its subsidiaries DS20001941M-page 17 24AA1025/24LC1025/24FC1025 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging D A N B E1 NOTE 1 1 2 TOP VIEW E C A2 A PLANE L c A1 e eB 8X b1 8X b .010 C SIDE VIEW END VIEW Microchip Technology Drawing No. C04-018-P Rev E Sheet 1 of 2 DS20001941M-page 18  2005-2021 Microchip Technology Inc. and its subsidiaries 24AA1025/24LC1025/24FC1025 8-Lead Plastic Dual In-Line (P) - 300 mil Body [PDIP] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging ALTERNATE LEAD DESIGN (NOTE 5) DATUM A DATUM A b b e 2 e 2 e e Units Dimension Limits Number of Pins N e Pitch Top to Seating Plane A Molded Package Thickness A2 Base to Seating Plane A1 Shoulder to Shoulder Width E Molded Package Width E1 Overall Length D Tip to Seating Plane L c Lead Thickness b1 Upper Lead Width b Lower Lead Width eB Overall Row Spacing § MIN .115 .015 .290 .240 .348 .115 .008 .040 .014 - INCHES NOM 8 .100 BSC .130 .310 .250 .365 .130 .010 .060 .018 - MAX .210 .195 .325 .280 .400 .150 .015 .070 .022 .430 Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. 5. Lead design above seating plane may vary, based on assembly vendor. Microchip Technology Drawing No. C04-018-P Rev E Sheet 2 of 2  2005-2021 Microchip Technology Inc. and its subsidiaries DS20001941M-page 19 24AA1025/24LC1025/24FC1025 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging 2X 0.10 C A–B D A D NOTE 5 N E 2 E1 2 E1 E 2X 0.10 C A–B 2X 0.10 C A–B NOTE 1 2 1 e B NX b 0.25 C A–B D NOTE 5 TOP VIEW 0.10 C C A A2 SEATING PLANE 8X A1 SIDE VIEW 0.10 C h R0.13 h R0.13 H SEE VIEW C VIEW A–A 0.23 L (L1) VIEW C Microchip Technology Drawing No. C04-057-SN Rev F Sheet 1 of 2 DS20001941M-page 20  2005-2021 Microchip Technology Inc. and its subsidiaries 24AA1025/24LC1025/24FC1025 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging Units Dimension Limits Number of Pins N e Pitch Overall Height A Molded Package Thickness A2 § Standoff A1 Overall Width E Molded Package Width E1 Overall Length D Chamfer (Optional) h Foot Length L L1 Footprint Foot Angle c Lead Thickness b Lead Width Mold Draft Angle Top Mold Draft Angle Bottom MIN 1.25 0.10 0.25 0.40 0° 0.17 0.31 5° 5° MILLIMETERS NOM 8 1.27 BSC 6.00 BSC 3.90 BSC 4.90 BSC 1.04 REF - MAX 1.75 0.25 0.50 1.27 8° 0.25 0.51 15° 15° Notes: 1. Pin 1 visual index feature may vary, but must be located within the hatched area. 2. § Significant Characteristic 3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15mm per side. 4. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. REF: Reference Dimension, usually without tolerance, for information purposes only. 5. Datums A & B to be determined at Datum H. Microchip Technology Drawing No. C04-057-SN Rev F Sheet 2 of 2  2005-2021 Microchip Technology Inc. and its subsidiaries DS20001941M-page 21 24AA1025/24LC1025/24FC1025 8-Lead Plastic Small Outline (SN) - Narrow, 3.90 mm (.150 In.) Body [SOIC] Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging SILK SCREEN C Y1 X1 E RECOMMENDED LAND PATTERN Units Dimension Limits E Contact Pitch Contact Pad Spacing C Contact Pad Width (X8) X1 Contact Pad Length (X8) Y1 MIN MILLIMETERS NOM 1.27 BSC 5.40 MAX 0.60 1.55 Notes: 1. Dimensioning and tolerancing per ASME Y14.5M BSC: Basic Dimension. Theoretically exact value shown without tolerances. Microchip Technology Drawing C04-2057-SN Rev F DS20001941M-page 22  2005-2021 Microchip Technology Inc. and its subsidiaries 24AA1025/24LC1025/24FC1025 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2005-2021 Microchip Technology Inc. and its subsidiaries DS20001941M-page 23 24AA1025/24LC1025/24FC1025 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20001941M-page 24  2005-2021 Microchip Technology Inc. and its subsidiaries 24AA1025/24LC1025/24FC1025 Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2005-2021 Microchip Technology Inc. and its subsidiaries DS20001941M-page 25 24AA1025/24LC1025/24FC1025 APPENDIX A: REVISION HISTORY Revision M (11/2021) Updated formatting to current template; Replaced terminology “Master” and “Slave” with “Host” and “Client” respectively; Added Automotive Product Identification System; Updated PDIP and SOIC package drawings. Revision B (09/2005) Section 1.0 Electrical Characteristics: revised Ambient Temperature; Revised Table 1-1; Revised Section 2.1 and Section 2.5. Revision A (02/2005) Original release. Revision L (08/2013) Features Section: Revised ESD Protection to 4000V. Revision K (04/2012) Revised document title (removed CMOS); Revised Section 5.1. Revision J (07/2011) Revised Table 1-2: AC Characteristics. Revision H (01/2011) Revised PDIP Package Type Diagram; Revised Section 1.0 Electrical Characteristics; Revised SOIC Package Marking Information (3.90mm). Revision G (01/2010) Added 8-Lead SOIC Package. Revision F (10/2008) Corrections on the Device Selection Table; Corrections on the Description; Corrections on the AC Characteristics table; Corrections on the Pin Function Table; Corrections on the Product ID System; Updated Package Drawings. Revision E (03/2007) Replaced Package Drawings (Rev. AM). Revision D (01/2007) Revised Device Selection Table; Features Section; Changed 1.8V to 1.7V; Revised Tables 1-1, 1-2, 2-1; Revised Product ID System; Replaced Package Drawings. Revision C (04/2006) Revised Features, Maximum Read Current and Table 1-1, D9; Revised Table 2-1, VCC; Revised Section 6.3. DS20001941M-page 26  2005-2021 Microchip Technology Inc. and its subsidiaries 24AA1025/24LC1025/24FC1025 THE MICROCHIP WEBSITE CUSTOMER SUPPORT Microchip provides online support via our website at www.microchip.com. This website is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the website contains the following information: Users of Microchip products can receive assistance through several channels: • Product Support – Data sheets and errata, application notes and sample programs, design resources, user’s guides and hardware support documents, latest software releases and archived software • General Technical Support – Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing • Business of Microchip – Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives • • • • Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Customers should contact their distributor, representative or Field Application Engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the website at: http://microchip.com/support CUSTOMER CHANGE NOTIFICATION SERVICE Microchip’s customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip website at www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.  2005-2021 Microchip Technology Inc. and its subsidiaries DS20001941M-page 27 24AA1025/24LC1025/24FC1025 PRODUCT IDENTIFICATION SYSTEM (NON-AUTOMOTIVE) To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. [X] PART NO. Device Device: (1) Tape and Reel 24AA1025 = 24LC1025 = 24FC1025 = -X /XX Temperature Range Package Examples: a) b) 1.7V, 1024-Kbit, I2C Serial EEPROM 2.5V, 1024-Kbit, I2C Serial EEPROM 1.8V, 1024-Kbit, I2C Serial EEPROM Tape and Reel Option: Blank = Standard packaging (tube or tray) T = Tape and Reel(1) Temperature Range: I E = = -40°C to +85°C (Industrial) -40°C to +125°C (Extended) Package: P = SN = SM = Plastic Dual In-Line – 300 mil Body, 8-Lead (PDIP) Plastic Small Outline - Narrow, 3.90 mm Body, 8-Lead (SOIC) Plastic Small Outline – Medium, 5.28 mm Body, 8-Lead (SOIJ) DS20001941M-page 28 c) d) e) 24AA1025T-I/SM: Tape and Reel, Industrial Temperature, SOIJ package. 24LC1025-I/P: Industrial Temperature, PDIP package. 24LC1025-E/SM: Extended Temperature, SOIJ package. 24LC1025T-I/SM: Tape and Reel, Industrial Temperature, SOIJ package. 24FC1025T-I/SN: Tape and Reel, Industrial Temperature, SOIC package. Note 1: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option.  2005-2021 Microchip Technology Inc. and its subsidiaries 24AA1025/24LC1025/24FC1025 PRODUCT IDENTIFICATION SYSTEM (AUTOMOTIVE) To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. (1) [X] PART NO. Device Tape and Reel Option (2, 3) X /XX XXX Temperature Range Package Variant Device: 24LC1024 = 2.5V, 1024-Kbit, I2C Serial EEPROM 24FC1024 = 1.8V, 1024-Kbit, I2C Serial EEPROM Tape and Reel Option: Blank T = Standard packaging (tube or tray) = Tape and Reel(1) Temperature Range: I E = -40C to +85C (AEC-Q100 Grade 3) = -40C to +125C (AEC-Q100 Grade 1) Package: SN = Plastic Small Outline – Narrow, 3.90 mm Body, 8-Lead (SOIC) = Plastic Small Outline – Medium, 5.28 mm Body, 8-Lead (SOIJ) SM Variant(2, 3): Examples: a) 24LC1025-E/SN16KVAO : Automotive Grade 1, 2.5V, SOIC Package. b) 24LC1025T-E/SN16KVAO : Tape and Reel, Automotive Grade 1, 2,5V, SOIC Package. c) 24FC1025T-I/SM16KVAO : Tape and Reel, Automotive Grade 3, 1.8V, SOIJ Package. Note 1: 2: 3: 16KVAO = Standard Automotive, 16K Process 16KVXX = Customer-Specific Automotive, 16K Process  2005-2021 Microchip Technology Inc. and its subsidiaries Tape and Reel identifier only appears in the catalog part number description. This identifier is used for ordering purposes and is not printed on the device package. Check with your Microchip Sales Office for package availability with the Tape and Reel option. The VAO/VXX automotive variants have been designed, manufactured, tested and qualified in accordance with AEC-Q100 requirements for automotive applications. For customers requesting a PPAP, a customer-specific part number will be generated and provided. A PPAP is not provided for VAO part numbers. DS20001941M-page 29 Note the following details of the code protection feature on Microchip products: • Microchip products meet the specifications contained in their particular Microchip Data Sheet. • Microchip believes that its family of products is secure when used in the intended manner, within operating specifications, and under normal conditions. • Microchip values and aggressively protects its intellectual property rights. Attempts to breach the code protection features of Microchip product is strictly prohibited and may violate the Digital Millennium Copyright Act. • Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not mean that we are guaranteeing the product is “unbreakable”. Code protection is constantly evolving. Microchip is committed to continuously improving the code protection features of our products. This publication and the information herein may be used only with Microchip products, including to design, test, and integrate Microchip products with your application. Use of this information in any other manner violates these terms. Information regarding device applications is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. Contact your local Microchip sales office for additional support or, obtain additional support at https:// www.microchip.com/en-us/support/design-help/client-supportservices. THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS". MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION INCLUDING BUT NOT LIMITED TO ANY IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A PARTICULAR PURPOSE, OR WARRANTIES RELATED TO ITS CONDITION, QUALITY, OR PERFORMANCE. IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL, OR CONSEQUENTIAL LOSS, DAMAGE, COST, OR EXPENSE OF ANY KIND WHATSOEVER RELATED TO THE INFORMATION OR ITS USE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES ARE FORESEEABLE. TO THE FULLEST EXTENT ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES, IF ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP FOR THE INFORMATION. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights unless otherwise stated. Trademarks The Microchip name and logo, the Microchip logo, Adaptec, AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, CryptoMemory, CryptoRF, dsPIC, flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower, PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. AgileSwitch, APT, ClockWorks, The Embedded Control Solutions Company, EtherSynch, Flashtec, Hyper Speed Control, HyperLight Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, QuietWire, SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub, TimePictra, TimeProvider, TrueTime, WinPath, and ZL are registered trademarks of Microchip Technology Incorporated in the U.S.A. Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any Capacitor, AnyIn, AnyOut, Augmented Switching, BlueSky, BodyCom, CodeGuard, CryptoAuthentication, CryptoAutomotive, CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average Matching, DAM, ECAN, Espresso T1S, EtherGREEN, GridTime, IdealBridge, In-Circuit Serial Programming, ICSP, INICnet, Intelligent Paralleling, Inter-Chip Connectivity, JitterBlocker, Knob-on-Display, maxCrypto, maxView, memBrain, Mindi, MiWi, MPASM, MPF, MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach, NVM Express, NVMe, Omniscient Code Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP, SimpliPHY, SmartBuffer, SmartHLS, SMART-I.S., storClad, SQI, SuperSwitcher, SuperSwitcher II, Switchtec, SynchroPHY, Total Endurance, TSHARC, USBCheck, VariSense, VectorBlox, VeriPHY, ViewSpan, WiperLock, XpressConnect, and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. The Adaptec logo, Frequency on Demand, Silicon Storage Technology, Symmcom, and Trusted Time are registered trademarks of Microchip Technology Inc. in other countries. GestIC is a registered trademark of Microchip Technology Germany II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in other countries. All other trademarks mentioned herein are property of their respective companies. © 2005-2021, Microchip Technology Incorporated and its subsidiaries. All Rights Reserved. For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality. DS20001941M-page 30 ISBN: 978-1-5224-9157-6  2005-2021 Microchip Technology Inc. Worldwide Sales and Service AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://www.microchip.com/ support Web Address: www.microchip.com Australia - Sydney Tel: 61-2-9868-6733 India - Bangalore Tel: 91-80-3090-4444 China - Beijing Tel: 86-10-8569-7000 India - New Delhi Tel: 91-11-4160-8631 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 China - Chengdu Tel: 86-28-8665-5511 India - Pune Tel: 91-20-4121-0141 Denmark - Copenhagen Tel: 45-4485-5910 Fax: 45-4485-2829 China - Chongqing Tel: 86-23-8980-9588 Japan - Osaka Tel: 81-6-6152-7160 Finland - Espoo Tel: 358-9-4520-820 China - Dongguan Tel: 86-769-8702-9880 Japan - Tokyo Tel: 81-3-6880- 3770 China - Guangzhou Tel: 86-20-8755-8029 Korea - Daegu Tel: 82-53-744-4301 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 China - Hangzhou Tel: 86-571-8792-8115 Korea - Seoul Tel: 82-2-554-7200 China - Hong Kong SAR Tel: 852-2943-5100 Malaysia - Kuala Lumpur Tel: 60-3-7651-7906 China - Nanjing Tel: 86-25-8473-2460 Malaysia - Penang Tel: 60-4-227-8870 China - Qingdao Tel: 86-532-8502-7355 Philippines - Manila Tel: 63-2-634-9065 China - Shanghai Tel: 86-21-3326-8000 Singapore Tel: 65-6334-8870 China - Shenyang Tel: 86-24-2334-2829 Taiwan - Hsin Chu Tel: 886-3-577-8366 China - Shenzhen Tel: 86-755-8864-2200 Taiwan - Kaohsiung Tel: 886-7-213-7830 Israel - Ra’anana Tel: 972-9-744-7705 China - Suzhou Tel: 86-186-6233-1526 Taiwan - Taipei Tel: 886-2-2508-8600 China - Wuhan Tel: 86-27-5980-5300 Thailand - Bangkok Tel: 66-2-694-1351 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 China - Xian Tel: 86-29-8833-7252 Vietnam - Ho Chi Minh Tel: 84-28-5448-2100 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Austin, TX Tel: 512-257-3370 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Novi, MI Tel: 248-848-4000 Houston, TX Tel: 281-894-5983 Indianapolis Noblesville, IN Tel: 317-773-8323 Fax: 317-773-5453 Tel: 317-536-2380 China - Xiamen Tel: 86-592-2388138 China - Zhuhai Tel: 86-756-3210040 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Tel: 951-273-7800 Raleigh, NC Tel: 919-844-7510 New York, NY Tel: 631-435-6000 San Jose, CA Tel: 408-735-9110 Tel: 408-436-4270 Canada - Toronto Tel: 905-695-1980 Fax: 905-695-2078  2005-2021 Microchip Technology Inc. and its subsidiaries Germany - Garching Tel: 49-8931-9700 Germany - Haan Tel: 49-2129-3766400 Germany - Heilbronn Tel: 49-7131-72400 Germany - Karlsruhe Tel: 49-721-625370 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Germany - Rosenheim Tel: 49-8031-354-560 Italy - Padova Tel: 39-049-7625286 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Norway - Trondheim Tel: 47-7288-4388 Poland - Warsaw Tel: 48-22-3325737 Romania - Bucharest Tel: 40-21-407-87-50 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 Sweden - Gothenberg Tel: 46-31-704-60-40 Sweden - Stockholm Tel: 46-8-5090-4654 UK - Wokingham Tel: 44-118-921-5800 Fax: 44-118-921-5820 DS20001941M-page 31 09/14/21