25AA02UID-I/SN

25AA02UID 2K SPI Bus Serial EEPROM with Unique 32-Bit Serial Number Device Selection Table Part Number 25AA02UID VCC Range Page Size Temp. Ranges Packages Unique ID Length 1.8-5.5V 16 Bytes I SN, OT 32-Bit Features: Description: • Preprogrammed 32-Bit Serial Number: - Unique across all UID-family EEPROMs - Scalable to 48-bit, 64-bit, 128-bit, 256-bit, and other lengths • 10 MHz max. Clock Frequency • Low-Power CMOS Technology: - Max. write current: 5 mA at 5.5V - Read current: 5 mA at 5.5V, 10 MHz - Standby current: 1 A at 2.5V • 256 x 8-Bit Organization • Write Page mode (up to 16 bytes) • Sequential Read • Self-Timed Erase and Write Cycles (5 ms max.) • Block Write Protection: - Protect none, 1/4, 1/2 or all of array • Built-in Write Protection: - Power-on/off data protection circuitry - Write enable latch - Write-protect pin • High Reliability: - Endurance: 1,000,000 erase/write cycles - Data retention: >200 years - ESD protection: >4000V • Temperature Ranges Supported: - Industrial (I): -40C to +85C The Microchip Technology Inc. 25AA02UID is a 2 Kbit Serial Electrically Erasable Programmable Read-Only Memory (EEPROM) with a preprogrammed, 32-bit unique ID. The memory is accessed via a simple Serial Peripheral Interface (SPI) compatible serial bus. The bus signals required are a clock input (SCK) plus separate data in (SI) and data out (SO) lines. Access to the device is controlled through a Chip Select (CS) input. • RoHS Compliant SOT-23 SOIC (OT) (SN) 1 6 VSS 2 5 CS SI 3 4 SO VDD  2013 Microchip Technology Inc. The 25AA02UID is available in the standard 8-lead SOIC and 6-lead SOT-23 packages. Pin Function Table Name CS SO 1 2 8 7 VCC HOLD WP 3 6 SCK VSS 4 5 SI Function CS Chip Select Input SO Serial Data Output WP Write-Protect VSS Ground SI Serial Data Input SCK Serial Clock Input HOLD VCC Package Types (not to scale) SCK Communication to the device can be paused via the hold pin (HOLD). While the device is paused, transitions on its inputs will be ignored, with the exception of Chip Select, allowing the host to service higher priority interrupts. Hold Input Supply Voltage DS20005205A-page 1 25AA02UID 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings(†) VCC .............................................................................................................................................................................6.5V All inputs and outputs w.r.t. VSS ......................................................................................................... -0.6V to VCC +1.0V Storage temperature .................................................................................................................................-65°C to 150°C Ambient temperature under bias .................................................................................................................-40°C to 85°C ESD protection on all pins ..........................................................................................................................................4 kV † NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for an extended period of time may affect device reliability. TABLE 1-1: DC CHARACTERISTICS DC CHARACTERISTICS Param. No. D001 Sym. Characteristic Industrial (I): TA = -40°C to +85°C Min. Max. Units VCC = 1.8V to 5.5V Test Conditions VIH1 High-level Input voltage 0.7 VCC VCC +1 V Low-level Input Voltage -0.3 0.3 VCC V VCC2.7V (Note 1) -0.3 0.2 VCC V VCC < 2.7V (Note 1) Low-level Output Voltage — 0.4 V IOL = 2.1 mA — 0.2 V IOL = 1.0 mA, VCC < 2.5V VCC -0.5 — V IOH = -400 A D002 VIL1 D003 VIL2 D004 VOL D005 VOL D006 VOH High-level Output Voltage D007 ILI Input Leakage Current — ±1 A CS = VCC, VIN = VSS or VCC D008 ILO Output Leakage Current — ±1 A CS = VCC, VOUT = VSS or VCC D009 CINT Internal Capacitance (all inputs and outputs) — 7 pF TA = 25°C, CLK = 1.0 MHz, VCC = 5.0V (Note 1) D010 ICC Read — 5 mA — 2.5 mA VCC = 5.5V; FCLK = 10.0 MHz; SO = Open VCC = 2.5V; FCLK = 5.0 MHz; SO = Open — — 5 3 mA mA VCC = 5.5V VCC = 2.5V — 1 A CS = VCC = 2.5V, Inputs tied to VCC or VSS, TA = +85°C Operating Current D011 ICC Write D012 ICCS Note: Standby Current This parameter is periodically sampled and not 100% tested. DS20005205A-page 2  2013 Microchip Technology Inc. 25AA02UID TABLE 1-2: AC CHARACTERISTICS AC CHARACTERISTICS Param. Sym. No. Characteristic Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 5.5V Min. Max. Units Test Conditions — — — 10 5 3 MHz MHz MHz 4.5V VCC  5.5V 2.5V VCC  4.5V 1.8V VCC  2.5V 1 FCLK Clock Frequency 2 TCSS CS Setup Time 50 100 150 — — — ns ns ns 4.5V VCC  5.5V 2.5V VCC  4.5V 1.8V VCC  2.5V 3 TCSH CS Hold Time 100 200 250 — — — ns ns ns 4.5V VCC  5.5V 2.5V VCC  4.5V 1.8V VCC  2.5V 4 TCSD CS Disable Time 50 — ns — 5 Tsu Data Setup Time 10 20 30 — — — ns ns ns 4.5V VCC  5.5V 2.5V VCC  4.5V 1.8V VCC  2.5V 6 THD Data Hold Time 20 40 50 — — — ns ns ns 4.5V VCC  5.5V 2.5V VCC  4.5V 1.8V VCC  2.5V 7 TR CLK Rise Time — 100 ns (Note 1) 8 TF CLK Fall Time — 100 ns (Note 1) 9 THI Clock High Time 50 100 150 — — — ns ns ns 4.5V VCC  5.5V 2.5V VCC  4.5V 1.8V VCC  2.5V 10 TLO Clock Low Time 50 100 150 — — — ns ns ns 4.5V VCC  5.5V 2.5V VCC  4.5V 1.8V VCC  2.5V 11 TCLD Clock Delay Time 50 — ns — 12 TCLE Clock Enable Time 50 — ns — 13 TV Output Valid from Clock Low — — — 50 100 160 ns ns ns 4.5V VCC  5.5V 2.5V VCC  4.5V 1.8V VCC  2.5V 14 THO Output Hold Time 0 — ns (Note 1) 15 TDIS Output Disable Time — — — 40 80 160 ns ns ns 4.5V VCC  5.5V (Note 1) 2.5V VCC  4.5V (Note 1) 1.8V VCC  2.5V (Note 1) 16 THS HOLD Setup Time 20 40 80 — — — ns ns ns 4.5V VCC  5.5V 2.5V VCC  4.5V 1.8V VCC  2.5V Note 1: This parameter is periodically sampled and not 100% tested. 2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.Microchip.com. 3: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is complete.  2013 Microchip Technology Inc. DS20005205A-page 3 25AA02UID TABLE 1-2: AC CHARACTERISTICS (CONTINUED) AC CHARACTERISTICS Param. Sym. No. Industrial (I): Characteristic TA = -40°C to +85°C Min. Max. Units VCC = 1.8V to 5.5V Test Conditions 17 THH HOLD Hold Time 20 40 80 — — — ns ns ns 4.5V VCC  5.5V 2.5V VCC  4.5V 1.8V VCC  2.5V 18 THZ HOLD Low to Output High-Z 30 60 160 — — — ns ns ns 4.5V VCC  5.5V (Note 1) 2.5V VCC  4.5V (Note 1) 1.8V VCC  2.5V (Note 1) 19 THV HOLD High to Output Valid 30 60 160 — — — ns ns ns 4.5V VCC  5.5V 2.5V VCC  4.5V 1.8V VCC  2.5V 20 TWC Internal Write Cycle Time (byte or page) — 5 ms (Note 3) 21 — Endurance 1M — E/W 25°C, VCC = 5.5V (Note 2) Cycles Note 1: This parameter is periodically sampled and not 100% tested. 2: This parameter is not tested but ensured by characterization. For endurance estimates in a specific application, please consult the Total Endurance™ Model which can be obtained from Microchip’s web site at www.Microchip.com. 3: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle is complete. TABLE 1-3: AC TEST CONDITIONS AC Waveform: VLO = 0.2V — VHI = VCC - 0.2V (Note 1) VHI = 4.0V (Note 2) CL = 100 pF — Timing Measurement Reference Level Input 0.5 VCC Output 0.5 VCC Note 1: For VCC  4.0V. 2: For VCC  4.0V. DS20005205A-page 4  2013 Microchip Technology Inc. 25AA02UID FIGURE 1-1: HOLD TIMING CS 17 16 17 16 SCK 18 SO n+2 SI n+2 n+1 n 19 High-Impedance n 5 Don’t Care n+1 n-1 n n n-1 HOLD FIGURE 1-2: SERIAL INPUT TIMING 4 CS 2 7 Mode 1,1 8 3 12 11 SCK Mode 0,0 5 SI 6 MSB in LSB in High-Impedance SO FIGURE 1-3: SERIAL OUTPUT TIMING CS 9 3 10 Mode 1,1 SCK Mode 0,0 13 SO 14 MSB out SI  2013 Microchip Technology Inc. 15 ISB out Don’t Care DS20005205A-page 5 25AA02UID 2.0 FUNCTIONAL DESCRIPTION 2.1 Principles of Operation The 25AA02UID is a 256-byte Serial EEPROM designed to interface directly with the Serial Peripheral Interface (SPI) port of many of today’s popular microcontroller families, including Microchip’s PIC® microcontrollers. It may also interface with microcontrollers that do not have a built-in SPI port by using discrete I/O lines programmed properly in software to match the SPI protocol. The 25AA02UID contains an 8-bit instruction register. The device is accessed via the SI pin, with data being clocked in on the rising edge of SCK. The CS pin must be low and the HOLD pin must be high for the entire operation. Table 2-1 contains a list of the possible instruction bytes and format for device operation. All instructions, addresses, and data are transferred MSb first, LSb last. Data (SI) is sampled on the first rising edge of SCK after CS goes low. If the clock line is shared with other peripheral devices on the SPI bus, the user can assert the HOLD input and place the 25AA02UID in ‘HOLD’ mode. After releasing the HOLD pin, operation will resume from the point when the HOLD was asserted. 2.2 Read Sequence The device is selected by pulling CS low. The 8-bit READ instruction is transmitted to the 25AA02UID followed by an 8-bit address. See Figure 2-1 for more details. After the correct READ instruction and address are sent, the data stored in the memory at the selected address is shifted out on the SO pin. Data stored in the memory at the next address can be read sequentially by continuing to provide clock pulses to the slave. The internal Address Pointer automatically increments to the next higher address after each byte of data is shifted out. When the highest address is reached (FFh), the address counter rolls over to address 00h, allowing the read cycle to be continued indefinitely. The read operation is terminated by raising the CS pin (Figure 2-1). 2.3 After setting the write enable latch, the user may proceed by driving CS low, issuing a WRITE instruction, followed by the remainder of the address, and then the data to be written. Up to 16 bytes of data can be sent to the device before a write cycle is necessary. The only restriction is that all of the bytes must reside in the same page. Additionally, a page address begins with XXXX 0000 and ends with XXXX 1111. If the internal address counter reaches XXXX 1111 and clock signals continue to be applied to the chip, the address counter will roll back to the first address of the page and overwrite any data that previously existed in those locations. Note: Page write operations are limited to writing bytes within a single physical page, regardless of the number of bytes actually being written. Physical page boundaries start at addresses that are integer multiples of the page buffer size (or ‘page size’) and, end at addresses that are integer multiples of page size – 1. If a page Write command attempts to write across a physical page boundary, the result is that the data wraps around to the beginning of the current page (overwriting data previously stored there), instead of being written to the next page as might be expected. It is therefore necessary for the application software to prevent page write operations that would attempt to cross a page boundary. For the data to be actually written to the array, the CS must be brought high after the Least Significant bit (D0) of the nth data byte has been clocked in. If CS is driven high at any other time, the write operation will not be completed. Refer to Figure 2-2 and Figure 2-3 for more detailed illustrations on the byte write sequence and the page write sequence, respectively. While the write is in progress, the STATUS register may be read to check the status of the WIP, WEL, BP1 and BP0 bits (Figure 2-6). Attempting to read a memory array location will not be possible during a write cycle. Polling the WIP bit in the STATUS register is recommended in order to determine if a write cycle is in progress. When the write cycle is completed, the write enable latch is reset. Write Sequence Prior to any attempt to write data to the 25AA02UID, the write enable latch must be set by issuing the WREN instruction (Figure 2-4). This is done by setting CS low and then clocking out the proper instruction into the 25AA02UID. After all eight bits of the instruction are transmitted, CS must be driven high to set the write enable latch. If the write operation is initiated immediately after the WREN instruction without CS driven high, data will not be written to the array since the write enable latch was not properly set. DS20005205A-page 6  2013 Microchip Technology Inc. 25AA02UID BLOCK DIAGRAM STATUS Register HV Generator Memory Control Logic I/O Control Logic EEPROM Array X Dec Page Latches SI SO Y Decoder CS SCK Sense Amp. R/W Control HOLD WP VCC VSS TABLE 2-1: INSTRUCTION SET Instruction Name Instruction Format Description READ 0000 x011 Read data from memory array beginning at selected address WRITE 0000 x010 Write data to memory array beginning at selected address WRDI 0000 x100 Reset the write enable latch (disable write operations) WREN 0000 x110 Set the write enable latch (enable write operations) RDSR 0000 x101 Read STATUS register WRSR 0000 x001 Write STATUS register x = don’t care FIGURE 2-1: READ SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCK Instruction SI 0 0 0 0 0 Address Byte 0 1 1 A7 A6 A5 A4 A3 A2 A1 A0 Data Out High-Impedance SO  2013 Microchip Technology Inc. 7 6 5 4 3 2 1 0 DS20005205A-page 7 25AA02UID FIGURE 2-2: BYTE WRITE SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCK Instruction SI 0 0 0 0 0 Address Byte 0 Data Byte 0 A7 A6 A5 A4 A3 A2 A1 A0 1 Twc 7 6 5 4 3 2 1 0 High-Impedance SO FIGURE 2-3: PAGE WRITE SEQUENCE CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 SCK Address Byte Instruction SI 0 0 0 0 0 0 1 Data Byte 1 0 A7 A6 A5 A4 A3 A2 A1 A0 7 6 5 4 3 2 1 0 CS 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 SCK Data Byte 2 SI 7 6 DS20005205A-page 8 5 4 3 2 Data Byte 3 1 0 7 6 5 4 3 2 Data Byte n (16 max) 1 0 7 6 5 4 3 2 1 0  2013 Microchip Technology Inc. 25AA02UID 2.4 Write Enable (WREN) and Write Disable (WRDI) The following is a list of conditions under which the write enable latch will be reset: • • • • • The 25AA02UID contains a write enable latch. See Table 2-4 for the Write-Protect Functionality Matrix. This latch must be set before any write operation will be completed internally. The WREN instruction will set the latch, and the WRDI will reset the latch. FIGURE 2-4: Power-up WRDI instruction successfully executed WRSR instruction successfully executed WRITE instruction successfully executed WP pin is brought low WRITE ENABLE SEQUENCE (WREN) CS 0 1 2 3 4 5 6 7 SCK 0 SI 0 0 0 1 1 0 High-Impedance SO FIGURE 2-5: 0 WRITE DISABLE SEQUENCE (WRDI) CS 0 1 2 3 4 5 6 7 SCK SI 0 0 0 0 0 1 0 0 High-Impedance SO  2013 Microchip Technology Inc. DS20005205A-page 9 25AA02UID 2.5 Read Status Register Instruction (RDSR) The Write Enable Latch (WEL) bit indicates the status of the write enable latch and is read-only. When set to a ‘1’, the latch allows writes to the array, when set to a ‘0’, the latch prohibits writes to the array. The state of this bit can always be updated via the WREN or WRDI commands regardless of the state of write protection on the STATUS register. These commands are shown in Figure 2-4 and Figure 2-5. The Read Status Register instruction (RDSR) provides access to the STATUS register. See Figure 2-6 for the RDSR timing sequence. The STATUS register may be read at any time, even during a write cycle. The STATUS register is formatted as follows: TABLE 2-2: The Block Protection (BP0 and BP1) bits indicate which blocks are currently write-protected. These bits are set by the user issuing the WRSR instruction, which is shown in Figure 2-7. These bits are nonvolatile and are described in more detail in Table 2-3. STATUS REGISTER 7 6 5 4 3 2 1 – – – – W/R W/R R X X X X BP1 BP0 WEL W/R = writable/readable. R = read-only. 0 R WIP The Write-In-Process (WIP) bit indicates whether the 25AA02UID is busy with a write operation. When set to a ‘1’, a write is in progress, when set to a ‘0’, no write is in progress. This bit is read-only. FIGURE 2-6: READ STATUS REGISTER TIMING SEQUENCE (RDSR) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0 SCK Instruction SI 0 0 0 0 0 High-Impedance SO DS20005205A-page 10 1 0 1 Data from STATUS register 7 6 5 4 3 2  2013 Microchip Technology Inc. 25AA02UID 2.6 Write Status Register Instruction (WRSR) TABLE 2-3: The Write Status Register instruction (WRSR) allows the user to write to the nonvolatile bits in the STATUS register, as shown in Table 2-2. See Figure 2-7 for the WRSR timing sequence. Four levels of protection for the array are selectable by writing to the appropriate bits in the STATUS register. The user has the ability to write-protect none, one, two, or all four of the segments of the array as shown in Table 2-3. FIGURE 2-7: ARRAY PROTECTION BP1 BP0 Array Addresses Write-Protected 0 0 none 0 1 upper 1/4 (C0h-FFh) 1 0 upper 1/2 (80h-FFh) 1 1 all (00h-FFh) WRITE STATUS REGISTER TIMING SEQUENCE (WRSR) CS 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 1 0 SCK Instruction SI 0 0 0 0 Data to STATUS register 0 0 0 1 7 6 5 4 3 2 High-Impedance SO  2013 Microchip Technology Inc. DS20005205A-page 11 25AA02UID 2.7 Data Protection 2.8 The following protection has been implemented to prevent inadvertent writes to the array: • The write enable latch is reset on power-up • A write enable instruction must be issued to set the write enable latch • After a byte write, page write or STATUS register write, the write enable latch is reset • CS must be set high after the proper number of clock cycles to start an internal write cycle • Access to the array during an internal write cycle is ignored and programming is continued TABLE 2-4: Power-On State The 25AA02UID powers on in the following state: • The device is in low-power Standby mode (CS = 1) • The write enable latch is reset • SO is in high-impedance state • A high-to-low-level transition on CS is required to enter active state WRITE-PROTECT FUNCTIONALITY MATRIX WP (pin 3) WEL (SR bit 1) Protected Blocks Unprotected Blocks STATUS Register 0 (low) x Protected Protected Protected 1 (high) 0 Protected Protected Protected 1 (high) 1 Protected Writable Writable x = don’t care DS20005205A-page 12  2013 Microchip Technology Inc. 25AA02UID 3.0 PREPROGRAMMED UNIQUE 32-BIT SERIAL NUMBER 3.1 In addition to the serial number, a manufacturer code is stored at location 0xFA and a device identifier is stored at 0xFB. The manufacturer code is fixed as 0x29. For the 25AA02UID, the device identifier is 0x51. The ‘5’ indicates the SPI family and the ‘1’ indicates a 2 Kbit memory density. The 25AA02UID is programmed at the factory with a unique 32-bit serial number stored in the upper 1/4 of the array and write-protected through the STATUS register. The remaining 1,536 bits are available for application use. Note: The 32-bit serial number is unique across all Microchip UID-family serial EEPROM devices. FIGURE 3-1: 3.2 00h 7 X — Standard EEPROM FFh Manufacturer Code Device Code Data 29h 51h Type 3.3 5 X — 4 X — 3 BP1 0 2 BP0 1 1 WEL — 0 WIP — SERIAL NUMBER PHYSICAL MEMORY MAP EXAMPLE Description Array Address 6 X — This protects the upper 1/4 of the array (0xC0 to 0xFF) from write operations. This array block can be utilized for writing by clearing the BP bits with a Write Status Register (WRSR) instruction. Note that if this is performed, care must be taken to prevent overwriting the serial number. C0h The 4-byte serial number is stored in array locations 0xFC through 0xFF, as shown in Figure 3-2. FIGURE 3-2: Factory-Programmed Write Protection In order to help guard against accidental corruption of the serial number, the BP1 and BP0 bits of the STATUS register are programmed at the factory to ‘0’ and ‘1’, respectively, as shown in the following table: MEMORY ORGANIZATION Write-Protected Serial Number Block Manufacturer and Device Codes 32-bit Serial Number 12h 34h Fixed FAh 78h FEh FFh Serialized FBh Extending the 32-bit Serial Number For applications that require serial numbers larger than 32 bits, additional data bytes can be used to pad the provided serial number to meet the required length. Any data byte values can be used for padding as the 32-bit serial number ensures the extended serial number remains unique. The padding can be performed in two ways. The first method is to pad the data in software by combining the 32-bit serial number from the 25AA02UID with fixed data. The second method is to extend the number of bytes read from the 25AA02UID to meet the required length. Table 3-1 shows example address ranges and their corresponding serial number lengths.  2013 Microchip Technology Inc. 56h FCh FDh TABLE 3-1: EXTENDED READ EXAMPLES Start Address End Address Serial Number Length 0xFC 0xFF 32 bits 0xFA 0xFF 48 bits 0xF8 0xFF 64 bits 0xF0 0xFF 128 bits 0xE0 0xFF 256 bits DS20005205A-page 13 25AA02UID 4.0 PIN DESCRIPTIONS The descriptions of the pins are listed in Table 4-1. 4.5 TABLE 4-1: The SCK is used to synchronize the communication between a master and the 25AA02UID. Instructions, addresses or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin is updated after the falling edge of the clock input. PIN FUNCTION TABLE Name SOIC SOT-23 Function Chip Select Input Serial Clock (SCK) CS 1 5 SO 2 4 Serial Data Output WP 3 — Write-Protect Pin 4.6 VSS 4 2 Ground SI 5 3 Serial Data Input Serial Clock Input The HOLD pin is used to suspend transmission to the 25AA02UID while in the middle of a serial sequence without having to retransmit the entire sequence again. It must be held high any time this function is not being used. Once the device is selected and a serial sequence is underway, the HOLD pin may be pulled low to pause further serial communication without resetting the serial sequence. The HOLD pin must be brought low while SCK is low, otherwise the HOLD function will not be invoked until the next SCK high-tolow transition. The 25AA02UID must remain selected during this sequence. The SI, SCK and SO pins are in a high-impedance state during the time the device is paused and transitions on these pins will be ignored. To resume serial communication, HOLD must be brought high while the SCK pin is low, otherwise serial communication will not resume. Lowering the HOLD line at any time will tri-state the SO line. SCK 6 1 HOLD 7 — Hold Input VCC 8 6 Supply Voltage 4.1 Chip Select (CS) A low level on this pin selects the device. A high level deselects the device and forces it into Standby mode. However, a programming cycle which is already initiated or in progress will be completed, regardless of the CS input signal. If CS is brought high during a program cycle, the device will go into Standby mode as soon as the programming cycle is complete. When the device is deselected, SO goes to the high-impedance state, allowing multiple parts to share the same SPI bus. A low-to-high transition on CS after a valid write sequence initiates an internal write cycle. After powerup, a low level on CS is required prior to any sequence being initiated. 4.2 Hold (HOLD) Serial Output (SO) The SO pin is used to transfer data out of the 25AA02UID. During a read cycle, data is shifted out on this pin after the falling edge of the serial clock. 4.3 Write-Protect (WP) The WP pin is a hardware write-protect input pin. When it is low, all writes to the array or STATUS register are disabled, but any other operations function normally. When WP is high, all functions, including nonvolatile writes operate normally. At any time, when WP is low, the write enable Reset latch will be reset and programming will be inhibited. However, if a write cycle is already in progress, WP going low will not change or disable the write cycle. See Table 2-4 for the Write-Protect Functionality Matrix. 4.4 Serial Input (SI) The SI pin is used to transfer data into the device. It receives instructions, addresses and data. Data is latched on the rising edge of the serial clock. DS20005205A-page 14  2013 Microchip Technology Inc. 25AA02UID 5.0 PACKAGING INFORMATION 5.1 Package Marking Information Example: 8-Lead SOIC 25A2UIDI SN e3 1327 1L7 XXXXXXXT XXXXYYWW NNN 6-Lead SOT-23 Example: XXXXY WWNNN AAAD3 271L7 1st Line Marking Code Part Number 25AA02UID Legend: XX...X T Y YY WW NNN e3 Note: Note: SOIC SOT-23 I Temp. I Temp. 25A2UIDT AAADY Part number or part number code Temperature (I, E) Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week ‘01’) Alphanumeric traceability code (2 characters for small packages) Pb-free JEDEC designator for Matte Tin (Sn) For very small packages with no room for the Pb-free JEDEC designator e3 , the marking will only appear on the outer carton or reel label. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. *Standard OTP marking consists of Microchip part number, year code, week code, and traceability code.  2013 Microchip Technology Inc. DS20005205A-page 15 25AA02UID Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging DS20005205A-page 16  2013 Microchip Technology Inc. 25AA02UID Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://www.microchip.com/packaging  2013 Microchip Technology Inc. DS20005205A-page 17 25AA02UID      !"#$% &  ! "# $% &"'"" ($)  % *++&&&!  !+$ DS20005205A-page 18  2013 Microchip Technology Inc. 25AA02UID '    ( ("()% &  ! "# $% &"'"" ($)  % *++&&&!  !+$ b 4 N E E1 PIN 1 ID BY LASER MARK 1 2 3 e e1 D A A2 c φ L A1 L1 >" !" ?!" @#!G  )(" ??6 6 @ @ @A E H (  ;< A#"%?%( 3 3;< A= J   K  %%($ $""  L K 3 31 % )) 3  K 3 A= N% 6  K 1  %%($N% 63 31 K 3L A= ?   K 13  ? ? 3 K H    ?3 1 K L    O K 1O ?% $""  L K H ?%N% G  K 3 & 3 !" "%63%  #%! %)"   #" " %)"   #" "" 7%3!! "%  !" %   683 ;