APT41F100J

APT41F100J 1000V, 42A, 0.20Ω Max, trr ≤400ns N-Channel FREDFET S S Power MOS 8™ is a high speed, high voltage N-channel switch-mode power MOSFET. This 'FREDFET' version has a drain-source (body) diode that has been optimized for high reliability in ZVS phase shifted bridge and other circuits through reduced trr, soft recovery, and high recovery dv/dt capability. Low gate charge, high gain, and a greatly reduced ratio of Crss/Ciss result in excellent noise immunity and low switching loss. The intrinsic gate resistance and capacitance of the poly-silicon gate structure help control di/dt during switching, resulting in low EMI and reliable paralleling, even when switching at very high frequency. D G SO 2 T- 27 "UL Recognized" file # E145592 IS OTO P ® D APT41F100J Single die FREDFET G S TYPICAL APPLICATIONS FEATURES • Fast switching with low EMI • ZVS phase shifted and other full bridge • Low trr for high reliability • Half bridge • Ultra low Crss for improved noise immunity • PFC and other boost converter • Low gate charge • Buck converter • Avalanche energy rated • Single and two switch forward • RoHS compliant • Flyback Absolute Maximum Ratings Symbol ID Parameter Unit Ratings Continuous Drain Current @ TC = 25°C 42 Continuous Drain Current @ TC = 100°C 27 A IDM Pulsed Drain Current VGS Gate-Source Voltage ±30 V EAS Single Pulse Avalanche Energy 2 4075 mJ IAR Avalanche Current, Repetitive or Non-Repetitive 33 A 1 260 Thermal and Mechanical Characteristics Min Characteristic Typ Max Unit W PD Total Power Dissipation @ TC = 25°C 960 RθJC Junction to Case Thermal Resistance 0.13 RθCS Case to Sink Thermal Resistance, Flat, Greased Surface TJ,TSTG Operating and Storage Junction Temperature Range VIsolation RMS Voltage (50-60hHz Sinusoidal Waveform from Terminals to Mounting Base for 1 Min.) WT Torque Package Weight Terminals and Mounting Screws. Microsemi Website - http://www.microsemi.com 0.15 -55 150 °C/W °C V 2500 1.03 oz 29.2 g 10 in·lbf 1.1 N·m 050-8128 Rev C 8-2011 Symbol Static Characteristics TJ = 25°C unless otherwise specified Symbol Parameter Test Conditions Min VBR(DSS) Drain-Source Breakdown Voltage VGS = 0V, ID = 250μA 1000 ∆VBR(DSS)/∆TJ Drain-Source On Resistance VGS(th) Gate-Source Threshold Voltage ∆VGS(th)/∆TJ VGS = 10V, ID = 33A 3 Zero Gate Voltage Drain Current IGSS Gate-Source Leakage Current Dynamic Characteristics VDS = 1000V Forward Transconductance Ciss Input Capacitance Crss Reverse Transfer Capacitance Coss Output Capacitance Typ Max 1.15 0.18 4 -10 0.20 5 TJ = 25°C VGS = 0V 250 1000 ±100 TJ = 125°C VGS = ±30V Unit V V/°C Ω V mV/°C μA nA TJ = 25°C unless otherwise specified Parameter gfs 2.5 VGS = VDS, ID = 5mA Threshold Voltage Temperature Coefficient IDSS Symbol Reference to 25°C, ID = 250μA Breakdown Voltage Temperature Coefficient RDS(on) APT41F100J Min Test Conditions VDS = 50V, ID = 33A 4 Effective Output Capacitance, Charge Related Co(er) 5 Effective Output Capacitance, Energy Related Max 75 18500 245 1555 VGS = 0V, VDS = 25V f = 1MHz Co(cr) Typ Unit S pF 635 VGS = 0V, VDS = 0V to 667V 325 Qg Total Gate Charge Qgs Gate-Source Charge Qgd Gate-Drain Charge td(on) Turn-On Delay Time Resistive Switching Current Rise Time VDD = 667V, ID = 33A tr td(off) tf Turn-Off Delay Time 570 100 270 55 55 235 55 VGS = 0 to 10V, ID = 33A, VDS = 500V RG = 2.2Ω 6 , VGG = 15V Current Fall Time nC ns Source-Drain Diode Characteristics Symbol IS ISM VSD Parameter Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) 1 Diode Forward Voltage trr Reverse Recovery Time Qrr Reverse Recovery Charge Irrm Reverse Recovery Current dv/dt Peak Recovery dv/dt Test Conditions Min Typ D MOSFET symbol showing the integral reverse p-n junction diode (body diode) A 260 S 1.0 400 800 TJ = 25°C TJ = 125°C TJ = 25°C VDD = 100V TJ = 125°C diSD/dt = 100A/μs TJ = 25°C Unit 42 G ISD = 33A, TJ = 25°C, VGS = 0V ISD = 33A 3 Max TJ = 125°C ISD ≤ 33A, di/dt ≤1000A/μs, VDD = 667V, TJ = 125°C 3.3 8.0 17.2 24.6 V ns μC A 25 V/ns 1 Repetitive Rating: Pulse width and case temperature limited by maximum junction temperature. 2 Starting at TJ = 25°C, L = 7.48mH, RG = 25Ω, IAS = 33A. 050-8128 Rev C 8-2011 3 Pulse test: Pulse Width < 380μs, duty cycle < 2%. 4 Co(cr) is defined as a fixed capacitance with the same stored charge as COSS with VDS = 67% of V(BR)DSS. 5 Co(er) is defined as a fixed capacitance with the same stored energy as COSS with VDS = 67% of V(BR)DSS. To calculate Co(er) for any value of VDS less than V(BR)DSS, use this equation: Co(er) = -5.37E-7/VDS^2 + 9.48E-8/VDS + 1.83E-10. 6 RG is external gate resistance, not including internal gate resistance or gate driver impedance. (MIC4452) Microsemi reserves the right to change, without notice, the specifications and information contained herein. APT41F100J 180 V GS 60 = 10V T = 125°C J GS 140 120 100 80 TJ = 25°C 60 40 40 30 5V 20 10 TJ = 125°C 20 TJ = 150°C 0 0 5 10 15 20 25 30 VDS(ON), DRAIN-TO-SOURCE VOLTAGE (V) 4.5V 0 Figure 2, Output Characteristics 250 NORMALIZED TO VDS> ID(ON) x RDS(ON) MAX. 250μSEC. PULSE TEST @