AT91SAM9260B-CU-999

SAM9260 Atmel | SMART ARM-based Embedded MPU DATASHEET Description The Atmel ® | SMART SAM9260 eMPU is based on the integration of an ARM926EJ-S™ processor with fast ROM and RAM memories and a wide range of peripherals. The SAM9260 embeds an Ethernet MAC, one USB Device Port, and a USB Host controller. It also integrates several standard peripherals, such as the USART, SPI, TWI, Timer Counters, Synchronous Serial Controller, ADC and MultiMedia Card Interface. The SAM9260 is architectured on a 6-layer matrix, allowing a maximum internal bandwidth of six 32-bit buses. It also features an External Bus Interface capable of interfacing with a wide range of memory devices. Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 Features 2  180 MHz ARM926EJ-S™ ARM® Thumb® Processor ̶ 8 Kbytes Data Cache, 8 Kbytes Instruction Cache, MMU  Memories ̶ 32-bit External Bus Interface supporting 4-bank SDRAM/LPSDR, Static Memories, CompactFlash, SLC NAND Flash with ECC ̶ Two 4-Kbyte internal SRAM, single-cycle access at system speed ̶ One 32-Kbyte internal ROM, embedding bootstrap routine  Peripherals ̶ ITU-R BT. 601/656 Image Sensor Interface (ISI) ̶ USB Device and USB Host with dedicated On-Chip Transceiver ̶ 10/100 Mbps Ethernet MAC Controller (EMAC) ̶ One High Speed Memory Card Host ̶ Two Master/Slave Serial Peripheral Interfaces (SPI) ̶ Two 3-channel 32-bit Timer/Counters (TC) ̶ One Synchronous Serial Controller (SSC) ̶ One Two-wire Interface (TWI) ̶ Four USARTs ̶ Two UARTs ̶ 4-channel 10-bit ADC  System ̶ 90 MHz six 32-bit layer AHB Bus Matrix ̶ 22 Peripheral DMA Channels ̶ Boot from NAND Flash, DataFlash or serial DataFlash ̶ Reset Controller (RSTC) with On-Chip Power-on Reset ̶ Selectable 32.768 kHz Low-Power and 3–20 MHz Main Oscillator ̶ Internal Low-Power 32 kHz RC Oscillator ̶ One PLL for the system and one PLL optimized for USB ̶ Two Programmable External Clock Signals ̶ Advanced Interrupt Controller (AIC) ̶ Debug Unit (DBGU) ̶ Periodic Interval Timer (PIT) ̶ Watchdog Timer (WDT) ̶ Real-time Timer (RTT)  I/O ̶ Three 32-bit Parallel Input/Output Controllers ̶ 96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os  Package ̶ 217-ball LFBGA – 15 x 15 x 1.4 mm, 0.8 mm pitch ̶ 208-pin PQFP – 28 x 28 x 4.1 mm, 0.5 mm pitch SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 1. SAM9260 Block Diagram Figure 1-1, “SAM9260 Block Diagram,” on page 4 shows all the features for the 217-LFBGA package. Some functions are not accessible in the 208-pin PQFP package and the unavailable pins are highlighted in “Multiplexing on PIO Controller A” on page 29, “Multiplexing on PIO Controller B” on page 30, “Multiplexing on PIO Controller C” on page 31. The USB Host Port B is not available in the 208-pin package. Table 1-1 defines all the multiplexed and not multiplexed pins not available in the 208-PQFP package. Table 1-1. Unavailable Signals in 208-lead PQFP Package PIO Peripheral A Peripheral B – HDPB – – HDMB – PA30 SCK2 RXD4 PA31 SCK0 TXD4 PB12 TXD5 ISI_D10 PB13 RXD5 ISI_D11 PC2 AD2 PCK1 PC3 AD3 SPI1_NPCS3 PC12 IRQ0 NCS7 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 3 I_ M IS CK I_ IS PC I_ K IS D0 I_ –I V IS SY SI_ I_ N D7 HS C YN C HD PA HD M A HD P HD B M B S BM IS L SE JT AG NT TDRS T TDI TMO TC S RTK CK System Controller TST JTAG Selection and Boundary Scan Transceiver Transceiver FIQ IRQ0–IRQ2 AIC DRXD DTXD PCK0–PCK1 DBGU In-Circuit Emulator PDC ICache 8 Kbytes Filter DCache 8 Kbytes MMU FIFO I FIFO DMA Bus Interface PLLA PLLRCA 10/100 Ethernet MAC ARM926EJ-S Processor PMC Image Sensor Interface USB OHCI DMA DMA D PLLB 3–20 MHz Main Osc. XIN XOUT WDT 6-layer Matrix PIT Backup Section RC Osc. 4 GPBR OSCSEL XIN32 XOUT32 32 kHz XTAL Osc. SHDN WKUP VDDBU POR VDDCORE POR RTT PIOA SHDWC Fast SRAM 4 Kbytes ROM 32 Kbytes PIOB Fast SRAM 4 Kbytes Peripheral Bridge PIOC EBI 22-channel Peripheral DMA CompactFlash NAND Flash RSTC NRST APB SDRAM Controller PDC MCI PDC PDC TWI USART0 USART1 USART2 USART3 USART4 USART5 SPI0 SPI1 PDC TC0 TC1 TC2 TC3 TC4 TC5 SSC PDC DPRAM 4-channel 10-bit ADC USB Device SPI0_, SPI1_ DD DDM P NP NPCS NPCS3 NPCS2 C 1 SP S0 M CK O TC M SI IS L O TI K0 O – TI A0–TCL O T K TC B0 IO 2 L –T A TI K3 IO 2 O – B TI A3 TC 2 O – LK B3 TI 5 –T OA IO 5 B5 TK TF TD RD RF R AD K 0– AD AD 3 TR IG AD VR EF VD DA NA G ND AN A T CT TWWD RTS0– CK C SC S0– TS R RX K0– TS3 S 3 TXD0– CK D0 RX 3 –T D X 5 DSD5 DCR0 D R0 DT I0 R0 –M C M DB A0 CC 3 –M DB C M DA CC 3 D M A CC K B0 CD M Static Memory Controller ECC Controller Transceiver CD SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 SLAVE ET ETXC K ECXE -E N R ERRS -E XC T ERXE -EC XE K R O ET X0 –E L R – M X0 ER RX D D – M C ET X3 V DI X3 F1 O 00 SAM9260 Block Diagram MASTER M 4 Figure 1-1. D0–D15 A0/NBS0 A1/NBS2/NWR2 A2–A15, A18–A20 A16/BA0 A17/BA1 NCS0 NCS1/SDCS NRD/CFOE NWR0/NWE/CFWE NWR1/NBS1/CFIOR NWR3/NBS3/CFIOW SDCK, SDCKE RAS, CAS SDWE, SDA10 NANDOE, NANDWE A21/NANDALE A22/NANDCLE D16–D31 NWAIT A23–A24 NCS4/CFCS0 NCS5/CFCS1 A25/CFRNW CFCE1–CFCE2 NCS2, NCS6, NCS7 NCS3/NANDCS 2. Signal Description Table 2-1. Signal Name Signal Description List Function Type Active Level Comments Power Supplies VDDIOM EBI I/O Lines Power Supply Power 1.65–1.95 V or 3.0–3.6 V VDDIOP0 Peripherals I/O Lines Power Supply Power 3.0–3.6 V VDDIOP1 Peripherals I/O Lines Power Supply Power 1.65–3.6 V VDDBU Backup I/O Lines Power Supply Power 1.65–1.95 V VDDANA Analog Power Supply Power 3.0–3.6 V VDDPLL PLL Power Supply Power 1.65–1.95 V VDDCORE Core Chip Power Supply Power 1.65–1.95 V GND Ground Ground GNDPLL PLL and Oscillator Ground Ground GNDANA Analog Ground Ground GNDBU Backup Ground Ground Clocks, Oscillators and PLLs XIN Main Oscillator Input Input XOUT Main Oscillator Output XIN32 Slow Clock Oscillator Input XOUT32 Slow Clock Oscillator Output OSCSEL Slow Clock Oscillator Selection Input PLLRCA PLL A Filter Input PCK0–PCK1 Programmable Clock Output Output Input Output Accepts between 0V and VDDBU Output Shutdown, Wakeup Logic SHDN Shutdown Control WKUP Wake-up Input Output Driven at 0V only. Do not tie over VDDBU. Input Accepts between 0V and VDDBU ICE and JTAG NTRST Test Reset Signal Input Low Pull-up resistor TCK Test Clock Input No pull-up resistor TDI Test Data In Input No pull-up resistor TDO Test Data Out TMS Test Mode Select Input No pull-up resistor JTAGSEL JTAG Selection Input Pull-down resistor. Accepts between 0V and VDDBU. RTCK Return Test Clock Output Output SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 5 Table 2-1. Signal Description List (Continued) Signal Name Function Type Active Level I/O Low Comments Reset/Test NRST Microcontroller Reset TST Test Mode Select Input BMS Boot Mode Select Input Pull-up resistor Pull-down resistor. Accepts between 0V and VDDBU. No pull-up resistor BMS = 0 when tied to GND BMS = 1 when tied to VDDIOP0 Debug Unit - DBGU DRXD Debug Receive Data Input DTXD Debug Transmit Data Output Advanced Interrupt Controller - AIC IRQ0–IRQ2 External Interrupt Inputs Input FIQ Fast Interrupt Input Input PIO Controller - PIOA / PIOB / PIOC PA0–PA31 Parallel IO Controller A I/O Pulled-up input at reset PB0–PB31 Parallel IO Controller B I/O Pulled-up input at reset PC0–PC31 Parallel IO Controller C I/O Pulled-up input at reset External Bus Interface - EBI D0–D31 Data Bus I/O A0–A25 Address Bus NWAIT External Wait Signal Pulled-up input at reset Output Input 0 at reset Low Static Memory Controller - SMC NCS0–NCS7 Chip Select Lines Output Low NWR0–NWR3 Write Signal Output Low NRD Read Signal Output Low NWE Write Enable Output Low NBS0–NBS3 Byte Mask Signal Output Low CompactFlash Support CFCE1–CFCE2 CompactFlash Chip Enable Output Low CFOE CompactFlash Output Enable Output Low CFWE CompactFlash Write Enable Output Low CFIOR CompactFlash IO Read Output Low CFIOW CompactFlash IO Write Output Low CFRNW CompactFlash Read Not Write Output CFCS0–CFCS1 CompactFlash Chip Select Lines Output 6 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 Low Table 2-1. Signal Description List (Continued) Signal Name Function Type Active Level Comments NAND Flash Support NANDCS NAND Flash Chip Select Output Low NANDOE NAND Flash Output Enable Output Low NANDWE NAND Flash Write Enable Output Low NANDALE NAND Flash Address Latch Enable Output Low NANDCLE NAND Flash Command Latch Enable Output Low SDRAM Controller - SDRAMC SDCK SDRAM Clock Output SDCKE SDRAM Clock Enable Output High SDCS SDRAM Controller Chip Select Output Low BA0–BA1 Bank Select Output SDWE SDRAM Write Enable Output Low RAS–CAS Row and Column Signal Output Low SDA10 SDRAM Address 10 Line Output MultiMedia Card Interface - MCI MCCK MultiMedia Card Clock Output MCCDA MultiMedia Card Slot A Command I/O MCDA0–MCDA3 MultiMedia Card Slot A Data I/O MCCDB MultiMedia Card Slot B Command I/O MCDB0–MCDB3 MultiMedia Card Slot B Data I/O Universal Synchronous Asynchronous Receiver Transmitter - USARTx SCKx USARTx Serial Clock I/O TXDx USARTx Transmit Data I/O RXDx USARTx Receive Data Input RTSx USARTx Request To Send CTSx USARTx Clear To Send DTR0 USART0 Data Terminal Ready DSR0 USART0 Data Set Ready Input DCD0 USART0 Data Carrier Detect Input RI0 USART0 Ring Indicator Input Output Input Output Synchronous Serial Controller - SSC TD SSC Transmit Data Output RD SSC Receive Data Input TK SSC Transmit Clock I/O RK SSC Receive Clock I/O TF SSC Transmit Frame Sync I/O RF SSC Receive Frame Sync I/O SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 7 Table 2-1. Signal Description List (Continued) Signal Name Function Type Active Level Comments Timer/Counter - TCx TCLKx TC Channel x External Clock Input Input TIOAx TC Channel x I/O Line A I/O TIOBx TC Channel x I/O Line B I/O Serial Peripheral Interface - SPIx_ SPIx_MISO Master In Slave Out I/O SPIx_MOSI Master Out Slave In I/O SPIx_SPCK SPI Serial Clock I/O SPIx_NPCS0 SPI Peripheral Chip Select 0 I/O Low SPIx_NPCS1–SPIx_NPCS3 SPI Peripheral Chip Select Output Low Two-wire Interface - TWI TWD Two-wire Serial Data I/O TWCK Two-wire Serial Clock I/O USB Host Port - UHP HDPA USB Host Port A Data + Analog HDMA USB Host Port A Data - Analog HDPB USB Host Port B Data + Analog HDMB USB Host Port B Data + Analog USB Device Port - UDP DDM USB Device Port Data - Analog DDP USB Device Port Data + Analog Ethernet 10/100 - EMAC ETXCK Transmit Clock or Reference Clock Input MII only, REFCK in RMII ERXCK Receive Clock Input MII only ETXEN Transmit Enable Output ETX0–ETX3 Transmit Data Output ETX0–ETX1 only in RMII ETXER Transmit Coding Error Output MII only ERXDV Receive Data Valid Input RXDV in MII, CRSDV in RMII ERX0–ERX3 Receive Data Input ERX0–ERX1 only in RMII ERXER Receive Error Input ECRS Carrier Sense and Data Valid Input MII only ECOL Collision Detect Input MII only EMDC Management Data Clock EMDIO Management Data Input/Output EF100 Force 100 Mbit/s 8 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 Output I/O Output High Table 2-1. Signal Description List (Continued) Signal Name Function Type Active Level Comments Image Sensor Interface - ISI ISI_D0–ISI_D11 Image Sensor Data Input ISI_MCK Image Sensor Reference Clock ISI_HSYNC Image Sensor Horizontal Synchro Input ISI_VSYNC Image Sensor Vertical Synchro Input ISI_PCK Image Sensor Data clock Input Output Analog-to-Digital Converter - ADC AD0–AD3 Analog Inputs Analog ADVREF Analog Positive Reference Analog ADTRG ADC Trigger Digital pulled-up inputs at reset Input SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 9 3. Package and Pinout The SAM9260 is available in two Green-compliant packages:  208-pin PQFP (0.5 mm pitch)  217-ball LFBGA (0.8 mm ball pitch) A detailed mechanical description and the orientation of the packages are given in Section 40. “SAM9260 Mechanical Characteristics”. 3.1 208-pin PQFP Pinout Table 3-1. Pinout for 208-pin PQFP Package Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name 1 PA24 53 GND 105 RAS 157 ADVREF 2 PA25 54 DDM 106 D0 158 PC0 3 PA26 55 DDP 107 D1 159 PC1 4 PA27 56 PC13 108 D2 160 VDDANA 5 VDDIOP0 57 PC11 109 D3 161 PB10 6 GND 58 PC10 110 D4 162 PB11 7 PA28 59 PC14 111 D5 163 PB20 8 PA29 60 PC9 112 D6 164 PB21 9 PB0 61 PC8 113 GND 165 PB22 10 PB1 62 PC4 114 VDDIOM 166 PB23 11 PB2 63 PC6 115 SDCK 167 PB24 12 PB3 64 PC7 116 SDWE 168 PB25 13 VDDIOP0 65 VDDIOM 117 SDCKE 169 VDDIOP1 14 GND 66 GND 118 D7 170 GND 15 PB4 67 PC5 119 D8 171 PB26 16 PB5 68 NCS0 120 D9 172 PB27 17 PB6 69 CFOE/NRD 121 D10 173 GND 18 PB7 70 CFWE/NWE/NWR0 122 D11 174 VDDCORE 19 PB8 71 NANDOE 123 D12 175 PB28 20 PB9 72 NANDWE 124 D13 176 PB29 21 PB14 73 A22 125 D14 177 PB30 22 PB15 74 A21 126 D15 178 PB31 23 PB16 75 A20 127 PC15 179 PA0 24 VDDIOP0 76 A19 128 PC16 180 PA1 25 GND 77 VDDCORE 129 PC17 181 PA2 26 PB17 78 GND 130 PC18 182 PA3 27 PB18 79 A18 131 PC19 183 PA4 28 PB19 80 BA1/A17 132 VDDIOM 184 PA5 29 TDO 81 BA0/A16 133 GND 185 PA6 10 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 Table 3-1. Pinout for 208-pin PQFP Package (Continued) Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name 30 TDI 82 A15 134 PC20 186 PA7 31 TMS 83 A14 135 PC21 187 VDDIOP0 32 VDDIOP0 84 A13 136 PC22 188 GND 33 GND 85 A12 137 PC23 189 PA8 34 TCK 86 A11 138 PC24 190 PA9 35 NTRST 87 A10 139 PC25 191 PA10 36 NRST 88 A9 140 PC26 192 PA11 37 RTCK 89 A8 141 PC27 193 PA12 38 VDDCORE 90 VDDIOM 142 PC28 194 PA13 39 GND 91 GND 143 PC29 195 PA14 40 BMS 92 A7 144 PC30 196 PA15 41 OSCSEL 93 A6 145 PC31 197 PA16 42 TST 94 A5 146 GND 198 PA17 43 JTAGSEL 95 A4 147 VDDCORE 199 VDDIOP0 44 GNDBU 96 A3 148 VDDPLL 200 GND 45 XOUT32 97 A2 149 XIN 201 PA18 46 XIN32 98 NWR2/NBS2/A1 150 XOUT 202 PA19 47 VDDBU 99 NBS0/A0 151 GNDPLL 203 VDDCORE 48 WKUP 100 SDA10 152 NC 204 GND 49 SHDN 101 CFIOW/NBS3/NWR3 153 GNDPLL 205 PA20 50 HDMA 102 CFIOR/NBS1/NWR1 154 PLLRCA 206 PA21 51 HDPA 103 SDCS/NCS1 155 VDDPLL 207 PA22 52 VDDIOP0 104 CAS 156 GNDANA 208 PA23 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 11 3.2 217-ball LFBGA Package A detailed mechanical description and the orientation of the 217-ball LFBGA package is given in Section 40. “SAM9260 Mechanical Characteristics”. 3.3 217-ball LFBGA Pinout Table 3-2. Pinout for 217-ball LFBGA Package Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name A1 CFIOW/NBS3/NWR3 D5 A5 J14 TDO P17 PB5 A2 NBS0/A0 D6 GND J15 PB19 R1 NC A3 NWR2/NBS2/A1 D7 A10 J16 TDI R2 GNDANA A4 A6 D8 GND J17 PB16 R3 PC29 A5 A8 D9 VDDCORE K1 PC24 R4 VDDANA A6 A11 D10 GND K2 PC20 R5 PB12 A7 A13 D11 VDDIOM K3 D15 R6 PB23 A8 BA0/A16 D12 GND K4 PC21 R7 GND A9 A18 D13 DDM K8 GND R8 PB26 A10 A21 D14 HDPB K9 GND R9 PB28 A11 A22 D15 NC K10 GND R10 PA0 A12 CFWE/NWE/NWR0 D16 VDDBU K14 PB4 R11 PA4 A13 CFOE/NRD D17 XIN32 K15 PB17 R12 PA5 A14 NCS0 E1 D10 K16 GND R13 PA10 A15 PC5 E2 D5 K17 PB15 R14 PA21 A16 PC6 E3 D3 L1 GND R15 PA23 A17 PC4 E4 D4 L2 PC26 R16 PA24 B1 SDCK E14 HDPA L3 PC25 R17 PA29 B2 CFIOR/NBS1/NWR1 E15 HDMA L4 VDDIOP0 T1 PLLRCA B3 SDCS/NCS1 E16 GNDBU L14 PA28 T2 GNDPLL B4 SDA10 E17 XOUT32 L15 PB9 T3 PC0 B5 A3 F1 D13 L16 PB8 T4 PC1 B6 A7 F2 SDWE L17 PB14 T5 PB10 B7 A12 F3 D6 M1 VDDCORE T6 PB22 B8 A15 F4 GND M2 PC31 T7 GND B9 A20 F14 OSCSEL M3 GND T8 PB29 B10 NANDWE F15 BMS M4 PC22 T9 PA2 B11 PC7 F16 JTAGSEL M14 PB1 T10 PA6 B12 PC10 F17 TST M15 PB2 T11 PA8 B13 PC13 G1 PC15 M16 PB3 T12 PA11 B14 PC11 G2 D7 M17 PB7 T13 VDDCORE B15 PC14 G3 SDCKE N1 XIN T14 PA20 12 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 Table 3-2. Pinout for 217-ball LFBGA Package (Continued) Pin Signal Name Pin Signal Name Pin Signal Name Pin Signal Name B16 PC8 G4 VDDIOM N2 VDDPLL T15 GND B17 WKUP G14 GND N3 PC23 T16 PA22 C1 D8 G15 NRST N4 PC27 T17 PA27 C2 D1 G16 RTCK N14 PA31 U1 GNDPLL C3 CAS G17 TMS N15 PA30 U2 ADVREF C4 A2 H1 PC18 N16 PB0 U3 PC2 C5 A4 H2 D14 N17 PB6 U4 PC3 C6 A9 H3 D12 P1 XOUT U5 PB20 C7 A14 H4 D11 P2 VDDPLL U6 PB21 C8 BA1/A17 H8 GND P3 PC30 U7 PB25 C9 A19 H9 GND P4 PC28 U8 PB27 C10 NANDOE H10 GND P5 PB11 U9 PA12 C11 PC9 H14 VDDCORE P6 PB13 U10 PA13 C12 PC12 H15 TCK P7 PB24 U11 PA14 C13 DDP H16 NTRST P8 VDDIOP1 U12 PA15 C14 HDMB H17 PB18 P9 PB30 U13 PA19 C15 NC J1 PC19 P10 PB31 U14 PA17 C16 VDDIOP0 J2 PC17 P11 PA1 U15 PA16 C17 SHDN J3 VDDIOM P12 PA3 U16 PA18 D1 D9 J4 PC16 P13 PA7 U17 VDDIOP0 D2 D2 J8 GND P14 PA9 D3 RAS J9 GND P15 PA26 D4 D0 J10 GND P16 PA25 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 13 4. Power Considerations 4.1 Power Supplies The SAM9260 devices have several types of power supply pins. Some supply pins share common ground (GND) pins whereas others have separate grounds. See Table 4-1. Table 4-1. Pin(s) SAM9260 Power Supply Pins Item(s) powered Range Typical 1.65–1.95 V 1.8V 1.65–1.95 V(1) 1.8V Ground Core, including the processor VDDCORE Embedded memories Peripherals VDDIOM VDDIOP0 VDDIOP1 VDDBU VDDPLL VDDANA Note: 1. External Bus Interface I/O lines Peripheral I/O lines USB transceivers Peripherals I/O lines involving the Image Sensor Interface Slow Clock oscillator Part of the System Controller Main oscillator PLL cells Analog-to-Digital Converter 3.0–3.6 V (1) 3.3V GND 3.0–3.6 V 3.3V 1.65–3.6 V 1.8V 2.5V 3.3V 1.65–1.95 V 1.8V GNDBU 1.65–1.95 V 1.8V GNDPLL 3.0–3.6 V 3.3V GNDANA Desired voltage range selectable by software The power supplies VDDIOM, VDDIOP0 and VDDIOP1 are identified in the pinout table and the multiplexing tables. These supplies enable the user to power the device differently for interfacing with memories and for interfacing with peripherals. 4.2 Power Sequence Requirements The SAM9260 board design must comply with the guidelines described in Section 4.2.1 “Power-up Sequence” and Section 4.2.2 “Power-down Sequence” to guarantee reliable operation of the device. Any deviation from these sequences may lead to preventing the device from booting. 14 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 4.2.1 Power-up Sequence Figure 4-1. VDDCORE and VVDDIO Constraints at Startup VDD (V) VDDIO VDDIOtyp VDDIO > Voh Voh VDDCORE VDDCOREtyp Vih VT+ tRST T1 t T2 Core Supply POR output SLCK VDDCORE and VDDBU are controlled by internal POR (Power On Reset) to guarantee that these power sources reach their target values prior to the release of POR. 4.2.1.1 VDDBU is Continuously Powered (used with a battery)  VDDIOM, VDDIOP0 and VDDIOP1 must NOT be powered until VDDCORE has reached a level superior to VT+.  VDDIOP0 must be ≥ VIH (refer to Table 39-2 “DC Characteristics” for more details) within (tRST + T1) after VDDCORE reached VT+.  VDDIOM must reach VOH (refer to Table 39-2 “DC Characteristics” for more details) within (tRST + T1 + T2) after VDDCORE has reached VT+. ̶ tRST is a POR characteristic T1 = 3 × tSLCK ̶ T2 = 16 × tSLCK ̶ The tSLCK min (22 µs) is obtained for the maximum frequency of the internal RC oscillator (44 kHz). ̶ 4.2.1.2 tRST = 100 µs ̶ T1 = 66 µs ̶ T2 = 352 µs VDDBU is not Continuously Powered (no backup features used) If VDDBU is not used with a battery, the power sequence can be less constrained. The user can power VDDCORE, then VDDIOM, VDDIOP0 and VDDIOP1, with VDDBU following last in the sequence, thus ensuring that BMS is correctly sampled. 4.2.2 Power-down Sequence Switch-off the VDDIOM, VDDIOP0 and VDDIOP1 power supply prior to or at the same time as VDDCORE. No power-up or power-down restrictions apply to VDDBU, VDDPLL and VDDANA. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 15 4.3 Programmable I/O Lines Power Supplies The power supplies pins VDDIOM accept two voltage ranges. This allows the device to reach its maximum speed either out of 1.8V or 3.3V external memories. The voltage ranges are determined by programming registers in the Chip Configuration registers located in Section 17.6 “Bus Matrix User Interface”. At reset, the selected voltage defaults to 3.3V nominal, and power supply pins can accept either 1.8V or 3.3V. The device cannot reach its maximum speed if the voltage supplied to the pins is 1.8V only. The user must program the EBI voltage range before getting the device out of its Slow Clock Mode. 16 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 5. I/O Line Considerations 5.1 JTAG Port Pins TMS, TDI and TCK are Schmitt trigger inputs and have no pull-up resistors. TDO and RTCK are outputs, driven at up to VDDIOP0, and have no pull-up resistors. The JTAGSEL pin is used to select the JTAG boundary scan when asserted at a high level (tied to VDDBU). It integrates a permanent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal operations. The NTRST signal is described in Section 5.3. All the JTAG signals are supplied with VDDIOP0. 5.2 Test Pin The TST pin is used for manufacturing test purposes when asserted high. It integrates a permanent pull-down resistor of about 15 kΩ to GNDBU, so that it can be left unconnected for normal operations. Driving this line at a high level leads to unpredictable results. This pin is supplied with VDDBU. 5.3 Reset Pins NRST is a bidirectional with an open-drain output integrating a non-programmable pull-up resistor. It can be driven with voltage at up to VDDIOP0. NTRST is an input which allows reset of the JTAG Test Access port. It has no action on the processor. As the product integrates power-on reset cells, which manages the processor and the JTAG reset, the NRST and NTRST pins can be left unconnected. The NRST and NTRST pins both integrate a permanent pull-up resistor to VDDIOP0. Its value can be found in Table 39-2 “DC Characteristics”. The NRST signal is inserted in the Boundary Scan. 5.4 PIO Controllers All the I/O lines managed by the PIO Controllers integrate a programmable pull-up resistor. Refer to Section 39.2 “DC Characteristics” for more information. Programming of this pull-up resistor is performed independently for each I/O line through the PIO Controllers. After reset, all the I/O lines default as inputs with pull-up resistors enabled, except those which are multiplexed with the External Bus Interface signals and that must be enabled as Peripheral at reset. This is explicitly indicated in the column “Reset State” of the PIO Controller multiplexing tables. 5.5 I/O Line Drive Levels The PIO lines are high-drive current capable. Each of these I/O lines can drive up to 16 mA permanently except PC4 to PC31 that are VDDIOM powered. 5.6 Shutdown Logic Pins The SHDN pin is a tri-state output pin, which is driven by the Shutdown Controller. There is no internal pull-up. An external pull-up tied to VDDBU is needed and its value must be higher than 1 MΩ. The resistor value is calculated according to the regulator enable implementation and the SHDN level. The pin WKUP is an input-only. It can accept voltages only between 0V and VDDBU. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 17 5.7 Slow Clock Selection The SAM9260 slow clock can be generated either by an external 32.768 kHz crystal or the on-chip RC oscillator. Table 5-1 defines the states for OSCSEL signal. Table 5-1. Slow Clock Selection OSCSEL Slow Clock Startup Time 0 Internal RC 240 µs 1 External 32.768 kHz 1200 ms The startup counter delay for the slow clock oscillator depends on the OSCSEL signal. The 32.768 kHz startup delay is 1200 ms whereas it is 240 µs for the internal RC oscillator (refer to Table 5-1). The pin OSCSEL must be tied either to GND or VDDBU for correct operation of the device. 18 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 6. Memories Figure 6-1. SAM9260 Memory Mapping Internal Memory Mapping Address Memory Space 0x0000 0000 Notes: 1. Can be ROM, EBI_NCS0 or SRAM depending on BMS and REMAP 0x0000 0000 Boot Memory (1) Internal Memories 256 Mbytes Reserved 256 Mbytes 0x20 0000 SRAM0 Reserved EBI Chip Select 1/ SDRAMC 0x30 0000 256 Mbytes SRAM1 Reserved 256 Mbytes 0x50 4000 EBI Chip Select 3/ NANDFlash 256 Mbytes 0x0FFF FFFF EBI Chip Select 4/ Compact Flash Slot 0 256 Mbytes EBI Chip Select 5/ Compact Flash Slot 1 256 Mbytes 0x3FFF FFFF 0x4000 0000 0x6FFF FFFF 0x7000 0000 4 Kbytes 0x30 1000 0x50 0000 EBI Chip Select 2 0x5FFF FFFF 0x6000 0000 4 Kbytes 0x20 1000 0x1FFF FFFF 0x2000 0000 0x4FFF FFFF 0x5000 0000 32 Kbytes 0x10 8000 EBI Chip Select 0 0x2FFF FFFF 0x3000 0000 0x10 0000 ROM 0x0FFF FFFF 0x1000 0000 UHP 16 Kbytes Reserved Peripheral Mapping 0xF000 0000 System Controller Mapping Reserved 0xFFFA 0000 EBI Chip Select 6 256 Mbytes 0x7FFF FFFF 0x8000 0000 16 Kbytes 0xFFFF C000 UDP 16 Kbytes 0xFFFF E800 MCI 16 Kbytes 0xFFFF EA00 TWI 16 Kbytes TCO, TC1, TC2 Reserved 0xFFFA 4000 0xFFFA 8000 EBI Chip Select 7 256 Mbytes 0xFFFA C000 0x8FFF FFFF 0x9000 0000 USART0 16 Kbytes 0xFFFB 4000 USART1 16 Kbytes USART2 16 Kbytes SSC 16 Kbytes ISI 16 Kbytes EMAC 16 Kbytes SPI0 16 Kbytes 0xFFFC C000 512 bytes AIC 512 bytes DBGU 512 bytes PIOA 512 bytes PIOB 512 bytes SPI1 16 Kbytes USART3 16 Kbytes PIOC 512 bytes 0xFFFF F800 0xFFFD 0000 0xFFFF FA00 Reserved 0xFFFD 4000 USART4 0xFFFD 8000 USART5 16 Kbytes 0xFFFF FC00 16 Kbytes 0xFFFF FD00 0xFFFF FD10 0xFFFD C000 TC3, TC4, TC5 16 Kbytes 0xFFFF FD20 0xFFFE 0000 ADC 0xFFFF FD30 16 Kbytes 0xFFFF FD40 0xFFFE 4000 0xFFFF FD50 0xFFFF FD60 Reserved 0xFFFF C000 System Controller 0xFFFF FFFF MATRIX 0xFFFF F600 0xFFFC 8000 0xFFFF FFFF 512 bytes 0xFFFF F400 0xFFFC 4000 256 Mbytes SMC 0xFFFF F200 0xFFFC 0000 Internal Peripherals 512 bytes 0xFFFF F000 0xFFFB C000 0xEFFF FFFF 0xF000 0000 SDRAMC 0xFFFF EE00 0xFFFB 8000 1518 Mbytes 512 bytes 0xFFFF EC00 0xFFFB 0000 Undefined (Abort) ECC 16 Kbytes PMC 256 bytes RSTC 16 bytes SHDWC 16 bytes RTT 16 bytes PIT 16 bytes WDT 16 bytes GPBR 16 bytes Reserved 0xFFFF FFFF SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 19 A first level of address decoding is performed by the Bus Matrix, i.e., the implementation of the Advanced High Performance Bus (AHB) for its Master and Slave interfaces with additional features. Decoding breaks up the 4 Gbytes of address space into 16 banks of 256 Mbytes. The banks 1 to 7 are directed to the EBI that associates these banks to the external chip selects EBI_NCS0 to EBI_NCS7. Bank 0 is reserved for the addressing of the internal memories, and a second level of decoding provides 1 Mbyte of internal memory area. Bank 15 is reserved for the peripherals and provides access to the Advanced Peripheral Bus (APB). Other areas are unused and performing an access within them provides an abort to the master requesting such an access. Each Master has its own bus and its own decoder, thus allowing a different memory mapping per Master. However, in order to simplify the mappings, all the masters have a similar address decoding. Regarding Master 0 and Master 1 (ARM926™ Instruction and Data), three different Slaves are assigned to the memory space decoded at address 0x0: one for internal boot, one for external boot, one after remap. Refer to Table 6-1 “Internal Memory Mapping” for details. A complete memory map is presented in Figure 6-1 on page 19. 6.1 Embedded Memories  32 KB ROM ̶  Single Cycle Access at full matrix speed Two 4 KB Fast SRAM ̶ 6.1.1 Single Cycle Access at full matrix speed Boot Strategies Table 6-1 summarizes the Internal Memory Mapping for each Master, depending on the Remap status and the BMS state at reset. Table 6-1. Internal Memory Mapping REMAP = 0 Address BMS = 1 BMS = 0 REMAP = 1 0x0000 0000 ROM EBI_NCS0 SRAM0 4K The system always boots at address 0x0. To ensure a maximum number of possibilities for boot, the memory layout can be configured with two parameters. After reset, the ROM is mapped at both addresses 0x0000_0000 and 0x0010_0000. REMAP allows the user to lay out the first internal SRAM bank to 0x0 to ease development. This is done by software once the system has booted. Refer to Section 17. “SAM9260 Bus Matrix” for more details. When REMAP = 0, BMS allows the user to lay out to 0x0, at his convenience, the ROM or an external memory. This is done via hardware at reset. Note: Memory blocks not affected by these parameters can always be seen at their specified base addresses. See the complete memory map presented in Figure 6-1 on page 19. The SAM9260 matrix manages a boot memory that depends on the level on the BMS pin at reset. The internal memory area mapped between address 0x0 and 0x000F FFFF is reserved for this purpose. If BMS is detected at 1, the boot memory is the embedded ROM. If BMS is detected at 0, the boot memory is the memory connected on the Chip Select 0 of the External Bus Interface. 20 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 6.1.1.1 BMS = 1, Boot on Embedded ROM The system boots using the Boot Program.  Boot on slow clock (on-chip RC or 32.768 kHz)  Auto baudrate detection  Downloads and runs an application from external storage media into internal SRAM  Downloaded code size depends on embedded SRAM size  Automatic detection of valid application  Bootloader on a non-volatile memory  ̶ SPI DataFlash connected on NPCS0 and NPCS1 of the SPI0 ̶ 8-bit and/or 16-bit NAND Flash SAM-BA® Monitor in case no valid program is detected in external NVM, supporting ̶ Serial communication on a DBGU ̶ USB Device Port 6.1.1.2 BMS = 0, Boot on External Memory  Boot on slow clock (on-chip RC or 32.768 kHz)  Boot with the default configuration for the Static Memory Controller, byte select mode, 16-bit data bus, Read/Write controlled by Chip Select, allows boot on 16-bit non-volatile memory. The customer-programmed software must perform a complete configuration. To speed up the boot sequence when booting at 32 kHz EBI CS0 (BMS = 0), the user must take the following steps: 6.2 1. Program the PMC (main oscillator enable or bypass mode). 2. Program and start the PLL. 3. Reprogram the SMC setup, cycle, hold, mode timings registers for CS0 to adapt them to the new clock. 4. Switch the main clock to the new value. External Memories The external memories are accessed through the External Bus Interface. Each Chip Select line has a 256-Mbyte memory area assigned. Refer to Figure 6-1, “SAM9260 Memory Mapping,” on page 19. 6.2.1 External Bus Interface  Integrates three External Memory Controllers ̶ Static Memory Controller ̶ SDRAM Controller ̶ ECC Controller  Additional logic for NAND Flash  Full 32-bit External Data Bus  Up to 26-bit Address Bus (up to 64 Mbytes linear)  Up to 8 chip selects, Configurable Assignment: ̶ ̶ Static Memory Controller on NCS0 ̶ SDRAM Controller or Static Memory Controller on NCS1 ̶ Static Memory Controller on NCS2 ̶ Static Memory Controller on NCS3, Optional NAND Flash support ̶ Static Memory Controller on NCS4–NCS5, Optional CompactFlash support Static Memory Controller on NCS6–NCS7 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 21 6.2.2 Static Memory Controller  8-, 16- or 32-bit Data Bus  Multiple Access Modes supported    6.2.3 ̶ Byte Write or Byte Select Lines ̶ Asynchronous read in Page Mode supported (4- up to 32-byte page size) Multiple device adaptability ̶ Compliant with LCD Module ̶ Control signals programmable setup, pulse and hold time for each Memory Bank Multiple Wait State Management ̶ Programmable Wait State Generation ̶ External Wait Request ̶ Programmable Data Float Time Slow Clock mode supported SDRAM Controller  Supported devices ̶    Standard and Low-power SDRAM (Mobile SDRAM) Numerous configurations supported ̶ 2K, 4K, 8K Row Address Memory Parts ̶ SDRAM with two or four Internal Banks ̶ SDRAM with 16- or 32-bit Datapath Programming facilities ̶ Word, half-word, byte access ̶ Automatic page break when Memory Boundary has been reached ̶ Multibank Ping-pong Access ̶ Timing parameters specified by software ̶ Automatic refresh operation, refresh rate is programmable Energy-saving capabilities ̶  Self-refresh, power down and deep power down modes supported Error detection ̶ 6.2.4  SDRAM Power-up Initialization by software  CAS Latency of 1, 2 and 3 supported  Auto Precharge Command not used Error Correction Code Controller  Tracking the accesses to a NAND Flash device by trigging on the corresponding chip select  Single bit error correction and 2-bit Random detection  Automatic Hamming Code Calculation while writing  Automatic Hamming Code Calculation while reading ̶ 22 Refresh Error Interrupt ECC value available in a register ̶ Error Report, including error flag, correctable error flag and word address being detected erroneous ̶ Support 8- or 16-bit NAND Flash devices with 512-, 1024-, 2048- or 4096-bytes pages SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 7. System Controller The System Controller is a set of peripherals that allows handling of key elements of the system, such as power, resets, clocks, time, interrupts, watchdog, etc. The System Controller User Interface also embeds the registers that configure the Matrix and a set of registers for the chip configuration. The chip configuration registers configure EBI chip select assignment and voltage range for external memories The System Controller’s peripherals are all mapped within the highest 16 Kbytes of address space, between addresses 0xFFFF E800 and 0xFFFF FFFF. However, all the registers of System Controller are mapped on the top of the address space. All the registers of the System Controller can be addressed from a single pointer by using the standard ARM instruction set, as the Load/Store instruction has an indexing mode of ±4 Kbytes. Figure 7-1 on page 24 shows the System Controller block diagram. Figure 6-1 on page 19 shows the mapping of the User Interfaces of the System Controller peripherals. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 23 7.1 System Controller Block Diagram Figure 7-1. SAM9260 System Controller Block Diagram System Controller VDDCORE Powered irq0–irq2 fiq periph_irq[2..24] nirq nfiq Advanced Interrupt Controller pit_irq rtt_irq wdt_irq dbgu_irq pmc_irq rstc_irq int MCK periph_nreset dbgu_irq Debug Unit dbgu_txd dbgu_rxd Periodic Interval Timer pit_irq Watchdog Timer wdt_irq NRST periph_nreset Reset Controller periph_nreset proc_nreset backup_nreset VDDBU VDDBU POR VDDBU Powered Bus Matrix UHPCK periph_clk[20] periph_nreset Real-time Timer rtt_irq rtt_alarm UDPCK SLCK SHDN periph_clk[10] WKUP RC Oscillator USB Host Port periph_irq[20] SLCK SLCK backup_nreset backup_nreset Shutdown Controller periph_nreset USB Device Port periph_irq[10] rtt0_alarm Slow Clock Oscillator 4 General-purpose Backup Registers XOUT32 SLCK PLLRCA Boundary Scan TAP Controller rstc_irq por_ntrst jtag_nreset VDDCORE POR XIN PCK MCK wdt_fault WDRPROC XOUT proc_nreset jtag_nreset SLCK debug idle proc_nreset XIN32 ARM926EJ-S debug MCK debug periph_nreset OSCSEL ntrst por_ntrst periph_clk[2..27] pck[0–1] int Main Oscillator PLLA PLLB PCK MAINCK PLLACK Power Management Controller UDPCK UHPCK MCK PLLBCK pmc_irq periph_nreset periph_clk[6..24] idle periph_nreset periph_nreset periph_clk[2..4] dbgu_rxd PA0–PA31 PB0–PB31 PC0–PC31 24 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 PIO Controllers periph_irq[2..4] irq0–irq2 fiq dbgu_txd Embedded Peripherals periph_irq[6..24] in out enable 7.2 Power Management Controller   Provides: ̶ Processor Clock PCK ̶ Master Clock MCK, in particular to the Matrix and the memory interfaces ̶ USB Device Clock UDPCK ̶ independent peripheral clocks, typically at the frequency of MCK ̶ 2 programmable clock outputs: PCK0, PCK1 Five flexible operating modes: ̶ Normal Mode, processor and peripherals running at a programmable frequency ̶ Idle Mode, processor stopped waiting for an interrupt ̶ Slow Clock Mode, processor and peripherals running at low frequency ̶ Standby Mode, mix of Idle and Backup Mode, peripheral running at low frequency, processor stopped waiting for an interrupt ̶ Backup Mode, Main Power Supplies off, VDDBU powered by a battery Figure 7-2. SAM9260 Power Management Controller Block Diagram Processor Clock Controller int Master Clock Controller SLCK MAINCK PLLACK PLLBCK Prescaler /1,/2,/4,...,/64 PCK Idle Mode Divider /1,/2,/4 MCK Peripherals Clock Controller periph_clk[..] ON/OFF Programmable Clock Controller SLCK MAINCK PLLACK PLLBCK ON/OFF Prescaler /1,/2,/4,...,/64 pck[..] USB Clock Controller ON/OFF PLLBCK 7.3 UDPCK UHPCK General-purpose Backup Registers  7.4 Divider /1,/2,/4 Four 32-bit general-purpose backup registers Chip Identification  Chip ID: 0x019803A2  JTAG ID: 0x05B1303F  ARM926 TAP ID: 0x0792603F SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 25 7.5 Backup Section The SAM9260 features a Backup Section that embeds:  RC Oscillator  Slow Clock Oscillator  RTT  Shutdown Controller  4 general-purpose backup registers (GPBR)  A part of RSTC This section is powered by the VDDBU rail. 26 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 8. Peripherals 8.1 User Interface As shown in Figure 6-1 “SAM9260 Memory Mapping”, the peripherals are mapped in the upper 256 Mbytes of the address space between the addresses 0xFFFA 0000 and 0xFFFC FFFF. Each user peripheral is allocated 16 Kbytes of address space. 8.2 Peripheral Identifiers Table 8-1 defines the peripheral identifiers of the SAM9260. A peripheral identifier is required for the control of the peripheral interrupt with the Advanced Interrupt Controller and for the control of the peripheral clock with the Power Management Controller. Table 8-1. SAM9260 Peripheral Identifiers Peripheral ID Peripheral Mnemonic Peripheral Name External Interrupt 0 AIC Advanced Interrupt Controller FIQ 1 SYSC System Controller Interrupt 2 PIOA Parallel I/O Controller A 3 PIOB Parallel I/O Controller B 4 PIOC Parallel I/O Controller C 5 ADC Analog-to-Digital Converter 6 US0 Universal Synchronous Asynchronous Receiver Transmitter 0 7 US1 Universal Synchronous Asynchronous Receiver Transmitter 1 8 US2 Universal Synchronous Asynchronous Receiver Transmitter 2 9 MCI MultiMedia Card Interface 10 UDP USB Device Port 11 TWI Two-wire Interface 12 SPI0 Serial Peripheral Interface 0 13 SPI1 Serial Peripheral Interface 1 14 SSC Synchronous Serial Controller 15 – Reserved 16 – Reserved 17 TC0 Timer/Counter 0 18 TC1 Timer/Counter 1 19 TC2 Timer/Counter 2 20 UHP USB Host Port 21 EMAC Ethernet MAC 22 ISI Image Sensor Interface 23 US3 Universal Synchronous Asynchronous Receiver Transmitter 3 24 US4 Universal Synchronous Asynchronous Receiver Transmitter 4 25 US5 Universal Synchronous Asynchronous Receiver Transmitter 5 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 27 Table 8-1. SAM9260 Peripheral Identifiers (Continued) Peripheral ID Peripheral Mnemonic Peripheral Name External Interrupt 26 TC3 Timer/Counter 3 27 TC4 Timer/Counter 4 28 TC5 Timer/Counter 5 29 AIC Advanced Interrupt Controller IRQ0 30 AIC Advanced Interrupt Controller IRQ1 31 AIC Advanced Interrupt Controller IRQ2 Note: Setting AIC, SYSC, UHP and IRQ0–2 bits in the clock set/clear registers of the PMC has no effect. 8.2.1 Peripheral Interrupts and Clock Control 8.2.1.1 System Interrupt The System Interrupt in Source 1 is the wired-OR of the interrupt signals coming from:  the SDRAM Controller  the Debug Unit  the Periodic Interval Timer  the Real-time Timer  the Watchdog Timer  the Reset Controller  the Power Management Controller The clock of these peripherals cannot be deactivated and Peripheral ID 1 can only be used within the Advanced Interrupt Controller. 8.2.1.2 External Interrupts All external interrupt signals, i.e., the Fast Interrupt signal FIQ or the Interrupt signals IRQ0 to IRQ2, use a dedicated Peripheral ID. However, there is no clock control associated with these peripheral IDs. 8.3 Peripheral Signal Multiplexing on I/O Lines The SAM9260 features three PIO controllers (PIOA, PIOB, PIOC) that multiplex the I/O lines of the peripheral set. Each PIO Controller controls up to 32 lines. Each line can be assigned to one of two peripheral functions, A or B. Table 8-2 on page 29, Table 8-3 on page 30 and Table 8-4 on page 31 define how the I/O lines of the peripherals A and B are multiplexed on the PIO Controllers. The two columns “Function” and “Comments” have been inserted in this table for the user’s own comments; they may be used to track how pins are defined in an application. Note that some peripheral functions which are output only might be duplicated within both tables. The column “Reset State” indicates whether the PIO Line resets in I/O mode or in peripheral mode. If I/O appears, the PIO Line resets in input with the pull-up enabled, so that the device is maintained in a static state as soon as the reset is released. As a result, the bit corresponding to the PIO Line in the register PIO_PSR (Peripheral Status Register) resets low. If a signal name appears in the “Reset State” column, the PIO Line is assigned to this function and the corresponding bit in PIO_PSR resets high. This is the case of pins controlling memories, in particular the address lines, which require the pin to be driven as soon as the reset is released. Note that the pull-up resistor is also enabled in this case. 28 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 8.3.1 PIO Controller A Multiplexing Table 8-2. Multiplexing on PIO Controller A PIO Controller A I/O Line Peripheral A Peripheral B PA0 SPI0_MISO PA1 SPI0_MOSI PA2 SPI0_SPCK PA3 SPI0_NPCS0 PA4 Reset State Power Supply MCDB0 I/O VDDIOP0 MCCDB I/O VDDIOP0 I/O VDDIOP0 MCDB3 I/O VDDIOP0 RTS2 MCDB2 I/O VDDIOP0 PA5 CTS2 MCDB1 I/O VDDIOP0 PA6 MCDA0 I/O VDDIOP0 PA7 MCCDA I/O VDDIOP0 PA8 MCCK I/O VDDIOP0 PA9 MCDA1 I/O VDDIOP0 PA10 MCDA2 ETX2 I/O VDDIOP0 PA11 MCDA3 ETX3 I/O VDDIOP0 PA12 ETX0 I/O VDDIOP0 PA13 ETX1 I/O VDDIOP0 PA14 ERX0 I/O VDDIOP0 PA15 ERX1 I/O VDDIOP0 PA16 ETXEN I/O VDDIOP0 PA17 ERXDV I/O VDDIOP0 PA18 ERXER I/O VDDIOP0 PA19 ETXCK I/O VDDIOP0 PA20 EMDC I/O VDDIOP0 PA21 EMDIO I/O VDDIOP0 PA22 ADTRG ETXER I/O VDDIOP0 PA23 TWD ETX2 I/O VDDIOP0 PA24 TWCK ETX3 I/O VDDIOP0 PA25 TCLK0 ERX2 I/O VDDIOP0 PA26 TIOA0 ERX3 I/O VDDIOP0 PA27 TIOA1 ERXCK I/O VDDIOP0 PA28 TIOA2 ECRS I/O VDDIOP0 PA29 SCK1 ECOL I/O VDDIOP0 (1) SCK2 RXD4 I/O VDDIOP0 (1) SCK0 TXD4 I/O VDDIOP0 PA30 PA31 Note: Comments Application Usage Function Comments 1. Not available in the 208-lead PQFP package. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 29 8.3.2 PIO Controller B Multiplexing Table 8-3. Multiplexing on PIO Controller B PIO Controller B I/O Line Peripheral A Peripheral B PB0 SPI1_MISO PB1 Reset State Power Supply TIOA3 I/O VDDIOP0 SPI1_MOSI TIOB3 I/O VDDIOP0 PB2 SPI1_SPCK TIOA4 I/O VDDIOP0 PB3 SPI1_NPCS0 TIOA5 I/O VDDIOP0 PB4 TXD0 I/O VDDIOP0 PB5 RXD0 I/O VDDIOP0 PB6 TXD1 TCLK1 I/O VDDIOP0 PB7 RXD1 TCLK2 I/O VDDIOP0 PB8 TXD2 I/O VDDIOP0 PB9 RXD2 I/O VDDIOP0 PB10 TXD3 ISI_D8 I/O VDDIOP1 PB11 Comments Application Usage RXD3 ISI_D9 I/O VDDIOP1 (1) TXD5 ISI_D10 I/O VDDIOP1 PB13(1) RXD5 ISI_D11 I/O VDDIOP1 PB14 DRXD I/O VDDIOP0 PB15 DTXD I/O VDDIOP0 PB16 TK0 TCLK3 I/O VDDIOP0 PB17 TF0 TCLK4 I/O VDDIOP0 PB18 TD0 TIOB4 I/O VDDIOP0 PB19 RD0 TIOB5 I/O VDDIOP0 PB20 RK0 ISI_D0 I/O VDDIOP1 PB21 RF0 ISI_D1 I/O VDDIOP1 PB22 DSR0 ISI_D2 I/O VDDIOP1 PB23 DCD0 ISI_D3 I/O VDDIOP1 PB24 DTR0 ISI_D4 I/O VDDIOP1 PB25 RI0 ISI_D5 I/O VDDIOP1 PB26 RTS0 ISI_D6 I/O VDDIOP1 PB27 CTS0 ISI_D7 I/O VDDIOP1 PB28 RTS1 ISI_PCK I/O VDDIOP1 PB29 CTS1 ISI_VSYNC I/O VDDIOP1 PB30 PCK0 ISI_HSYNC I/O VDDIOP1 PB31 PCK1 I/O VDDIOP1 PB12 Note: 30 1. Not available in the 208-lead PQFP package. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 Function Comments 8.3.3 PIO Controller C Multiplexing Table 8-4. Multiplexing on PIO Controller C PIO Controller C I/O Line Peripheral A Application Usage Peripheral B Comments Reset State Power Supply PC0 SCK3 AD0 I/O VDDANA PC1 PCK0 AD1 I/O VDDANA (1) PCK1 AD2 I/O VDDANA (1) SPI1_NPCS3 AD3 I/O VDDANA PC2 PC3 PC4 A23 SPI1_NPCS2 A23 VDDIOM PC5 A24 SPI1_NPCS1 A24 VDDIOM PC6 TIOB2 CFCE1 I/O VDDIOM PC7 TIOB1 CFCE2 I/O VDDIOM PC8 NCS4/CFCS0 RTS3 I/O VDDIOM PC9 NCS5/CFCS1 TIOB0 I/O VDDIOM PC10 A25/CFRNW CTS3 A25 VDDIOM PC11 NCS2 SPI0_NPCS1 I/O VDDIOM PC12 IRQ0 NCS7 I/O VDDIOM PC13 FIQ NCS6 I/O VDDIOM PC14 NCS3/NANDCS IRQ2 I/O VDDIOM PC15 NWAIT IRQ1 I/O VDDIOM PC16 D16 SPI0_NPCS2 I/O VDDIOM PC17 D17 SPI0_NPCS3 I/O VDDIOM PC18 D18 SPI1_NPCS1 I/O VDDIOM PC19 D19 SPI1_NPCS2 I/O VDDIOM PC20 D20 SPI1_NPCS3 I/O VDDIOM PC21 D21 EF100 I/O VDDIOM PC22 D22 TCLK5 I/O VDDIOM PC23 D23 I/O VDDIOM PC24 D24 I/O VDDIOM PC25 D25 I/O VDDIOM PC26 D26 I/O VDDIOM PC27 D27 I/O VDDIOM PC28 D28 I/O VDDIOM PC29 D29 I/O VDDIOM PC30 D30 I/O VDDIOM PC31 D31 I/O VDDIOM (1) Note: Function Comments 1. Not available in the 208-lead PQFP package. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 31 9. ARM926EJ-S Processor Overview 9.1 Description The ARM926EJ-S processor is a member of the ARM9™ family of general-purpose microprocessors. The ARM926EJ-S implements ARM architecture version 5TEJ and is targeted at multi-tasking applications where full memory management, high performance, low die size and low power are all important features. The ARM926EJ-S processor supports the 32-bit ARM and 16-bit THUMB instruction sets, enabling the user to trade off between high performance and high code density. It also supports 8-bit Java instruction set and includes features for efficient execution of Java bytecode, providing a Java performance similar to a JIT (Just-In-Time compilers), for the next generation of Java-powered wireless and embedded devices. It includes an enhanced multiplier design for improved DSP performance. The ARM926EJ-S processor supports the ARM debug architecture and includes logic to assist in both hardware and software debug. The ARM926EJ-S provides a complete high performance processor subsystem, including: 32  an ARM9EJ-S™ integer core  a Memory Management Unit (MMU)  separate instruction and data AMBA™ AHB bus interfaces  separate instruction and data TCM interfaces SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 9.2 Embedded Characteristics  RISC Processor Based on ARM v5TEJ Architecture with Jazelle technology for Java acceleration  Two Instruction Sets ̶ ARM High-performance 32-bit Instruction Set ̶ Thumb High Code Density 16-bit Instruction Set  DSP Instruction Extensions  5-Stage Pipeline Architecture ̶ ̶ Instruction Fetch (F)    Instruction Decode (D) ̶ Execute (E) ̶ Data Memory (M) ̶ Register Write (W) 8-Kbyte Data Cache, 8-Kbyte Instruction Cache ̶ Virtually-addressed 4-way Associative Cache ̶ Eight words per line ̶ Write-through and Write-back Operation ̶ Pseudo-random or Round-robin Replacement Write Buffer ̶ Main Write Buffer with 16-word Data Buffer and 4-address Buffer ̶ DCache Write-back Buffer with 8-word Entries and a Single Address Entry ̶ Software Control Drain Standard ARM v4 and v5 Memory Management Unit (MMU) Access Permission for Sections ̶ Access Permission for large pages and small pages can be specified separately for each quarter of the page ̶ ̶  16 embedded domains Bus Interface Unit (BIU) ̶ ̶ Arbitrates and Schedules AHB Requests ̶ Separate Masters for both instruction and data access providing complete Matrix system flexibility Separate Address and Data Buses for both the 32-bit instruction interface and the 32-bit data interface On Address and Data Buses, data can be 8-bit (Bytes), 16-bit (Half-words) or 32-bit (Words) SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 33 9.3 Block Diagram Figure 9-1. ARM926EJ-S Internal Functional Block Diagram ARM926EJ-S TCM Interface Coprocessor Interface ETM Interface DEXT Droute Data AHB Interface AHB DCACHE WDATA Bus Interface Unit RDATA ARM9EJ-S DA MMU EmbeddedICE -RT Processor Instruction AHB Interface IA INSTR ICE Interface ICACHE Iroute IEXT 34 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 AHB 9.4 ARM9EJ-S Processor 9.4.1 ARM9EJ-S Operating States The ARM9EJ-S processor can operate in three different states, each with a specific instruction set:  ARM state: 32-bit, word-aligned ARM instructions.  THUMB state: 16-bit, halfword-aligned Thumb instructions.  Jazelle state: variable length, byte-aligned Jazelle instructions. In Jazelle state, all instruction Fetches are in words. 9.4.2 Switching State The operating state of the ARM9EJ-S core can be switched between:  ARM state and THUMB state using the BX and BLX instructions, and loads to the PC  ARM state and Jazelle state using the BXJ instruction All exceptions are entered, handled and exited in ARM state. If an exception occurs in Thumb or Jazelle states, the processor reverts to ARM state. The transition back to Thumb or Jazelle states occurs automatically on return from the exception handler. 9.4.3 Instruction Pipelines The ARM9EJ-S core uses two kinds of pipelines to increase the speed of the flow of instructions to the processor. A five-stage (five clock cycles) pipeline is used for ARM and Thumb states. It consists of Fetch, Decode, Execute, Memory and Writeback stages. A six-stage (six clock cycles) pipeline is used for Jazelle state It consists of Fetch, Jazelle/Decode (two clock cycles), Execute, Memory and Writeback stages. 9.4.4 Memory Access The ARM9EJ-S core supports byte (8-bit), half-word (16-bit) and word (32-bit) access. Words must be aligned to four-byte boundaries, half-words must be aligned to two-byte boundaries and bytes can be placed on any byte boundary. Because of the nature of the pipelines, it is possible for a value to be required for use before it has been placed in the register bank by the actions of an earlier instruction. The ARM9EJ-S control logic automatically detects these cases and stalls the core or forward data. 9.4.5 Jazelle Technology The Jazelle technology enables direct and efficient execution of Java byte codes on ARM processors, providing high performance for the next generation of Java-powered wireless and embedded devices. The new Java feature of ARM9EJ-S can be described as a hardware emulation of a JVM (Java Virtual Machine). Java mode appears as another state: instead of executing ARM or Thumb instructions, it executes Java byte codes. The Java byte code decoder logic implemented in ARM9EJ-S decodes 95% of executed byte codes and turns them into ARM instructions without any overhead, while less frequently used byte codes are broken down into optimized sequences of ARM instructions. The hardware/software split is invisible to the programmer, invisible to the application and invisible to the operating system. All existing ARM registers are re-used in Jazelle state and all registers then have particular functions in this mode. Minimum interrupt latency is maintained across both ARM state and Java state. Since byte codes execution can be restarted, an interrupt automatically triggers the core to switch from Java state to ARM state for the execution of the interrupt handler. This means that no special provision has to be made for handling interrupts while executing byte codes, whether in hardware or in software. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 35 9.4.6 ARM9EJ-S Operating Modes In all states, there are seven operation modes:  User mode is the usual ARM program execution state. It is used for executing most application programs  Fast Interrupt (FIQ) mode is used for handling fast interrupts. It is suitable for high-speed data transfer or channel process  Interrupt (IRQ) mode is used for general-purpose interrupt handling  Supervisor mode is a protected mode for the operating system  Abort mode is entered after a data or instruction prefetch abort  System mode is a privileged user mode for the operating system  Undefined mode is entered when an undefined instruction exception occurs Mode changes may be made under software control, or may be brought about by external interrupts or exception processing. Most application programs execute in User Mode. The non-user modes, known as privileged modes, are entered in order to service interrupts or exceptions or to access protected resources. 36 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 9.4.7 ARM9EJ-S Registers The ARM9EJ-S core has a total of 37 registers.  31 general-purpose 32-bit registers  Six 32-bit status registers Table 9-1 shows all the registers in all modes. Table 9-1. ARM9EJ-S Modes and Registers Layout User and System Mode Supervisor Mode Abort Mode Undefined Mode Interrupt Mode Fast Interrupt Mode R0 R0 R0 R0 R0 R0 R1 R1 R1 R1 R1 R1 R2 R2 R2 R2 R2 R2 R3 R3 R3 R3 R3 R3 R4 R4 R4 R4 R4 R4 R5 R5 R5 R5 R5 R5 R6 R6 R6 R6 R6 R6 R7 R7 R7 R7 R7 R7 R8 R8 R8 R8 R8 R8_FIQ R9 R9 R9 R9 R9 R9_FIQ R10 R10 R10 R10 R10 R10_FIQ R11 R11 R11 R11 R11 R11_FIQ R12 R12 R12 R12 R12 R12_FIQ R13 R13_SVC R13_ABORT R13_UNDEF R13_IRQ R13_FIQ R14 R14_SVC R14_ABORT R14_UNDEF R14_IRQ R14_FIQ PC PC PC PC PC PC CPSR CPSR CPSR CPSR CPSR CPSR SPSR_SVC SPSR_ABORT SPSR_UNDEF SPSR_IRQ SPSR_FIQ Mode-specific banked registers The ARM state register set contains 16 directly-accessible registers, r0 to r15, and an additional register, the Current Program Status Register (CPSR). Registers r0 to r13 are general-purpose registers used to hold either data or address values. Register r14 is used as a Link register that holds a value (return address) of r15 when BL or BLX is executed. Register r15 is used as a program counter (PC), whereas the Current Program Status Register (CPSR) contains condition code flags and the current mode bits. In privileged modes (FIQ, Supervisor, Abort, IRQ, Undefined), mode-specific banked registers (r8 to r14 in FIQ mode or r13 to r14 in the other modes) become available. The corresponding banked registers r14_fiq, r14_svc, r14_abt, r14_irq, r14_und are similarly used to hold the values (return address for each mode) of r15 (PC) when interrupts and exceptions arise, or when BL or BLX instructions are executed within interrupt or exception routines. There is another register called Saved Program Status Register (SPSR) that becomes available in privileged modes instead of CPSR. This register contains condition code flags and the current mode bits saved as a result of the exception that caused entry to the current (privileged) mode. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 37 In all modes and due to a software agreement, register r13 is used as stack pointer. The use and the function of all the registers described above should obey ARM Procedure Call Standard (APCS) which defines:  constraints on the use of registers  stack conventions  argument passing and result return The Thumb state register set is a subset of the ARM state set. The programmer has direct access to:  Eight general-purpose registers r0–r7  Stack pointer, SP  Link register, LR (ARM r14)  PC  CPSR There are banked registers SPs, LRs and SPSRs for each privileged mode (for more details see the ARM9EJ-S Technical Reference Manual, ref. DDI0222B, revision r1p2 page 2-12). 9.4.7.1 Status Registers The ARM9EJ-S core contains one CPSR, and five SPSRs for exception handlers to use. The program status registers:  hold information about the most recently performed ALU operation  control the enabling and disabling of interrupts  set the processor operation mode Figure 9-2. Status Register Format 31 30 29 28 27 24 N Z C V Q J 7 6 5 Reserved Jazelle state bit Reserved Sticky Overflow Overflow Carry/Borrow/Extend Zero Negative/Less than I F T 0 Mode Mode bits Thumb state bit FIQ disable IRQ disable Figure 9-2 shows the status register format, where:  N: Negative, Z: Zero, C: Carry, and V: Overflow are the four ALU flags  The Sticky Overflow (Q) flag can be set by certain multiply and fractional arithmetic instructions like QADD, QDADD, QSUB, QDSUB, SMLAxy, and SMLAWy needed to achieve DSP operations. The Q flag is sticky in that, when set by an instruction, it remains set until explicitly cleared by an MSR instruction writing to the CPSR. Instructions cannot execute conditionally on the status of the Q flag.  The J bit in the CPSR indicates when the ARM9EJ-S core is in Jazelle state, where:  38 ̶ J = 0: The processor is in ARM or Thumb state, depending on the T bit ̶ J = 1: The processor is in Jazelle state. Mode: five bits to encode the current processor mode SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 9.4.7.2 Exceptions Exception Types and Priorities The ARM9EJ-S supports five types of exceptions. Each type drives the ARM9EJ-S in a privileged mode. The types of exceptions are:  Fast interrupt (FIQ)  Normal interrupt (IRQ)  Data and Prefetched aborts (Abort)  Undefined instruction (Undefined)  Software interrupt and Reset (Supervisor) When an exception occurs, the banked version of R14 and the SPSR for the exception mode are used to save the state. More than one exception can happen at a time, therefore the ARM9EJ-S takes the arisen exceptions according to the following priority order:  Reset (highest priority)  Data Abort  FIQ  IRQ  Prefetch Abort  BKPT, Undefined instruction, and Software Interrupt (SWI) (Lowest priority) The BKPT, or Undefined instruction, and SWI exceptions are mutually exclusive. There is one exception in the priority scheme though, when FIQs are enabled and a Data Abort occurs at the same time as an FIQ, the ARM9EJ-S core enters the Data Abort handler, and proceeds immediately to FIQ vector. A normal return from the FIQ causes the Data Abort handler to resume execution. Data Aborts must have higher priority than FIQs to ensure that the transfer error does not escape detection. Exception Modes and Handling Exceptions arise whenever the normal flow of a program must be halted temporarily, for example, to service an interrupt from a peripheral. When handling an ARM exception, the ARM9EJ-S core performs the following operations: 1. Preserves the address of the next instruction in the appropriate Link Register that corresponds to the new mode that has been entered. When the exception entry is from: ̶ ̶ ARM and Jazelle states, the ARM9EJ-S copies the address of the next instruction into LR (current PC(r15) + 4 or PC + 8 depending on the exception). THUMB state, the ARM9EJ-S writes the value of the PC into LR, offset by a value (current PC + 2, PC + 4 or PC + 8 depending on the exception) that causes the program to resume from the correct place on return. 2. Copies the CPSR into the appropriate SPSR. 3. Forces the CPSR mode bits to a value that depends on the exception. 4. Forces the PC to fetch the next instruction from the relevant exception vector. The register r13 is also banked across exception modes to provide each exception handler with private stack pointer. The ARM9EJ-S can also set the interrupt disable flags to prevent otherwise unmanageable nesting of exceptions. When an exception has completed, the exception handler must move both the return value in the banked LR minus an offset to the PC and the SPSR to the CPSR. The offset value varies according to the type of exception. This action restores both PC and the CPSR. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 39 The fast interrupt mode has seven private registers r8 to r14 (banked registers) to reduce or remove the requirement for register saving which minimizes the overhead of context switching. The Prefetch Abort is one of the aborts that indicates that the current memory access cannot be completed. When a Prefetch Abort occurs, the ARM9EJ-S marks the prefetched instruction as invalid, but does not take the exception until the instruction reaches the Execute stage in the pipeline. If the instruction is not executed, for example because a branch occurs while it is in the pipeline, the abort does not take place. The breakpoint (BKPT) instruction is a new feature of ARM9EJ-S that is destined to solve the problem of the Prefetch Abort. A breakpoint instruction operates as though the instruction caused a Prefetch Abort. A breakpoint instruction does not cause the ARM9EJ-S to take the Prefetch Abort exception until the instruction reaches the Execute stage of the pipeline. If the instruction is not executed, for example because a branch occurs while it is in the pipeline, the breakpoint does not take place. 40 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 9.4.8 ARM Instruction Set Overview The ARM instruction set is divided into:  Branch instructions  Data processing instructions  Status register transfer instructions  Load and Store instructions  Coprocessor instructions  Exception-generating instructions ARM instructions can be executed conditionally. Every instruction contains a 4-bit condition code field (bits[31:28]). Table 9-2 gives the ARM instruction mnemonic list. Table 9-2. Mnemonic ARM Instruction Mnemonic List Operation Mnemonic Operation MOV Move MVN Move Not ADD Add ADC Add with Carry SUB Subtract SBC Subtract with Carry RSB Reverse Subtract RSC Reverse Subtract with Carry CMP Compare CMN Compare Negated TST Test TEQ Test Equivalence AND Logical AND BIC Bit Clear EOR Logical Exclusive OR ORR Logical (inclusive) OR MUL Multiply MLA Multiply Accumulate SMULL Sign Long Multiply UMULL Unsigned Long Multiply SMLAL Signed Long Multiply Accumulate UMLAL Unsigned Long Multiply Accumulate MSR B BX LDR Move to Status Register Branch MRS BL Move From Status Register Branch and Link Branch and Exchange SWI Software Interrupt Load Word STR Store Word LDRSH Load Signed Halfword LDRSB Load Signed Byte LDRH Load Half Word STRH Store Half Word LDRB Load Byte STRB Store Byte LDRBT Load Register Byte with Translation STRBT Store Register Byte with Translation LDRT Load Register with Translation STRT Store Register with Translation LDM Load Multiple STM Store Multiple SWP Swap Word MCR Move To Coprocessor MRC Move From Coprocessor LDC Load To Coprocessor STC Store From Coprocessor CDP Coprocessor Data Processing SWPB Swap Byte SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 41 9.4.9 New ARM Instruction Set Table 9-3. New ARM Instruction Mnemonic List Mnemonic BXJ Operation Mnemonic Operation Branch and exchange to Java MRRC Move double from coprocessor Branch, Link and exchange MCR2 Alternative move of ARM reg to coprocessor SMLAxy Signed Multiply Accumulate 16 * 16 bit MCRR Move double to coprocessor SMLAL Signed Multiply Accumulate Long CDP2 Alternative Coprocessor Data Processing SMLAWy Signed Multiply Accumulate 32 * 16 bit BKPT Breakpoint SMULxy Signed Multiply 16 * 16 bit PLD SMULWy Signed Multiply 32 * 16 bit STRD Store Double Saturated Add STC2 Alternative Store from Coprocessor Saturated Add with Double LDRD Load Double Saturated subtract LDC2 Alternative Load to Coprocessor BLX (1) QADD QDADD QSUB QDSUB Note: 42 Saturated Subtract with double CLZ Soft Preload, Memory prepare to load from address Count Leading Zeroes 1. A Thumb BLX contains two consecutive Thumb instructions, and takes four cycles. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 9.4.10 Thumb Instruction Set Overview The Thumb instruction set is a re-encoded subset of the ARM instruction set. The Thumb instruction set is divided into:  Branch instructions  Data processing instructions  Load and Store instructions  Load and Store multiple instructions  Exception-generating instruction Table 9-4 gives the Thumb instruction mnemonic list. Table 9-4. Thumb Instruction Mnemonic List Mnemonic Operation Mnemonic Operation MOV Move MVN Move Not ADD Add ADC Add with Carry SUB Subtract SBC Subtract with Carry CMP Compare CMN Compare Negated TST Test NEG Negate AND Logical AND BIC Bit Clear EOR Logical Exclusive OR ORR Logical (inclusive) OR LSL Logical Shift Left LSR Logical Shift Right ASR Arithmetic Shift Right ROR Rotate Right MUL Multiply BLX Branch, Link, and Exchange B Branch BL Branch and Link BX Branch and Exchange SWI Software Interrupt LDR Load Word STR Store Word LDRH Load Half Word STRH Store Half Word LDRB Load Byte STRB Store Byte LDRSH Load Signed Halfword LDRSB Load Signed Byte LDMIA Load Multiple STMIA Store Multiple PUSH Push Register to stack POP Pop Register from stack BCC Conditional Branch BKPT Breakpoint SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 43 9.5 CP15 Coprocessor Coprocessor 15, or System Control Coprocessor CP15, is used to configure and control all the items in the list below:  ARM9EJ-S  Caches (ICache, DCache and write buffer)  TCM  MMU  Other system options To control these features, CP15 provides 16 additional registers. See Table 9-5. Table 9-5. CP15 Registers Register 0 Read/Unpredictable ID Code 0 Cache type Read/Unpredictable 0 TCM status(1) Read/Unpredictable 1 Control Read/Write 2 Translation Table Base Read/Write 3 Domain Access Control Read/Write 4 Reserved None Data fault Status (1) Read/Write (1) 5 Instruction fault status Read/Write 6 Fault Address Read/Write 7 Cache Operations Read/Write 8 TLB operations Unpredictable/Write (2) 9 Cache lockdown Read/Write 9 TCM region Read/Write 10 TLB lockdown Read/Write 11 Reserved None 12 Reserved None 13 (1) FCSE PID Read/Write 13 Context ID(1) Read/Write 14 Reserved None 15 Test configuration Read/Write 1. 2. 44 Read/Write (1) (1) 5 Notes: Name Register locations 0, 5 and 13 each provide access to more than one register. The register accessed depends on the value of the opcode_2 field. Register location 9 provides access to more than one register. The register accessed depends on the value of the CRm field. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 9.5.1 CP15 Registers Access CP15 registers can only be accessed in privileged mode by:  MCR (Move to Coprocessor from ARM Register) instruction is used to write an ARM register to CP15.  MRC (Move to ARM Register from Coprocessor) instruction is used to read the value of CP15 to an ARM register. Other instructions like CDP, LDC, STC can cause an undefined instruction exception. The assembler code for these instructions is: MCR/MRC{cond} p15, opcode_1, Rd, CRn, CRm, opcode_2. The MCR, MRC instructions bit pattern is shown below: 31 30 29 28 cond 23 22 21 opcode_1 15 20 13 12 Rd 6 26 25 24 1 1 1 0 19 18 17 16 L 14 7 27 5 opcode_2 4 CRn 11 10 9 8 1 1 1 1 3 2 1 0 1 CRm • CRm[3:0]: Specified Coprocessor Action Determines specific coprocessor action. Its value is dependent on the CP15 register used. For details, refer to CP15 specific register behavior. • opcode_2[7:5] Determines specific coprocessor operation code. By default, set to 0. • Rd[15:12]: ARM Register Defines the ARM register whose value is transferred to the coprocessor. If R15 is chosen, the result is unpredictable. • CRn[19:16]: Coprocessor Register Determines the destination coprocessor register. • L: Instruction Bit 0 = MCR instruction 1 = MRC instruction • opcode_1[23:20]: Coprocessor Code Defines the coprocessor specific code. Value is c15 for CP15. • cond [31:28]: Condition For more details, see Chapter 2 in ARM926EJ-S TRM, ref. DDI0198B. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 45 9.6 Memory Management Unit (MMU) The ARM926EJ-S processor implements an enhanced ARM architecture v5 MMU to provide virtual memory features required by operating systems like Symbian OS®, Windows CE, and Linux. These virtual memory features are memory access permission controls and virtual to physical address translations. The Virtual Address generated by the CPU core is converted to a Modified Virtual Address (MVA) by the FCSE (Fast Context Switch Extension) using the value in CP15 register13. The MMU translates modified virtual addresses to physical addresses by using a single, two-level page table set stored in physical memory. Each entry in the set contains the access permissions and the physical address that correspond to the virtual address. The first level translation tables contain 4096 entries indexed by bits [31:20] of the MVA. These entries contain a pointer to either a 1 MB section of physical memory along with attribute information (access permissions, domain, etc.) or an entry in the second level translation tables; coarse table and fine table. The second level translation tables contain two subtables, coarse table and fine table. An entry in the coarse table contains a pointer to both large pages and small pages along with access permissions. An entry in the fine table contains a pointer to large, small and tiny pages. Table 9-6 shows the different attributes of each page in the physical memory. Table 9-6. Mapping Details Mapping Name Mapping Size Access Permission By Subpage Size Section 1 Mbyte Section - Large Page 64 Kbytes 4 separated subpages 16 Kbytes Small Page 4 Kbytes 4 separated subpages 1 Kbyte Tiny Page 1 Kbyte Tiny Page - The MMU consists of: 9.6.1  Access control logic  Translation Look-aside Buffer (TLB)  Translation table walk hardware Access Control Logic The access control logic controls access information for every entry in the translation table. The access control logic checks two pieces of access information: domain and access permissions. The domain is the primary access control mechanism for a memory region; there are 16 of them. It defines the conditions necessary for an access to proceed. The domain determines whether the access permissions are used to qualify the access or whether they should be ignored. The second access control mechanism is access permissions that are defined for sections and for large, small and tiny pages. Sections and tiny pages have a single set of access permissions whereas large and small pages can be associated with 4 sets of access permissions, one for each subpage (quarter of a page). 9.6.2 Translation Look-aside Buffer (TLB) The Translation Look-aside Buffer (TLB) caches translated entries and thus avoids going through the translation process every time. When the TLB contains an entry for the MVA (Modified Virtual Address), the access control logic determines if the access is permitted and outputs the appropriate physical address corresponding to the MVA. If access is not permitted, the MMU signals the CPU core to abort. If the TLB does not contain an entry for the MVA, the translation table walk hardware is invoked to retrieve the translation information from the translation table in physical memory. 46 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 9.6.3 Translation Table Walk Hardware The translation table walk hardware is a logic that traverses the translation tables located in physical memory, gets the physical address and access permissions and updates the TLB. The number of stages in the hardware table walking is one or two depending whether the address is marked as a section-mapped access or a page-mapped access. There are three sizes of page-mapped accesses and one size of section-mapped access. Page-mapped accesses are for large pages, small pages and tiny pages. The translation process always begins with a level one fetch. A section-mapped access requires only a level one fetch, but a page-mapped access requires an additional level two fetch. For further details on the MMU, please refer to chapter 3 in ARM926EJ-S Technical Reference Manual, ref. DDI0198B. 9.6.4 MMU Faults The MMU generates an abort on the following types of faults:  Alignment faults (for data accesses only)  Translation faults  Domain faults  Permission faults The access control mechanism of the MMU detects the conditions that produce these faults. If the fault is a result of memory access, the MMU aborts the access and signals the fault to the CPU core. The MMU retains status and address information about faults generated by the data accesses in the data fault status register and fault address register. It also retains the status of faults generated by instruction fetches in the instruction fault status register. The fault status register (register 5 in CP15) indicates the cause of a data or prefetch abort, and the domain number of the aborted access when it happens. The fault address register (register 6 in CP15) holds the MVA associated with the access that caused the Data Abort. For further details on MMU faults, please refer to chapter 3 in ARM926EJ-S Technical Reference Manual, ref. DDI0198B. 9.7 Caches and Write Buffer The ARM926EJ-S contains an 8 KB Instruction Cache (ICache), an 8 KB Data Cache (DCache), and a write buffer. Although the ICache and DCache share common features, each still has some specific mechanisms. The caches (ICache and DCache) are four-way set associative, addressed, indexed and tagged using the Modified Virtual Address (MVA), with a cache line length of eight words with two dirty bits for the DCache. The ICache and DCache provide mechanisms for cache lockdown, cache pollution control, and line replacement. A new feature is now supported by ARM926EJ-S caches called allocate on read-miss commonly known as wrapping. This feature enables the caches to perform critical word first cache refilling. This means that when a request for a word causes a read-miss, the cache performs an AHB access. Instead of loading the whole line (eight words), the cache loads the critical word first, so the processor can reach it quickly, and then the remaining words, no matter where the word is located in the line. The caches and the write buffer are controlled by the CP15 register 1 (Control), CP15 register 7 (cache operations) and CP15 register 9 (cache lockdown). 9.7.1 Instruction Cache (ICache) The ICache caches fetched instructions to be executed by the processor. The ICache can be enabled by writing 1 to I bit of the CP15 Register 1 and disabled by writing 0 to this same bit. When the MMU is enabled, all instruction fetches are subject to translation and permission checks. If the MMU is disabled, all instructions fetches are cachable, no protection checks are made and the physical address is flat- SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 47 mapped to the modified virtual address. With the MVA use disabled, context switching incurs ICache cleaning and/or invalidating. When the ICache is disabled, all instruction fetches appear on external memory (AHB) (see Tables 4-1 and 4-2 in page 4-4 in ARM926EJ-S TRM, ref. DDI0198B). On reset, the ICache entries are invalidated and the ICache is disabled. For best performance, ICache should be enabled as soon as possible after reset. 9.7.2 Data Cache (DCache) and Write Buffer ARM926EJ-S includes a DCache and a write buffer to reduce the effect of main memory bandwidth and latency on data access performance. The operations of DCache and write buffer are closely connected. 9.7.2.1 DCache The DCache needs the MMU to be enabled. All data accesses are subject to MMU permission and translation checks. Data accesses that are aborted by the MMU do not cause linefills or data accesses to appear on the AMBA AHB interface. If the MMU is disabled, all data accesses are noncachable, nonbufferable, with no protection checks, and appear on the AHB bus. All addresses are flat-mapped, VA = MVA = PA, which incurs DCache cleaning and/or invalidating every time a context switch occurs. The DCache stores the Physical Address Tag (PA Tag) from which every line was loaded and uses it when writing modified lines back to external memory. This means that the MMU is not involved in write-back operations. Each line (8 words) in the DCache has two dirty bits, one for the first four words and the other one for the second four words. These bits, if set, mark the associated half-lines as dirty. If the cache line is replaced due to a linefill or a cache clean operation, the dirty bits are used to decide whether all, half or none is written back to memory. DCache can be enabled or disabled by writing either 1 or 0 to bit C in register 1 of CP15 (see Tables 4-3 and 4-4 on page 4-5 in ARM926EJ-S TRM, ref. DDI0222B). The DCache supports write-through and write-back cache operations, selected by memory region using the C and B bits in the MMU translation tables. The DCache contains an eight data word entry, single address entry write-back buffer used to hold write-back data for cache line eviction or cleaning of dirty cache lines. The Write Buffer can hold up to 16 words of data and four separate addresses. DCache and Write Buffer operations are closely connected as their configuration is set in each section by the page descriptor in the MMU translation table. 9.7.2.2 Write Buffer The ARM926EJ-S contains a write buffer that has a 16-word data buffer and a four- address buffer. The write buffer is used for all writes to a bufferable region, write-through region and write-back region. It also allows to avoid stalling the processor when writes to external memory are performed. When a store occurs, data is written to the write buffer at core speed (high speed). The write buffer then completes the store to external memory at bus speed (typically slower than the core speed). During this time, the ARM9EJ-S processor can preform other tasks. DCache and Write Buffer support write-back and write-through memory regions, controlled by C and B bits in each section and page descriptor within the MMU translation tables. Write-though Operation When a cache write hit occurs, the DCache line is updated. The updated data is then written to the write buffer which transfers it to external memory. When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer which transfers it to external memory. 48 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 Write-back Operation When a cache write hit occurs, the cache line or half line is marked as dirty, meaning that its contents are not upto-date with those in the external memory. When a cache write miss occurs, a line, chosen by round robin or another algorithm, is stored in the write buffer which transfers it to external memory. 9.8 Bus Interface Unit The ARM926EJ-S features a Bus Interface Unit (BIU) that arbitrates and schedules AHB requests. The BIU implements a multi-layer AHB, based on the AHB-Lite protocol, that enables parallel access paths between multiple AHB masters and slaves in a system. This is achieved by using a more complex interconnection matrix and gives the benefit of increased overall bus bandwidth, and a more flexible system architecture. The multi-master bus architecture has a number of benefits: 9.8.1  It allows the development of multi-master systems with an increased bus bandwidth and a flexible architecture.  Each AHB layer becomes simple because it only has one master, so no arbitration or master-to-slave muxing is required. AHB layers, implementing AHB-Lite protocol, do not have to support request and grant, nor do they have to support retry and split transactions.  The arbitration becomes effective when more than one master wants to access the same slave simultaneously. Supported Transfers The ARM926EJ-S processor performs all AHB accesses as single word, bursts of four words, or bursts of eight words. Any ARM9EJ-S core request that is not 1, 4, 8 words in size is split into packets of these sizes. Note that the Atmel bus is AHB-Lite protocol compliant, hence it does not support split and retry requests. Table 9-7 gives an overview of the supported transfers and different kinds of transactions they are used for. Table 9-7. HBurst[2:0] Supported Transfers Description Operation Single transfer of word, half word, or byte: Single Single transfer  data write (NCNB, NCB, WT, or WB that has missed in DCache)  data read (NCNB or NCB)  NC instruction fetch (prefetched and non-prefetched)  page table walk read Incr4 Four-word incrementing burst Half-line cache write-back, Instruction prefetch, if enabled. Four-word burst NCNB, NCB, WT, or WB write. Incr8 Eight-word incrementing burst Full-line cache write-back, eight-word burst NCNB, NCB, WT, or WB write Wrap8 Eight-word wrapping burst Cache linefill 9.8.2 Thumb Instruction Fetches All instructions fetches, regardless of the state of ARM9EJ-S core, are made as 32-bit accesses on the AHB. If the ARM9EJ-S is in Thumb state, then two instructions can be fetched at a time. 9.8.3 Address Alignment The ARM926EJ-S BIU performs address alignment checking and aligns AHB addresses to the necessary boundary. 16-bit accesses are aligned to halfword boundaries, and 32-bit accesses are aligned to word boundaries. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 49 10. SAM9260 Debug and Test 10.1 Description The SAM9260 features a number of complementary debug and test capabilities. A common JTAG/ICE (In-Circuit Emulator) port is used for standard debugging functions, such as downloading code and single-stepping through programs. The Debug Unit provides a two-pin UART that can be used to upload an application into internal SRAM. It manages the interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the Debug Communication Channel. A set of dedicated debug and test input/output pins gives direct access to these capabilities from a PC-based test environment. 10.2 Embedded Characteristics    50 ARM926 Real-time In-circuit Emulator ̶ Two real-time Watchpoint Units ̶ Two Independent Registers: Debug Control Register and Debug Status Register ̶ Test Access Port Accessible through JTAG Protocol ̶ Debug Communications Channel Debug Unit ̶ Two-pin UART ̶ Debug Communication Channel Interrupt Handling ̶ Chip ID Register IEEE1149.1 JTAG Boundary-scan on All Digital Pins SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 Block Diagram Figure 10-1. Debug and Test Block Diagram TMS TCK TDI NTRST ICE/JTAG TAP Boundary Port JTAGSEL TDO RTCK POR Reset and Test ARM9EJ-S TST ICE-RT ARM926EJ-S PDC DBGU PIO 10.3 DTXD DRXD TAP: Test Access Port SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 51 10.4 Application Examples 10.4.1 Debug Environment Figure 10-2 shows a complete debug environment example. The ICE/JTAG interface is used for standard debugging functions, such as downloading code and single-stepping through the program. A software debugger running on a personal computer provides the user interface for configuring a Trace Port interface utilizing the ICE/JTAG interface. Figure 10-2. Application Debug and Trace Environment Example Host Debugger ICE/JTAG Interface ICE/JTAG Connector SAM9260 RS232 Connector SAM9260-based Application Board 52 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 Terminal 10.4.2 Test Environment Figure 10-3 shows a test environment example. Test vectors are sent and interpreted by the tester. In this example, the “board in test” is designed using a number of JTAG-compliant devices. These devices can be connected to form a single scan chain. Figure 10-3. Application Test Environment Example Test Adaptor Tester JTAG Interface ICE/JTAG Connector SAM9260 Chip n Chip 2 Chip 1 SAM9260-based Application Board In Test 10.5 Debug and Test Pin Description Table 10-1. Pin Name Debug and Test Pin List Function Type Active Level Input/Output Low Input High Low Reset/Test NRST Microcontroller Reset TST Test Mode Select ICE and JTAG NTRST Test Reset Signal Input TCK Test Clock Input TDI Test Data In Input TDO Test Data Out TMS Test Mode Select RTCK Returned Test Clock JTAGSEL JTAG Selection Output Input Output Input Debug Unit DRXD Debug Receive Data Input DTXD Debug Transmit Data Output SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 53 10.6 Functional Description 10.6.1 Test Pin One dedicated pin, TST, is used to define the device operating mode. The user must make sure that this pin is tied at low level to ensure normal operating conditions. Other values associated with this pin are reserved for manufacturing test. 10.6.2 EmbeddedICE The ARM9EJ-S EmbeddedICE-RT™ is supported via the ICE/JTAG port. It is connected to a host computer via an ICE interface. Debug support is implemented using an ARM9EJ-S core embedded within the ARM926EJ-S. The internal state of the ARM926EJ-S is examined through an ICE/JTAG port which allows instructions to be serially inserted into the pipeline of the core without using the external data bus. Therefore, when in debug state, a storemultiple (STM) can be inserted into the instruction pipeline. This exports the contents of the ARM9EJ-S registers. This data can be serially shifted out without affecting the rest of the system. There are two scan chains inside the ARM9EJ-S processor which support testing, debugging, and programming of the EmbeddedICE-RT. The scan chains are controlled by the ICE/JTAG port. EmbeddedICE mode is selected when JTAGSEL is low. It is not possible to switch directly between ICE and JTAG operations. A chip reset must be performed after JTAGSEL is changed. For further details on the EmbeddedICE-RT, see the ARM document ARM9EJ-S Technical Reference Manual (DDI 0222A). 10.6.3 JTAG Signal Description TMS is the Test Mode Select input which controls the transitions of the test interface state machine. TDI is the Test Data Input line which supplies the data to the JTAG registers (Boundary Scan Register, Instruction Register, or other data registers). TDO is the Test Data Output line which is used to serially output the data from the JTAG registers to the equipment controlling the test. It carries the sampled values from the boundary scan chain (or other JTAG registers) and propagates them to the next chip in the serial test circuit. NTRST (optional in IEEE Standard 1149.1) is a Test-ReSeT input which is mandatory in ARM cores and used to reset the debug logic. On Atmel ARM926EJ-S-based cores, NTRST is a Power On Reset output. It is asserted on power on. If necessary, the user can also reset the debug logic with the NTRST pin assertion during 2.5 MCK periods. TCK is the Test ClocK input which enables the test interface. TCK is pulsed by the equipment controlling the test and not by the tested device. It can be pulsed at any frequency. Note the maximum JTAG clock rate on ARM926EJ-S cores is 1/6th the clock of the CPU. This gives 5.45 kHz maximum initial JTAG clock rate for an ARM9E running from the 32.768 kHz slow clock. RTCK is the Return Test Clock. Not an IEEE Standard 1149.1 signal added for a better clock handling by emulators. From some ICE Interface probes, this return signal can be used to synchronize the TCK clock and take not care about the given ratio between the ICE Interface clock and system clock equal to 1/6th. This signal is only available in JTAG ICE Mode and not in boundary scan mode. 10.6.4 Debug Unit The Debug Unit provides a two-pin (DXRD and TXRD) USART that can be used for several debug and trace purposes and offers an ideal means for in-situ programming solutions and debug monitor communication. Moreover, the association with two peripheral data controller channels permits packet handling of these tasks with processor time reduced to a minimum. 54 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 The Debug Unit also manages the interrupt handling of the COMMTX and COMMRX signals that come from the ICE and that trace the activity of the Debug Communication Channel. The Debug Unit allows blockage of access to the system through the ICE interface. A specific register, the Debug Unit Chip ID Register, gives information about the product version and its internal configuration. The SAM9260 Debug Unit Chip ID value is 0x0198 03A0 on 32-bit width. For further details on the Debug Unit, see Section 26. “Debug Unit (DBGU)”. 10.6.5 IEEE 1149.1 JTAG Boundary Scan IEEE 1149.1 JTAG Boundary Scan allows pin-level access independent of the device packaging technology. IEEE 1149.1 JTAG Boundary Scan is enabled when JTAGSEL is high. The SAMPLE, EXTEST and BYPASS functions are implemented. In ICE debug mode, the ARM processor responds with a non-JTAG chip ID that identifies the processor to the ICE system. This is not IEEE 1149.1 JTAG-compliant. It is not possible to switch directly between JTAG and ICE operations. A chip reset must be performed after JTAGSEL is changed. A Boundary-scan Descriptor Language (BSDL) file is provided to set up test. 10.6.5.1 JTAG Boundary-scan Register The Boundary-scan Register (BSR) contains 484 bits that correspond to active pins and associated control signals. Each SAM9260 input/output pin corresponds to a 3-bit register in the BSR. The OUTPUT bit contains data that can be forced on the pad. The INPUT bit facilitates the observability of data applied to the pad. The CONTROL bit selects the direction of the pad. Table 10-2. SAM9260 JTAG Boundary Scan Register Bit Number Pin Name Pin Type A0 IN/OUT 307 CONTROL 306 INPUT/OUTPUT 305 CONTROL A1 IN/OUT 304 INPUT/OUTPUT 303 CONTROL A10 IN/OUT 302 INPUT/OUTPUT 301 CONTROL A11 IN/OUT 300 INPUT/OUTPUT 299 CONTROL A12 IN/OUT 298 INPUT/OUTPUT 297 CONTROL A13 IN/OUT 296 INPUT/OUTPUT 295 CONTROL A14 IN/OUT 294 INPUT/OUTPUT 293 CONTROL A15 292 Associated BSR Cells IN/OUT INPUT/OUTPUT SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 55 Table 10-2. SAM9260 JTAG Boundary Scan Register (Continued) Bit Number Pin Name Pin Type A16 IN/OUT 291 CONTROL 290 INPUT/OUTPUT 289 CONTROL A17 IN/OUT 288 INPUT/OUTPUT 287 CONTROL A18 IN/OUT 286 INPUT/OUTPUT 285 CONTROL A19 IN/OUT 284 INPUT/OUTPUT 283 CONTROL A2 IN/OUT 282 INPUT/OUTPUT 281 CONTROL A20 IN/OUT 280 INPUT/OUTPUT 279 CONTROL A21 IN/OUT 278 INPUT/OUTPUT 277 CONTROL A22 IN/OUT 276 INPUT/OUTPUT 275 CONTROL A3 IN/OUT 274 INPUT/OUTPUT 273 CONTROL A4 IN/OUT 272 INPUT/OUTPUT 271 CONTROL A5 IN/OUT 270 INPUT/OUTPUT 269 CONTROL A6 IN/OUT 268 INPUT/OUTPUT 267 CONTROL A7 IN/OUT 266 INPUT/OUTPUT 265 CONTROL A8 IN/OUT 264 INPUT/OUTPUT 263 CONTROL A9 IN/OUT 262 261 INPUT/OUTPUT BMS INPUT CAS IN/OUT 260 INPUT/OUTPUT 258 CONTROL D0 IN/OUT 257 INPUT/OUTPUT 256 CONTROL D1 56 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 INPUT CONTROL 259 255 Associated BSR Cells IN/OUT INPUT/OUTPUT Table 10-2. SAM9260 JTAG Boundary Scan Register (Continued) Bit Number Pin Name Pin Type D10 IN/OUT 254 CONTROL 253 INPUT/OUTPUT 252 CONTROL D11 IN/OUT 251 INPUT/OUTPUT 250 CONTROL D12 IN/OUT 249 INPUT/OUTPUT 248 CONTROL D13 IN/OUT 247 INPUT/OUTPUT 246 CONTROL D14 IN/OUT 245 INPUT/OUTPUT 244 CONTROL D15 IN/OUT 243 INPUT/OUTPUT 242 CONTROL D2 IN/OUT 241 INPUT/OUTPUT 240 CONTROL D3 IN/OUT 239 INPUT/OUTPUT 238 CONTROL D4 IN/OUT 237 INPUT/OUTPUT 236 CONTROL D5 IN/OUT 235 INPUT/OUTPUT 234 CONTROL D6 IN/OUT 233 INPUT/OUTPUT 232 CONTROL D7 IN/OUT 231 INPUT/OUTPUT 230 CONTROL D8 IN/OUT 229 INPUT/OUTPUT 228 CONTROL D9 IN/OUT 227 INPUT/OUTPUT 226 CONTROL NANDOE IN/OUT 225 INPUT/OUTPUT 224 CONTROL NANDWE IN/OUT 223 INPUT/OUTPUT 222 CONTROL NCS0 IN/OUT 221 INPUT/OUTPUT 220 CONTROL NCS1 219 Associated BSR Cells IN/OUT INPUT/OUTPUT SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 57 Table 10-2. SAM9260 JTAG Boundary Scan Register (Continued) Bit Number Pin Name Pin Type NRD IN/OUT 218 CONTROL 217 INPUT/OUTPUT 216 CONTROL NRST IN/OUT 215 INPUT/OUTPUT 214 CONTROL NWR0 IN/OUT 213 INPUT/OUTPUT 212 CONTROL NWR1 IN/OUT 211 INPUT/OUTPUT 210 CONTROL NWR3 IN/OUT 209 208 INPUT/OUTPUT OSCSEL INPUT PA0 IN/OUT 207 INPUT/OUTPUT 205 CONTROL PA1 IN/OUT 204 INPUT/OUTPUT 203 CONTROL PA10 IN/OUT 202 INPUT/OUTPUT 201 CONTROL PA11 IN/OUT 200 INPUT/OUTPUT 199 CONTROL PA12 IN/OUT 198 INPUT/OUTPUT 197 CONTROL PA13 IN/OUT 196 INPUT/OUTPUT 195 CONTROL PA14 IN/OUT 194 INPUT/OUTPUT 193 CONTROL PA15 IN/OUT 192 INPUT/OUTPUT 191 CONTROL PA16 IN/OUT 190 INPUT/OUTPUT 189 CONTROL PA17 IN/OUT 188 INPUT/OUTPUT 187 CONTROL PA18 IN/OUT 186 INPUT/OUTPUT 185 CONTROL PA19 IN/OUT 184 INPUT/OUTPUT 183 CONTROL PA2 182 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 INPUT CONTROL 206 58 Associated BSR Cells IN/OUT INPUT/OUTPUT Table 10-2. SAM9260 JTAG Boundary Scan Register (Continued) Bit Number Pin Name Pin Type PA20 IN/OUT 181 CONTROL 180 INPUT/OUTPUT 179 CONTROL PA21 IN/OUT 178 INPUT/OUTPUT 177 CONTROL PA22 IN/OUT 176 INPUT/OUTPUT 175 CONTROL PA23 IN/OUT 174 INPUT/OUTPUT 173 CONTROL PA24 IN/OUT 172 INPUT/OUTPUT 171 CONTROL PA25 IN/OUT 170 INPUT/OUTPUT 169 CONTROL PA26 IN/OUT 168 INPUT/OUTPUT 167 CONTROL PA27 IN/OUT 166 INPUT/OUTPUT 165 CONTROL PA28 IN/OUT 164 INPUT/OUTPUT 163 CONTROL PA29 IN/OUT 162 INPUT/OUTPUT 161 CONTROL PA3 IN/OUT 160 INPUT/OUTPUT 159 internal 158 internal 157 internal 156 internal 155 CONTROL PA4 IN/OUT 154 INPUT/OUTPUT 153 CONTROL PA5 IN/OUT 152 INPUT/OUTPUT 151 CONTROL PA6 IN/OUT 150 INPUT/OUTPUT 149 CONTROL PA7 IN/OUT 148 INPUT/OUTPUT 147 CONTROL PA8 146 Associated BSR Cells IN/OUT INPUT/OUTPUT SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 59 Table 10-2. SAM9260 JTAG Boundary Scan Register (Continued) Bit Number Pin Name Pin Type PA9 IN/OUT 145 CONTROL 144 INPUT/OUTPUT 143 CONTROL PB0 IN/OUT 142 INPUT/OUTPUT 141 CONTROL PB1 IN/OUT 140 INPUT/OUTPUT 139 CONTROL PB10 IN/OUT 138 INPUT/OUTPUT 137 CONTROL PB11 IN/OUT 136 INPUT/OUTPUT 135 internal 134 internal 133 internal 132 internal 131 CONTROL PB14 IN/OUT 130 INPUT/OUTPUT 129 CONTROL PB15 IN/OUT 128 INPUT/OUTPUT 127 CONTROL PB16 IN/OUT 126 INPUT/OUTPUT 125 CONTROL PB17 IN/OUT 124 INPUT/OUTPUT 123 CONTROL PB18 IN/OUT 122 INPUT/OUTPUT 121 CONTROL PB19 IN/OUT 120 INPUT/OUTPUT 119 CONTROL PB2 IN/OUT 118 INPUT/OUTPUT 117 CONTROL PB20 IN/OUT 116 INPUT/OUTPUT 115 CONTROL PB21 IN/OUT 114 INPUT/OUTPUT 113 CONTROL PB22 IN/OUT 112 INPUT/OUTPUT 111 CONTROL PB23 110 60 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 Associated BSR Cells IN/OUT INPUT/OUTPUT Table 10-2. SAM9260 JTAG Boundary Scan Register (Continued) Bit Number Pin Name Pin Type PB24 IN/OUT 109 CONTROL 108 INPUT/OUTPUT 107 CONTROL PB25 IN/OUT 106 INPUT/OUTPUT 105 CONTROL PB26 IN/OUT 104 INPUT/OUTPUT 103 CONTROL PB27 IN/OUT 102 INPUT/OUTPUT 101 CONTROL PB28 IN/OUT 100 INPUT/OUTPUT 99 CONTROL PB29 IN/OUT 98 INPUT/OUTPUT 97 CONTROL PB3 IN/OUT 96 INPUT/OUTPUT 95 CONTROL PB30 IN/OUT 94 INPUT/OUTPUT 93 CONTROL PB31 IN/OUT 92 INPUT/OUTPUT 91 CONTROL PB4 IN/OUT 90 INPUT/OUTPUT 89 CONTROL PB5 IN/OUT 88 INPUT/OUTPUT 87 CONTROL PB6 IN/OUT 86 INPUT/OUTPUT 85 CONTROL PB7 IN/OUT 84 INPUT/OUTPUT 83 CONTROL PB8 IN/OUT 82 INPUT/OUTPUT 81 CONTROL PB9 IN/OUT 80 INPUT/OUTPUT 79 CONTROL PC0 IN/OUT 78 INPUT/OUTPUT 77 CONTROL PC1 IN/OUT 76 INPUT/OUTPUT 75 CONTROL PC10 74 Associated BSR Cells IN/OUT INPUT/OUTPUT SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 61 Table 10-2. SAM9260 JTAG Boundary Scan Register (Continued) Bit Number Pin Name Pin Type PC11 IN/OUT 73 CONTROL 72 INPUT/OUTPUT 71 internal 70 internal 69 CONTROL PC13 IN/OUT 68 INPUT/OUTPUT 67 CONTROL PC14 IN/OUT 66 INPUT/OUTPUT 65 CONTROL PC15 IN/OUT 64 INPUT/OUTPUT 63 CONTROL PC16 IN/OUT 62 INPUT/OUTPUT 61 CONTROL PC17 IN/OUT 60 INPUT/OUTPUT 59 CONTROL PC18 IN/OUT 58 INPUT/OUTPUT 57 CONTROL PC19 IN/OUT 56 INPUT/OUTPUT 55 internal 54 internal 53 CONTROL PC20 IN/OUT 52 INPUT/OUTPUT 51 CONTROL PC21 IN/OUT 50 INPUT/OUTPUT 49 CONTROL PC22 IN/OUT 48 INPUT/OUTPUT 47 CONTROL PC23 IN/OUT 46 INPUT/OUTPUT 45 CONTROL PC24 IN/OUT 44 INPUT/OUTPUT 43 CONTROL PC25 IN/OUT 42 INPUT/OUTPUT 41 CONTROL PC26 IN/OUT 40 INPUT/OUTPUT 39 CONTROL PC27 38 62 Associated BSR Cells SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 IN/OUT INPUT/OUTPUT Table 10-2. SAM9260 JTAG Boundary Scan Register (Continued) Bit Number Pin Name Pin Type PC28 IN/OUT 37 CONTROL 36 INPUT/OUTPUT 35 CONTROL PC29 IN/OUT 34 INPUT/OUTPUT 33 internal 32 internal 31 CONTROL PC30 IN/OUT 30 INPUT/OUTPUT 29 CONTROL PC31 IN/OUT 28 INPUT/OUTPUT 27 CONTROL PC4 IN/OUT 26 INPUT/OUTPUT 25 CONTROL PC5 IN/OUT 24 INPUT/OUTPUT 23 CONTROL PC6 IN/OUT 22 INPUT/OUTPUT 21 CONTROL PC7 IN/OUT 20 INPUT/OUTPUT 19 CONTROL PC8 IN/OUT 18 INPUT/OUTPUT 17 CONTROL PC9 IN/OUT 16 INPUT/OUTPUT 15 CONTROL RAS IN/OUT 14 INPUT/OUTPUT 13 CONTROL RTCK OUT 12 OUTPUT 11 CONTROL SDA10 IN/OUT 10 INPUT/OUTPUT 09 CONTROL SDCK IN/OUT 08 INPUT/OUTPUT 07 CONTROL SDCKE IN/OUT 06 INPUT/OUTPUT 05 CONTROL SDWE 04 Associated BSR Cells IN/OUT INPUT/OUTPUT SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 63 Table 10-2. SAM9260 JTAG Boundary Scan Register (Continued) Bit Number Pin Name Pin Type SHDN OUT 03 CONTROL 02 64 Associated BSR Cells OUTPUT 01 TST INPUT INPUT 00 WKUP INPUT INPUT SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 10.6.6 JID Code Register Access: Read-only 31 30 29 28 27 VERSION 23 22 26 25 24 PART NUMBER 21 20 19 18 17 16 10 9 8 PART NUMBER 15 14 13 12 11 PART NUMBER 7 6 MANUFACTURER IDENTITY 5 4 3 2 1 MANUFACTURER IDENTITY 0 1 • VERSION[31:28]: Product Version Number Set to 0x0. • PART NUMBER[27:12]: Product Part Number Product part Number is 0x5B13 • MANUFACTURER IDENTITY[11:1] Set to 0x01F.i Bit[0] required by IEEE Std. 1149.1. Set to 0x1. JTAG ID Code value is 0x05B1_303F. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 65 11. SAM9260 Boot Program 11.1 Description The Boot Program integrates different programs permitting download and/or upload into the different memories of the product. First, it initializes the Debug Unit serial port (DBGU) and the USB Device Port. Then the DataFlash Boot program is executed. It looks for a sequence of eight valid ARM exception vectors in a DataFlash connected to the SPI. All these vectors must be B-branch or LDR load register instructions except for the sixth vector. This vector is used to store the size of the image to download. If a valid sequence is found, code is downloaded into the internal SRAM. This is followed by a remap and a jump to the first address of the SRAM. If no valid ARM vector sequence is found, the DataFlash Boot program is executed on the second chip select. If no valid ARM vector sequence is found, NAND Flash Boot program is then executed. The NAND Flash Boot program looks for a sequence of eight valid ARM exception vectors. If such a sequence is found, code is downloaded into the internal SRAM. This is followed by a remap and a jump to the first address of the SRAM. If no valid ARM vector sequence is found, SAM-BA Monitor is then executed. It waits for transactions either on the USB device, or on the DBGU serial port. 66 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 11.2 Flow Diagram The Boot Program implements the algorithm in Figure 11-1. Figure 11-1. Boot Program Algorithm Flow Diagram Start Internal RC Oscillator Yes Main Oscillator Bypass No No Large Crystal Table Reduced Crystal Table SPI DataFlash Boot Yes Input Frequency Table Yes Download from DataFlash (NPCS0) Run DataFlash Boot Yes Download from DataFlash (NPCS1) Run DataFlash Boot Yes Download from NAND Flash Run NandFlash Boot No SPI DataFlash Boot No NAND Flash Boot No No USB Enumeration Successful ? Yes Run SAM-BA Monitor No Character(s) received on DBGU ? SAM-BA Monitor Yes Run SAM-BA Monitor SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 67 11.3 Device Initialization Initialization follows the steps described below: 1. FIQ Initialization 2. Stack setup for ARM supervisor mode 3. External Clock Detection 4. Switch Master Clock on Main Oscillator 5. C variable initialization 6. Main oscillator frequency detection if no external clock detected 7. PLL setup: PLLB is initialized to generate a 48 MHz clock necessary to use the USB Device. A register located in the Power Management Controller (PMC) determines the frequency of the main oscillator and thus the correct factor for the PLLB. a. If Internal RC Oscillator is used (OSCSEL = 0) and Main Oscillator is active, Table 11-1 defines the crystals supported by the Boot Program when using the internal RC oscillator. Table 11-1. Reduced Crystal Table (MHz) OSCSEL = 0 3.0 6.0 18.432 Other Boot on DBGU Yes Yes Yes Yes Boot on USB Yes Yes Yes No Note: Any other crystal can be used but it prevents using the USB. b. If Internal RC Oscillator is used (OSCSEL = 0) and Main Oscillator is bypassed, Table 11-2 defines the frequencies supported by the Boot Program when bypassing main oscillator. Table 11-2. 1.0 2.0 6.0 12.0 25.0 50.0 Other Boot on DBGU Yes Yes Yes Yes Yes Yes Yes Boot on USB Yes Yes Yes Yes Yes Yes No Note: Any other input frequency can be used but it prevents using the USB. c. Table 11-3. If an external 32.768 kHz Oscillator is used (OSCSEL = 1), Table 11-3 defines the crystals supported by the Boot Program. Large Crystal Table (MHz) OSCSEL = 1 3.0 3.2768 3.6864 3.84 4.0 4.433619 4.9152 5.0 5.24288 6.0 6.144 6.4 6.5536 7.159090 7.3728 7.864320 8.0 9.8304 10.0 11.05920 12.0 12.288 13.56 14.31818 14.7456 16.0 16.367667 17.734470 18.432 20.0 Note: 68 Input Frequencies Supported by Software Auto-detection (MHz) OSCSEL = 0 Booting either on USB or on DBGU is possible with any of these crystals. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 d. Table 11-4. If an external 32.768 kHz Oscillator is used (OSCSEL = 1) and Main Oscillator is bypassed, Table 11-4 defines the crystals supported by the Boot Program. Input Frequencies Supported (OSCSEL = 1) 3.0 3.2768 3.6864 3.84 4.0 4.433619 4.9152 5.0 5.24288 6.0 6.144 6.4 6.5536 7.159090 7.3728 7.864320 8.0 9.8304 10.0 11.05920 12.0 12.288 13.56 14.31818 14.7456 16.0 16.367667 17.734470 18.432 20.0 24 25 28.224 32 33 40.0 48.0 50.0 Note: Booting either on USB or on DBGU is possible with any of these input frequencies. 8. Initialization of the DBGU serial port (115200 baud, 8, N, 1) only if OSCSEL = 1 9. Jump to DataFlash Boot sequence through NPCS0. If DataFlash Boot succeeds, perform a remap and jump to 0x0. 10. Jump to DataFlash Boot sequence through NPCS1. If DataFlash Boot succeeds, perform a remap and jump to 0x0. 11. Jump to NAND Flash Boot sequence. If NAND Flash Boot succeeds, perform a remap and jump to 0x0. 12. Activation of the Instruction Cache 13. Jump to SAM-BA Monitor sequence 14. Disable the WatchDog 15. Initialization of the USB Device Port SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 69 Figure 11-2. Clocks and DBGU Configurations Start No Internal RC Oscillator? (OSCSEL = 0) Scan Large Crystal Table or Input Frequencies Supported (OSCEL =1 Scan Reduced Cystal Table or Inut Frequencies Supported by Software Auto-detection MCK = PLLB/2 UDPCK = PLLB/2 MCK = Mosc UDPCK = PLLB/2 "ROMBoot>" displayed on DBGU DBGU not configured DataFlash Boot ? NANDFlash Boot ? Yes DataFlash Boot ? NANDFlash Boot ? End No End SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 Yes End No No 70 Yes (USB) Autobaudrate ? Yes (DBGU) MCK = Mosc UDPCK = PLLB/2 MCK = PLLB UDPCK = xxxx DBGU not configured DBGU configured End End Figure 11-3. Remap Action after Download Completion 0x0000_0000 0x0000_0000 Internal ROM Internal SRAM REMAP 0x0030_0000 0x0010_0000 Internal SRAM 11.4 Internal ROM DataFlash Boot The DataFlash Boot program searches for a valid application in the SPI DataFlash memory. If a valid application is found, this application is loaded into internal SRAM and executed by branching at address 0x0000_0000 after remap. This application may be the application code or a second-level bootloader. All the calls to functions are PC relative and do not use absolute addresses. 11.4.1 Valid Image Detection The DataFlash Boot software looks for a valid application by analyzing the first 28 bytes corresponding to the ARM exception vectors. These bytes must implement ARM instructions for either branch or load PC with PC relative addressing. The sixth vector, at offset 0x14, contains the size of the image to download. The user must replace this vector with his own vector (see Section 11.4.2 “Structure of ARM Vector 6”). Figure 11-4. LDR Opcode 31 1 28 27 1 Figure 11-5. 1 0 24 23 1 I P U 20 19 0 W 1 16 15 Rn 12 11 Rd 0 Addressing Mode B Opcode 31 1 0 28 27 1 1 0 1 24 23 0 1 0 0 Offset (24 bits) Unconditional instruction: 0xE for bits 31 to 28 Load PC with PC relative addressing instruction: ̶ Rn = Rd = PC = 0xF ̶ I==1 ̶ P==1 ̶ U offset added (U==1) or subtracted (U==0) ̶ W==1 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 71 11.4.2 Structure of ARM Vector 6 The ARM exception vector 6 is used to store information needed by the DataFlash boot program. This information is described below. Figure 11-6. Structure of the ARM Vector 6 31 0 Size of the code to download in bytes 11.4.2.1 Example An example of valid vectors follows: Address Value 00 ea000006 04 eafffffe 08 ea00002f 0c eafffffe 10 eafffffe 14 00001000 18 eafffffe Code B 0x20 B 0x04 B _main B 0x0c B 0x10 Code size = 4096 bytes (less than or equal to 4096 bytes) B 0x18 The size of the image to load into SRAM is contained in the location of the sixth ARM vector. Thus the user must replace this vector by the correct vector for his application. 11.4.3 DataFlash Boot Sequence The DataFlash boot program performs device initialization followed by the download procedure. The DataFlash boot program supports the DataFlash devices listed in Table 11-5. The table summarizes the parameters to include in the ARM vector 6 for all devices. Table 11-5. DataFlash Devices Device Density Page Size (bytes) Number of Pages AT45DB011 1 Mbit 264 512 AT45DB021 2 Mbits 264 1024 AT45DB041 4 Mbits 264 2048 AT45DB081 8 Mbits 264 4096 AT45DB161 16 Mbits 528 4096 AT45DB321 32 Mbits 528 8192 AT45DB642 64 Mbits 1056 8192 The DataFlash has a Status Register that determines all the parameters required to access the device. The DataFlash boot is configured to be compatible with the future design of the DataFlash. 72 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 Figure 11-7. Serial DataFlash Download Start Send status command Is status OK ? No Jump to next boot solution Yes Read the first 7 instructions (28 bytes). Decode the sixth ARM vector 7 vectors (except vector 6) are LDR or Branch instruction No Yes Read the DataFlash into the internal SRAM. (code size to read in vector 6) Restore the reset value for the peripherals. Set the PC to 0 and perform the REMAP to jump to the downloaded application End SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 73 11.5 NAND Flash Boot The NAND Flash Boot program searches for a valid application in the NAND Flash memory. The first block must be guaranteed by the manufacturer. There is no ECC. The NAND Flash Boot program searches for a valid application in the NAND Flash memory. If a valid application is found, this application is loaded into internal SRAM and executed by branching at address 0x0000_0000 after remap. See “DataFlash Boot” on page 71 for more information on Valid Image Detection. Note: It is not necessary to indicate size to download in ARM vector 6 as 4096 bytes are downloaded in every case. 11.5.1 Supported NAND Flash Devices Any 8 or 16-bits NAND Flash Devices from 1 Mbit to 16 Gbit density are supported. Table 11-6. Supported NAND Flash Manufacturers Manufacturer 74 Identifier TOSHIBA 0x98 SAMSUNG 0xEC FUJITSU 0x04 NATIONAL Semiconductor 0x8F RENESAS 0x07 ST Microelectronics 0x20 MICRON 0x2C SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 11.6 SAM-BA Monitor If no valid DataFlash device has been found during the DataFlash boot sequence, the SAM-BA Monitor program is performed. The SAM-BA Monitor principle is to: ̶ Check if USB Device enumeration has occurred. ̶ Check if the AutoBaudrate sequence has succeeded (see Figure 11-8) ̶ Figure 11-8. Check if characters have been received on the DBGU if MCK is configured to 48 MHz (OSCSEL = 1). AutoBaudrate Flow Diagram Device Setup Character '0x80' received ? No 1st measurement Yes Character '0x80' received ? No 2nd measurement No Test Communication Yes Character '#' received ? Yes Send Character '>' UART operational Run SAM-BA Monitor Once the communication interface is identified, the application runs in an infinite loop waiting for different commands as listed in Table 11-7 on page 76. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 75 11.6.1 Command List Table 11-7. Command Action Argument(s) Example N set Normal mode No argument N# T set Terminal mode No argument T# O write a byte Address, Value# O200001,CA# o read a byte Address,# o200001,# H write a half word Address, Value# H200002,CAFE# h read a half word Address,# h200002,# W write a word Address, Value# W200000,CAFEDECA# w read a word Address,# w200000,# S send a file Address,# S200000,# R receive a file Address, NbOfBytes# R200000,1234# G go Address# G200200# V display version No argument V#  Mode commands: ̶ Normal mode configures SAM-BA Monitor to send / receive data in binary format, ̶  ̶ ̶   ̶ Address: Address in hexadecimal ̶ Output: The byte, halfword or word read in hexadecimal following by ‘>’ Send a file (S): Send a file to a specified address ̶ Address: Address in hexadecimal ̶ Output: ‘>’. There is a time-out on this command which is reached when the prompt ‘>’ appears before the end of the command execution. Receive a file (R): Receive data into a file from a specified address ̶ ̶  Value: Byte, halfword or word to write in hexadecimal. Output: ‘>’. ̶  Address: Address in hexadecimal. Read commands: Read a byte (o), a halfword (h) or a word (w) from the target. Note:  Terminal mode configures SAM-BA Monitor to send / receive data in ascii format. Write commands: Write a byte (O), a halfword (H) or a word (W) to the target. ̶ Address: Address in hexadecimal NbOfBytes: Number of bytes in hexadecimal to receive Output: ‘>’ Go (G): Jump to a specified address and execute the code ̶ Address: Address to jump in hexadecimal ̶ Output: ‘>’ Get Version (V): Return the SAM-BA Monitor version ̶ 76 Commands Available through the SAM-BA Monitor Output: ROM code version, date and time (example: v1.7 Jul 13 2007 14:54:32), followed by the prompt ‘>’ SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 11.6.2 DBGU Serial Port Communication is performed through the DBGU serial port initialized to 115200 baud, 8, n, 1. 11.6.3 Xmodem Protocol The Send and Receive File commands use the Xmodem protocol to communicate. Any terminal performing this protocol can be used to send the application file to the target. The size of the binary file to send depends on the SRAM size embedded in the product. In all cases, the size of the binary file must be lower than the SRAM size because the Xmodem protocol requires some SRAM memory to work. The Xmodem protocol supported is the 128-byte length block. This protocol uses a two-character CRC-16 to guarantee detection of a maximum bit error. Xmodem protocol with CRC is accurate provided both sender and receiver report successful transmission. Each block of the transfer looks like: in which: ̶ = 01 hex ̶ = binary number, starts at 01, increments by 1, and wraps 0FFH to 00H (not to 01) ̶ = 1’s complement of the blk#. ̶ = 2 bytes CRC16 Figure 11-9 shows a transmission using this protocol. Figure 11-9. Xmodem Transfer Example Host Device C SOH 01 FE Data[128] CRC CRC ACK SOH 02 FD Data[128] CRC CRC ACK SOH 03 FC Data[100] CRC CRC ACK EOT ACK 11.6.4 USB Device Port A 48 MHz USB clock is necessary to use the USB Device port. It has been programmed earlier in the device initialization procedure with PLLB configuration. The device uses the USB communication device class (CDC) drivers to take advantage of the installed PC RS-232 software to talk over the USB. The CDC class is implemented in all releases of Windows ® , beginning with Windows 98SE. The CDC document, available at www.usb.org, describes a way to implement devices such as ISDN modems and virtual COM ports. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 77 The Vendor ID is Atmel’s vendor ID 0x03EB. The product ID is 0x6124. These references are used by the host operating system to mount the correct driver. On Windows systems, the INF files contain the correspondence between vendor ID and product ID. Atmel provides an INF example to see the device as a new serial port and also provides another custom driver used by the SAM-BA application: atm6124.sys. Refer to the document USB Basic Application, literature number 6123, for more details. 11.6.4.1 Enumeration Process The USB protocol is a master/slave protocol. This is the host that starts the enumeration sending requests to the device through the control endpoint. The device handles standard requests as defined in the USB Specification. Table 11-8. Handled Standard Requests Request Definition GET_DESCRIPTOR Returns the current device configuration value. SET_ADDRESS Sets the device address for all future device access. SET_CONFIGURATION Sets the device configuration. GET_CONFIGURATION Returns the current device configuration value. GET_STATUS Returns status for the specified recipient. SET_FEATURE Used to set or enable a specific feature. CLEAR_FEATURE Used to clear or disable a specific feature. The device also handles some class requests defined in the CDC class. Table 11-9. Handled Class Requests Request Definition SET_LINE_CODING Configures DTE rate, stop bits, parity and number of character bits. GET_LINE_CODING Requests current DTE rate, stop bits, parity and number of character bits. SET_CONTROL_LINE_STATE RS-232 signal used to tell the DCE device the DTE device is now present. Unhandled requests are STALLed. 11.6.4.2 Communication Endpoints There are two communication endpoints and endpoint 0 is used for the enumeration process. Endpoint 1 is a 64byte Bulk OUT endpoint and endpoint 2 is a 64-byte Bulk IN endpoint. SAM-BA Monitor commands are sent by the host through the endpoint 1. If required, the message is split by the host into several data payloads by the host driver. If the command requires a response, the host can send IN transactions to pick up the response. 78 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 11.7 Hardware and Software Constraints  The SAM-BA Monitor can use two blocks of internal SRAM. The first block is available for user code. Its size is 4 Kbytes. The second block is used for variables and stacks. Table 11-10. User Area Address Start Address End Address Size (bytes) 0x200000 0x201000 4096  The DataFlash and NAND Flash downloaded code size must be inferior to 4096 bytes.  The code is always downloaded from the device address 0x0000_0000 to the address 0x0000_0000 of the internal SRAM (after remap).  The downloaded code must be position-independent or linked at address 0x0000_0000.  The DataFlash must be connected to NPCS0 and/or NPCS1 of the SPI.  USB requirements: ̶ Crystal or Input Frequencies supported by Software Auto-detection. See Table 11-1, Table 11-2 and Table 11-3 on page 68 for more information. The SPI and NAND Flash drivers use several PIOs in alternate functions to communicate with devices. Care must be taken when these PIOs are used by the application. The devices connected could be unintentionally driven at boot time, and electrical conflicts between SPI output pins and the connected devices may appear. To assure correct functionality, it is recommended to plug in critical devices to other pins. Table 11-11 contains a list of pins that are driven during the boot program execution. These pins are driven during the boot sequence for a period of less than 1 second if no correct boot program is found. For the DataFlash driven by the SPCK signal at 1 MHz, the time to download 4096 bytes is reduced to 200 ms. Before performing the jump to the application in internal SRAM, all the PIOs and peripherals used in the boot program are set to their reset state. Table 11-11. 11.8 Pins Driven During Boot Program Execution Peripheral Pin PIO Line SPI0 MOSI PIOA1 SPI0 MISO PIOA0 SPI0 SPCK PIOA2 SPI0 NPCS0 PIOA3 SPI0 NPCS1 PIOC11 PIOC NANDCS PIOC14 DBGU DRXD PIOB14 DBGU DTXD PIOB15 ROM Code Change Log Here are the evolutions between ROM Code V1.4 and V1.7:  User Reset is no longer enabled  NAND Flash Ready/Busy pin (PIOC 13) is no longer used  There are no more Timeouts in the NAND Flash Boot sequence Note: To know which ROM Code version is in the chip, use the SAM-BA Monitor command “V#” (see Table 11-8 on page 78). SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 79 12. Reset Controller (RSTC) 12.1 Description The Reset Controller (RSTC), based on power-on reset cells, handles all the resets of the system without any external components. It reports which reset occurred last. The Reset Controller also drives independently or simultaneously the external reset and the peripheral and processor resets. 12.2 Embedded Characteristics  Based on two Power-On Reset cells  Status of the last reset ̶ One on VDDBU and one on VDDCORE ̶  Either general reset (VDDBU rising), wake-up reset (VDDCORE rising), software reset, user reset or watchdog reset Controls the internal resets and the NRST pin output ̶ 12.3 Allows shaping a reset signal for the external devices Block Diagram Figure 12-1. Reset Controller Block Diagram Reset Controller Main Supply POR Backup Supply POR rstc_irq Startup Counter Reset State Manager proc_nreset user_reset NRST nrst_out NRST Manager periph_nreset exter_nreset backup_neset WDRPROC wd_fault SLCK 80 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 12.4 Functional Description 12.4.1 Reset Controller Overview The Reset Controller is made up of an NRST Manager, a Startup Counter and a Reset State Manager. It runs at Slow Clock and generates the following reset signals:  proc_nreset: Processor reset line. It also resets the Watchdog Timer.  backup_nreset: Affects all the peripherals powered by VDDBU.  periph_nreset: Affects the whole set of embedded peripherals.  nrst_out: Drives the NRST pin. These reset signals are asserted by the Reset Controller, either on external events or on software action. The Reset State Manager controls the generation of reset signals and provides a signal to the NRST Manager when an assertion of the NRST pin is required. The NRST Manager shapes the NRST assertion during a programmable time, thus controlling external device resets. The startup counter waits for the complete crystal oscillator startup. The wait delay is given by the crystal oscillator startup time maximum value that can be found in the section Crystal Oscillator Characteristics in the Electrical Characteristics section of the product documentation. The Reset Controller Mode Register (RSTC_MR), allowing the configuration of the Reset Controller, is powered with VDDBU, so that its configuration is saved as long as VDDBU is on. 12.4.2 NRST Manager The NRST Manager samples the NRST input pin and drives this pin low when required by the Reset State Manager. Figure 12-2 shows the block diagram of the NRST Manager. Figure 12-2. NRST Manager RSTC_MR URSTIEN RSTC_SR URSTS NRSTL rstc_irq RSTC_MR URSTEN Other interrupt sources user_reset NRST RSTC_MR ERSTL nrst_out External Reset Timer exter_nreset 12.4.2.1 NRST Signal or Interrupt The NRST Manager samples the NRST pin at Slow Clock speed. When the line is detected low, a User Reset is reported to the Reset State Manager. However, the NRST Manager can be programmed to not trigger a reset when an assertion of NRST occurs. Writing the bit URSTEN at 0 in RSTC_MR disables the User Reset trigger. The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in RSTC_SR. As soon as the pin NRST is asserted, the bit URSTS in RSTC_SR is set. This bit clears only when RSTC_SR is read. The Reset Controller can also be programmed to generate an interrupt instead of generating a reset. To do so, the bit URSTIEN in RSTC_MR must be written at 1. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 81 12.4.2.2 NRST External Reset Control The Reset State Manager asserts the signal ext_nreset to assert the NRST pin. When this occurs, the “nrst_out” signal is driven low by the NRST Manager for a time programmed by the field ERSTL in RSTC_MR. This assertion duration, named EXTERNAL_RESET_LENGTH, lasts 2(ERSTL+1) Slow Clock cycles. This gives the approximate duration of an assertion between 60 µs and 2 seconds. Note that ERSTL at 0 defines a two-cycle duration for the NRST pulse. This feature allows the Reset Controller to shape the NRST pin level, and thus to guarantee that the NRST line is driven low for a time compliant with potential external devices connected on the system reset. As the field is within RSTC_MR, which is backed-up, this field can be used to shape the system power-up reset for devices requiring a longer startup time than the Slow Clock Oscillator. 12.4.3 BMS Sampling The product matrix manages a boot memory that depends on the level on the BMS pin at reset. The BMS signal is sampled three slow clock cycles after the Core Power-On Reset output rising edge. Figure 12-3. BMS Sampling SLCK Core Supply POR output BMS Signal XXX H or L BMS sampling delay = 3 cycles proc_nreset 12.4.4 Reset States The Reset State Manager handles the different reset sources and generates the internal reset signals. It reports the reset status in the field RSTTYP of the Status Register (RSTC_SR). The update of the field RSTTYP is performed when the processor reset is released. 82 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 12.4.4.1 General Reset A general reset occurs when VDDBU and VDDCORE are powered on. The backup supply POR cell output rises and is filtered with a Startup Counter, which operates at Slow Clock. The purpose of this counter is to make sure the Slow Clock oscillator is stable before starting up the device. The length of startup time is hardcoded to comply with the Slow Clock Oscillator startup time. After this time, the processor clock is released at Slow Clock and all the other signals remain valid for three cycles for proper processor and logic reset. Then, all the reset signals are released and the field RSTTYP in RSTC_SR reports a General Reset. As the RSTC_MR is reset, the NRST line rises two cycles after the backup_nreset, as ERSTL defaults at value 0x0. When VDDBU is detected low by the Backup Supply POR Cell, all resets signals are immediately asserted, even if the Main Supply POR Cell does not report a Main Supply shutdown. VDDBU only activates the backup_nreset signal. The backup_nreset must be released so that any other reset can be generated by VDDCORE (Main Supply POR output). Figure 12-4 shows how the General Reset affects the reset signals. Figure 12-4. General Reset State SLCK Any Freq. MCK Backup Supply POR output Startup Time Main Supply POR output backup_nreset Processor Startup = 3 cycles proc_nreset RSTTYP XXX 0x0 = General Reset XXX periph_nreset NRST (nrst_out) BMS Sampling EXTERNAL_RESET_LENGTH = 2 cycles SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 83 12.4.4.2 Wake-up Reset The Wake-up Reset occurs when the Main Supply is down. When the Main Supply POR output is active, all the reset signals are asserted except backup_nreset. When the Main Supply powers up, the POR output is resynchronized on Slow Clock. The processor clock is then re-enabled during three Slow Clock cycles, depending on the requirements of the ARM processor. At the end of this delay, the processor and other reset signals rise. The field RSTTYP in RSTC_SR is updated to report a Wake-up Reset. The “nrst_out” remains asserted for EXTERNAL_RESET_LENGTH cycles. As RSTC_MR is backed-up, the programmed number of cycles is applicable. When the Main Supply is detected falling, the reset signals are immediately asserted. This transition is synchronous with the output of the Main Supply POR. Figure 12-5. Wake-up State SLCK Any Freq. MCK Main Supply POR output backup_nreset Resynch. 2 cycles proc_nreset RSTTYP Processor Startup = 3 cycles XXX periph_nreset NRST (nrst_out) EXTERNAL_RESET_LENGTH = 4 cycles (ERSTL = 1) 84 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 0x1 = WakeUp Reset XXX 12.4.4.3 User Reset The User Reset is entered when a low level is detected on the NRST pin and the bit URSTEN in RSTC_MR is at 1. The NRST input signal is resynchronized with SLCK to insure proper behavior of the system. The User Reset is entered as soon as a low level is detected on NRST. The Processor Reset and the Peripheral Reset are asserted. The User Reset is left when NRST rises, after a two-cycle resynchronization time and a three-cycle processor startup. The processor clock is re-enabled as soon as NRST is confirmed high. When the processor reset signal is released, the RSTTYP field of the Status Register (RSTC_SR) is loaded with the value 0x4, indicating a User Reset. The NRST Manager guarantees that the NRST line is asserted for EXTERNAL_RESET_LENGTH Slow Clock cycles, as programmed in the field ERSTL. However, if NRST does not rise after EXTERNAL_RESET_LENGTH because it is driven low externally, the internal reset lines remain asserted until NRST actually rises. Figure 12-6. User Reset State SLCK MCK Any Freq. NRST Resynch. 2 cycles Resynch. 2 cycles Processor Startup = 3 cycles proc_nreset RSTTYP Any XXX 0x4 = User Reset periph_nreset NRST (nrst_out) >= EXTERNAL_RESET_LENGTH SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 85 12.4.4.4 Software Reset The Reset Controller offers several commands used to assert the different reset signals. These commands are performed by writing the Control Register (RSTC_CR) with the following bits at 1:  PROCRST: Writing PROCRST at 1 resets the processor and the watchdog timer.  PERRST: Writing PERRST at 1 resets all the embedded peripherals, including the memory system, and, in particular, the Remap Command. The Peripheral Reset is generally used for debug purposes.  EXTRST: Writing EXTRST at 1 asserts low the NRST pin during a time defined by the field ERSTL in the Mode Register (RSTC_MR). The software reset is entered if at least one of these bits is set by the software. All these commands can be performed independently or simultaneously. The software reset lasts three Slow Clock cycles. The internal reset signals are asserted as soon as the register write is performed. This is detected on the Master Clock (MCK). They are released when the software reset is left, i.e., synchronously to SLCK. If EXTRST is set, the nrst_out signal is asserted depending on the programming of the field ERSTL. However, the resulting falling edge on NRST does not lead to a User Reset. If and only if the PROCRST bit is set, the Reset Controller reports the software status in the field RSTTYP of the Status Register (RSTC_SR). Other Software Resets are not reported in RSTTYP. As soon as a software operation is detected, the bit SRCMP (Software Reset Command in Progress) is set in the Status Register (RSTC_SR). It is cleared as soon as the software reset is left. No other software reset can be performed while the SRCMP bit is set, and writing any value in RSTC_CR has no effect. Figure 12-7. Software Reset SLCK MCK Any Freq. Write RSTC_CR Resynch. 1 cycle Processor Startup = 3 cycles proc_nreset if PROCRST=1 RSTTYP Any XXX 0x3 = Software Reset periph_nreset if PERRST=1 NRST (nrst_out) if EXTRST=1 EXTERNAL_RESET_LENGTH 8 cycles (ERSTL=2) SRCMP in RSTC_SR 86 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 12.4.4.5 Watchdog Reset The Watchdog Reset is entered when a watchdog fault occurs. This state lasts three Slow Clock cycles. When in Watchdog Reset, assertion of the reset signals depends on the WDRPROC bit in WDT_MR:  If WDRPROC is 0, the Processor Reset and the Peripheral Reset are asserted. The NRST line is also asserted, depending on the programming of the field ERSTL. However, the resulting low level on NRST does not result in a User Reset state.  If WDRPROC = 1, only the processor reset is asserted. The Watchdog Timer is reset by the proc_nreset signal. As the watchdog fault always causes a processor reset if WDRSTEN is set, the Watchdog Timer is always reset after a Watchdog Reset, and the Watchdog is enabled by default and with a period set to a maximum. When the WDRSTEN in WDT_MR bit is reset, the watchdog fault has no impact on the reset controller. Figure 12-8. Watchdog Reset SLCK MCK Any Freq. wd_fault Processor Startup = 3 cycles proc_nreset RSTTYP Any XXX 0x2 = Watchdog Reset periph_nreset Only if WDRPROC = 0 NRST (nrst_out) EXTERNAL_RESET_LENGTH 8 cycles (ERSTL=2) SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 87 12.4.5 Reset State Priorities The Reset State Manager manages the following priorities between the different reset sources, given in descending order:  Backup Reset  Wake-up Reset  Watchdog Reset  Software Reset  User Reset Particular cases are listed below:  When in User Reset: ̶ ̶ A watchdog event is impossible because the Watchdog Timer is being reset by the proc_nreset signal.   88 A software reset is impossible, since the processor reset is being activated. When in Software Reset: ̶ A watchdog event has priority over the current state. ̶ The NRST has no effect. When in Watchdog Reset: ̶ The processor reset is active and so a Software Reset cannot be programmed. ̶ A User Reset cannot be entered. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 12.4.6 Reset Controller Status Register The Reset Controller Status Register (RSTC_SR) provides several status fields:  RSTTYP field: This field gives the type of the last reset, as explained in previous sections.  SRCMP bit: This field indicates that a Software Reset Command is in progress and that no further software reset should be performed until the end of the current one. This bit is automatically cleared at the end of the current software reset.  NRSTL bit: The NRSTL bit of the Status Register gives the level of the NRST pin sampled on each MCK rising edge.  URSTS bit: A high-to-low transition of the NRST pin sets the URSTS bit of the RSTC_SR. This transition is also detected on the Master Clock (MCK) rising edge (see Figure 12-9). If the User Reset is disabled (URSTEN = 0) and if the interruption is enabled by the URSTIEN bit in the RSTC_MR, the URSTS bit triggers an interrupt. Reading the RSTC_SR resets the URSTS bit and clears the interrupt. Figure 12-9. Reset Controller Status and Interrupt MCK read RSTC_SR Peripheral Access 2 cycle resynchronization 2 cycle resynchronization NRST NRSTL URSTS rstc_irq if (URSTEN = 0) and (URSTIEN = 1) SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 89 12.5 Reset Controller (RSTC) User Interface Table 12-1. Register Mapping Offset Register Name 0x00 Control Register 0x04 0x08 Note: 90 Access Reset Back-up Reset RSTC_CR Write-only - Status Register RSTC_SR Read-only 0x0000_0001 0x0000_0000 Mode Register RSTC_MR Read/Write - 0x0000_0000 1. The reset value of RSTC_SR either reports a General Reset or a Wake-up Reset depending on last rising power supply. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 12.5.1 Reset Controller Control Register Name: RSTC_CR Access: Write-only 31 30 29 28 27 26 25 24 KEY 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 8 – 7 – 6 – 5 – 4 – 3 EXTRST 2 PERRST 1 – 0 PROCRST • PROCRST: Processor Reset 0: No effect. 1: If KEY is correct, resets the processor. • PERRST: Peripheral Reset 0: No effect. 1: If KEY is correct, resets the peripherals. • EXTRST: External Reset 0: No effect. 1: If KEY is correct, asserts the NRST pin. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 91 12.5.2 Reset Controller Status Register Name: RSTC_SR Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 SRCMP 16 NRSTL 15 – 14 – 13 – 12 – 11 – 10 9 RSTTYP 8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 URSTS • URSTS: User Reset Status 0: No high-to-low edge on NRST happened since the last read of RSTC_SR. 1: At least one high-to-low transition of NRST has been detected since the last read of RSTC_SR. • RSTTYP: Reset Type Reports the cause of the last processor reset. Reading this RSTC_SR does not reset this field. RSTTYP Reset Type Comments 0 0 0 General Reset Both VDDCORE and VDDBU rising 0 0 1 Wake Up Reset VDDCORE rising 0 1 0 Watchdog Reset Watchdog fault occurred 0 1 1 Software Reset Processor reset required by the software 1 0 0 User Reset NRST pin detected low • NRSTL: NRST Pin Level Registers the NRST Pin Level at Master Clock (MCK). • SRCMP: Software Reset Command in Progress 0: No software command is being performed by the reset controller. The reset controller is ready for a software command. 1: A software reset command is being performed by the reset controller. The reset controller is busy. 92 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 12.5.3 Reset Controller Mode Register Name: RSTC_MR Access: Read/Write 31 30 29 28 27 26 25 24 17 – 16 – 9 8 1 – 0 URSTEN KEY 23 – 22 – 21 – 20 – 19 – 18 – 15 – 14 – 13 – 12 – 11 10 7 – 6 – 5 4 URSTIEN 3 – ERSTL 2 – • URSTEN: User Reset Enable 0: The detection of a low level on the pin NRST does not generate a User Reset. 1: The detection of a low level on the pin NRST triggers a User Reset. • URSTIEN: User Reset Interrupt Enable 0: USRTS bit in RSTC_SR at 1 has no effect on rstc_irq. 1: USRTS bit in RSTC_SR at 1 asserts rstc_irq if URSTEN = 0. • ERSTL: External Reset Length This field defines the external reset length. The external reset is asserted during a time of 2(ERSTL+1) Slow Clock cycles. This allows assertion duration to be programmed between 60 µs and 2 seconds. • KEY: Password Should be written at value 0xA5. Writing any other value in this field aborts the write operation. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 93 13. Real-time Timer (RTT) 13.1 Description The Real-time Timer is built around a 32-bit counter and used to count elapsed seconds. It generates a periodic interrupt and/or triggers an alarm on a programmed value. 13.2 13.3 Embedded Characteristics ̶ Real-time Timer 32-bit free-running back-up Counter ̶ Integrates a 16-bit programmable prescaler running on slow clock ̶ Alarm Register capable of generating a wake-up of the system through the Shutdown Controller Block Diagram Figure 13-1. Real-time Timer RTT_MR RTTRST RTT_MR RTPRES RTT_MR SLCK RTTINCIEN reload 16-bit Divider set 0 RTT_MR RTTRST RTT_SR 1 RTTINC reset 0 rtt_int 32-bit Counter read RTT_SR RTT_MR ALMIEN RTT_VR reset CRTV RTT_SR ALMS set = RTT_AR 94 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 ALMV rtt_alarm 13.4 Functional Description The Real-time Timer is used to count elapsed seconds. It is built around a 32-bit counter fed by Slow Clock divided by a programmable 16-bit value. The value can be programmed in the field RTPRES of the Real-time Mode Register (RTT_MR). Programming RTPRES at 0x00008000 corresponds to feeding the real-time counter with a 1 Hz signal (if the Slow Clock is 32.768 kHz). The 32-bit counter can count up to 232 seconds, corresponding to more than 136 years, then roll over to 0. The Real-time Timer can also be used as a free-running timer with a lower time-base. The best accuracy is achieved by writing RTPRES to 3. Programming RTPRES to 1 or 2 is possible, but may result in losing status events because the status register is cleared two Slow Clock cycles after read. Thus if the RTT is configured to trigger an interrupt, the interrupt occurs during 2 Slow Clock cycles after reading RTT_SR. To prevent several executions of the interrupt handler, the interrupt must be disabled in the interrupt handler and re-enabled when the status register is clear. The Real-time Timer value (CRTV) can be read at any time in the register RTT_VR (Real-time Value Register). As this value can be updated asynchronously from the Master Clock, it is advisable to read this register twice at the same value to improve accuracy of the returned value. The current value of the counter is compared with the value written in the alarm register RTT_AR (Real-time Alarm Register). If the counter value matches the alarm, the bit ALMS in RTT_SR is set. The alarm register is set to its maximum value, corresponding to 0xFFFF_FFFF, after a reset. The bit RTTINC in RTT_SR is set each time the Real-time Timer counter is incremented. This bit can be used to start a periodic interrupt, the period being one second when the RTPRES is programmed with 0x8000 and Slow Clock equal to 32.768 kHz. Reading the RTT_SR status register resets the RTTINC and ALMS fields. Writing the bit RTTRST in RTT_MR immediately reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. Note: Because of the asynchronism between the Slow Clock (SCLK) and the System Clock (MCK): 1) The restart of the counter and the reset of the RTT_VR current value register is effective only 2 slow clock cycles after the write of the RTTRST bit in the RTT_MR. 2) The status register flags reset is taken into account only 2 slow clock cycles after the read of the RTT_SR (Status Register). SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 95 Figure 13-2. RTT Counting APB cycle APB cycle MCK RTPRES - 1 Prescaler 0 RTT 0 ... ALMV-1 ALMV ALMV+1 RTTINC (RTT_SR) ALMS (RTT_SR) APB Interface read RTT_SR 96 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 ALMV+2 ALMV+3 13.5 Real-time Timer (RTT) User Interface Table 13-1. Register Mapping Offset Register Name Access Reset 0x00 Mode Register RTT_MR Read/Write 0x0000_8000 0x04 Alarm Register RTT_AR Read/Write 0xFFFF_FFFF 0x08 Value Register RTT_VR Read-only 0x0000_0000 0x0C Status Register RTT_SR Read-only 0x0000_0000 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 97 13.5.1 Real-time Timer Mode Register Name: RTT_MR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 RTTRST 17 RTTINCIEN 16 ALMIEN 15 14 13 12 11 10 9 8 3 2 1 0 RTPRES 7 6 5 4 RTPRES • RTPRES: Real-time Timer Prescaler Value Defines the number of SLCK periods required to increment the Real-time timer. RTPRES is defined as follows: RTPRES = 0: The prescaler period is equal to 216. RTPRES ≠ 0: The prescaler period is equal to RTPRES. • ALMIEN: Alarm Interrupt Enable 0: The bit ALMS in RTT_SR has no effect on interrupt. 1: The bit ALMS in RTT_SR asserts interrupt. • RTTINCIEN: Real-time Timer Increment Interrupt Enable 0: The bit RTTINC in RTT_SR has no effect on interrupt. 1: The bit RTTINC in RTT_SR asserts interrupt. • RTTRST: Real-time Timer Restart 1: Reloads and restarts the clock divider with the new programmed value. This also resets the 32-bit counter. 98 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 13.5.2 Real-time Timer Alarm Register Name: RTT_AR Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 ALMV 23 22 21 20 ALMV 15 14 13 12 ALMV 7 6 5 4 ALMV • ALMV: Alarm Value Defines the alarm value (ALMV + 1) compared with the Real-time Timer. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 99 13.5.3 Real-time Timer Value Register Name: RTT_VR Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 CRTV 23 22 21 20 CRTV 15 14 13 12 CRTV 7 6 5 4 CRTV • CRTV: Current Real-time Value Returns the current value of the Real-time Timer. 100 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 13.5.4 Real-time Timer Status Register Name: RTT_SR Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 RTTINC 0 ALMS • ALMS: Real-time Alarm Status 0: The Real-time Alarm has not occurred since the last read of RTT_SR. 1: The Real-time Alarm occurred since the last read of RTT_SR. • RTTINC: Real-time Timer Increment 0: The Real-time Timer has not been incremented since the last read of the RTT_SR. 1: The Real-time Timer has been incremented since the last read of the RTT_SR. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 101 14. Periodic Interval Timer (PIT) 14.1 Description The Periodic Interval Timer (PIT) provides the operating system’s scheduler interrupt. It is designed to offer maximum accuracy and efficient management, even for systems with long response time. 14.2 14.3 Embedded Characteristics  Includes a 20-bit Periodic Counter, with less than 1 µs accuracy  Includes a 12-bit Interval Overlay Counter  Real Time OS or Linux®/Windows CE® compliant tick generator Block Diagram Figure 14-1. Periodic Interval Timer PIT_MR PIV =? PIT_MR PITIEN set 0 PIT_SR PITS reset 0 MCK Prescaler 102 0 0 1 12-bit Adder 1 20-bit Counter MCK/16 CPIV PIT_PIVR CPIV PIT_PIIR SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 PICNT PICNT read PIT_PIVR pit_irq 14.4 Functional Description The Periodic Interval Timer aims at providing periodic interrupts for use by operating systems. The PIT provides a programmable overflow counter and a reset-on-read feature. It is built around two counters: a 20-bit CPIV counter and a 12-bit PICNT counter. Both counters work at Master Clock /16. The first 20-bit CPIV counter increments from 0 up to a programmable overflow value set in the field PIV of the Mode Register (PIT_MR). When the counter CPIV reaches this value, it resets to 0 and increments the Periodic Interval Counter, PICNT. The status bit PITS in the Status Register (PIT_SR) rises and triggers an interrupt, provided the interrupt is enabled (PITIEN in PIT_MR). Writing a new PIV value in PIT_MR does not reset/restart the counters. When CPIV and PICNT values are obtained by reading the Periodic Interval Value Register (PIT_PIVR), the overflow counter (PICNT) is reset and the PITS is cleared, thus acknowledging the interrupt. The value of PICNT gives the number of periodic intervals elapsed since the last read of PIT_PIVR. When CPIV and PICNT values are obtained by reading the Periodic Interval Image Register (PIT_PIIR), there is no effect on the counters CPIV and PICNT, nor on the bit PITS. For example, a profiler can read PIT_PIIR without clearing any pending interrupt, whereas a timer interrupt clears the interrupt by reading PIT_PIVR. The PIT may be enabled/disabled using the PITEN bit in the PIT_MR (disabled on reset). The PITEN bit only becomes effective when the CPIV value is 0. Figure 14-2 illustrates the PIT counting. After the PIT Enable bit is reset (PITEN = 0), the CPIV goes on counting until the PIV value is reached, and is then reset. PIT restarts counting, only if the PITEN is set again. The PIT is stopped when the core enters debug state. Figure 14-2. Enabling/Disabling PIT with PITEN APB cycle APB cycle MCK 15 restarts MCK Prescaler MCK Prescaler 0 PITEN CPIV PICNT 0 1 PIV - 1 0 PIV 1 0 1 0 PITS (PIT_SR) APB Interface read PIT_PIVR SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 103 14.5 Periodic Interval Timer (PIT) User Interface Table 14-1. Register Mapping Offset Register Name Access Reset 0x00 Mode Register PIT_MR Read/Write 0x000F_FFFF 0x04 Status Register PIT_SR Read-only 0x0000_0000 0x08 Periodic Interval Value Register PIT_PIVR Read-only 0x0000_0000 0x0C Periodic Interval Image Register PIT_PIIR Read-only 0x0000_0000 104 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 14.5.1 Periodic Interval Timer Mode Register Name: PIT_MR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 23 – 22 – 21 – 20 – 19 18 15 14 13 12 25 PITIEN 24 PITEN 17 16 PIV 11 10 9 8 3 2 1 0 PIV 7 6 5 4 PIV • PIV: Periodic Interval Value Defines the value compared with the primary 20-bit counter of the Periodic Interval Timer (CPIV). The period is equal to (PIV + 1). • PITEN: Period Interval Timer Enabled 0: The Periodic Interval Timer is disabled when the PIV value is reached. 1: The Periodic Interval Timer is enabled. • PITIEN: Periodic Interval Timer Interrupt Enable 0: The bit PITS in PIT_SR has no effect on interrupt. 1: The bit PITS in PIT_SR asserts interrupt. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 105 14.5.2 Periodic Interval Timer Status Register Name: PIT_SR Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 PITS • PITS: Periodic Interval Timer Status 0: The Periodic Interval timer has not reached PIV since the last read of PIT_PIVR. 1: The Periodic Interval timer has reached PIV since the last read of PIT_PIVR. 106 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 14.5.3 Periodic Interval Timer Value Register Name: PIT_PIVR Access: Read-only 31 30 29 28 27 26 19 18 25 24 17 16 PICNT 23 22 21 20 PICNT 15 14 CPIV 13 12 11 10 9 8 3 2 1 0 CPIV 7 6 5 4 CPIV Reading this register clears PITS in PIT_SR. • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 107 14.5.4 Periodic Interval Timer Image Register Name: PIT_PIIR Access: Read-only 31 30 29 28 27 26 19 18 25 24 17 16 PICNT 23 22 21 20 PICNT 15 14 CPIV 13 12 11 10 9 8 3 2 1 0 CPIV 7 6 5 4 CPIV • CPIV: Current Periodic Interval Value Returns the current value of the periodic interval timer. • PICNT: Periodic Interval Counter Returns the number of occurrences of periodic intervals since the last read of PIT_PIVR. 108 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 15. Watchdog Timer (WDT) 15.1 Description The Watchdog Timer can be used to prevent system lock-up if the software becomes trapped in a deadlock. It features a 12-bit down counter that allows a watchdog period of up to 16 seconds (slow clock at 32.768 kHz). It can generate a general reset or a processor reset only. In addition, it can be stopped while the processor is in debug mode or idle mode. 15.2 15.3 Embedded Characteristics  16-bit key-protected only-once-Programmable Counter  Windowed, prevents the processor being in a dead-lock on the watchdog access Block Diagram Figure 15-1. Watchdog Timer Block Diagram write WDT_MR WDT_MR WDV WDT_CR WDRSTT reload 1 0 12-bit Down Counter WDT_MR WDD reload Current Value 1/128 SLCK bit MREAD = 0 Load Transmit register TWI_THR = Data to send Read Status register No TXRDY = 1? Yes Read Status register No TXCOMP = 1? Yes Transfer finished SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 411 Figure 29-15. TWI Write Operation with Single Data Byte and Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address (DADR) - Internal address size (IADRSZ) - Transfer direction bit Write ==> bit MREAD = 0 Set the internal address TWI_IADR = address Load transmit register TWI_THR = Data to send Read Status register No TXRDY = 1? Yes Read Status register TXCOMP = 1? No Yes Transfer finished 412 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 Figure 29-16. TWI Write Operation with Multiple Data Bytes with or without Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Internal address size (if IADR used) - Transfer direction bit Write ==> bit MREAD = 0 No Internal address size = 0? Set the internal address TWI_IADR = address Yes Load Transmit register TWI_THR = Data to send Read Status register TWI_THR = data to send No TXRDY = 1? Yes Data to send? Yes Read Status register Yes No TXCOMP = 1? END SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 413 Figure 29-17. TWI Read Operation with Single Data Byte without Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Transfer direction bit Read ==> bit MREAD = 1 Start the transfer TWI_CR = START | STOP Read status register RXRDY = 1? No Yes Read Receive Holding Register Read Status register No TXCOMP = 1? Yes END 414 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 Figure 29-18. TWI Read Operation with Single Data Byte and Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Internal address size (IADRSZ) - Transfer direction bit Read ==> bit MREAD = 1 Set the internal address TWI_IADR = address Start the transfer TWI_CR = START | STOP Read Status register No RXRDY = 1? Yes Read Receive Holding register Read Status register No TXCOMP = 1? Yes END SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 415 Figure 29-19. TWI Read Operation with Multiple Data Bytes with or without Internal Address BEGIN Set TWI clock (CLDIV, CHDIV, CKDIV) in TWI_CWGR (Needed only once) Set the Control register: - Master enable TWI_CR = MSEN + SVDIS Set the Master Mode register: - Device slave address - Internal address size (if IADR used) - Transfer direction bit Read ==> bit MREAD = 1 Internal address size = 0? Set the internal address TWI_IADR = address Yes Start the transfer TWI_CR = START Read Status register RXRDY = 1? No Yes Read Receive Holding register (TWI_RHR) No Last data to read but one? Yes Stop the transfer TWI_CR = STOP Read Status register No RXRDY = 1? Yes Read Receive Holding register (TWI_RHR) Read status register TXCOMP = 1? Yes END 416 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 No 29.7.4 Multi-master Mode 29.7.4.1 Definition More than one master may handle the bus at the same time without data corruption by using arbitration. Arbitration starts as soon as two or more masters place information on the bus at the same time, and stops (arbitration is lost) for the master that intends to send a logical one while the other master sends a logical zero. As soon as arbitration is lost by a master, it stops sending data and listens to the bus in order to detect a stop. When the stop is detected, the master who has lost arbitration may put its data on the bus by respecting arbitration. Arbitration is illustrated in Figure 29-21 on page 418. 29.7.4.2 Different Multi-master Modes Two multi-master modes may be distinguished: 1. TWI is considered as a Master only and will never be addressed. 2. TWI may be either a Master or a Slave and may be addressed. Note: In both Multi-master modes arbitration is supported. TWI as Master Only In this mode, TWI is considered as a Master only (MSEN is always at one) and must be driven like a Master with the ARBLST (ARBitration Lost) flag in addition. If arbitration is lost (ARBLST = 1), the programmer must reinitiate the data transfer. If the user starts a transfer (ex.: DADR + START + W + Write in THR) and if the bus is busy, the TWI automatically waits for a STOP condition on the bus to initiate the transfer (see Figure 29-20 on page 418). Note: The state of the bus (busy or free) is not indicated in the user interface. TWI as Master or Slave The automatic reversal from Master to Slave is not supported in case of a lost arbitration. Then, in the case where TWI may be either a Master or a Slave, the programmer must manage the pseudo Multimaster mode described in the steps below. 1. Program TWI in Slave mode (SADR + MSDIS + SVEN) and perform Slave Access (if TWI is addressed). 2. If TWI has to be set in Master mode, wait until TXCOMP flag is at 1. 3. Program Master mode (DADR + SVDIS + MSEN) and start the transfer (ex: START + Write in THR). 4. As soon as the Master mode is enabled, TWI scans the bus in order to detect if it is busy or free. When the bus is considered as free, TWI initiates the transfer. 5. As soon as the transfer is initiated and until a STOP condition is sent, the arbitration becomes relevant and the user must monitor the ARBLST flag. 6. If the arbitration is lost (ARBLST is set to 1), the user must program the TWI in Slave mode in the case where the Master that won the arbitration wanted to access the TWI. 7. If TWI has to be set in Slave mode, wait until TXCOMP flag is at 1 and then program the Slave mode. Note: In the case where the arbitration is lost and TWI is addressed, TWI will not acknowledge even if it is programmed in Slave mode as soon as ARBLST is set to 1. Then, the Master must repeat SADR. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 417 Figure 29-20. Programmer Sends Data While the Bus is Busy TWCK START sent by the TWI STOP sent by the master DATA sent by a master TWD DATA sent by the TWI Bus is busy Bus is free Transfer is kept TWI DATA transfer A transfer is programmed (DADR + W + START + Write THR) Bus is considered as free Transfer is initiated Figure 29-21. Arbitration Cases TWCK TWD TWCK Data from a Master S 1 0 0 1 1 Data from TWI S 1 0 TWD S 1 0 0 1 P Arbitration is lost TWI stops sending data 1 1 Data from the master P Arbitration is lost S 1 0 1 S 1 0 0 1 1 S 1 0 0 1 1 The master stops sending data Data from the TWI ARBLST Bus is busy Transfer is kept TWI DATA transfer A transfer is programmed (DADR + W + START + Write THR) Bus is free Transfer is stopped Transfer is programmed again (DADR + W + START + Write THR) Bus is considered as free Transfer is initiated The flowchart shown in Figure 29-22 on page 419 gives an example of read and write operations in Multi-master mode. 418 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 Figure 29-22. Multi-master Flowchart START Programm the SLAVE mode: SADR + MSDIS + SVEN Read Status Register SVACC = 1 ? Yes GACC = 1 ? SVREAD = 0 ? EOSACC = 1 ? TXRDY= 1 ? Yes Yes Yes Write in TWI_THR TXCOMP = 1 ? RXRDY= 0 ? Yes Yes Read TWI_RHR Need to perform a master access ? GENERAL CALL TREATMENT Yes Decoding of the programming sequence Prog seq OK ? Change SADR Program the Master mode DADR + SVDIS + MSEN + CLK + R / W Read Status Register Yes ARBLST = 1 ? Yes Yes Read TWI_RHR Yes MREAD = 1 ? RXRDY= 0 ? TXRDY= 0 ? Data to read? Data to send ? Yes Yes Write in TWI_THR Stop transfer Read Status Register Yes TXCOMP = 0 ? SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 419 29.7.5 Slave Mode 29.7.5.1 Definition The Slave Mode is defined as a mode where the device receives the clock and the address from another device called the master. In this mode, the device never initiates and never completes the transmission (START, REPEATED_START and STOP conditions are always provided by the master). 29.7.5.2 Application Block Diagram Figure 29-23. Slave Mode Typical Application Block Diagram VDD R Master Host with TWI Interface R TWD TWCK Host with TWI Interface Host with TWI Interface LCD Controller Slave 1 Slave 2 Slave 3 29.7.5.3 Programming Slave Mode The following fields must be programmed before entering Slave mode: 1. SADR (TWI_SMR): The slave device address is used in order to be accessed by master devices in read or write mode. 2. MSDIS (TWI_CR): Disable the master mode. 3. SVEN (TWI_CR): Enable the slave mode. As the device receives the clock, values written in TWI_CWGR are not taken into account. 29.7.5.4 Receiving Data After a Start or Repeated Start condition is detected and if the address sent by the Master matches with the Slave address programmed in the SADR (Slave ADdress) field, SVACC (Slave ACCess) flag is set and SVREAD (Slave READ) indicates the direction of the transfer. SVACC remains high until a STOP condition or a repeated START is detected. When such a condition is detected, EOSACC (End Of Slave ACCess) flag is set. Read Sequence In the case of a Read sequence (SVREAD is high), TWI transfers data written in the TWI_THR (TWI Transmit Holding Register) until a STOP condition or a REPEATED_START + an address different from SADR is detected. Note that at the end of the read sequence TXCOMP (Transmission Complete) flag is set and SVACC reset. As soon as data is written in the TWI_THR, TXRDY (Transmit Holding Register Ready) flag is reset, and it is set when the shift register is empty and the sent data acknowledged or not. If the data is not acknowledged, the NACK flag is set. Note that a STOP or a repeated START always follows a NACK. See Figure 29-24 on page 421. 420 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 Write Sequence In the case of a Write sequence (SVREAD is low), the RXRDY (Receive Holding Register Ready) flag is set as soon as a character has been received in the TWI_RHR (TWI Receive Holding Register). RXRDY is reset when reading the TWI_RHR. TWI continues receiving data until a STOP condition or a REPEATED_START + an address different from SADR is detected. Note that at the end of the write sequence TXCOMP flag is set and SVACC reset. See Figure 29-25 on page 422. Clock Synchronization Sequence In the case where TWI_THR or TWI_RHR is not written/read in time, TWI performs a clock synchronization. Clock stretching information is given by the SCLWS (Clock Wait state) bit. See Figure 29-27 on page 423 and Figure 29-28 on page 424. General Call In the case where a GENERAL CALL is performed, GACC (General Call ACCess) flag is set. After GACC is set, it is up to the programmer to interpret the meaning of the GENERAL CALL and to decode the new address programming sequence. See Figure 29-26 on page 422. 29.7.6 Data Transfer Read Operation The read mode is defined as a data requirement from the master. After a START or a REPEATED START condition is detected, the decoding of the address starts. If the slave address (SADR) is decoded, SVACC is set and SVREAD indicates the direction of the transfer. Until a STOP or REPEATED START condition is detected, TWI continues sending data loaded in the TWI_THR. If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset. Figure 29-24 describes the write operation. Figure 29-24. Read Access Ordered by a MASTER SADR matches, TWI answers with an ACK SADR does not match, TWI answers with a NACK TWD S ADR R NA DATA NA P/S/Sr SADR R A DATA A ACK/NACK from the Master A DATA NA S/Sr TXRDY NACK Write THR Read RHR SVACC SVREAD SVREAD has to be taken into account only while SVACC is active EOSVACC Notes: 1. When SVACC is low, the state of SVREAD becomes irrelevant. 2. TXRDY is reset when data has been transmitted from TWI_THR to the shift register and set when this data has been acknowledged or non acknowledged. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 421 Write Operation The write mode is defined as a data transmission from the master. After a START or a REPEATED START, the decoding of the address starts. If the slave address is decoded, SVACC is set and SVREAD indicates the direction of the transfer (SVREAD is low in this case). Until a STOP or REPEATED START condition is detected, TWI stores the received data in the TWI_RHR. If a STOP condition or a REPEATED START + an address different from SADR is detected, SVACC is reset. Figure 29-25 describes the Write operation. Figure 29-25. Write Access Ordered by a Master SADR does not match, TWI answers with a NACK S TWD ADR W NA DATA NA SADR matches, TWI answers with an ACK P/S/Sr SADR W A DATA Read RHR A A DATA NA S/Sr RXRDY SVACC SVREAD has to be taken into account only while SVACC is active SVREAD EOSVACC Notes: 1. When SVACC is low, the state of SVREAD becomes irrelevant. 2. RXRDY is set when data has been transmitted from the shift register to the TWI_RHR and reset when this data is read. General Call The general call is performed in order to change the address of the slave. If a GENERAL CALL is detected, GACC is set. After the detection of General Call, it is up to the programmer to decode the commands which come afterwards. In case of a WRITE command, the programmer has to decode the programming sequence and program a new SADR if the programming sequence matches. Figure 29-26 describes the General Call access. Figure 29-26. Master Performs a General Call 0000000 + W TXD S GENERAL CALL RESET command = 00000110X WRITE command = 00000100X A Reset or write DADD A DATA1 A DATA2 A New SADR A P New SADR Programming sequence GCACC Reset after read SVACC Note: This method allows the user to create an own programming sequence by choosing the programming bytes and the number of them. The programming sequence has to be provided to the master. Clock Synchronization In both read and write modes, it may happen that TWI_THR/TWI_RHR buffer is not filled /emptied before the emission/reception of a new character. In this case, to avoid sending/receiving undesired data, a clock stretching mechanism is implemented. 422 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 Clock Synchronization in Read Mode The clock is tied low if the shift register is empty and if a STOP or REPEATED START condition was not detected. It is tied low until the shift register is loaded. Figure 29-27 describes the clock synchronization in Read mode. Figure 29-27. Clock Synchronization in Read Mode TWI_THR S SADR R DATA1 1 DATA0 A DATA0 A DATA1 DATA2 A XXXXXXX DATA2 NA S 2 TWCK Write THR CLOCK is tied low by the TWI as long as THR is empty SCLWS TXRDY SVACC SVREAD As soon as a START is detected TXCOMP TWI_THR is transmitted to the shift register Notes: Ack or Nack from the master 1 The data is memorized in TWI_THR until a new value is written 2 The clock is stretched after the ACK, the state of TWD is undefined during clock stretching 1. TXRDY is reset when data has been written in the TWI_TH to the shift register and set when this data has been acknowledged or non acknowledged. 2. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from SADR. 3. SCLWS is automatically set when the clock synchronization mechanism is started. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 423 Clock Synchronization in Write Mode The clock is tied low if the shift register and the TWI_RHR is full. If a STOP or REPEATED_START condition was not detected, it is tied low until TWI_RHR is read. Figure 29-28 describes the clock synchronization in Write mode. Figure 29-28. Clock Synchronization in Write Mode TWCK CLOCK is tied low by the TWI as long as RHR is full TWD S SADR W A DATA0 TWI_RHR A DATA1 A DATA0 is not read in the RHR DATA2 DATA1 NA S ADR DATA2 SCLWS SCL is stretched on the last bit of DATA1 RXRDY Rd DATA0 Rd DATA1 Rd DATA2 SVACC SVREAD TXCOMP Notes: 424 As soon as a START is detected 1. At the end of the read sequence, TXCOMP is set after a STOP or after a REPEATED_START + an address different from SADR. 2. SCLWS is automatically set when the clock synchronization mechanism is started and automatically reset when the mechanism is finished. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 Reversal after a Repeated Start Reversal of Read to Write The master initiates the communication by a read command and finishes it by a write command. Figure 29-29 describes the repeated start + reversal from Read to Write mode. Figure 29-29. Repeated Start + Reversal from Read to Write Mode TWI_THR TWD DATA0 S SADR R A DATA0 DATA1 A DATA1 NA Sr SADR W A DATA2 TWI_RHR A DATA3 DATA2 A P DATA3 SVACC SVREAD TXRDY RXRDY EOSACC Cleared after read As soon as a START is detected TXCOMP Note: 1. TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected again. Reversal of Write to Read The master initiates the communication by a write command and finishes it by a read command. Figure 29-30 describes the repeated start + reversal from Write to Read mode. Figure 29-30. Repeated Start + Reversal from Write to Read Mode DATA2 TWI_THR TWD S SADR W A DATA0 TWI_RHR A DATA1 DATA0 A Sr SADR R A DATA3 DATA2 A DATA3 NA P DATA1 SVACC SVREAD TXRDY RXRDY EOSACC TXCOMP Notes: Read TWI_RHR Cleared after read As soon as a START is detected 1. In this case, if TWI_THR has not been written at the end of the read command, the clock is automatically stretched before the ACK. 2. TXCOMP is only set at the end of the transmission because after the repeated start, SADR is detected again. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 425 29.7.6.1 Read Write Flowcharts The flowchart shown in Figure 29-31 gives an example of read and write operations in Slave mode. A polling or interrupt method can be used to check the status bits. The interrupt method requires that the interrupt enable register (TWI_IER) be configured first. Figure 29-31. Read Write Flowchart in Slave Mode Set the SLAVE mode: SADR + MSDIS + SVEN Read Status Register SVACC = 1 ? GACC = 1 ? SVREAD = 0 ? TXRDY= 1 ? EOSACC = 1 ? Write in TWI_THR TXCOMP = 1 ? RXRDY= 0 ? END Read TWI_RHR GENERAL CALL TREATMENT Decoding of the programming sequence Prog seq OK ? Change SADR 426 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 29.8 Two-wire Interface (TWI) User Interface Table 29-4. Register Mapping Offset Register Name Access Reset 0x00 Control Register TWI_CR Write-only – 0x04 Master Mode Register TWI_MMR Read/Write 0x00000000 0x08 Slave Mode Register TWI_SMR Read/Write 0x00000000 0x0C Internal Address Register TWI_IADR Read/Write 0x00000000 0x10 Clock Waveform Generator Register TWI_CWGR Read/Write 0x00000000 0x20 Status Register TWI_SR Read-only 0x0000F009 0x24 Interrupt Enable Register TWI_IER Write-only – 0x28 Interrupt Disable Register TWI_IDR Write-only – 0x2C Interrupt Mask Register TWI_IMR Read-only 0x00000000 0x30 Receive Holding Register TWI_RHR Read-only 0x00000000 0x34 Transmit Holding Register TWI_THR Write-only – 0x38–0xFC Reserved – – – SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 427 29.8.1 TWI Control Register Name: TWI_CR Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 SWRST 6 – 5 SVDIS 4 SVEN 3 MSDIS 2 MSEN 1 STOP 0 START • START: Send a START Condition 0: No effect. 1: A frame beginning with a START bit is transmitted according to the features defined in the mode register. This action is necessary when the TWI peripheral wants to read data from a slave. When configured in Master Mode with a write operation, a frame is sent as soon as the user writes a character in the Transmit Holding Register (TWI_THR). • STOP: Send a STOP Condition 0: No effect. 1: STOP Condition is sent just after completing the current byte transmission in master read mode. – In single data byte master read, the START and STOP must both be set. – In multiple data bytes master read, the STOP must be set after the last data received but one. – In master read mode, if a NACK bit is received, the STOP is automatically performed. – In multiple data write operation, when both THR and shift register are empty, a STOP condition is automatically sent. • MSEN: TWI Master Mode Enabled 0: No effect. 1: If MSDIS = 0, the master mode is enabled. Note: Switching from Slave to Master mode is only permitted when TXCOMP = 1. • MSDIS: TWI Master Mode Disabled 0: No effect. 1: The master mode is disabled, all pending data is transmitted. The shifter and holding characters (if it contains data) are transmitted in case of write operation. In read operation, the character being transferred must be completely received before disabling. • SVEN: TWI Slave Mode Enabled 0: No effect. 1: If SVDIS = 0, the slave mode is enabled. Note: Switching from Master to Slave mode is only permitted when TXCOMP = 1. 428 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 • SVDIS: TWI Slave Mode Disabled 0: No effect. 1: The slave mode is disabled. The shifter and holding characters (if it contains data) are transmitted in case of read operation. In write operation, the character being transferred must be completely received before disabling. • SWRST: Software Reset 0: No effect. 1: Equivalent to a system reset. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 429 29.8.2 TWI Master Mode Register Name: TWI_MMR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 21 20 19 DADR 18 17 16 15 – 14 – 13 – 12 MREAD 11 – 10 – 9 7 – 6 – 5 – 4 – 3 – 2 – 1 – 8 IADRSZ 0 – • IADRSZ: Internal Device Address Size Value Description 0 0 No internal device address 0 1 One-byte internal device address 1 0 Two-byte internal device address 1 1 Three-byte internal device address • MREAD: Master Read Direction 0: Master write direction. 1: Master read direction. • DADR: Device Address The device address is used to access slave devices in read or write mode. Those bits are only used in Master mode. 430 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 29.8.3 TWI Slave Mode Register Name: TWI_SMR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 21 20 19 SADR 18 17 16 15 – 14 – 13 – 12 – 11 – 10 – 9 8 7 – 6 – 5 – 4 – 3 – 2 – 1 – 0 – • SADR: Slave Address The slave device address is used in Slave mode in order to be accessed by master devices in read or write mode. SADR must be programmed before enabling the Slave mode or after a general call. Writes at other times have no effect. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 431 29.8.4 TWI Internal Address Register Name: TWI_IADR Access: Read/Write 31 – 30 – 29 – 28 – 23 22 21 20 27 – 26 – 25 – 24 – 19 18 17 16 11 10 9 8 3 2 1 0 IADR 15 14 13 12 IADR 7 6 5 4 IADR • IADR: Internal Address 0, 1, 2 or 3 bytes depending on IADRSZ. 432 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 29.8.5 TWI Clock Waveform Generator Register Name: TWI_CWGR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 22 21 20 19 18 17 CKDIV 16 15 14 13 12 11 10 9 8 3 2 1 0 CHDIV 7 6 5 4 CLDIV TWI_CWGR is only used in Master mode. • CLDIV: Clock Low Divider The SCL low period is defined as follows: tlow = ((CLDIV × 2CKDIV) + 4 × tMCK • CHDIV: Clock High Divider The SCL high period is defined as follows: thigh = ((CHDIV × 2CKDIV) + 4 × tMCK • CKDIV: Clock Divider The CKDIV is used to increase both SCL high and low periods. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 433 29.8.6 TWI Status Register Name: TWI_SR Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 EOSACC 10 SCLWS 9 ARBLST 8 NACK 7 – 6 OVRE 5 GACC 4 SVACC 3 SVREAD 2 TXRDY 1 RXRDY 0 TXCOMP • TXCOMP: Transmission Completed (automatically set / reset) TXCOMP used in Master mode: 0: During the length of the current frame. 1: When both holding and shifter registers are empty and STOP condition has been sent. TXCOMP behavior in Master mode can be seen in Figure 29-8 on page 407 and in Figure 29-10 on page 408. TXCOMP used in Slave mode: 0: As soon as a Start is detected. 1: After a Stop or a Repeated Start + an address different from SADR is detected. TXCOMP behavior in Slave mode can be seen in Figure 29-27 on page 423, Figure 29-28 on page 424, Figure 29-29 on page 425 and Figure 29-30 on page 425. • RXRDY: Receive Holding Register Ready (automatically set / reset) 0: No character has been received since the last TWI_RHR read operation. 1: A byte has been received in the TWI_RHR since the last read. RXRDY behavior in Master mode can be seen in Figure 29-10 on page 408. RXRDY behavior in Slave mode can be seen in Figure 29-25 on page 422, Figure 29-28 on page 424, Figure 29-29 on page 425 and Figure 29-30 on page 425. • TXRDY: Transmit Holding Register Ready (automatically set / reset) TXRDY used in Master mode: 0: The transmit holding register has not been transferred into shift register. Set to 0 when writing into TWI_THR. 1: As soon as a data byte is transferred from TWI_THR to internal shifter or if a NACK error is detected, TXRDY is set at the same time as TXCOMP and NACK. TXRDY is also set when MSEN is set (enable TWI). TXRDY behavior in Master mode can be seen in Figure 29-8 on page 407. TXRDY used in Slave mode: 0: As soon as data is written in the TWI_THR, until this data has been transmitted and acknowledged (ACK or NACK). 1: It indicates that the TWI_THR is empty and that data has been transmitted and acknowledged. 434 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 If TXRDY is high and if a NACK has been detected, the transmission will be stopped. Thus when TRDY = NACK = 1, the programmer must not fill TWI_THR to avoid losing it. TXRDY behavior in Slave mode can be seen in Figure 29-24 on page 421, Figure 29-27 on page 423, Figure 29-29 on page 425 and Figure 29-30 on page 425. • SVREAD: Slave Read (automatically set / reset) This bit is only used in Slave mode. When SVACC is low (no Slave access has been detected) SVREAD is irrelevant. 0: Indicates that a write access is performed by a Master. 1: Indicates that a read access is performed by a Master. SVREAD behavior can be seen in Figure 29-24 on page 421, Figure 29-25 on page 422, Figure 29-29 on page 425 and Figure 29-30 on page 425. • SVACC: Slave Access (automatically set / reset) This bit is only used in Slave mode. 0: TWI is not addressed. SVACC is automatically cleared after a NACK or a STOP condition is detected. 1: Indicates that the address decoding sequence has matched (A Master has sent SADR). SVACC remains high until a NACK or a STOP condition is detected. SVACC behavior can be seen in Figure 29-24 on page 421, Figure 29-25 on page 422, Figure 29-29 on page 425 and Figure 29-30 on page 425. • GACC: General Call Access (clear on read) This bit is only used in Slave mode. 0: No General Call has been detected. 1: A General Call has been detected. After the detection of General Call, the programmer decoded the commands that follow and the programming sequence. GACC behavior can be seen in Figure 29-26 on page 422. • OVRE: Overrun Error (clear on read) This bit is only used in Master mode. 0: TWI_RHR has not been loaded while RXRDY was set 1: TWI_RHR has been loaded while RXRDY was set. Reset by read in TWI_SR when TXCOMP is set. • NACK: Not Acknowledged (clear on read) NACK used in Master mode: 0: Each data byte has been correctly received by the far-end side TWI slave component. 1: A data byte has not been acknowledged by the slave component. Set at the same time as TXCOMP. NACK used in Slave Read mode: 0: Each data byte has been correctly received by the Master. 1: In read mode, a data byte has not been acknowledged by the Master. When NACK is set the programmer must not fill TWI_THR even if TXRDY is set, because it means that the Master will stop the data transfer or re initiate it. Note that in Slave Write mode all data are acknowledged by the TWI. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 435 • ARBLST: Arbitration Lost (clear on read) This bit is only used in Master mode. 0: Arbitration won. 1: Arbitration lost. Another master of the TWI bus has won the multi-master arbitration. TXCOMP is set at the same time. • SCLWS: Clock Wait State (automatically set / reset) This bit is only used in Slave mode. 0: The clock is not stretched. 1: The clock is stretched. TWI_THR / TWI_RHR buffer is not filled / emptied before the emission / reception of a new character. SCLWS behavior can be seen in Figure 29-27 on page 423 and Figure 29-28 on page 424. • EOSACC: End Of Slave Access (clear on read) This bit is only used in Slave mode. 0: A slave access is being performing. 1: The Slave Access is finished. End Of Slave Access is automatically set as soon as SVACC is reset. EOSACC behavior can be seen in Figure 29-29 on page 425 and Figure 29-30 on page 425. 436 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 29.8.7 TWI Interrupt Enable Register Name: TWI_IER Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 EOSACC 10 SCL_WS 9 ARBLST 8 NACK 7 – 6 OVRE 5 GACC 4 SVACC 3 – 2 TXRDY 1 RXRDY 0 TXCOMP • TXCOMP: Transmission Completed Interrupt Enable • RXRDY: Receive Holding Register Ready Interrupt Enable • TXRDY: Transmit Holding Register Ready Interrupt Enable • SVACC: Slave Access Interrupt Enable • GACC: General Call Access Interrupt Enable • OVRE: Overrun Error Interrupt Enable • NACK: Not Acknowledge Interrupt Enable • ARBLST: Arbitration Lost Interrupt Enable • SCL_WS: Clock Wait State Interrupt Enable • EOSACC: End Of Slave Access Interrupt Enable 0: No effect. 1: Enables the corresponding interrupt. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 437 29.8.8 TWI Interrupt Disable Register Name: TWI_IDR Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 EOSACC 10 SCL_WS 9 ARBLST 8 NACK 7 – 6 OVRE 5 GACC 4 SVACC 3 – 2 TXRDY 1 RXRDY 0 TXCOMP • TXCOMP: Transmission Completed Interrupt Disable • RXRDY: Receive Holding Register Ready Interrupt Disable • TXRDY: Transmit Holding Register Ready Interrupt Disable • SVACC: Slave Access Interrupt Disable • GACC: General Call Access Interrupt Disable • OVRE: Overrun Error Interrupt Disable • NACK: Not Acknowledge Interrupt Disable • ARBLST: Arbitration Lost Interrupt Disable • SCL_WS: Clock Wait State Interrupt Disable • EOSACC: End Of Slave Access Interrupt Disable 0: No effect. 1: Disables the corresponding interrupt. 438 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 29.8.9 TWI Interrupt Mask Register Name: TWI_IMR Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 EOSACC 10 SCL_WS 9 ARBLST 8 NACK 7 – 6 OVRE 5 GACC 4 SVACC 3 – 2 TXRDY 1 RXRDY 0 TXCOMP • TXCOMP: Transmission Completed Interrupt Mask • RXRDY: Receive Holding Register Ready Interrupt Mask • TXRDY: Transmit Holding Register Ready Interrupt Mask • SVACC: Slave Access Interrupt Mask • GACC: General Call Access Interrupt Mask • OVRE: Overrun Error Interrupt Mask • NACK: Not Acknowledge Interrupt Mask • ARBLST: Arbitration Lost Interrupt Mask • SCL_WS: Clock Wait State Interrupt Mask • EOSACC: End Of Slave Access Interrupt Mask 0: The corresponding interrupt is disabled. 1: The corresponding interrupt is enabled. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 439 29.8.10 TWI Receive Holding Register Name: TWI_RHR Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 RXDATA • RXDATA: Master or Slave Receive Holding Data 440 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 29.8.11 TWI Transmit Holding Register Name: TWI_THR Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 TXDATA • TXDATA: Master or Slave Transmit Holding Data SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 441 30. Universal Synchronous Asynchronous Receiver Transmitter (USART) 30.1 Description The Universal Synchronous Asynchronous Receiver Transmitter (USART) provides one full duplex universal synchronous asynchronous serial link. Data frame format is widely programmable (data length, parity, number of stop bits) to support a maximum of standards. The receiver implements parity error, framing error and overrun error detection. The receiver time-out enables handling variable-length frames and the transmitter timeguard facilitates communications with slow remote devices. Multidrop communications are also supported through address bit handling in reception and transmission. The USART features three test modes: remote loopback, local loopback and automatic echo. The USART supports specific operating modes providing interfaces on RS485 buses, with ISO7816 T = 0 or T = 1 smart card slots, infrared transceivers and connection to modem ports. The hardware handshaking feature enables an out-of-band flow control by automatic management of the pins RTS and CTS. The USART supports the connection to the Peripheral DMA Controller, which enables data transfers to the transmitter and from the receiver. The PDC provides chained buffer management without any intervention of the processor. 30.2 Embedded Characteristics  Programmable Baud Rate Generator  5- to 9-bit full-duplex synchronous or asynchronous serial communications ̶ 1, 1.5 or 2 stop bits in Asynchronous Mode or 1 or 2 stop bits in Synchronous Mode ̶ Parity generation and error detection ̶ Framing error detection, overrun error detection ̶ MSB- or LSB-first ̶ Optional break generation and detection ̶ By 8 or by-16 over-sampling receiver frequency ̶ Hardware handshaking RTS-CTS ̶ Optional modem signal management DTR-DSR-DCD-RI ̶ Receiver time-out and transmitter timeguard ̶ Optional Multi-drop Mode with address generation and detection  RS485 with driver control signal  ISO7816, T = 0 or T = 1 Protocols for interfacing with smart cards  IrDA modulation and demodulation ̶ ̶ NACK handling, error counter with repetition and iteration limit  Communication at up to 115.2 Kbps Test Modes ̶ Remote Loopback, Local Loopback, Automatic Echo The USART contains features allowing management of the Modem Signals DTR, DSR, DCD and RI. In the SAM9260, only the USART0 implements these signals, named DTR0, DSR0, DCD0 and RI0. The USART1 and USART2 do not implement all the modem signals. Only RTS and CTS (RTS1 and CTS1, RTS2 and CTS2, respectively) are implemented in these USARTs for other features. Thus, programming the USART1, USART2 or the USART3 in Modem Mode may lead to unpredictable results. In these USARTs, the commands relating to the Modem Mode have no effect and the status bits relating the status of the modem signals are never activated. 442 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 30.3 Block Diagram Figure 30-1. USART Block Diagram Peripheral DMA Controller Channel Channel PIO Controller USART RXD Receiver RTS AIC TXD USART Interrupt Transmitter CTS DTR PMC Modem Signals Control MCK DIV DSR DCD MCK/DIV RI SLCK Baud Rate Generator SCK User Interface APB SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 443 30.4 Application Block Diagram Figure 30-2. Application Block Diagram IrLAP PPP Modem Driver Serial Driver Field Bus Driver EMV Driver IrDA Driver USART RS232 Drivers RS232 Drivers RS485 Drivers Serial Port Differential Bus Smart Card Slot IrDA Transceivers Modem PSTN 30.5 I/O Lines Description Table 30-1. 444 I/O Line Description Name Description Type Active Level SCK Serial Clock I/O – TXD Transmit Serial Data I/O – RXD Receive Serial Data Input – RI Ring Indicator Input Low DSR Data Set Ready Input Low DCD Data Carrier Detect Input Low DTR Data Terminal Ready Output Low CTS Clear to Send Input Low RTS Request to Send Output Low SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 30.6 Product Dependencies 30.6.1 I/O Lines The pins used for interfacing the USART may be multiplexed with the PIO lines. The programmer must first program the PIO controller to assign the desired USART pins to their peripheral function. If I/O lines of the USART are not used by the application, they can be used for other purposes by the PIO Controller. To prevent the TXD line from falling when the USART is disabled, the use of an internal pull up is mandatory. If the hardware handshaking feature or Modem mode is used, the internal pull up on TXD must also be enabled. All the pins of the modems may or may not be implemented on the USART. Only USART0 is fully equipped with all the modem signals. On USARTs not equipped with the corresponding pin, the associated control bits and statuses have no effect on the behavior of the USART. 30.6.2 Power Management The USART is not continuously clocked. The programmer must first enable the USART Clock in the Power Management Controller (PMC) before using the USART. However, if the application does not require USART operations, the USART clock can be stopped when not needed and be restarted later. In this case, the USART will resume its operations where it left off. Configuring the USART does not require the USART clock to be enabled. 30.6.3 Interrupt The USART interrupt line is connected on one of the internal sources of the Advanced Interrupt Controller. Using the USART interrupt requires the AIC to be programmed first. Note that it is not recommended to use the USART interrupt line in edge sensitive mode. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 445 30.7 Functional Description The USART is capable of managing several types of serial synchronous or asynchronous communications. It supports the following communication modes:   5- to 9-bit full-duplex asynchronous serial communication ̶ MSB- or LSB-first ̶ 1, 1.5 or 2 stop bits ̶ Parity even, odd, marked, space or none ̶ By 8 or by 16 over-sampling receiver frequency ̶ Optional hardware handshaking ̶ Optional modem signals management ̶ Optional break management ̶ Optional multidrop serial communication High-speed 5- to 9-bit full-duplex synchronous serial communication ̶ MSB- or LSB-first ̶ 1 or 2 stop bits ̶ Parity even, odd, marked, space or none ̶ By 8 or by 16 over-sampling frequency ̶ Optional hardware handshaking ̶ Optional modem signals management ̶ Optional break management ̶ Optional multidrop serial communication  RS485 with driver control signal  ISO7816, T0 or T1 protocols for interfacing with smart cards ̶ NACK handling, error counter with repetition and iteration limit  InfraRed IrDA Modulation and Demodulation  Test modes ̶ 446 Remote loopback, local loopback, automatic echo SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 30.7.1 Baud Rate Generator The Baud Rate Generator provides the bit period clock named the Baud Rate Clock to both the receiver and the transmitter. The Baud Rate Generator clock source can be selected by setting the USCLKS field in the Mode Register (US_MR) between:  the Master Clock MCK  a division of the Master Clock, the divider being product dependent, but generally set to 8  the external clock, available on the SCK pin The Baud Rate Generator is based upon a 16-bit divider, which is programmed with the CD field of the Baud Rate Generator Register (US_BRGR). If CD is programmed at 0, the Baud Rate Generator does not generate any clock. If CD is programmed at 1, the divider is bypassed and becomes inactive. If the external SCK clock is selected, the duration of the low and high levels of the signal provided on the SCK pin must be longer than a Master Clock (MCK) period. The frequency of the signal provided on SCK must be at least 4.5 times lower than MCK. Figure 30-3. Baud Rate Generator USCLKS MCK MCK/DIV SCK Reserved CD CD SCK 0 1 2 16-bit Counter FIDI >1 3 1 0 0 0 SYNC OVER Sampling Divider 0 Baud Rate Clock 1 1 SYNC USCLKS = 3 Sampling Clock 30.7.1.1 Baud Rate in Asynchronous Mode If the USART is programmed to operate in asynchronous mode, the selected clock is first divided by CD, which is field programmed in the Baud Rate Generator Register (US_BRGR). The resulting clock is provided to the receiver as a sampling clock and then divided by 16 or 8, depending on the programming of the OVER bit in US_MR. If OVER is set to 1, the receiver sampling is 8 times higher than the baud rate clock. If OVER is cleared, the sampling is performed at 16 times the baud rate clock. The following formula performs the calculation of the baud rate: SelectedClock Baudrate = -------------------------------------------( 8 ( 2 – Over )CD ) This gives a maximum baud rate of MCK divided by 8, assuming that MCK is the highest possible clock and that OVER is programmed at 1. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 447 Baud Rate Calculation Example Table 30-2 shows calculations of CD to obtain a baud rate at 38400 baud for different source clock frequencies. This table also shows the actual resulting baud rate and the error. Table 30-2. Baud Rate Example (OVER = 0) Source Clock (MHz) Expected Baud Rate (bit/s) Calculation Result CD Actual Baud Rate (bit/s) Error 3 686 400 38 400 6.00 6 38 400.00 0.00% 4 915 200 38 400 8.00 8 38 400.00 0.00% 5 000 000 38 400 8.14 8 39 062.50 1.70% 7 372 800 38 400 12.00 12 38 400.00 0.00% 8 000 000 38 400 13.02 13 38 461.54 0.16% 12 000 000 38 400 19.53 20 37 500.00 2.40% 12 288 000 38 400 20.00 20 38 400.00 0.00% 14 318 180 38 400 23.30 23 38 908.10 1.31% 14 745 600 38 400 24.00 24 38 400.00 0.00% 18 432 000 38 400 30.00 30 38 400.00 0.00% 24 000 000 38 400 39.06 39 38 461.54 0.16% 24 576 000 38 400 40.00 40 38 400.00 0.00% 25 000 000 38 400 40.69 40 38 109.76 0.76% 32 000 000 38 400 52.08 52 38 461.54 0.16% 32 768 000 38 400 53.33 53 38 641.51 0.63% 33 000 000 38 400 53.71 54 38 194.44 0.54% 40 000 000 38 400 65.10 65 38 461.54 0.16% 50 000 000 38 400 81.38 81 38 580.25 0.47% The baud rate is calculated with the following formula: BaudRate = MCK ⁄ CD × 16 The baud rate error is calculated with the following formula. It is not recommended to work with an error higher than 5%. ExpectedBaudRate Error = 1 –  --------------------------------------------------- ActualBaudRate 448 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 30.7.1.2 Fractional Baud Rate in Asynchronous Mode The Baud Rate Generator previously defined is subject to the following limitation: the output frequency changes by only integer multiples of the reference frequency. An approach to this problem is to integrate a fractional N clock generator that has a high resolution. The generator architecture is modified to obtain baud rate changes by a fraction of the reference source clock. This fractional part is programmed with the FP field in the Baud Rate Generator Register (US_BRGR). If FP is not 0, the fractional part is activated. The resolution is one eighth of the clock divider. This feature is only available when using USART normal mode. The fractional baud rate is calculated using the following formula: SelectedClock Baudrate = --------------------------------------------------------------- 8 ( 2 – Over )  CD + FP -------    8  The modified architecture is presented below. Figure 30-4. Fractional Baud Rate Generator FP USCLKS CD Modulus Control FP MCK MCK/DIV SCK Reserved CD SCK 0 1 2 16-bit Counter 3 glitch-free logic 1 0 FIDI >1 0 0 SYNC OVER Sampling Divider 0 Baud Rate Clock 1 1 SYNC Sampling Clock USCLKS = 3 30.7.1.3 Baud Rate in Synchronous Mode If the USART is programmed to operate in synchronous mode, the selected clock is simply divided by the field CD in US_BRGR. SelectedClock BaudRate = -------------------------------------CD In synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided directly by the signal on the USART SCK pin. No division is active. The value written in US_BRGR has no effect. The external clock frequency must be at least 4.5 times lower than the system clock. When either the external clock SCK or the internal clock divided (MCK/DIV) is selected, the value programmed in CD must be even if the user has to ensure a 50:50 mark/space ratio on the SCK pin. If the internal clock MCK is selected, the Baud Rate Generator ensures a 50:50 duty cycle on the SCK pin, even if the value programmed in CD is odd. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 449 30.7.1.4 Baud Rate in ISO 7816 Mode The ISO7816 specification defines the bit rate with the following formula: Di B = ------ × f Fi where:  B is the bit rate  Di is the bit-rate adjustment factor  Fi is the clock frequency division factor  f is the ISO7816 clock frequency (Hz) Di is a binary value encoded on a 4-bit field, named DI, as represented in Table 30-3. Table 30-3. Binary and Decimal Values for Di DI field 0001 0010 0011 0100 0101 0110 1000 1001 1 2 4 8 16 32 12 20 Di (decimal) Fi is a binary value encoded on a 4-bit field, named FI, as represented in Table 30-4. Table 30-4. Binary and Decimal Values for Fi FI field 0000 0001 0010 0011 0100 0101 0110 1001 1010 1011 1100 1101 Fi (decimal 372 372 558 744 1116 1488 1860 512 768 1024 1536 2048 Table 30-5 shows the resulting Fi/Di Ratio, which is the ratio between the ISO7816 clock and the baud rate clock. Table 30-5. Possible Values for the Fi/Di Ratio Fi/Di 372 558 744 1116 1488 1806 512 768 1024 1536 2048 1 372 558 744 1116 1488 1860 512 768 1024 1536 2048 2 186 279 372 558 744 930 256 384 512 768 1024 4 93 139.5 186 279 372 465 128 192 256 384 512 8 46.5 69.75 93 139.5 186 232.5 64 96 128 192 256 16 23.25 34.87 46.5 69.75 93 116.2 32 48 64 96 128 32 11.62 17.43 23.25 34.87 46.5 58.13 16 24 32 48 64 12 31 46.5 62 93 124 155 42.66 64 85.33 128 170.6 20 18.6 27.9 37.2 55.8 74.4 93 25.6 38.4 51.2 76.8 102.4 If the USART is configured in ISO7816 Mode, the clock selected by the USCLKS field in the Mode Register (US_MR) is first divided by the value programmed in the field CD in the Baud Rate Generator Register (US_BRGR). The resulting clock can be provided to the SCK pin to feed the smart card clock inputs. This means that the CLKO bit can be set in US_MR. This clock is then divided by the value programmed in the FI_DI_RATIO field in the FI_DI_Ratio register (US_FIDI). This is performed by the Sampling Divider, which performs a division by up to 2047 in ISO7816 Mode. The non-integer values of the Fi/Di Ratio are not supported and the user must program the FI_DI_RATIO field to a value as close as possible to the expected value. The FI_DI_RATIO field resets to the value 0x174 (372 in decimal) and is the most common divider between the ISO7816 clock and the bit rate (Fi = 372, Di = 1). 450 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 Figure 30-5 shows the relation between the Elementary Time Unit, corresponding to a bit time, and the ISO 7816 clock. Figure 30-5. Elementary Time Unit (ETU) FI_DI_RATIO ISO7816 Clock Cycles ISO7816 Clock on SCK ISO7816 I/O Line on TXD 1 ETU 30.7.2 Receiver and Transmitter Control After reset, the receiver is disabled. The user must enable the receiver by setting the RXEN bit in the Control Register (US_CR). However, the receiver registers can be programmed before the receiver clock is enabled. After reset, the transmitter is disabled. The user must enable it by setting the TXEN bit in the Control Register (US_CR). However, the transmitter registers can be programmed before being enabled. The Receiver and the Transmitter can be enabled together or independently. At any time, the software can perform a reset on the receiver or the transmitter of the USART by setting the corresponding bit, RSTRX and RSTTX respectively, in the Control Register (US_CR). The software resets clear the status flag and reset internal state machines but the user interface configuration registers hold the value configured prior to software reset. Regardless of what the receiver or the transmitter is performing, the communication is immediately stopped. The user can also independently disable the receiver or the transmitter by setting RXDIS and TXDIS respectively in US_CR. If the receiver is disabled during a character reception, the USART waits until the end of reception of the current character, then the reception is stopped. If the transmitter is disabled while it is operating, the USART waits the end of transmission of both the current character and character being stored in the Transmit Holding Register (US_THR). If a timeguard is programmed, it is handled normally. 30.7.3 Synchronous and Asynchronous Modes 30.7.3.1 Transmitter Operations The transmitter performs the same in both synchronous and asynchronous operating modes (SYNC = 0 or SYNC = 1). One start bit, up to 9 data bits, one optional parity bit and up to two stop bits are successively shifted out on the TXD pin at each falling edge of the programmed serial clock. The number of data bits is selected by the CHRL field and the MODE 9 bit in the Mode Register (US_MR). Nine bits are selected by setting the MODE 9 bit regardless of the CHRL field. The parity bit is set according to the PAR field in US_MR. The even, odd, space, marked or none parity bit can be configured. The MSBF field in US_MR configures which data bit is sent first. If written at 1, the most significant bit is sent first. At 0, the less significant bit is sent first. The number of stop bits is selected by the NBSTOP field in US_MR. The 1.5 stop bit is supported in asynchronous mode only. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 451 Figure 30-6. Character Transmit Example: 8-bit, Parity Enabled One Stop Baud Rate Clock TXD D0 Start Bit D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit The characters are sent by writing in the Transmit Holding Register (US_THR). The transmitter reports two status bits in the Channel Status Register (US_CSR): TXRDY (Transmitter Ready), which indicates that US_THR is empty and TXEMPTY, which indicates that all the characters written in US_THR have been processed. When the current character processing is completed, the last character written in US_THR is transferred into the Shift Register of the transmitter and US_THR becomes empty, thus TXRDY rises. Both TXRDY and TXEMPTY bits are low when the transmitter is disabled. Writing a character in US_THR while TXRDY is low has no effect and the written character is lost. Figure 30-7. Transmitter Status Baud Rate Clock TXD Start D0 Bit D1 Write US_THR TXRDY TXEMPTY 452 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 D2 D3 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit 30.7.3.2 Asynchronous Receiver If the USART is programmed in asynchronous operating mode (SYNC = 0), the receiver oversamples the RXD input line. The oversampling is either 16 or 8 times the Baud Rate Clock, depending on the OVER bit in the Mode Register (US_MR). The receiver samples the RXD line. If the line is sampled during one half of a bit time at 0, a start bit is detected and data, parity and stop bits are successively sampled on the bit rate clock. If the oversampling is 16, (OVER at 0), a start is detected at the eighth sample at 0. Then, data bits, parity bit and stop bit are sampled on each 16 sampling clock cycle. If the oversampling is 8 (OVER at 1), a start bit is detected at the fourth sample at 0. Then, data bits, parity bit and stop bit are sampled on each 8 sampling clock cycle. The number of data bits, first bit sent and parity mode are selected by the same fields and bits as the transmitter, i.e. respectively CHRL, MODE9, MSBF and PAR. For the synchronization mechanism only, the number of stop bits has no effect on the receiver as it considers only one stop bit, regardless of the field NBSTOP, so that resynchronization between the receiver and the transmitter can occur. Moreover, as soon as the stop bit is sampled, the receiver starts looking for a new start bit so that resynchronization can also be accomplished when the transmitter is operating with one stop bit. Figure 30-8 and Figure 30-9 illustrate start detection and character reception when USART operates in asynchronous mode. Figure 30-8. Asynchronous Start Detection Baud Rate Clock Sampling Clock (x16) RXD Sampling 1 2 3 4 5 6 7 8 1 2 3 4 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 D0 Sampling Start Detection RXD Sampling 1 Figure 30-9. 2 3 4 5 6 7 0 1 Start Rejection Asynchronous Character Reception Example: 8-bit, Parity Enabled Baud Rate Clock RXD Start Detection 16 16 16 16 16 16 16 16 16 16 samples samples samples samples samples samples samples samples samples samples D0 D1 D2 D3 D4 D5 D6 D7 Parity Bit Stop Bit SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 453 30.7.3.3 Synchronous Receiver In synchronous mode (SYNC = 1), the receiver samples the RXD signal on each rising edge of the Baud Rate Clock. If a low level is detected, it is considered as a start. All data bits, the parity bit and the stop bits are sampled and the receiver waits for the next start bit. Synchronous mode operations provide a high speed transfer capability. Configuration fields and bits are the same as in asynchronous mode. Figure 30-10 illustrates a character reception in synchronous mode. Figure 30-10. Synchronous Mode Character Reception Example: 8-bit, Parity Enabled 1 Stop Baud Rate Clock RXD Sampling Start D0 D1 D2 D3 D4 D5 D6 D7 Stop Bit Parity Bit 30.7.3.4 Receiver Operations When a character reception is completed, it is transferred to the Receive Holding Register (US_RHR) and the RXRDY bit in the Status Register (US_CSR) rises. If a character is completed while the RXRDY is set, the OVRE (Overrun Error) bit is set. The last character is transferred into US_RHR and overwrites the previous one. The OVRE bit is cleared by writing the Control Register (US_CR) with the RSTSTA (Reset Status) bit at 1. Figure 30-11. Receiver Status Baud Rate Clock RXD Start D0 Bit D1 D2 D3 Write US_CR Read US_RHR RXRDY OVRE 454 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 D4 D5 D6 D7 Parity Stop Start D0 Bit Bit Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit RSTSTA = 1 30.7.3.5 Parity The USART supports five parity modes selected by programming the PAR field in the Mode Register (US_MR). The PAR field also enables the Multidrop mode, see “Multidrop Mode” on page 456. Even and odd parity bit generation and error detection are supported. If even parity is selected, the parity generator of the transmitter drives the parity bit at 0 if a number of 1s in the character data bit is even, and at 1 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. If odd parity is selected, the parity generator of the transmitter drives the parity bit at 1 if a number of 1s in the character data bit is even, and at 0 if the number of 1s is odd. Accordingly, the receiver parity checker counts the number of received 1s and reports a parity error if the sampled parity bit does not correspond. If the mark parity is used, the parity generator of the transmitter drives the parity bit at 1 for all characters. The receiver parity checker reports an error if the parity bit is sampled at 0. If the space parity is used, the parity generator of the transmitter drives the parity bit at 0 for all characters. The receiver parity checker reports an error if the parity bit is sampled at 1. If parity is disabled, the transmitter does not generate any parity bit and the receiver does not report any parity error. Table 30-6 shows an example of the parity bit for the character 0x41 (character ASCII “A”) depending on the configuration of the USART. Because there are two bits at 1, 1 bit is added when a parity is odd, or 0 is added when a parity is even. Table 30-6. Parity Bit Examples Character Hexadecimal Binary Parity Bit Parity Mode A 0x41 0100 0001 1 Odd A 0x41 0100 0001 0 Even A 0x41 0100 0001 1 Mark A 0x41 0100 0001 0 Space A 0x41 0100 0001 None None When the receiver detects a parity error, it sets the PARE (Parity Error) bit in the Channel Status Register (US_CSR). The PARE bit can be cleared by writing the Control Register (US_CR) with the RSTSTA bit at 1. Figure 30-12 illustrates the parity bit status setting and clearing. Figure 30-12. Parity Error Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Bad Stop Parity Bit Bit RSTSTA = 1 Write US_CR PARE RXRDY SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 455 30.7.3.6 Multidrop Mode If the PAR field in the Mode Register (US_MR) is programmed to the value 0x6 or 0x07, the USART runs in Multidrop Mode. This mode differentiates the data characters and the address characters. Data is transmitted with the parity bit at 0 and addresses are transmitted with the parity bit at 1. If the USART is configured in multidrop mode, the receiver sets the PARE parity error bit when the parity bit is high and the transmitter is able to send a character with the parity bit high when the Control Register is written with the SENDA bit at 1. To handle parity error, the PARE bit is cleared when the Control Register is written with the bit RSTSTA at 1. The transmitter sends an address byte (parity bit set) when SENDA is written to US_CR. In this case, the next byte written to US_THR is transmitted as an address. Any character written in US_THR without having written the command SENDA is transmitted normally with the parity at 0. 30.7.3.7 Transmitter Timeguard The timeguard feature enables the USART interface with slow remote devices. The timeguard function enables the transmitter to insert an idle state on the TXD line between two characters. This idle state actually acts as a long stop bit. The duration of the idle state is programmed in the TG field of the Transmitter Timeguard Register (US_TTGR). When this field is programmed at zero no timeguard is generated. Otherwise, the transmitter holds a high level on TXD after each transmitted byte during the number of bit periods programmed in TG in addition to the number of stop bits. As illustrated in Figure 30-13, the behavior of TXRDY and TXEMPTY status bits is modified by the programming of a timeguard. TXRDY rises only when the start bit of the next character is sent, and thus remains at 0 during the timeguard transmission if a character has been written in US_THR. TXEMPTY remains low until the timeguard transmission is completed as the timeguard is part of the current character being transmitted. Figure 30-13. Timeguard Operations TG = 4 TG = 4 Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 Write US_THR TXRDY TXEMPTY 456 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 D7 Parity Stop Bit Bit Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Table 30-7 indicates the maximum length of a timeguard period that the transmitter can handle according to the baud rate. Table 30-7. Maximum Timeguard Length Depending on Baud Rate Baud Rate (bit/s) Bit time (µs) Timeguard (ms) 1200 833 212.50 9600 104 26.56 14400 69.4 17.71 19200 52.1 13.28 28800 34.7 8.85 33400 29.9 7.63 56000 17.9 4.55 57600 17.4 4.43 115200 8.7 2.21 30.7.3.8 Receiver Time-out The Receiver Time-out provides support in handling variable-length frames. This feature detects an idle condition on the RXD line. When a time-out is detected, the bit TIMEOUT in the Channel Status Register (US_CSR) rises and can generate an interrupt, thus indicating to the driver an end of frame. The time-out delay period (during which the receiver waits for a new character) is programmed in the TO field of the Receiver Time-out Register (US_RTOR). If the TO field is programmed at 0, the Receiver Time-out is disabled and no time-out is detected. The TIMEOUT bit in US_CSR remains at 0. Otherwise, the receiver loads a 16-bit counter with the value programmed in TO. This counter is decremented at each bit period and reloaded each time a new character is received. If the counter reaches 0, the TIMEOUT bit in the Status Register rises. Then, the user can either:  Stop the counter clock until a new character is received. This is performed by writing the Control Register (US_CR) with the STTTO (Start Time-out) bit at 1. In this case, the idle state on RXD before a new character is received will not provide a time-out. This prevents having to handle an interrupt before a character is received and allows waiting for the next idle state on RXD after a frame is received.  Obtain an interrupt while no character is received. This is performed by writing US_CR with the RETTO (Reload and Start Time-out) bit at 1. If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. If STTTO is performed, the counter clock is stopped until a first character is received. The idle state on RXD before the start of the frame does not provide a time-out. This prevents having to obtain a periodic interrupt and enables a wait of the end of frame when the idle state on RXD is detected. If RETTO is performed, the counter starts counting down immediately from the value TO. This enables generation of a periodic interrupt so that a user time-out can be handled, for example when no key is pressed on a keyboard. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 457 Figure 30-14 shows the block diagram of the Receiver Time-out feature. Figure 30-14. Receiver Time-out Block Diagram TO Baud Rate Clock 1 D Q Clock 16-bit Time-out Counter 16-bit Value = STTTO Character Received Load Clear TIMEOUT 0 RETTO Table 30-8 gives the maximum time-out period for some standard baud rates. Table 30-8. 458 Maximum Time-out Period Baud Rate (bit/s) Bit Time (µs) Time-out (ms) 600 1667 109225 1200 833 54613 2400 417 27306 4800 208 13653 9600 104 6827 14400 69 4551 19200 52 3413 28800 35 2276 33400 30 1962 56000 18 1170 57600 17 1138 200000 5 328 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 30.7.3.9 Framing Error The receiver is capable of detecting framing errors. A framing error happens when the stop bit of a received character is detected at level 0. This can occur if the receiver and the transmitter are fully desynchronized. A framing error is reported on the FRAME bit of the Channel Status Register (US_CSR). The FRAME bit is asserted in the middle of the stop bit as soon as the framing error is detected. It is cleared by writing the Control Register (US_CR) with the RSTSTA bit at 1. Figure 30-15. Framing Error Status Baud Rate Clock RXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit RSTSTA = 1 Write US_CR FRAME RXRDY 30.7.3.10 Transmit Break The user can request the transmitter to generate a break condition on the TXD line. A break condition drives the TXD line low during at least one complete character. It appears the same as a 0x00 character sent with the parity and the stop bits at 0. However, the transmitter holds the TXD line at least during one character until the user requests the break condition to be removed. A break is transmitted by writing the Control Register (US_CR) with the STTBRK bit at 1. This can be performed at any time, either while the transmitter is empty (no character in either the Shift Register or in US_THR) or when a character is being transmitted. If a break is requested while a character is being shifted out, the character is first completed before the TXD line is held low. Once STTBRK command is requested further STTBRK commands are ignored until the end of the break is completed. The break condition is removed by writing US_CR with the STPBRK bit at 1. If the STPBRK is requested before the end of the minimum break duration (one character, including start, data, parity and stop bits), the transmitter ensures that the break condition completes. The transmitter considers the break as though it is a character, i.e. the STTBRK and STPBRK commands are taken into account only if the TXRDY bit in US_CSR is at 1 and the start of the break condition clears the TXRDY and TXEMPTY bits as if a character is processed. Writing US_CR with the both STTBRK and STPBRK bits at 1 can lead to an unpredictable result. All STPBRK commands requested without a previous STTBRK command are ignored. A byte written into the Transmit Holding Register while a break is pending, but not started, is ignored. After the break condition, the transmitter returns the TXD line to 1 for a minimum of 12 bit times. Thus, the transmitter ensures that the remote receiver detects correctly the end of break and the start of the next character. If the timeguard is programmed with a value higher than 12, the TXD line is held high for the timeguard period. After holding the TXD line for this period, the transmitter resumes normal operations. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 459 Figure 30-16 illustrates the effect of both the Start Break (STTBRK) and Stop Break (STPBRK) commands on the TXD line. Figure 30-16. Break Transmission Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit STTBRK = 1 Break Transmission End of Break STPBRK = 1 Write US_CR TXRDY TXEMPTY 30.7.3.11 Receive Break The receiver detects a break condition when all data, parity and stop bits are low. This corresponds to detecting a framing error with data at 0x00, but FRAME remains low. When the low stop bit is detected, the receiver asserts the RXBRK bit in US_CSR. This bit may be cleared by writing the Control Register (US_CR) with the bit RSTSTA at 1. An end of receive break is detected by a high level for at least 2/16 of a bit period in asynchronous operating mode or one sample at high level in synchronous operating mode. The end of break detection also asserts the RXBRK bit. 30.7.3.12 Hardware Handshaking The USART features a hardware handshaking out-of-band flow control. The RTS and CTS pins are used to connect with the remote device, as shown in Figure 30-17. Figure 30-17. Connection with a Remote Device for Hardware Handshaking USART Remote Device TXD RXD RXD TXD CTS RTS RTS CTS Setting the USART to operate with hardware handshaking is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x2. The USART behavior when hardware handshaking is enabled is the same as the behavior in standard synchronous or asynchronous mode, except that the receiver drives the RTS pin as described below and the level on the CTS pin modifies the behavior of the transmitter as described below. Using this mode requires using the PDC channel for reception. The transmitter can handle hardware handshaking in any case. 460 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 Figure 30-18 shows how the receiver operates if hardware handshaking is enabled. The RTS pin is driven high if the receiver is disabled and if the status RXBUFF (Receive Buffer Full) coming from the PDC channel is high. Normally, the remote device does not start transmitting while its CTS pin (driven by RTS) is high. As soon as the Receiver is enabled, the RTS falls, indicating to the remote device that it can start transmitting. Defining a new buffer to the PDC clears the status bit RXBUFF and, as a result, asserts the pin RTS low. Figure 30-18. Receiver Behavior when Operating with Hardware Handshaking RXD RXEN = 1 RXDIS = 1 Write US_CR RTS RXBUFF Figure 30-19 shows how the transmitter operates if hardware handshaking is enabled. The CTS pin disables the transmitter. If a character is being processing, the transmitter is disabled only after the completion of the current character and transmission of the next character happens as soon as the pin CTS falls. Figure 30-19. Transmitter Behavior when Operating with Hardware Handshaking CTS TXD 30.7.4 ISO7816 Mode The USART features an ISO7816-compatible operating mode. This mode permits interfacing with smart cards and Security Access Modules (SAM) communicating through an ISO7816 link. Both T = 0 and T = 1 protocols defined by the ISO7816 specification are supported. Setting the USART in ISO7816 mode is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x4 for protocol T = 0 and to the value 0x5 for protocol T = 1. 30.7.4.1 ISO7816 Mode Overview The ISO7816 is a half duplex communication on only one bidirectional line. The baud rate is determined by a division of the clock provided to the remote device (see “Baud Rate Generator” on page 447). The USART connects to a smart card as shown in Figure 30-20. The TXD line becomes bidirectional and the Baud Rate Generator feeds the ISO7816 clock on the SCK pin. As the TXD pin becomes bidirectional, its output remains driven by the output of the transmitter but only when the transmitter is active while its input is directed to the input of the receiver. The USART is considered as the master of the communication as it generates the clock. Figure 30-20. Connection of a Smart Card to the USART USART SCK TXD CLK I/O Smart Card SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 461 When operating in ISO7816, either in T = 0 or T = 1 modes, the character format is fixed. The configuration is 8 data bits, even parity and 1 or 2 stop bits, regardless of the values programmed in the CHRL, MODE9, PAR and CHMODE fields. MSBF can be used to transmit LSB or MSB first. Parity Bit (PAR) can be used to transmit in normal or inverse mode. Refer to “USART Mode Register” on page 474 and “PAR: Parity Type” on page 475. The USART cannot operate concurrently in both receiver and transmitter modes as the communication is unidirectional at a time. It has to be configured according to the required mode by enabling or disabling either the receiver or the transmitter as desired. Enabling both the receiver and the transmitter at the same time in ISO7816 mode may lead to unpredictable results. The ISO7816 specification defines an inverse transmission format. Data bits of the character must be transmitted on the I/O line at their negative value. The USART does not support this format and the user has to perform an exclusive OR on the data before writing it in the Transmit Holding Register (US_THR) or after reading it in the Receive Holding Register (US_RHR). 30.7.4.2 Protocol T = 0 In T = 0 protocol, a character is made up of one start bit, eight data bits, one parity bit and one guard time, which lasts two bit times. The transmitter shifts out the bits and does not drive the I/O line during the guard time. If no parity error is detected, the I/O line remains at 1 during the guard time and the transmitter can continue with the transmission of the next character, as shown in Figure 30-21. If a parity error is detected by the receiver, it drives the I/O line at 0 during the guard time, as shown in Figure 3022. This error bit is also named NACK, for Non Acknowledge. In this case, the character lasts 1 bit time more, as the guard time length is the same and is added to the error bit time which lasts 1 bit time. When the USART is the receiver and it detects an error, it does not load the erroneous character in the Receive Holding Register (US_RHR). It appropriately sets the PARE bit in the Status Register (US_SR) so that the software can handle the error. Figure 30-21. T = 0 Protocol without Parity Error Baud Rate Clock RXD Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Guard Guard Next Bit Time 1 Time 2 Start Bit Figure 30-22. T = 0 Protocol with Parity Error Baud Rate Clock Error I/O Start Bit D0 D1 D2 D3 D4 D5 D6 D7 Parity Guard Bit Time 1 Guard Start Time 2 Bit D0 D1 Repetition Receive Error Counter The USART receiver also records the total number of errors. This can be read in the Number of Error (US_NER) register. The NB_ERRORS field can record up to 255 errors. Reading US_NER automatically clears the NB_ERRORS field. 462 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 Receive NACK Inhibit The USART can also be configured to inhibit an error. This can be achieved by setting the INACK bit in the Mode Register (US_MR). If INACK is at 1, no error signal is driven on the I/O line even if a parity bit is detected, but the INACK bit is set in the Status Register (US_SR). The INACK bit can be cleared by writing the Control Register (US_CR) with the RSTNACK bit at 1. Moreover, if INACK is set, the erroneous received character is stored in the Receive Holding Register, as if no error occurred. However, the RXRDY bit does not raise. Transmit Character Repetition When the USART is transmitting a character and gets a NACK, it can automatically repeat the character before moving on to the next one. Repetition is enabled by writing the MAX_ITERATION field in the Mode Register (US_MR) at a value higher than 0. Each character can be transmitted up to eight times; the first transmission plus seven repetitions. If MAX_ITERATION does not equal zero, the USART repeats the character as many times as the value loaded in MAX_ITERATION. When the USART repetition number reaches MAX_ITERATION, the ITERATION bit is set in the Channel Status Register (US_CSR). If the repetition of the character is acknowledged by the receiver, the repetitions are stopped and the iteration counter is cleared. The ITERATION bit in US_CSR can be cleared by writing the Control Register with the RSIT bit at 1. Disable Successive Receive NACK The receiver can limit the number of successive NACKs sent back to the remote transmitter. This is programmed by setting the bit DSNACK in the Mode Register (US_MR). The maximum number of NACK transmitted is programmed in the MAX_ITERATION field. As soon as MAX_ITERATION is reached, the character is considered as correct, an acknowledge is sent on the line and the ITERATION bit in the Channel Status Register is set. 30.7.4.3 Protocol T = 1 When operating in ISO7816 protocol T = 1, the transmission is similar to an asynchronous format with only one stop bit. The parity is generated when transmitting and checked when receiving. Parity error detection sets the PARE bit in the Channel Status Register (US_CSR). SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 463 30.7.5 IrDA Mode The USART features an IrDA mode supplying half-duplex point-to-point wireless communication. It embeds the modulator and demodulator which allows a glueless connection to the infrared transceivers, as shown in Figure 30-23. The modulator and demodulator are compliant with the IrDA specification version 1.1 and support data transfer speeds ranging from 2.4 kbit/s to 115.2 kbit/s. The USART IrDA mode is enabled by setting the USART_MODE field in the Mode Register (US_MR) to the value 0x8. The IrDA Filter Register (US_IF) allows configuring the demodulator filter. The USART transmitter and receiver operate in a normal asynchronous mode and all parameters are accessible. Note that the modulator and the demodulator are activated. Figure 30-23. Connection to IrDA Transceivers USART IrDA Transceivers Receiver Demodulator Transmitter Modulator RXD RX TX TXD The receiver and the transmitter must be enabled or disabled according to the direction of the transmission to be managed. 464 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 30.7.5.1 IrDA Modulation For baud rates up to and including 115.2 kbit/s, the RZI modulation scheme is used. “0” is represented by a light pulse of 3/16th of a bit time. Some examples of signal pulse duration are shown in Table 30-9. Table 30-9. IrDA Pulse Duration Baud Rate Pulse Duration (3/16) 2.4 kbit/s 78.13 µs 9.6 kbit/s 19.53 µs 19.2 kbit/s 9.77 µs 38.4 kbit/s 4.88 µs 57.6 kbit/s 3.26 µs 115.2 kbit/s 1.63 µs Figure 30-24 shows an example of character transmission. Figure 30-24. IrDA Modulation Start Bit Transmitter Output 0 Stop Bit Data Bits 1 0 1 0 0 1 1 0 1 TXD Bit Period 3 16 Bit Period SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 465 30.7.5.2 IrDA Baud Rate Table 30-10 gives some examples of CD values, baud rate error and pulse duration. Note that the requirement on the maximum acceptable error of ±1.87% must be met. Table 30-10. 466 IrDA Baud Rate Error Peripheral Clock Baud Rate (bit/s) CD Baud Rate Error Pulse Time (µs) 3 686 400 115 200 2 0.00% 1.63 20 000 000 115 200 11 1.38% 1.63 32 768 000 115 200 18 1.25% 1.63 40 000 000 115 200 22 1.38% 1.63 3 686 400 57 600 4 0.00% 3.26 20 000 000 57 600 22 1.38% 3.26 32 768 000 57 600 36 1.25% 3.26 40 000 000 57 600 43 0.93% 3.26 3 686 400 38 400 6 0.00% 4.88 20 000 000 38 400 33 1.38% 4.88 32 768 000 38 400 53 0.63% 4.88 40 000 000 38 400 65 0.16% 4.88 3 686 400 19 200 12 0.00% 9.77 20 000 000 19 200 65 0.16% 9.77 32 768 000 19 200 107 0.31% 9.77 40 000 000 19 200 130 0.16% 9.77 3 686 400 9 600 24 0.00% 19.53 20 000 000 9 600 130 0.16% 19.53 32 768 000 9 600 213 0.16% 19.53 40 000 000 9 600 260 0.16% 19.53 3 686 400 2 400 96 0.00% 78.13 20 000 000 2 400 521 0.03% 78.13 32 768 000 2 400 853 0.04% 78.13 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 30.7.5.3 IrDA Demodulator The demodulator is based on the IrDA Receive filter comprised of an 8-bit down counter which is loaded with the value programmed in US_IF. When a falling edge is detected on the RXD pin, the Filter Counter starts counting down at the Master Clock (MCK) speed. If a rising edge is detected on the RXD pin, the counter stops and is reloaded with US_IF. If no rising edge is detected when the counter reaches 0, the input of the receiver is driven low during one bit time. Figure 30-25 illustrates the operations of the IrDA demodulator. Figure 30-25. IrDA Demodulator Operations MCK RXD Counter Value Receiver Input 6 5 4 3 Pulse Rejected 2 6 6 5 4 3 2 1 0 Pulse Accepted As the IrDA mode uses the same logic as the ISO7816, note that the FI_DI_RATIO field in US_FIDI must be set to a value higher than 0 in order to assure IrDA communications operate correctly. 30.7.6 RS485 Mode The USART features the RS485 mode to enable line driver control. While operating in RS485 mode, the USART behaves as though in asynchronous or synchronous mode and configuration of all the parameters is possible. The difference is that the RTS pin is driven high when the transmitter is operating. The behavior of the RTS pin is controlled by the TXEMPTY bit. A typical connection of the USART to a RS485 bus is shown in Figure 30-26. Figure 30-26. Typical Connection to a RS485 Bus USART RXD TXD Differential Bus RTS The USART is set in RS485 mode by programming the USART_MODE field in the Mode Register (US_MR) to the value 0x1. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 467 The RTS pin is at a level inverse to the TXEMPTY bit. Significantly, the RTS pin remains high when a timeguard is programmed so that the line can remain driven after the last character completion. Figure 30-27 gives an example of the RTS waveform during a character transmission when the timeguard is enabled. Figure 30-27. Example of RTS Drive with Timeguard TG = 4 Baud Rate Clock TXD Start D0 Bit D1 D2 D3 D4 D5 D6 D7 Parity Stop Bit Bit Write US_THR TXRDY TXEMPTY RTS 30.7.7 Modem Mode The USART features modem mode, which enables control of the signals: DTR (Data Terminal Ready), DSR (Data Set Ready), RTS (Request to Send), CTS (Clear to Send), DCD (Data Carrier Detect) and RI (Ring Indicator). While operating in modem mode, the USART behaves as a DTE (Data Terminal Equipment) as it drives DTR and RTS and can detect level change on DSR, DCD, CTS and RI. Setting the USART in modem mode is performed by writing the USART_MODE field in the Mode Register (US_MR) to the value 0x3. While operating in modem mode the USART behaves as though in asynchronous mode and all the parameter configurations are available. Table 30-11 gives the correspondence of the USART signals with modem connection standards. Table 30-11. Circuit References USART Pin V24 CCITT Direction TXD 2 103 From terminal to modem RTS 4 105 From terminal to modem DTR 20 108.2 From terminal to modem RXD 3 104 From modem to terminal CTS 5 106 From terminal to modem DSR 6 107 From terminal to modem DCD 8 109 From terminal to modem RI 22 125 From terminal to modem The control of the DTR output pin is performed by writing the Control Register (US_CR) with the DTRDIS and DTREN bits respectively at 1. The disable command forces the corresponding pin to its inactive level, i.e. high. The enable command forces the corresponding pin to its active level, i.e. low. RTS output pin is automatically controlled in this mode. 468 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 The level changes are detected on the RI, DSR, DCD and CTS pins. If an input change is detected, the RIIC, DSRIC, DCDIC and CTSIC bits in the Channel Status Register (US_CSR) are set respectively and can trigger an interrupt. The status is automatically cleared when US_CSR is read. Furthermore, the CTS automatically disables the transmitter when it is detected at its inactive state. If a character is being transmitted when the CTS rises, the character transmission is completed before the transmitter is actually disabled. 30.7.8 Test Modes The USART can be programmed to operate in three different test modes. The internal loopback capability allows on-board diagnostics. In the loopback mode the USART interface pins are disconnected or not and reconfigured for loopback internally or externally. 30.7.8.1 Normal Mode Normal mode connects the RXD pin on the receiver input and the transmitter output on the TXD pin. Figure 30-28. Normal Mode Configuration RXD Receiver TXD Transmitter 30.7.8.2 Automatic Echo Mode Automatic echo mode allows bit-by-bit retransmission. When a bit is received on the RXD pin, it is sent to the TXD pin, as shown in Figure 30-29. Programming the transmitter has no effect on the TXD pin. The RXD pin is still connected to the receiver input, thus the receiver remains active. Figure 30-29. Automatic Echo Mode Configuration RXD Receiver TXD Transmitter 30.7.8.3 Local Loopback Mode Local loopback mode connects the output of the transmitter directly to the input of the receiver, as shown in Figure 30-30. The TXD and RXD pins are not used. The RXD pin has no effect on the receiver and the TXD pin is continuously driven high, as in idle state. Figure 30-30. Local Loopback Mode Configuration RXD Receiver Transmitter 1 TXD SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 469 30.7.8.4 Remote Loopback Mode Remote loopback mode directly connects the RXD pin to the TXD pin, as shown in Figure 30-31. The transmitter and the receiver are disabled and have no effect. This mode allows bit-by-bit retransmission. Figure 30-31. Remote Loopback Mode Configuration Receiver 1 RXD TXD Transmitter 470 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 30.8 Universal Synchronous Asynchronous Receiver Transmitter (USART) User Interface Table 30-12. Register Mapping Offset Register Name Access Reset 0x0000 Control Register US_CR Write-only – 0x0004 Mode Register US_MR Read/Write 0x0 0x0008 Interrupt Enable Register US_IER Write-only – 0x000C Interrupt Disable Register US_IDR Write-only – 0x0010 Interrupt Mask Register US_IMR Read-only 0x0 0x0014 Channel Status Register US_CSR Read-only 0x0 0x0018 Receiver Holding Register US_RHR Read-only 0x0 0x001C Transmitter Holding Register US_THR Write-only – 0x0020 Baud Rate Generator Register US_BRGR Read/Write 0x0 0x0024 Receiver Time-out Register US_RTOR Read/Write 0x0 0x0028 Transmitter Timeguard Register US_TTGR Read/Write 0x0 Reserved – – – 0x0040 FI DI Ratio Register US_FIDI Read/Write 0x174 0x0044 Number of Errors Register US_NER Read-only 0x0 0x0048 Reserved – – – 0x004C IrDA Filter Register US_IF Read/Write 0x0 Reserved – – – Reserved for PDC Registers – – – 0x2C–0x3C 0x5C–0xFC 0x100–0x128 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 471 30.8.1 USART Control Register Name: US_CR Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 RTSDIS 18 RTSEN 17 DTRDIS 16 DTREN 15 RETTO 14 RSTNACK 13 RSTIT 12 SENDA 11 STTTO 10 STPBRK 9 STTBRK 8 RSTSTA 7 TXDIS 6 TXEN 5 RXDIS 4 RXEN 3 RSTTX 2 RSTRX 1 – 0 – • RSTRX: Reset Receiver 0: No effect. 1: Resets the receiver. • RSTTX: Reset Transmitter 0: No effect. 1: Resets the transmitter. • RXEN: Receiver Enable 0: No effect. 1: Enables the receiver, if RXDIS is 0. • RXDIS: Receiver Disable 0: No effect. 1: Disables the receiver. • TXEN: Transmitter Enable 0: No effect. 1: Enables the transmitter if TXDIS is 0. • TXDIS: Transmitter Disable 0: No effect. 1: Disables the transmitter. • RSTSTA: Reset Status Bits 0: No effect. 1: Resets the status bits PARE, FRAME, OVRE and RXBRK in US_CSR. 472 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 • STTBRK: Start Break 0: No effect. 1: Starts transmission of a break after the characters present in US_THR and the Transmit Shift Register have been transmitted. No effect if a break is already being transmitted. • STPBRK: Stop Break 0: No effect. 1: Stops transmission of the break after a minimum of one character length and transmits a high level during 12-bit periods. No effect if no break is being transmitted. • STTTO: Start Time-out 0: No effect. 1: Starts waiting for a character before clocking the time-out counter. Resets the status bit TIMEOUT in US_CSR. • SENDA: Send Address 0: No effect. 1: In Multidrop Mode only, the next character written to the US_THR is sent with the address bit set. • RSTIT: Reset Iterations 0: No effect. 1: Resets ITERATION in US_CSR. No effect if the ISO7816 is not enabled. • RSTNACK: Reset Non Acknowledge 0: No effect 1: Resets NACK in US_CSR. • RETTO: Rearm Time-out 0: No effect 1: Restart Time-out • DTREN: Data Terminal Ready Enable 0: No effect. 1: Drives the pin DTR at 0. • DTRDIS: Data Terminal Ready Disable 0: No effect. 1: Drives the pin DTR to 1. • RTSEN: Request to Send Enable 0: No effect. 1: Drives the pin RTS to 0. • RTSDIS: Request to Send Disable 0: No effect. 1: Drives the pin RTS to 1. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 473 30.8.2 USART Mode Register Name: US_MR Access: Read/Write 31 – 30 – 29 – 28 FILTER 27 – 26 25 MAX_ITERATION 24 23 – 22 – 21 DSNACK 20 INACK 19 OVER 18 CLKO 17 MODE9 16 MSBF 14 13 12 11 10 PAR 9 8 SYNC 4 3 2 1 0 15 CHMODE NBSTOP 7 6 5 CHRL USCLKS • USART_MODE Value Mode of the USART 0 0 0 0 Normal 0 0 0 1 RS485 0 0 1 0 Hardware Handshaking 0 0 1 1 Modem 0 1 0 0 IS07816 Protocol: T = 0 0 1 1 0 IS07816 Protocol: T = 1 1 0 0 0 IrDA Others Reserved • USCLKS: Clock Selection Value Selected Clock 0 0 MCK 0 1 MCK/DIV (DIV = 8) 1 0 Reserved 1 1 SCK • CHRL: Character Length. Value Character Length 0 0 5 bits 0 1 6 bits 1 0 7 bits 1 1 8 bits • SYNC: Synchronous Mode Select 0: USART operates in Asynchronous Mode. 1: USART operates in Synchronous Mode. 474 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 USART_MODE • PAR: Parity Type Value Parity Type 0 0 0 Even parity 0 0 1 Odd parity 0 1 0 Parity forced to 0 (Space) 0 1 1 Parity forced to 1 (Mark) 1 0 x No parity 1 1 x Multidrop mode • NBSTOP: Number of Stop Bits Value Asynchronous (SYNC = 0) Synchronous (SYNC = 1) 0 0 1 stop bit 1 stop bit 0 1 1.5 stop bits Reserved 1 0 2 stop bits 2 stop bits 1 1 Reserved Reserved • CHMODE: Channel Mode Value Mode Description 0 0 Normal Mode 0 1 Automatic Echo. Receiver input is connected to the TXD pin. 1 0 Local Loopback. Transmitter output is connected to the Receiver Input.. 1 1 Remote Loopback. RXD pin is internally connected to the TXD pin. • MSBF: Bit Order 0: Least Significant Bit is sent/received first. 1: Most Significant Bit is sent/received first. • MODE9: 9-bit Character Length 0: CHRL defines character length. 1: 9-bit character length. • CLKO: Clock Output Select 0: The USART does not drive the SCK pin. 1: The USART drives the SCK pin if USCLKS does not select the external clock SCK. • OVER: Oversampling Mode 0: 16x Oversampling. 1: 8x Oversampling. • INACK: Inhibit Non Acknowledge 0: The NACK is generated. 1: The NACK is not generated. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 475 • DSNACK: Disable Successive NACK 0: NACK is sent on the ISO line as soon as a parity error occurs in the received character (unless INACK is set). 1: Successive parity errors are counted up to the value specified in the MAX_ITERATION field. These parity errors generate a NACK on the ISO line. As soon as this value is reached, no additional NACK is sent on the ISO line. The flag ITERATION is asserted. • MAX_ITERATION Defines the maximum number of iterations in mode ISO7816, protocol T = 0. • FILTER: Infrared Receive Line Filter 0: The USART does not filter the receive line. 1: The USART filters the receive line using a three-sample filter (1/16-bit clock) (2 over 3 majority). 476 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 30.8.3 USART Interrupt Enable Register Name: US_IER Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 CTSIC 18 DCDIC 17 DSRIC 16 RIIC 15 – 14 – 13 NACK 12 RXBUFF 11 TXBUFE 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 ENDTX 3 ENDRX 2 RXBRK 1 TXRDY 0 RXRDY • RXRDY: RXRDY Interrupt Enable • TXRDY: TXRDY Interrupt Enable • RXBRK: Receiver Break Interrupt Enable • ENDRX: End of Receive Transfer Interrupt Enable • ENDTX: End of Transmit Interrupt Enable • OVRE: Overrun Error Interrupt Enable • FRAME: Framing Error Interrupt Enable • PARE: Parity Error Interrupt Enable • TIMEOUT: Time-out Interrupt Enable • TXEMPTY: TXEMPTY Interrupt Enable • ITER: Iteration Interrupt Enable • TXBUFE: Buffer Empty Interrupt Enable • RXBUFF: Buffer Full Interrupt Enable • NACK: Non Acknowledge Interrupt Enable • RIIC: Ring Indicator Input Change Enable • DSRIC: Data Set Ready Input Change Enable • DCDIC: Data Carrier Detect Input Change Interrupt Enable • CTSIC: Clear to Send Input Change Interrupt Enable SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 477 30.8.4 USART Interrupt Disable Register Name: US_IDR Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 CTSIC 18 DCDIC 17 DSRIC 16 RIIC 15 – 14 – 13 NACK 12 RXBUFF 11 TXBUFE 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 ENDTX 3 ENDRX 2 RXBRK 1 TXRDY 0 RXRDY • RXRDY: RXRDY Interrupt Disable • TXRDY: TXRDY Interrupt Disable • RXBRK: Receiver Break Interrupt Disable • ENDRX: End of Receive Transfer Interrupt Disable • ENDTX: End of Transmit Interrupt Disable • OVRE: Overrun Error Interrupt Disable • FRAME: Framing Error Interrupt Disable • PARE: Parity Error Interrupt Disable • TIMEOUT: Time-out Interrupt Disable • TXEMPTY: TXEMPTY Interrupt Disable • ITER: Iteration Interrupt Enable • TXBUFE: Buffer Empty Interrupt Disable • RXBUFF: Buffer Full Interrupt Disable • NACK: Non Acknowledge Interrupt Disable • RIIC: Ring Indicator Input Change Disable • DSRIC: Data Set Ready Input Change Disable • DCDIC: Data Carrier Detect Input Change Interrupt Disable • CTSIC: Clear to Send Input Change Interrupt Disable 478 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 30.8.5 USART Interrupt Mask Register Name: US_IMR Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 CTSIC 18 DCDIC 17 DSRIC 16 RIIC 15 – 14 – 13 NACK 12 RXBUFF 11 TXBUFE 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 ENDTX 3 ENDRX 2 RXBRK 1 TXRDY 0 RXRDY • RXRDY: RXRDY Interrupt Mask • TXRDY: TXRDY Interrupt Mask • RXBRK: Receiver Break Interrupt Mask • ENDRX: End of Receive Transfer Interrupt Mask • ENDTX: End of Transmit Interrupt Mask • OVRE: Overrun Error Interrupt Mask • FRAME: Framing Error Interrupt Mask • PARE: Parity Error Interrupt Mask • TIMEOUT: Time-out Interrupt Mask • TXEMPTY: TXEMPTY Interrupt Mask • ITER: Iteration Interrupt Enable • TXBUFE: Buffer Empty Interrupt Mask • RXBUFF: Buffer Full Interrupt Mask • NACK: Non Acknowledge Interrupt Mask • RIIC: Ring Indicator Input Change Mask • DSRIC: Data Set Ready Input Change Mask • DCDIC: Data Carrier Detect Input Change Interrupt Mask • CTSIC: Clear to Send Input Change Interrupt Mask SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 479 30.8.6 USART Channel Status Register Name: US_CSR Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 CTS 22 DCD 21 DSR 20 RI 19 CTSIC 18 DCDIC 17 DSRIC 16 RIIC 15 – 14 – 13 NACK 12 RXBUFF 11 TXBUFE 10 ITER 9 TXEMPTY 8 TIMEOUT 7 PARE 6 FRAME 5 OVRE 4 ENDTX 3 ENDRX 2 RXBRK 1 TXRDY 0 RXRDY • RXRDY: Receiver Ready 0: No complete character has been received since the last read of US_RHR or the receiver is disabled. If characters were being received when the receiver was disabled, RXRDY changes to 1 when the receiver is enabled. 1: At least one complete character has been received and US_RHR has not yet been read. • TXRDY: Transmitter Ready 0: A character is in the US_THR waiting to be transferred to the Transmit Shift Register, or an STTBRK command has been requested, or the transmitter is disabled. As soon as the transmitter is enabled, TXRDY becomes 1. 1: There is no character in the US_THR. • RXBRK: Break Received/End of Break 0: No Break received or End of Break detected since the last RSTSTA. 1: Break Received or End of Break detected since the last RSTSTA. • ENDRX: End of Receiver Transfer 0: The End of Transfer signal from the Receive PDC channel is inactive. 1: The End of Transfer signal from the Receive PDC channel is active. • ENDTX: End of Transmitter Transfer 0: The End of Transfer signal from the Transmit PDC channel is inactive. 1: The End of Transfer signal from the Transmit PDC channel is active. • OVRE: Overrun Error 0: No overrun error has occurred since the last RSTSTA. 1: At least one overrun error has occurred since the last RSTSTA. • FRAME: Framing Error 0: No stop bit has been detected low since the last RSTSTA. 1: At least one stop bit has been detected low since the last RSTSTA. 480 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 • PARE: Parity Error 0: No parity error has been detected since the last RSTSTA. 1: At least one parity error has been detected since the last RSTSTA. • TIMEOUT: Receiver Time-out 0: There has not been a time-out since the last Start Time-out command (STTTO in US_CR) or the Time-out Register is 0. 1: There has been a time-out since the last Start Time-out command (STTTO in US_CR). • TXEMPTY: Transmitter Empty 0: There are characters in either US_THR or the Transmit Shift Register, or the transmitter is disabled. 1: There are no characters in US_THR, nor in the Transmit Shift Register. • ITER: Max number of Repetitions Reached 0: Maximum number of repetitions has not been reached since the last RSTSTA. 1: Maximum number of repetitions has been reached since the last RSTSTA. • TXBUFE: Transmission Buffer Empty 0: The signal Buffer Empty from the Transmit PDC channel is inactive. 1: The signal Buffer Empty from the Transmit PDC channel is active. • RXBUFF: Reception Buffer Full 0: The signal Buffer Full from the Receive PDC channel is inactive. 1: The signal Buffer Full from the Receive PDC channel is active. • NACK: Non Acknowledge 0: No Non Acknowledge has not been detected since the last RSTNACK. 1: At least one Non Acknowledge has been detected since the last RSTNACK. • RIIC: Ring Indicator Input Change Flag 0: No input change has been detected on the RI pin since the last read of US_CSR. 1: At least one input change has been detected on the RI pin since the last read of US_CSR. • DSRIC: Data Set Ready Input Change Flag 0: No input change has been detected on the DSR pin since the last read of US_CSR. 1: At least one input change has been detected on the DSR pin since the last read of US_CSR. • DCDIC: Data Carrier Detect Input Change Flag 0: No input change has been detected on the DCD pin since the last read of US_CSR. 1: At least one input change has been detected on the DCD pin since the last read of US_CSR. • CTSIC: Clear to Send Input Change Flag 0: No input change has been detected on the CTS pin since the last read of US_CSR. 1: At least one input change has been detected on the CTS pin since the last read of US_CSR. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 481 • RI: Image of RI Input 0: RI is at 0. 1: RI is at 1. • DSR: Image of DSR Input 0: DSR is at 0 1: DSR is at 1. • DCD: Image of DCD Input 0: DCD is at 0. 1: DCD is at 1. • CTS: Image of CTS Input 0: CTS is at 0. 1: CTS is at 1. 482 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 30.8.7 USART Receive Holding Register Name: US_RHR Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 RXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 RXCHR 7 6 5 4 3 2 1 0 RXCHR • RXCHR: Received Character Last character received if RXRDY is set. • RXSYNH: Received Sync 0: Last Character received is a Data. 1: Last Character received is a Command. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 483 30.8.8 USART Transmit Holding Register Name: US_THR Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 TXSYNH 14 – 13 – 12 – 11 – 10 – 9 – 8 TXCHR 7 6 5 4 3 2 1 0 TXCHR • TXCHR: Character to be Transmitted Next character to be transmitted after the current character if TXRDY is not set. • TXSYNH: Sync Field to be transmitted 0: The next character sent is encoded as a data. Start Frame Delimiter is DATA SYNC. 1: The next character sent is encoded as a command. Start Frame Delimiter is COMMAND SYNC. 484 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 30.8.9 USART Baud Rate Generator Register Name: US_BRGR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 17 FP– 16 15 14 13 12 11 10 9 8 3 2 1 0 CD 7 6 5 4 CD • CD: Clock Divider USART_MODE ≠ ISO7816 SYNC = 0 Value OVER = 0 OVER = 1 0 1–65535 SYNC = 1 USART_MODE = ISO7816 Baud Rate Clock Disabled Baud Rate = Selected Clock/16/CD Baud Rate = Selected Clock/8/CD Baud Rate = Selected Clock /CD Baud Rate = Selected Clock/CD/FI_DI_RATIO • FP: Fractional Part 0: Fractional divider is disabled. 1–7: Baudrate resolution, defined by FP × 1/8. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 485 30.8.10 USART Receiver Time-out Register Name: US_RTOR Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TO 7 6 5 4 TO • TO: Time-out Value 0: The Receiver Time-out is disabled. 1–65535: The Receiver Time-out is enabled and the Time-out delay is TO × Bit Period. 486 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 30.8.11 USART Transmitter Timeguard Register Name: US_TTGR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 TG • TG: Timeguard Value 0: The Transmitter Timeguard is disabled. 1–255: The Transmitter timeguard is enabled and the timeguard delay is TG × Bit Period. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 487 30.8.12 USART FI DI RATIO Register Name: US_FIDI Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 9 FI_DI_RATIO 8 7 6 5 4 3 2 1 0 FI_DI_RATIO • FI_DI_RATIO: FI Over DI Ratio Value 0: If ISO7816 mode is selected, the Baud Rate Generator generates no signal. 1–2047: If ISO7816 mode is selected, the baud rate is the clock provided on SCK divided by FI_DI_RATIO. 488 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 30.8.13 USART Number of Errors Register Name: US_NER Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 NB_ERRORS • NB_ERRORS: Number of Errors Total number of errors that occurred during an ISO7816 transfer. This register automatically clears when read. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 489 30.8.14 USART IrDA FILTER Register Name: US_IF Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 – 10 – 9 – 8 – 7 6 5 4 3 2 1 0 IRDA_FILTER • IRDA_FILTER: IrDA Filter Sets the filter of the IrDA demodulator. 490 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 31. Synchronous Serial Controller (SSC) 31.1 Description The Atmel Synchronous Serial Controller (SSC) provides a synchronous communication link with external devices. It supports many serial synchronous communication protocols generally used in audio and telecom applications such as I2S, Short Frame Sync, Long Frame Sync, etc. The SSC contains an independent receiver and transmitter and a common clock divider. The receiver and the transmitter each interface with three signals: the TD/RD signal for data, the TK/RK signal for the clock and the TF/RF signal for the Frame Sync. The transfers can be programmed to start automatically or on different events detected on the Frame Sync signal. The SSC’s high-level of programmability and its two dedicated PDC channels of up to 32 bits permit a continuous high bit rate data transfer without processor intervention. Featuring connection to two PDC channels, the SSC permits interfacing with low processor overhead to the following: 31.2  Codecs in master or slave mode  DAC through dedicated serial interface, particularly I2S  Magnetic card reader Embedded Characteristics  Provides serial synchronous communication links used in audio and telecom applications (with Codecs in Master or Slave Modes, I2S, TDM Buses, Magnetic Card Reader, etc.)  Contains an independent receiver and transmitter and a common clock divider  Offers a configurable frame sync and data length  Receiver and transmitter can be programmed to start automatically or on detection of different event on the frame sync signal  Receiver and transmitter include a data signal, a clock signal and a frame synchronization signal SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 491 31.3 Block Diagram Figure 31-1. Block Diagram System Bus APB Bridge PDC Peripheral Bus TF TK PMC TD MCK PIO SSC Interface RF RK Interrupt Control RD SSC Interrupt 31.4 Application Block Diagram Figure 31-2. Application Block Diagram OS or RTOS Driver Power Management Interrupt Management Test Management SSC Serial AUDIO 492 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 Codec Time Slot Management Frame Management Line Interface 31.5 Pin Name List Table 31-1. I/O Lines Description Pin Name 31.6 Pin Description Type RF Receiver Frame Synchro Input/Output RK Receiver Clock Input/Output RD Receiver Data Input TF Transmitter Frame Synchro Input/Output TK Transmitter Clock Input/Output TD Transmitter Data Output Product Dependencies 31.6.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. Before using the SSC receiver, the PIO controller must be configured to dedicate the SSC receiver I/O lines to the SSC peripheral mode. Before using the SSC transmitter, the PIO controller must be configured to dedicate the SSC transmitter I/O lines to the SSC peripheral mode. 31.6.2 Power Management The SSC is not continuously clocked. The SSC interface may be clocked through the Power Management Controller (PMC), therefore the programmer must first configure the PMC to enable the SSC clock. 31.6.3 Interrupt The SSC interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling interrupts requires programming the AIC before configuring the SSC. All SSC interrupts can be enabled/disabled configuring the SSC Interrupt mask register. Each pending and unmasked SSC interrupt will assert the SSC interrupt line. The SSC interrupt service routine can get the interrupt origin by reading the SSC interrupt status register. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 493 31.7 Functional Description This chapter contains the functional description of the following: SSC Functional Block, Clock Management, Data format, Start, Transmitter, Receiver and Frame Sync. The receiver and transmitter operate separately. However, they can work synchronously by programming the receiver to use the transmit clock and/or to start a data transfer when transmission starts. Alternatively, this can be done by programming the transmitter to use the receive clock and/or to start a data transfer when reception starts. The transmitter and the receiver can be programmed to operate with the clock signals provided on either the TK or RK pins. This allows the SSC to support many slave-mode data transfers. The maximum clock speed allowed on the TK and RK pins is the master clock divided by 2. Figure 31-3. SSC Functional Block Diagram Transmitter MCK TK Input Clock Divider Transmit Clock Controller RX clock TF RF Start Selector TX clock Clock Output Controller TK Frame Sync Controller TF Transmit Shift Register TX PDC APB Transmit Holding Register TD Transmit Sync Holding Register Load Shift User Interface Receiver RK Input Receive Clock RX Clock Controller TX Clock RF TF Start Selector Interrupt Control AIC 494 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 RK Frame Sync Controller RF Receive Shift Register RX PDC PDC Clock Output Controller Receive Holding Register Load Shift Receive Sync Holding Register RD 31.7.1 Clock Management The transmitter clock can be generated by:  an external clock received on the TK I/O pad  the receiver clock  the internal clock divider The receiver clock can be generated by:  an external clock received on the RK I/O pad  the transmitter clock  the internal clock divider Furthermore, the transmitter block can generate an external clock on the TK I/O pad, and the receiver block can generate an external clock on the RK I/O pad. This allows the SSC to support many Master and Slave Mode data transfers. 31.7.1.1 Clock Divider Figure 31-4. Divided Clock Block Diagram Clock Divider SSC_CMR MCK /2 12-bit Counter Divided Clock The Master Clock divider is determined by the 12-bit field DIV counter and comparator (so its maximal value is 4095) in the Clock Mode Register SSC_CMR, allowing a Master Clock division by up to 8190. The Divided Clock is provided to both the Receiver and Transmitter. When this field is programmed to 0, the Clock Divider is not used and remains inactive. When DIV is set to a value equal to or greater than 1, the Divided Clock has a frequency of Master Clock divided by 2 times DIV. Each level of the Divided Clock has a duration of the Master Clock multiplied by DIV. This ensures a 50% duty cycle for the Divided Clock regardless of whether the DIV value is even or odd. Figure 31-5. Divided Clock Generation Master Clock Divided Clock DIV = 1 Divided Clock Frequency = MCK/2 Master Clock Divided Clock DIV = 3 Divided Clock Frequency = MCK/6 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 495 31.7.1.2 Transmitter Clock Management The transmitter clock is generated from the receiver clock or the divider clock or an external clock scanned on the TK I/O pad. The transmitter clock is selected by the CKS field in SSC_TCMR (Transmit Clock Mode Register). Transmit Clock can be inverted independently by the CKI bits in SSC_TCMR. The transmitter can also drive the TK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_TCMR. The Transmit Clock Inversion (CKI) bits have no effect on the clock outputs. Programming the TCMR to select TK pin (CKS field) and at the same time Continuous Transmit Clock (CKO field) might lead to unpredictable results. Figure 31-6. Transmitter Clock Management TK (pin) Clock Output Tri_state Controller MUX Receiver Clock Divider Clock Data Transfer CKO CKS 496 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 INV MUX Tri-state Controller CKI CKG Transmitter Clock 31.7.1.3 Receiver Clock Management The receiver clock is generated from the transmitter clock or the divider clock or an external clock scanned on the RK I/O pad. The Receive Clock is selected by the CKS field in SSC_RCMR (Receive Clock Mode Register). Receive Clocks can be inverted independently by the CKI bits in SSC_RCMR. The receiver can also drive the RK I/O pad continuously or be limited to the actual data transfer. The clock output is configured by the SSC_RCMR. The Receive Clock Inversion (CKI) bits have no effect on the clock outputs. Programming the RCMR register to select RK pin (CKS field) and at the same time Continuous Receive Clock (CKO field) can lead to unpredictable results. Figure 31-7. Receiver Clock Management RK (pin) Tri-state Controller MUX Clock Output Transmitter Clock Divider Clock Data Transfer CKO CKS INV MUX Tri-state Controller CKI CKG Receiver Clock 31.7.1.4 Serial Clock Ratio Considerations The Transmitter and the Receiver can be programmed to operate with the clock signals provided on either the TK or RK pins. This allows the SSC to support many slave-mode data transfers. In this case, the maximum clock speed allowed on the RK pin is: ̶ Master Clock divided by 2 if Receiver Frame Synchro is input ̶ Master Clock divided by 3 if Receiver Frame Synchro is output In addition, the maximum clock speed allowed on the TK pin is: ̶ ̶ Master Clock divided by 6 if Transmit Frame Synchro is input Master Clock divided by 2 if Transmit Frame Synchro is output SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 497 31.7.2 Transmitter Operations A transmitted frame is triggered by a start event and can be followed by synchronization data before data transmission. The start event is configured by setting the Transmit Clock Mode Register (SSC_TCMR). See “Start” on page 499. The frame synchronization is configured setting the Transmit Frame Mode Register (SSC_TFMR). See “Frame Sync” on page 501. To transmit data, the transmitter uses a shift register clocked by the transmitter clock signal and the start mode selected in the SSC_TCMR. Data is written by the application to the SSC_THR then transferred to the shift register according to the data format selected. When both the SSC_THR and the transmit shift register are empty, the status flag TXEMPTY is set in SSC_SR. When the Transmit Holding register is transferred in the Transmit shift register, the status flag TXRDY is set in SSC_SR and additional data can be loaded in the holding register. Figure 31-8. Transmitter Block Diagram SSC_CR.TXEN SSC_SR.TXEN SSC_CR.TXDIS SSC_TFMR.DATDEF 1 RF Transmitter Clock TF Transmit Shift Register 0 SSC_TFMR.FSDEN SSC_TCMR.STTDLY SSC_TFMR.DATLEN 498 TD 0 SSC_TFMR.MSBF Start Selector SSC_TCMR.STTDLY SSC_TFMR.FSDEN SSC_TFMR.DATNB SSC_THR SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 1 SSC_TSHR SSC_TFMR.FSLEN 31.7.3 Receiver Operations A received frame is triggered by a start event and can be followed by synchronization data before data transmission. The start event is configured setting the Receive Clock Mode Register (SSC_RCMR). See Section 31.7.4 “Start”. The frame synchronization is configured setting the Receive Frame Mode Register (SSC_RFMR). See “Frame Sync” on page 501. The receiver uses a shift register clocked by the receiver clock signal and the start mode selected in the SSC_RCMR. The data is transferred from the shift register depending on the data format selected. When the receiver shift register is full, the SSC transfers this data in the holding register, the status flag RXRDY is set in SSC_SR and the data can be read in the receiver holding register. If another transfer occurs before read of the RHR register, the status flag OVERUN is set in SSC_SR and the receiver shift register is transferred in the RHR register. Figure 31-9. Receiver Block Diagram SSC_CR.RXEN SSC_SR.RXEN SSC_CR.RXDIS RF Receiver Clock TF Start Selector SSC_RFMR.MSBF SSC_RFMR.DATNB Receive Shift Register SSC_RSHR SSC_RHR SSC_RFMR.FSLEN SSC_RFMR.DATLEN RD SSC_RCMR.STTDLY 31.7.4 Start The transmitter and receiver can both be programmed to start their operations when an event occurs, respectively in the Transmit Start Selection (START) field of SSC_TCMR and in the Receive Start Selection (START) field of SSC_RCMR. Under the following conditions the start event is independently programmable:  Continuous. In this case, the transmission starts as soon as a word is written in SSC_THR and the reception starts as soon as the Receiver is enabled.  Synchronously with the transmitter/receiver  On detection of a falling/rising edge on TF/RF  On detection of a low level/high level on TF/RF  On detection of a level change or an edge on TF/RF A start can be programmed in the same manner on either side of the Transmit/Receive Clock Register (RCMR/TCMR). Thus, the start could be on TF (Transmit) or RF (Receive). Moreover, the Receiver can start when data is detected in the bit stream with the Compare Functions. Detection on TF/RF input/output is done by the field FSOS of the Transmit/Receive Frame Mode Register (TFMR/RFMR). SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 499 Figure 31-10. Transmit Start Mode TK TF (Input) Start = Low Level on TF Start = Falling Edge on TF Start = High Level on TF Start = Rising Edge on TF Start = Level Change on TF Start = Any Edge on TF TD (Output) TD (Output) X BO STTDLY BO X B1 STTDLY BO X TD (Output) B1 STTDLY TD (Output) BO X B1 STTDLY TD (Output) TD (Output) B1 BO X B1 BO B1 STTDLY X B1 BO BO B1 STTDLY Figure 31-11. Receive Pulse/Edge Start Modes RK RF (Input) Start = Low Level on RF Start = Falling Edge on RF Start = High Level on RF Start = Rising Edge on RF Start = Level Change on RF Start = Any Edge on RF RD (Input) RD (Input) X BO STTDLY BO X B1 STTDLY BO X RD (Input) B1 STTDLY RD (Input) BO X B1 STTDLY RD (Input) RD (Input) B1 BO X B1 BO B1 STTDLY X BO B1 BO B1 STTDLY 500 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 31.7.5 Frame Sync The Transmitter and Receiver Frame Sync pins, TF and RF, can be programmed to generate different kinds of frame synchronization signals. The Frame Sync Output Selection (FSOS) field in the Receive Frame Mode Register (SSC_RFMR) and in the Transmit Frame Mode Register (SSC_TFMR) are used to select the required waveform.  Programmable low or high levels during data transfer are supported.  Programmable high levels before the start of data transfers or toggling are also supported. If a pulse waveform is selected, the Frame Sync Length (FSLEN) field in SSC_RFMR and SSC_TFMR programs the length of the pulse, from 1 bit time up to 16 bit time. The periodicity of the Receive and Transmit Frame Sync pulse output can be programmed through the Period Divider Selection (PERIOD) field in SSC_RCMR and SSC_TCMR. 31.7.5.1 Frame Sync Data Frame Sync Data transmits or receives a specific tag during the Frame Sync signal. During the Frame Sync signal, the Receiver can sample the RD line and store the data in the Receive Sync Holding Register and the transmitter can transfer Transmit Sync Holding Register in the Shifter Register. The data length to be sampled/shifted out during the Frame Sync signal is programmed by the FSLEN field in SSC_RFMR/SSC_TFMR and has a maximum value of 16. Concerning the Receive Frame Sync Data operation, if the Frame Sync Length is equal to or lower than the delay between the start event and the actual data reception, the data sampling operation is performed in the Receive Sync Holding Register through the Receive Shift Register. The Transmit Frame Sync Operation is performed by the transmitter only if the bit Frame Sync Data Enable (FSDEN) in SSC_TFMR is set. If the Frame Sync length is equal to or lower than the delay between the start event and the actual data transmission, the normal transmission has priority and the data contained in the Transmit Sync Holding Register is transferred in the Transmit Register, then shifted out. 31.7.5.2 Frame Sync Edge Detection The Frame Sync Edge detection is programmed by the FSEDGE field in SSC_RFMR/SSC_TFMR. This sets the corresponding flags RXSYN/TXSYN in the SSC Status Register (SSC_SR) on frame synchro edge detection (signals RF/TF). 31.7.6 Receive Compare Modes Figure 31-12. Receive Compare Modes RK RD (Input) CMP0 CMP1 CMP2 CMP3 Ignored B0 B1 B2 Start FSLEN Up to 16 Bits (4 in This Example) STDLY DATLEN SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 501 31.7.6.1 Compare Functions Length of the comparison patterns (Compare 0, Compare 1) and thus the number of bits they are compared to is defined by FSLEN, but with a maximum value of 16 bits. Comparison is always done by comparing the last bits received with the comparison pattern. Compare 0 can be one start event of the Receiver. In this case, the receiver compares at each new sample the last bits received at the Compare 0 pattern contained in the Compare 0 Register (SSC_RC0R). When this start event is selected, the user can program the Receiver to start a new data transfer either by writing a new Compare 0, or by receiving continuously until Compare 1 occurs. This selection is done with the bit (STOP) in SSC_RCMR. 31.7.7 Data Format The data framing format of both the transmitter and the receiver are programmable through the Transmitter Frame Mode Register (SSC_TFMR) and the Receiver Frame Mode Register (SSC_RFMR). In either case, the user can independently select:  the event that starts the data transfer (START)  the delay in number of bit periods between the start event and the first data bit (STTDLY)  the length of the data (DATLEN)  the number of data to be transferred for each start event (DATNB).  the length of synchronization transferred for each start event (FSLEN)  the bit sense: most or lowest significant bit first (MSBF) Additionally, the transmitter can be used to transfer synchronization and select the level driven on the TD pin while not in data transfer operation. This is done respectively by the Frame Sync Data Enable (FSDEN) and by the Data Default Value (DATDEF) bits in SSC_TFMR. Table 31-2. Data Frame Registers Transmitter Receiver Field Length Comment SSC_TFMR SSC_RFMR DATLEN Up to 32 Size of word SSC_TFMR SSC_RFMR DATNB Up to 16 Number of words transmitted in frame SSC_TFMR SSC_RFMR MSBF SSC_TFMR SSC_RFMR FSLEN Up to 16 Size of Synchro data register SSC_TFMR DATDEF 0 or 1 Data default value ended SSC_TFMR FSDEN Most significant bit first Enable send SSC_TSHR SSC_TCMR SSC_RCMR PERIOD Up to 512 Frame size SSC_TCMR SSC_RCMR STTDLY Up to 255 Size of transmit start delay 502 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 Figure 31-13. Transmit and Receive Frame Format in Edge/Pulse Start Modes Start Start PERIOD TF/RF (1) FSLEN TD (If FSDEN = 1) Sync Data Data Data From SSC_THR From SSC_THR Default TD (If FSDEN = 0) RD Default From SSC_TSHR FromDATDEF Sync Data Data Data From SSC_THR From DATDEF Ignored From DATDEF Ignored Data To SSC_RHR To SSC_RHR DATLEN DATLEN STTDLY Sync Data Default From SSC_THR Data To SSC_RSHR Default FromDATDEF Sync Data DATNB Note: 1. Example of input on falling edge of TF/RF. Figure 31-14. Transmit Frame Format in Continuous Mode Start Data TD Default Data From SSC_THR From SSC_THR DATLEN DATLEN Start: 1. TXEMPTY set to 1 2. Write into the SSC_THR Note: 1. STTDLY is set to 0. In this example, SSC_THR is loaded twice. FSDEN value has no effect on the transmission. SyncData cannot be output in continuous mode. Figure 31-15. Receive Frame Format in Continuous Mode Start = Enable Receiver RD Note: 1. Data Data To SSC_RHR To SSC_RHR DATLEN DATLEN STTDLY is set to 0. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 503 31.7.8 Loop Mode The receiver can be programmed to receive transmissions from the transmitter. This is done by setting the Loop Mode (LOOP) bit in SSC_RFMR. In this case, RD is connected to TD, RF is connected to TF and RK is connected to TK. 31.7.9 Interrupt Most bits in SSC_SR have a corresponding bit in interrupt management registers. The SSC can be programmed to generate an interrupt when it detects an event. The interrupt is controlled by writing SSC_IER (Interrupt Enable Register) and SSC_IDR (Interrupt Disable Register) These registers enable and disable, respectively, the corresponding interrupt by setting and clearing the corresponding bit in SSC_IMR (Interrupt Mask Register), which controls the generation of interrupts by asserting the SSC interrupt line connected to the AIC. Figure 31-16. Interrupt Block Diagram SSC_IMR SSC_IER PDC SSC_IDR Set Clear TXBUFE ENDTX Transmitter TXRDY TXEMPTY TXSYNC Interrupt Control RXBUFF ENDRX Receiver RXRDY OVRUN RXSYNC 504 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 SSC Interrupt 31.8 SSC Application Examples The SSC can support several serial communication modes used in audio or high speed serial links. Some standard applications are shown in the following figures. All serial link applications supported by the SSC are not listed here. Figure 31-17. Audio Application Block Diagram Clock SCK TK Word Select WS I2S RECEIVER TF Data SD SSC TD RD Clock SCK RF Word Select WS RK MSB Data SD LSB MSB Right Channel Left Channel Figure 31-18. Codec Application Block Diagram Serial Data Clock (SCLK) TK Frame sync (FSYNC) TF Serial Data Out SSC CODEC TD Serial Data In RD RF RK Serial Data Clock (SCLK) Frame sync (FSYNC) First Time Slot Dstart Dend Serial Data Out Serial Data In SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 505 Figure 31-19. Time Slot Application Block Diagram SCLK TK FSYNC TF CODEC First Time Slot Data Out TD SSC RD Data in RF RK CODEC Second Time Slot Serial Data Clock (SCLK) Frame sync (FSYNC) First Time Slot Dstart Serial Data Out Serial Data in 506 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 Second Time Slot Dend 31.9 Synchronous Serial Controller (SSC) User Interface Table 31-3. Offset Register Mapping Register Name Access Reset 0x0 Control Register SSC_CR Write-only – 0x4 Clock Mode Register SSC_CMR Read/Write 0x0 0x8 Reserved – – – 0xC Reserved – – – 0x10 Receive Clock Mode Register SSC_RCMR Read/Write 0x0 0x14 Receive Frame Mode Register SSC_RFMR Read/Write 0x0 0x18 Transmit Clock Mode Register SSC_TCMR Read/Write 0x0 0x1C Transmit Frame Mode Register SSC_TFMR Read/Write 0x0 0x20 Receive Holding Register SSC_RHR Read-only 0x0 0x24 Transmit Holding Register SSC_THR Write-only – 0x28 Reserved – – – 0x2C Reserved – – – 0x30 Receive Sync. Holding Register SSC_RSHR Read-only 0x0 0x34 Transmit Sync. Holding Register SSC_TSHR Read/Write 0x0 0x38 Receive Compare 0 Register SSC_RC0R Read/Write 0x0 0x3C Receive Compare 1 Register SSC_RC1R Read/Write 0x0 0x40 Status Register SSC_SR Read-only 0x000000CC 0x44 Interrupt Enable Register SSC_IER Write-only – 0x48 Interrupt Disable Register SSC_IDR Write-only – 0x4C Interrupt Mask Register SSC_IMR Read-only 0x0 Reserved – – – Reserved for Peripheral Data Controller (PDC) – – – 0x50–0xFC 0x100–0x124 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 507 31.9.1 SSC Control Register Name: SSC_CR Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 SWRST 14 – 13 – 12 – 11 – 10 – 9 TXDIS 8 TXEN 7 – 6 – 5 – 4 – 3 – 2 – 1 RXDIS 0 RXEN • RXEN: Receive Enable 0: No effect. 1: Enables Receive if RXDIS is not set. • RXDIS: Receive Disable 0: No effect. 1: Disables Receive. If a character is currently being received, disables at end of current character reception. • TXEN: Transmit Enable 0: No effect. 1: Enables Transmit if TXDIS is not set. • TXDIS: Transmit Disable 0: No effect. 1: Disables Transmit. If a character is currently being transmitted, disables at end of current character transmission. • SWRST: Software Reset 0: No effect. 1: Performs a software reset. Has priority on any other bit in SSC_CR. 508 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 31.9.2 SSC Clock Mode Register Name: SSC_CMR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 10 9 8 7 6 5 4 1 0 DIV 3 2 DIV • DIV: Clock Divider 0: The Clock Divider is not active. Any Other Value: The Divided Clock equals the Master Clock divided by 2 times DIV. The maximum bit rate is MCK/2. The minimum bit rate is MCK/2 × 4095 = MCK/8190. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 509 31.9.3 SSC Receive Clock Mode Register Name: SSC_RCMR Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 10 9 8 PERIOD 23 22 21 20 STTDLY 15 – 7 14 – 13 – 12 STOP 11 6 5 CKI 4 3 CKO CKG START 2 1 0 CKS • CKS: Receive Clock Selection Value Selected Receive Clock 0x0 Divided Clock 0x1 TK Clock signal 0x2 RK pin 0x3 Reserved • CKO: Receive Clock Output Mode Selection Value Receive Clock Output Mode RK Pin 0x0 None 0x1 Continuous Receive Clock Output 0x2 Receive Clock only during data transfers Output 0x3–0x7 Input-only Reserved • CKI: Receive Clock Inversion 0: The data inputs (Data and Frame Sync signals) are sampled on Receive Clock falling edge. The Frame Sync signal output is shifted out on Receive Clock rising edge. 1: The data inputs (Data and Frame Sync signals) are sampled on Receive Clock rising edge. The Frame Sync signal output is shifted out on Receive Clock falling edge. CKI affects only the Receive Clock and not the output clock signal. • CKG: Receive Clock Gating Selection 510 Value Receive Clock Gating 0x0 None, continuous clock 0x1 Receive Clock enabled only if RF Low 0x2 Receive Clock enabled only if RF High 0x3 Reserved SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 • START: Receive Start Selection Value Receive Start 0x0 Continuous, as soon as the receiver is enabled, and immediately after the end of transfer of the previous data. 0x1 Transmit start 0x2 Detection of a low level on RF signal 0x3 Detection of a high level on RF signal 0x4 Detection of a falling edge on RF signal 0x5 Detection of a rising edge on RF signal 0x6 Detection of any level change on RF signal 0x7 Detection of any edge on RF signal 0x8 Compare 0 0x9–0xF Reserved • STOP: Receive Stop Selection 0: After completion of a data transfer when starting with a Compare 0, the receiver stops the data transfer and waits for a new compare 0. 1: After starting a receive with a Compare 0, the receiver operates in a continuous mode until a Compare 1 is detected. • STTDLY: Receive Start Delay If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of reception. When the Receiver is programmed to start synchronously with the Transmitter, the delay is also applied. Note: It is very important that STTDLY be set carefully. If STTDLY must be set, it should be done in relation to TAG (Receive Sync Data) reception. • PERIOD: Receive Period Divider Selection This field selects the divider to apply to the selected Receive Clock in order to generate a new Frame Sync Signal. If 0, no PERIOD signal is generated. If not 0, a PERIOD signal is generated each 2 × (PERIOD + 1) Receive Clock. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 511 31.9.4 SSC Receive Frame Mode Register Name: SSC_RFMR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 23 – 22 21 FSOS 20 19 18 15 – 14 – 13 – 12 – 11 7 MSBF 6 – 5 LOOP 4 3 25 – 24 FSEDGE 17 16 9 8 1 0 FSLEN 10 DATNB 2 DATLEN • DATLEN: Data Length 0: Forbidden value (1-bit data length not supported). Any other value: The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the PDC2 assigned to the Receiver. If DATLEN is lower or equal to 7, data transfers are in bytes. If DATLEN is between 8 and 15 (included), half-words are transferred, and for any other value, 32-bit words are transferred. • LOOP: Loop Mode 0: Normal operating mode. 1: RD is driven by TD, RF is driven by TF and TK drives RK. • MSBF: Most Significant Bit First 0: The lowest significant bit of the data register is sampled first in the bit stream. 1: The most significant bit of the data register is sampled first in the bit stream. • DATNB: Data Number per Frame This field defines the number of data words to be received after each transfer start, which is equal to (DATNB + 1). • FSLEN: Receive Frame Sync Length This field defines the number of bits sampled and stored in the Receive Sync Data Register. When this mode is selected by the START field in the Receive Clock Mode Register, it also determines the length of the sampled data to be compared to the Compare 0 or Compare 1 register. This field is used with FSLEN_EXT to determine the pulse length of the Receive Frame Sync signal. Pulse length is equal to FSLEN + 1 Receive Clock periods. 512 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 • FSOS: Receive Frame Sync Output Selection Value Selected Receive Frame Sync Signal RF Pin 0x0 None 0x1 Negative Pulse Output 0x2 Positive Pulse Output 0x3 Driven Low during data transfer Output 0x4 Driven High during data transfer Output 0x5 Toggling at each start of data transfer Output 0x6–0x7 Input-only Reserved Undefined • FSEDGE: Frame Sync Edge Detection Determines which edge on Frame Sync will generate the interrupt RXSYN in the SSC Status Register. Value Frame Sync Edge Detection 0x0 Positive Edge Detection 0x1 Negative Edge Detection SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 513 31.9.5 SSC Transmit Clock Mode Register Name: SSC_TCMR Access: Read/Write 31 30 29 28 27 26 25 24 19 18 17 16 10 9 8 PERIOD 23 22 21 20 STTDLY 15 – 7 14 – 13 – 12 – 11 6 5 CKI 4 3 CKO CKG START 2 1 0 CKS • CKS: Transmit Clock Selection Value Selected Transmit Clock 0x0 Divided Clock 0x1 RK Clock signal 0x2 TK Pin 0x3 Reserved • CKO: Transmit Clock Output Mode Selection Value Transmit Clock Output Mode TK pin 0x0 None 0x1 Continuous Transmit Clock Output 0x2 Transmit Clock only during data transfers Output 0x3–0x7 Input-only Reserved • CKI: Transmit Clock Inversion 0: The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock falling edge. The Frame sync signal input is sampled on Transmit clock rising edge. 1: The data outputs (Data and Frame Sync signals) are shifted out on Transmit Clock rising edge. The Frame sync signal input is sampled on Transmit clock falling edge. CKI affects only the Transmit Clock and not the output clock signal. • CKG: Transmit Clock Gating Selection Value 514 Transmit Clock Gating 0x0 None, continuous clock 0x1 Transmit Clock enabled only if TF Low 0x2 Transmit Clock enabled only if TF High 0x3 Reserved SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 • START: Transmit Start Selection Value Transmit Start 0x0 Continuous, as soon as a word is written in the SSC_THR Register (if Transmit is enabled), and immediately after the end of transfer of the previous data. 0x1 Receive start 0x2 Detection of a low level on TF signal 0x3 Detection of a high level on TF signal 0x4 Detection of a falling edge on TF signal 0x5 Detection of a rising edge on TF signal 0x6 Detection of any level change on TF signal 0x7 Detection of any edge on TF signal 0x8–0xF Reserved • STTDLY: Transmit Start Delay If STTDLY is not 0, a delay of STTDLY clock cycles is inserted between the start event and the actual start of transmission of data. When the Transmitter is programmed to start synchronously with the Receiver, the delay is also applied. Note: STTDLY must be set carefully. If STTDLY is too short in respect to TAG (Transmit Sync Data) emission, data is emitted instead of the end of TAG. • PERIOD: Transmit Period Divider Selection This field selects the divider to apply to the selected Transmit Clock to generate a new Frame Sync Signal. If 0, no period signal is generated. If not 0, a period signal is generated at each 2 × (PERIOD + 1) Transmit Clock. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 515 31.9.6 SSC Transmit Frame Mode Register Name: SSC_TFMR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 23 FSDEN 22 21 FSOS 20 19 18 15 – 14 – 13 – 12 – 11 7 MSBF 6 – 5 DATDEF 4 3 25 – 24 FSEDGE 17 16 9 8 1 0 FSLEN 10 DATNB 2 DATLEN • DATLEN: Data Length 0: Forbidden value (1-bit data length not supported). Any other value: The bit stream contains DATLEN + 1 data bits. Moreover, it defines the transfer size performed by the PDC2 assigned to the Transmit. If DATLEN is lower or equal to 7, data transfers are bytes, if DATLEN is between 8 and 15 (included), half-words are transferred, and for any other value, 32-bit words are transferred. • DATDEF: Data Default Value This bit defines the level driven on the TD pin while out of transmission. Note that if the pin is defined as multi-drive by the PIO Controller, the pin is enabled only if the SCC TD output is 1. • MSBF: Most Significant Bit First 0: The lowest significant bit of the data register is shifted out first in the bit stream. 1: The most significant bit of the data register is shifted out first in the bit stream. • DATNB: Data Number per frame This field defines the number of data words to be transferred after each transfer start, which is equal to (DATNB + 1). • FSLEN: Transmit Frame Sync Length This field defines the length of the Transmit Frame Sync signal and the number of bits shifted out from the Transmit Sync Data Register if FSDEN is 1. This field is used with FSLEN_EXT to determine the pulse length of the Transmit Frame Sync signal. Pulse length is equal to FSLEN + 1 Transmit Clock periods. 516 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 • FSOS: Transmit Frame Sync Output Selection Value Selected Transmit Frame Sync Signal TF Pin 0x0 None 0x1 Negative Pulse Output 0x2 Positive Pulse Output 0x3 Driven Low during data transfer Output 0x4 Driven High during data transfer Output 0x5 Toggling at each start of data transfer Output 0x6–0x7 Input-only Reserved Undefined • FSDEN: Frame Sync Data Enable 0: The TD line is driven with the default value during the Transmit Frame Sync signal. 1: SSC_TSHR value is shifted out during the transmission of the Transmit Frame Sync signal. • FSEDGE: Frame Sync Edge Detection Determines which edge on frame sync will generate the interrupt TXSYN (Status Register). Value Frame Sync Edge Detection 0x0 Positive Edge Detection 0x1 Negative Edge Detection SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 517 31.9.7 SSC Receive Holding Register Name: SSC_RHR Access: Read-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 RDAT 23 22 21 20 RDAT 15 14 13 12 RDAT 7 6 5 4 RDAT • RDAT: Receive Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_RFMR. 518 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 31.9.8 SSC Transmit Holding Register Name: SSC_THR Access: Write-only 31 30 29 28 27 26 25 24 19 18 17 16 11 10 9 8 3 2 1 0 TDAT 23 22 21 20 TDAT 15 14 13 12 TDAT 7 6 5 4 TDAT • TDAT: Transmit Data Right aligned regardless of the number of data bits defined by DATLEN in SSC_TFMR. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 519 31.9.9 SSC Receive Synchronization Holding Register Name: SSC_RSHR Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 RSDAT 7 6 5 4 RSDAT • RSDAT: Receive Synchronization Data 520 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 31.9.10 SSC Transmit Synchronization Holding Register Name: SSC_TSHR Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 TSDAT 7 6 5 4 TSDAT • TSDAT: Transmit Synchronization Data SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 521 31.9.11 SSC Receive Compare 0 Register Name: SSC_RC0R Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 CP0 7 6 5 4 CP0 • CP0: Receive Compare Data 0 522 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 31.9.12 SSC Receive Compare 1 Register Name: SSC_RC1R Access: Read/Write 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 14 13 12 11 10 9 8 3 2 1 0 CP1 7 6 5 4 CP1 • CP1: Receive Compare Data 1 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 523 31.9.13 SSC Status Register Name: SSC_SR Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 RXEN 16 TXEN 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUFF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready 0: Data has been loaded in SSC_THR and is waiting to be loaded in the Transmit Shift Register (TSR). 1: SSC_THR is empty. • TXEMPTY: Transmit Empty 0: Data remains in SSC_THR or is currently transmitted from TSR. 1: Last data written in SSC_THR has been loaded in TSR and last data loaded in TSR has been transmitted. • ENDTX: End of Transmission 0: The register SSC_TCR has not reached 0 since the last write in SSC_TCR or SSC_TNCR. 1: The register SSC_TCR has reached 0 since the last write in SSC_TCR or SSC_TNCR. • TXBUFE: Transmit Buffer Empty 0: SSC_TCR or SSC_TNCR have a value other than 0. 1: Both SSC_TCR and SSC_TNCR have a value of 0. • RXRDY: Receive Ready 0: SSC_RHR is empty. 1: Data has been received and loaded in SSC_RHR. • OVRUN: Receive Overrun 0: No data has been loaded in SSC_RHR while previous data has not been read since the last read of the Status Register. 1: Data has been loaded in SSC_RHR while previous data has not yet been read since the last read of the Status Register. • ENDRX: End of Reception 0: Data is written on the Receive Counter Register or Receive Next Counter Register. 1: End of PDC transfer when Receive Counter Register has arrived at zero. • RXBUFF: Receive Buffer Full 0: SSC_RCR or SSC_RNCR have a value other than 0. 1: Both SSC_RCR and SSC_RNCR have a value of 0. 524 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 • CP0: Compare 0 0: A compare 0 has not occurred since the last read of the Status Register. 1: A compare 0 has occurred since the last read of the Status Register. • CP1: Compare 1 0: A compare 1 has not occurred since the last read of the Status Register. 1: A compare 1 has occurred since the last read of the Status Register. • TXSYN: Transmit Sync 0: A Tx Sync has not occurred since the last read of the Status Register. 1: A Tx Sync has occurred since the last read of the Status Register. • RXSYN: Receive Sync 0: An Rx Sync has not occurred since the last read of the Status Register. 1: An Rx Sync has occurred since the last read of the Status Register. • TXEN: Transmit Enable 0: Transmit is disabled. 1: Transmit is enabled. • RXEN: Receive Enable 0: Receive is disabled. 1: Receive is enabled. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 525 31.9.14 SSC Interrupt Enable Register Name: SSC_IER Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUFF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready Interrupt Enable 0: No effect. 1: Enables the Transmit Ready Interrupt. • TXEMPTY: Transmit Empty Interrupt Enable 0: No effect. 1: Enables the Transmit Empty Interrupt. • ENDTX: End of Transmission Interrupt Enable 0: No effect. 1: Enables the End of Transmission Interrupt. • TXBUFE: Transmit Buffer Empty Interrupt Enable 0: No effect. 1: Enables the Transmit Buffer Empty Interrupt • RXRDY: Receive Ready Interrupt Enable 0: No effect. 1: Enables the Receive Ready Interrupt. • OVRUN: Receive Overrun Interrupt Enable 0: No effect. 1: Enables the Receive Overrun Interrupt. • ENDRX: End of Reception Interrupt Enable 0: No effect. 1: Enables the End of Reception Interrupt. • RXBUFF: Receive Buffer Full Interrupt Enable 0: No effect. 1: Enables the Receive Buffer Full Interrupt. 526 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 • CP0: Compare 0 Interrupt Enable 0: No effect. 1: Enables the Compare 0 Interrupt. • CP1: Compare 1 Interrupt Enable 0: No effect. 1: Enables the Compare 1 Interrupt. • TXSYN: Tx Sync Interrupt Enable 0: No effect. 1: Enables the Tx Sync Interrupt. • RXSYN: Rx Sync Interrupt Enable 0: No effect. 1: Enables the Rx Sync Interrupt. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 527 31.9.15 SSC Interrupt Disable Register Name: SSC_IDR Access: Write-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUFF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready Interrupt Disable 0: No effect. 1: Disables the Transmit Ready Interrupt. • TXEMPTY: Transmit Empty Interrupt Disable 0: No effect. 1: Disables the Transmit Empty Interrupt. • ENDTX: End of Transmission Interrupt Disable 0: No effect. 1: Disables the End of Transmission Interrupt. • TXBUFE: Transmit Buffer Empty Interrupt Disable 0: No effect. 1: Disables the Transmit Buffer Empty Interrupt. • RXRDY: Receive Ready Interrupt Disable 0: No effect. 1: Disables the Receive Ready Interrupt. • OVRUN: Receive Overrun Interrupt Disable 0: No effect. 1: Disables the Receive Overrun Interrupt. • ENDRX: End of Reception Interrupt Disable 0: No effect. 1: Disables the End of Reception Interrupt. • RXBUFF: Receive Buffer Full Interrupt Disable 0: No effect. 1: Disables the Receive Buffer Full Interrupt. 528 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 • CP0: Compare 0 Interrupt Disable 0: No effect. 1: Disables the Compare 0 Interrupt. • CP1: Compare 1 Interrupt Disable 0: No effect. 1: Disables the Compare 1 Interrupt. • TXSYN: Tx Sync Interrupt Enable 0: No effect. 1: Disables the Tx Sync Interrupt. • RXSYN: Rx Sync Interrupt Enable 0: No effect. 1: Disables the Rx Sync Interrupt. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 529 31.9.16 SSC Interrupt Mask Register Name: SSC_IMR Access: Read-only 31 – 30 – 29 – 28 – 27 – 26 – 25 – 24 – 23 – 22 – 21 – 20 – 19 – 18 – 17 – 16 – 15 – 14 – 13 – 12 – 11 RXSYN 10 TXSYN 9 CP1 8 CP0 7 RXBUF 6 ENDRX 5 OVRUN 4 RXRDY 3 TXBUFE 2 ENDTX 1 TXEMPTY 0 TXRDY • TXRDY: Transmit Ready Interrupt Mask 0: The Transmit Ready Interrupt is disabled. 1: The Transmit Ready Interrupt is enabled. • TXEMPTY: Transmit Empty Interrupt Mask 0: The Transmit Empty Interrupt is disabled. 1: The Transmit Empty Interrupt is enabled. • ENDTX: End of Transmission Interrupt Mask 0: The End of Transmission Interrupt is disabled. 1: The End of Transmission Interrupt is enabled. • TXBUFE: Transmit Buffer Empty Interrupt Mask 0: The Transmit Buffer Empty Interrupt is disabled. 1: The Transmit Buffer Empty Interrupt is enabled. • RXRDY: Receive Ready Interrupt Mask 0: The Receive Ready Interrupt is disabled. 1: The Receive Ready Interrupt is enabled. • OVRUN: Receive Overrun Interrupt Mask 0: The Receive Overrun Interrupt is disabled. 1: The Receive Overrun Interrupt is enabled. • ENDRX: End of Reception Interrupt Mask 0: The End of Reception Interrupt is disabled. 1: The End of Reception Interrupt is enabled. • RXBUFF: Receive Buffer Full Interrupt Mask 0: The Receive Buffer Full Interrupt is disabled. 1: The Receive Buffer Full Interrupt is enabled. 530 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 • CP0: Compare 0 Interrupt Mask 0: The Compare 0 Interrupt is disabled. 1: The Compare 0 Interrupt is enabled. • CP1: Compare 1 Interrupt Mask 0: The Compare 1 Interrupt is disabled. 1: The Compare 1 Interrupt is enabled. • TXSYN: Tx Sync Interrupt Mask 0: The Tx Sync Interrupt is disabled. 1: The Tx Sync Interrupt is enabled. • RXSYN: Rx Sync Interrupt Mask 0: The Rx Sync Interrupt is disabled. 1: The Rx Sync Interrupt is enabled. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 531 32. Timer Counter (TC) 32.1 Description The Timer Counter (TC) includes three identical 16-bit Timer Counter channels. Each channel can be independently programmed to perform a wide range of functions including frequency measurement, event counting, interval measurement, pulse generation, delay timing and pulse width modulation. Each channel has three external clock inputs, five internal clock inputs and two multi-purpose input/output signals which can be configured by the user. Each channel drives an internal interrupt signal which can be programmed to generate processor interrupts. The Timer Counter block has two global registers which act upon all three TC channels. The Block Control Register allows the three channels to be started simultaneously with the same instruction. The Block Mode Register defines the external clock inputs for each channel, allowing them to be chained. Table 32-1 gives the assignment of the device Timer Counter clock inputs common to Timer Counter 0 to 2 Table 32-1. 32.2 Name Definition TIMER_CLOCK1 MCK/2 TIMER_CLOCK2 MCK/8 TIMER_CLOCK3 MCK/32 TIMER_CLOCK4 MCK/128 TIMER_CLOCK5 SLCK Embedded Characteristics  Two blocks of three 16-bit Timer Counter channels  Each channel can be individually programmed to perform a wide range of functions including:   Note: 532 Timer Counter Clock Assignment ̶ Frequency Measurement ̶ Event Counting ̶ Interval Measurement ̶ Pulse Generation ̶ Delay Timing ̶ Pulse Width Modulation ̶ Up/down Capabilities Each channel is user-configurable and contains: ̶ Three external clock inputs ̶ Five internal clock inputs ̶ Two multi-purpose input/output signals Each block contains two global registers that act on all three TC Channels TC Block 0 (TC0, TC1, TC2) and TC Block 1 (TC3, TC4, TC5) have identical user interfaces. See Figure 6-1, “SAM9260 Memory Mapping,” on page 19 for TC Block 0 and TC Block 1 base addresses. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 32.3 Block Diagram Figure 32-1. Timer Counter Block Diagram Parallel I/O Controller TIMER_CLOCK1 TCLK0 TIMER_CLOCK2 TIOA1 TIOA2 TIMER_CLOCK3 XC0 TCLK1 XC1 TCLK2 XC2 Timer/Counter Channel 0 TIOA TIOA0 TIOB0 TIOA0 TIOB TIMER_CLOCK4 TIMER_CLOCK5 TIOB0 TC0XC0S SYNC TCLK0 TCLK1 TCLK2 INT0 TCLK0 TCLK1 XC0 TIOA0 XC1 Timer/Counter Channel 1 TIOA TIOA1 TIOB1 TIOA1 TIOB TIOA2 TIOB1 XC2 TCLK2 SYNC TC1XC1S TCLK0 XC0 TCLK1 XC1 Timer/Counter Channel 2 INT1 TIOA TIOA2 TIOB2 TIOA2 TIOB TCLK2 XC2 TIOA0 TC2XC2S TIOA1 TIOB2 SYNC INT2 Timer Counter Advanced Interrupt Controller Table 32-2. Channel Signal Description Signal Name XC0, XC1, XC2 External Clock Inputs TIOA Capture Mode: Timer Counter Input Waveform Mode: Timer Counter Output TIOB Capture Mode: Timer Counter Input Waveform Mode: Timer Counter Input/Output INT SYNC 32.4 Description Interrupt Signal Output Synchronization Input Signal Pin Name List Table 32-3. TC Pin List Pin Name Description Type TCLK0–TCLK2 External Clock Input Input TIOA0–TIOA2 I/O Line A I/O TIOB0–TIOB2 I/O Line B I/O SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 533 32.5 Product Dependencies 32.5.1 I/O Lines The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the TC pins to their peripheral functions. 32.5.2 Power Management The TC is clocked through the Power Management Controller (PMC), thus the programmer must first configure the PMC to enable the Timer Counter clock. 32.5.3 Interrupt The TC has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the TC interrupt requires programming the AIC before configuring the TC. 32.6 Functional Description 32.6.1 TC Description The three channels of the Timer Counter are independent and identical in operation. The registers for channel programming are listed in Table 32-4 on page 546. 32.6.2 16-bit Counter Each channel is organized around a 16-bit counter. The value of the counter is incremented at each positive edge of the selected clock. When the counter has reached the value 0xFFFF and passes to 0x0000, an overflow occurs and the COVFS bit in TC_SR (Status Register) is set. The current value of the counter is accessible in real time by reading the Counter Value Register (TC_CV). The counter can be reset by a trigger. In this case, the counter value passes to 0x0000 on the next valid edge of the selected clock. 32.6.3 Clock Selection At block level, input clock signals of each channel can either be connected to the external inputs TCLK0, TCLK1 or TCLK2, or be connected to the internal I/O signals TIOA0, TIOA1 or TIOA2 for chaining by programming the TC_BMR (Block Mode). See Figure 32-2 on page 535. Each channel can independently select an internal or external clock source for its counter:  Internal clock signals: TIMER_CLOCK1, TIMER_CLOCK2, TIMER_CLOCK3, TIMER_CLOCK4, TIMER_CLOCK5  External clock signals: XC0, XC1 or XC2 This selection is made by the TCCLKS bits in the TC Channel Mode Register. The selected clock can be inverted with the CLKI bit in TC_CMR. This allows counting on the opposite edges of the clock. The burst function allows the clock to be validated when an external signal is high. The BURST parameter in the Mode Register defines this signal (none, XC0, XC1, XC2). See Figure 32-3 on page 535. Note: 534 In all cases, if an external clock is used, the duration of each of its levels must be longer than the master clock period. The external clock frequency must be at least 2.5 times lower than the master clock. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 Figure 32-2. Clock Chaining Selection TC0XC0S Timer/Counter Channel 0 TCLK0 TIOA1 XC0 TIOA2 TIOA0 XC1 = TCLK1 XC2 = TCLK2 TIOB0 SYNC TC1XC1S Timer/Counter Channel 1 TCLK1 XC0 = TCLK2 TIOA0 TIOA1 XC1 TIOA2 XC2 = TCLK2 TIOB1 SYNC Timer/Counter Channel 2 TC2XC2S XC0 = TCLK0 TCLK2 TIOA2 XC1 = TCLK1 TIOA0 XC2 TIOB2 TIOA1 SYNC Figure 32-3. Clock Selection TCCLKS TIMER_CLOCK1 TIMER_CLOCK2 CLKI TIMER_CLOCK3 TIMER_CLOCK4 TIMER_CLOCK5 Selected Clock XC0 XC1 XC2 BURST 1 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 535 32.6.4 Clock Control The clock of each counter can be controlled in two different ways: it can be enabled/disabled and started/stopped. See Figure 32-4.  The clock can be enabled or disabled by the user with the CLKEN and the CLKDIS commands in the Control Register. In Capture Mode it can be disabled by an RB load event if LDBDIS is set to 1 in TC_CMR. In Waveform Mode, it can be disabled by an RC Compare event if CPCDIS is set to 1 in TC_CMR. When disabled, the start or the stop actions have no effect: only a CLKEN command in the Control Register can reenable the clock. When the clock is enabled, the CLKSTA bit is set in the Status Register.  The clock can also be started or stopped: a trigger (software, synchro, external or compare) always starts the clock. The clock can be stopped by an RB load event in Capture Mode (LDBSTOP = 1 in TC_CMR) or a RC compare event in Waveform Mode (CPCSTOP = 1 in TC_CMR). The start and the stop commands have effect only if the clock is enabled. Figure 32-4. Clock Control Selected Clock Trigger CLKSTA Q Q S CLKEN CLKDIS S R R Counter Clock Stop Event Disable Event 32.6.5 TC Operating Modes Each channel can independently operate in two different modes:  Capture Mode provides measurement on signals.  Waveform Mode provides wave generation. The TC Operating Mode is programmed with the WAVE bit in the TC Channel Mode Register. In Capture Mode, TIOA and TIOB are configured as inputs. In Waveform Mode, TIOA is always configured to be an output and TIOB is an output if it is not selected to be the external trigger. 536 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 32.6.6 Trigger A trigger resets the counter and starts the counter clock. Three types of triggers are common to both modes, and a fourth external trigger is available to each mode. The following triggers are common to both modes:  Software Trigger: Each channel has a software trigger, available by setting SWTRG in TC_CCR.  SYNC: Each channel has a synchronization signal SYNC. When asserted, this signal has the same effect as a software trigger. The SYNC signals of all channels are asserted simultaneously by writing TC_BCR (Block Control) with SYNC set.  Compare RC Trigger: RC is implemented in each channel and can provide a trigger when the counter value matches the RC value if CPCTRG is set in TC_CMR. The channel can also be configured to have an external trigger. In Capture Mode, the external trigger signal can be selected between TIOA and TIOB. In Waveform Mode, an external event can be programmed on one of the following signals: TIOB, XC0, XC1 or XC2. This external event can then be programmed to perform a trigger by setting ENETRG in TC_CMR. If an external trigger is used, the duration of the pulses must be longer than the master clock period in order to be detected. Regardless of the trigger used, it will be taken into account at the following active edge of the selected clock. This means that the counter value can be read differently from zero just after a trigger, especially when a low frequency signal is selected as the clock. 32.6.7 Capture Operating Mode This mode is entered by clearing the WAVE parameter in TC_CMR (Channel Mode Register). Capture Mode allows the TC channel to perform measurements such as pulse timing, frequency, period, duty cycle and phase on TIOA and TIOB signals which are considered as inputs. Figure 32-5 shows the configuration of the TC channel when programmed in Capture Mode. 32.6.8 Capture Registers A and B Registers A and B (RA and RB) are used as capture registers. This means that they can be loaded with the counter value when a programmable event occurs on the signal TIOA. The LDRA parameter in TC_CMR defines the TIOA edge for the loading of register A, and the LDRB parameter defines the TIOA edge for the loading of Register B. RA is loaded only if it has not been loaded since the last trigger or if RB has been loaded since the last loading of RA. RB is loaded only if RA has been loaded since the last trigger or the last loading of RB. Loading RA or RB before the read of the last value loaded sets the Overrun Error Flag (LOVRS) in TC_SR (Status Register). In this case, the old value is overwritten. 32.6.9 Trigger Conditions In addition to the SYNC signal, the software trigger and the RC compare trigger, an external trigger can be defined. The ABETRG bit in TC_CMR selects TIOA or TIOB input signal as an external trigger. The ETRGEDG parameter defines the edge (rising, falling or both) detected to generate an external trigger. If ETRGEDG = 0 (none), the external trigger is disabled. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 537 538 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 MTIOA MTIOB 1 If RA is not loaded or RB is Loaded Edge Detector ETRGEDG SWTRG Timer/Counter Channel ABETRG BURST CLKI R S OVF LDRB Edge Detector Edge Detector Capture Register A LDBSTOP R S CLKEN LDRA If RA is Loaded CPCTRG 16-bit Counter RESET Trig CLK Q Q CLKSTA LDBDIS Capture Register B CLKDIS TC1_SR TIOA TIOB SYNC XC2 XC1 XC0 TIMER_CLOCK5 TIMER_CLOCK4 TIMER_CLOCK3 TIMER_CLOCK2 TIMER_CLOCK1 TCCLKS Compare RC = Register C COVFS INT Figure 32-5. Capture Mode CPCS LOVRS LDRBS ETRGS LDRAS TC1_IMR 32.6.10 Waveform Operating Mode Waveform operating mode is entered by setting the WAVE parameter in TC_CMR (Channel Mode Register). In Waveform Operating Mode the TC channel generates 1 or 2 PWM signals with the same frequency and independently programmable duty cycles, or generates different types of one-shot or repetitive pulses. In this mode, TIOA is configured as an output and TIOB is defined as an output if it is not used as an external event (EEVT parameter in TC_CMR). Figure 32-6 on page 540 shows the configuration of the TC channel when programmed in Waveform Operating Mode. 32.6.11 Waveform Selection Depending on the WAVSEL parameter in TC_CMR (Channel Mode Register), the behavior of TC_CV varies. With any selection, RA, RB and RC can all be used as compare registers. RA Compare is used to control the TIOA output, RB Compare is used to control the TIOB output (if correctly configured) and RC Compare is used to control TIOA and/or TIOB outputs. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 539 540 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 TIOB SYNC XC2 XC1 XC0 TIMER_CLOCK5 TIMER_CLOCK4 TIMER_CLOCK3 TIMER_CLOCK2 TIMER_CLOCK1 1 EEVT BURST TCCLKS Timer/Counter Channel Edge Detector EEVTEDG SWTRG ENETRG CLKI Trig CLK R S OVF WAVSEL RESET 16-bit Counter WAVSEL Q Compare RA = Register A Q CLKSTA Compare RC = Compare RB = CPCSTOP CPCDIS Register C CLKDIS Register B R S CLKEN CPAS INT BSWTRG BEEVT BCPB BCPC ASWTRG AEEVT ACPA ACPC Output Controller Output Controller TIOB MTIOB TIOA MTIOA Figure 32-6. Waveform Mode CPCS CPBS COVFS TC1_SR ETRGS TC1_IMR 32.6.11.1 WAVSEL = 00 When WAVSEL = 00, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF has been reached, the value of TC_CV is reset. Incrementation of TC_CV starts again and the cycle continues. See Figure 32-7. An external event trigger or a software trigger can reset the value of TC_CV. It is important to note that the trigger may occur at any time. See Figure 32-8. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock (CPCDIS = 1 in TC_CMR). Figure 32-7. WAVSEL = 00 Without Trigger Counter Value Counter cleared by compare match with 0xFFFF 0xFFFF RC RB RA Time Waveform Examples TIOB TIOA Figure 32-8. WAVSEL = 00 With Trigger Counter Value Counter cleared by compare match with 0xFFFF 0xFFFF RC Counter cleared by trigger RB RA Waveform Examples Time TIOB TIOA SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 541 32.6.11.2 WAVSEL = 10 When WAVSEL = 10, the value of TC_CV is incremented from 0 to the value of RC, then automatically reset on a RC Compare. Once the value of TC_CV has been reset, it is then incremented and so on. See Figure 32-9. It is important to note that TC_CV can be reset at any time by an external event or a software trigger if both are programmed correctly. See Figure 32-10. In addition, RC Compare can stop the counter clock (CPCSTOP = 1 in TC_CMR) and/or disable the counter clock (CPCDIS = 1 in TC_CMR). Figure 32-9. WAVSEL = 10 Without Trigger Counter Value 0xFFFF Counter cleared by compare match with RC RC RB RA Waveform Examples Time TIOB TIOA Figure 32-10. WAVSEL = 10 With Trigger Counter Value 0xFFFF Counter cleared by compare match with RC Counter cleared by trigger RC RB RA Waveform Examples TIOB TIOA 542 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 Time 32.6.11.3 WAVSEL = 01 When WAVSEL = 01, the value of TC_CV is incremented from 0 to 0xFFFF. Once 0xFFFF is reached, the value of TC_CV is decremented to 0, then re-incremented to 0xFFFF and so on. See Figure 32-11. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 32-12. RC Compare cannot be programmed to generate a trigger in this configuration. At the same time, RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock (CPCDIS = 1). Figure 32-11. WAVSEL = 01 Without Trigger Counter Value Counter decremented by compare match with 0xFFFF 0xFFFF RC RB RA Time Waveform Examples TIOB TIOA Figure 32-12. WAVSEL = 01 With Trigger Counter Value Counter decremented by compare match with 0xFFFF 0xFFFF Counter decremented by trigger RC RB Counter incremented by trigger RA Time Waveform Examples TIOB TIOA SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 543 32.6.11.4 WAVSEL = 11 When WAVSEL = 11, the value of TC_CV is incremented from 0 to RC. Once RC is reached, the value of TC_CV is decremented to 0, then re-incremented to RC and so on. See Figure 32-13. A trigger such as an external event or a software trigger can modify TC_CV at any time. If a trigger occurs while TC_CV is incrementing, TC_CV then decrements. If a trigger is received while TC_CV is decrementing, TC_CV then increments. See Figure 32-14. RC Compare can stop the counter clock (CPCSTOP = 1) and/or disable the counter clock (CPCDIS = 1). Figure 32-13. WAVSEL = 11 Without Trigger Counter Value 0xFFFF Counter decremented by compare match with RC RC RB RA Time Waveform Examples TIOB TIOA Figure 32-14. WAVSEL = 11 With Trigger Counter Value 0xFFFF Counter decremented by compare match with RC RC RB Counter decremented by trigger Counter incremented by trigger RA Waveform Examples TIOB TIOA 544 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 Time 32.6.12 External Event/Trigger Conditions An external event can be programmed to be detected on one of the clock sources (XC0, XC1, XC2) or TIOB. The external event selected can then be used as a trigger. The EEVT parameter in TC_CMR selects the external trigger. The EEVTEDG parameter defines the trigger edge for each of the possible external triggers (rising, falling or both). If EEVTEDG is cleared (none), no external event is defined. If TIOB is defined as an external event signal (EEVT = 0), TIOB is no longer used as an output and the compare register B is not used to generate waveforms and subsequently no IRQs. In this case the TC channel can only generate a waveform on TIOA. When an external event is defined, it can be used as a trigger by setting bit ENETRG in TC_CMR. As in Capture Mode, the SYNC signal and the software trigger are also available as triggers. RC Compare can also be used as a trigger depending on the parameter WAVSEL. 32.6.13 Output Controller The output controller defines the output level changes on TIOA and TIOB following an event. TIOB control is used only if TIOB is defined as output (not as an external event). The following events control TIOA and TIOB: software trigger, external event and RC compare. RA compare controls TIOA and RB compare controls TIOB. Each of these events can be programmed to set, clear or toggle the output as defined in the corresponding parameter in TC_CMR. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 545 32.7 Timer Counter (TC) User Interface Table 32-4. Register Mapping Offset(1) Register Name 0x00 + channel * 0x40 + 0x00 Channel Control Register 0x00 + channel * 0x40 + 0x04 Channel Mode Register 0x00 + channel * 0x40 + 0x08 Reserved 0x00 + channel * 0x40 + 0x0C Reserved 0x00 + channel * 0x40 + 0x10 Counter Value 0x00 + channel * 0x40 + 0x14 Register A Access Reset TC_CCR Write-only – TC_CMR Read/Write 0 TC_CV Read-only 0 TC_RA (2) 0 (2) 0 Read/Write 0x00 + channel * 0x40 + 0x18 Register B TC_RB 0x00 + channel * 0x40 + 0x1C Register C TC_RC Read/Write 0 0x00 + channel * 0x40 + 0x20 Status Register TC_SR Read-only 0 0x00 + channel * 0x40 + 0x24 Interrupt Enable Register TC_IER Write-only – 0x00 + channel * 0x40 + 0x28 Interrupt Disable Register TC_IDR Write-only – 0x00 + channel * 0x40 + 0x2C Interrupt Mask Register TC_IMR Read-only 0 0xC0 Block Control Register TC_BCR Write-only – 0xC4 Block Mode Register TC_BMR Read/Write 0 0xFC Reserved – – – Notes: 546 1. Channel index ranges from 0 to 2. 2. Read-only if WAVE = 0 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 Read/Write 32.7.1 TC Block Control Register Name: TC_BCR Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – – – SYNC • SYNC: Synchro Command 0: No effect. 1: Asserts the SYNC signal which generates a software trigger simultaneously for each of the channels. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 547 32.7.2 TC Block Mode Register Name: TC_BMR Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 – – TC2XC2S • TC0XC0S: External Clock Signal 0 Selection Value Signal Connected to XC0 0 0 TCLK0 0 1 none 1 0 TIOA1 1 1 TIOA2 • TC1XC1S: External Clock Signal 1 Selection Value Signal Connected to XC1 0 0 TCLK1 0 1 none 1 0 TIOA0 1 1 TIOA2 • TC2XC2S: External Clock Signal 2 Selection Value Signal Connected to XC2 0 0 TCLK2 0 1 none 1 0 TIOA0 1 1 TIOA1 548 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 TC1XC1S 0 TC0XC0S 32.7.3 TC Channel Control Register Name: TC_CCRx [x = 0..2] Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 – – – – – SWTRG CLKDIS CLKEN • CLKEN: Counter Clock Enable Command 0: No effect. 1: Enables the clock if CLKDIS is not 1. • CLKDIS: Counter Clock Disable Command 0: No effect. 1: Disables the clock. • SWTRG: Software Trigger Command 0: No effect. 1: A software trigger is performed: the counter is reset and the clock is started. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 549 32.7.4 TC Channel Mode Register: Capture Mode Name: TC_CMRx [x = 0..2] (WAVE = 0) Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 – – – – 15 14 13 12 11 10 WAVE CPCTRG – – – ABETRG 7 6 5 3 2 LDBDIS LDBSTOP 4 BURST • TCCLKS: Clock Selection Value Clock Selected 0 0 0 TIMER_CLOCK1 0 0 1 TIMER_CLOCK2 0 1 0 TIMER_CLOCK3 0 1 1 TIMER_CLOCK4 1 0 0 TIMER_CLOCK5 1 0 1 XC0 1 1 0 XC1 1 1 1 XC2 • CLKI: Clock Invert 0: Counter is incremented on rising edge of the clock. 1: Counter is incremented on falling edge of the clock. • BURST: Burst Signal Selection Value 0 0 The clock is not gated by an external signal. 0 1 XC0 is ANDed with the selected clock. 1 0 XC1 is ANDed with the selected clock. 1 1 XC2 is ANDed with the selected clock. • LDBSTOP: Counter Clock Stopped with RB Loading 0: Counter clock is not stopped when RB loading occurs. 1: Counter clock is stopped when RB loading occurs. • LDBDIS: Counter Clock Disable with RB Loading 0: Counter clock is not disabled when RB loading occurs. 1: Counter clock is disabled when RB loading occurs. 550 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 16 LDRB CLKI LDRA 9 8 ETRGEDG 1 TCCLKS 0 • ETRGEDG: External Trigger Edge Selection Value Edge 0 0 none 0 1 rising edge 1 0 falling edge 1 1 each edge • ABETRG: TIOA or TIOB External Trigger Selection 0: TIOB is used as an external trigger. 1: TIOA is used as an external trigger. • CPCTRG: RC Compare Trigger Enable 0: RC Compare has no effect on the counter and its clock. 1: RC Compare resets the counter and starts the counter clock. • WAVE 0: Capture Mode is enabled. 1: Capture Mode is disabled (Waveform Mode is enabled). • LDRA: RA Loading Selection Value Edge 0 0 none 0 1 rising edge of TIOA 1 0 falling edge of TIOA 1 1 each edge of TIOA • LDRB: RB Loading Selection Value Edge 0 0 none 0 1 rising edge of TIOA 1 0 falling edge of TIOA 1 1 each edge of TIOA SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 551 32.7.5 TC Channel Mode Register: Waveform Mode Name: TC_CMRx [x = 0..2] (WAVE = 1) Access: Read/Write 31 30 29 BSWTRG 23 22 20 14 7 6 CPCDIS CPCSTOP 12 5 4 BURST Clock Selected 0 0 TIMER_CLOCK1 0 0 1 TIMER_CLOCK2 0 1 0 TIMER_CLOCK3 0 1 1 TIMER_CLOCK4 1 0 0 TIMER_CLOCK5 1 0 1 XC0 1 1 0 XC1 1 1 1 XC2 • CLKI: Clock Invert 0: Counter is incremented on rising edge of the clock. 1: Counter is incremented on falling edge of the clock. • BURST: Burst Signal Selection Value 0 0 The clock is not gated by an external signal. 0 1 XC0 is ANDed with the selected clock. 1 0 XC1 is ANDed with the selected clock. 1 1 XC2 is ANDed with the selected clock. • CPCSTOP: Counter Clock Stopped with RC Compare 0: Counter clock is not stopped when counter reaches RC. 1: Counter clock is stopped when counter reaches RC. • CPCDIS: Counter Clock Disable with RC Compare 0: Counter clock is not disabled when counter reaches RC. 1: Counter clock is disabled when counter reaches RC. 552 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 24 BCPB 18 11 ENETRG • TCCLKS: Clock Selection 0 25 17 16 ACPC 13 WAVSEL 26 19 AEEVT WAVE Value 27 BCPC 21 ASWTRG 15 28 BEEVT ACPA 10 9 EEVT 3 CLKI 8 EEVTEDG 2 1 TCCLKS 0 • EEVTEDG: External Event Edge Selection Value Edge 0 0 none 0 1 rising edge 1 0 falling edge 1 1 each edge • EEVT: External Event Selection Value Signal selected as external event TIOB Direction 0 0 TIOB input (1) 0 1 XC0 output 1 0 XC1 output 1 1 XC2 output Note: 1. If TIOB is chosen as the external event signal, it is configured as an input and no longer generates waveforms and subsequently no IRQs. • ENETRG: External Event Trigger Enable 0: The external event has no effect on the counter and its clock. In this case, the selected external event only controls the TIOA output. 1: The external event resets the counter and starts the counter clock. • WAVSEL: Waveform Selection Value Effect 0 0 UP mode without automatic trigger on RC Compare 1 0 UP mode with automatic trigger on RC Compare 0 1 UPDOWN mode without automatic trigger on RC Compare 1 1 UPDOWN mode with automatic trigger on RC Compare • WAVE 0: Waveform Mode is disabled (Capture Mode is enabled). 1: Waveform Mode is enabled. • ACPA: RA Compare Effect on TIOA Value Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 553 • ACPC: RC Compare Effect on TIOA Value Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • AEEVT: External Event Effect on TIOA Value Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • ASWTRG: Software Trigger Effect on TIOA Value Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • BCPB: RB Compare Effect on TIOB Value Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • BCPC: RC Compare Effect on TIOB Value Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle • BEEVT: External Event Effect on TIOB Value Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle 554 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 • BSWTRG: Software Trigger Effect on TIOB Value Effect 0 0 none 0 1 set 1 0 clear 1 1 toggle SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 555 32.7.6 TC Counter Value Register Name: TC_CVx [x = 0..2] Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 3 2 1 0 CV 7 6 5 4 CV • CV: Counter Value CV contains the counter value in real time. 556 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 32.7.7 TC Register A Name: TC_RAx [x = 0..2] Access: Read-only if WAVE = 0, Read/Write if WAVE = 1 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 3 2 1 0 RA 7 6 5 4 RA • RA: Register A RA contains the Register A value in real time. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 557 32.7.8 TC Register B Name: TC_RBx [x = 0..2] Access: Read-only if WAVE = 0, Read/Write if WAVE = 1 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 3 2 1 0 RB 7 6 5 4 RB • RB: Register B RB contains the Register B value in real time. 558 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 32.7.9 TC Register C Name: TC_RCx [x = 0..2] Access: Read/Write 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 3 2 1 0 RC 7 6 5 4 RC • RC: Register C RC contains the Register C value in real time. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 559 32.7.10 TC Status Register Name: TC_SRx [x = 0..2] Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – MTIOB MTIOA CLKSTA 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS • COVFS: Counter Overflow Status 0: No counter overflow has occurred since the last read of the Status Register. 1: A counter overflow has occurred since the last read of the Status Register. • LOVRS: Load Overrun Status 0: Load overrun has not occurred since the last read of the Status Register or WAVE = 1. 1: RA or RB have been loaded at least twice without any read of the corresponding register since the last read of the Status Register, if WAVE = 0. • CPAS: RA Compare Status 0: RA Compare has not occurred since the last read of the Status Register or WAVE = 0. 1: RA Compare has occurred since the last read of the Status Register, if WAVE = 1. • CPBS: RB Compare Status 0: RB Compare has not occurred since the last read of the Status Register or WAVE = 0. 1: RB Compare has occurred since the last read of the Status Register, if WAVE = 1. • CPCS: RC Compare Status 0: RC Compare has not occurred since the last read of the Status Register. 1: RC Compare has occurred since the last read of the Status Register. • LDRAS: RA Loading Status 0: RA Load has not occurred since the last read of the Status Register or WAVE = 1. 1: RA Load has occurred since the last read of the Status Register, if WAVE = 0. • LDRBS: RB Loading Status 0: RB Load has not occurred since the last read of the Status Register or WAVE = 1. 1: RB Load has occurred since the last read of the Status Register, if WAVE = 0. • ETRGS: External Trigger Status 0: External trigger has not occurred since the last read of the Status Register. 1: External trigger has occurred since the last read of the Status Register. 560 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 • CLKSTA: Clock Enabling Status 0: Clock is disabled. 1: Clock is enabled. • MTIOA: TIOA Mirror 0: TIOA is low. If WAVE = 0, this means that TIOA pin is low. If WAVE = 1, this means that TIOA is driven low. 1: TIOA is high. If WAVE = 0, this means that TIOA pin is high. If WAVE = 1, this means that TIOA is driven high. • MTIOB: TIOB Mirror 0: TIOB is low. If WAVE = 0, this means that TIOB pin is low. If WAVE = 1, this means that TIOB is driven low. 1: TIOB is high. If WAVE = 0, this means that TIOB pin is high. If WAVE = 1, this means that TIOB is driven high. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 561 32.7.11 TC Interrupt Enable Register Name: TC_IERx [x = 0..2] Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS • COVFS: Counter Overflow 0: No effect. 1: Enables the Counter Overflow Interrupt. • LOVRS: Load Overrun 0: No effect. 1: Enables the Load Overrun Interrupt. • CPAS: RA Compare 0: No effect. 1: Enables the RA Compare Interrupt. • CPBS: RB Compare 0: No effect. 1: Enables the RB Compare Interrupt. • CPCS: RC Compare 0: No effect. 1: Enables the RC Compare Interrupt. • LDRAS: RA Loading 0: No effect. 1: Enables the RA Load Interrupt. • LDRBS: RB Loading 0: No effect. 1: Enables the RB Load Interrupt. • ETRGS: External Trigger 0: No effect. 1: Enables the External Trigger Interrupt. 562 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 32.7.12 TC Interrupt Disable Register Name: TC_IDRx [x = 0..2] Access: Write-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS • COVFS: Counter Overflow 0: No effect. 1: Disables the Counter Overflow Interrupt. • LOVRS: Load Overrun 0: No effect. 1: Disables the Load Overrun Interrupt (if WAVE = 0). • CPAS: RA Compare 0: No effect. 1: Disables the RA Compare Interrupt (if WAVE = 1). • CPBS: RB Compare 0: No effect. 1: Disables the RB Compare Interrupt (if WAVE = 1). • CPCS: RC Compare 0: No effect. 1: Disables the RC Compare Interrupt. • LDRAS: RA Loading 0: No effect. 1: Disables the RA Load Interrupt (if WAVE = 0). • LDRBS: RB Loading 0: No effect. 1: Disables the RB Load Interrupt (if WAVE = 0). • ETRGS: External Trigger 0: No effect. 1: Disables the External Trigger Interrupt. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 563 32.7.13 TC Interrupt Mask Register Name: TC_IMRx [x = 0..2] Access: Read-only 31 30 29 28 27 26 25 24 – – – – – – – – 23 22 21 20 19 18 17 16 – – – – – – – – 15 14 13 12 11 10 9 8 – – – – – – – – 7 6 5 4 3 2 1 0 ETRGS LDRBS LDRAS CPCS CPBS CPAS LOVRS COVFS • COVFS: Counter Overflow 0: The Counter Overflow Interrupt is disabled. 1: The Counter Overflow Interrupt is enabled. • LOVRS: Load Overrun 0: The Load Overrun Interrupt is disabled. 1: The Load Overrun Interrupt is enabled. • CPAS: RA Compare 0: The RA Compare Interrupt is disabled. 1: The RA Compare Interrupt is enabled. • CPBS: RB Compare 0: The RB Compare Interrupt is disabled. 1: The RB Compare Interrupt is enabled. • CPCS: RC Compare 0: The RC Compare Interrupt is disabled. 1: The RC Compare Interrupt is enabled. • LDRAS: RA Loading 0: The Load RA Interrupt is disabled. 1: The Load RA Interrupt is enabled. • LDRBS: RB Loading 0: The Load RB Interrupt is disabled. 1: The Load RB Interrupt is enabled. • ETRGS: External Trigger 0: The External Trigger Interrupt is disabled. 1: The External Trigger Interrupt is enabled. 564 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 33. MultiMedia Card Interface (MCI) 33.1 Description The MultiMedia Card Interface (MCI) supports the MultiMedia Card (MMC) Specification V3.31, the SDIO Specification V1.1 and the SD Memory Card Specification V1.0. The MCI includes a command register, response registers, data registers, timeout counters and error detection logic that automatically handle the transmission of commands and, when required, the reception of the associated responses and data with a limited processor overhead. The MCI supports stream, block and multi-block data read and write, and is compatible with the Peripheral DMA Controller (PDC) channels, minimizing processor intervention for large buffer transfers. The MCI operates at a rate of up to Master Clock divided by 2 and supports the interfacing of 2 slots. Each slot may be used to interface with a MultiMedia Card bus (up to 30 cards) or with a SD Memory Card. Only one slot can be selected at a time (slots are multiplexed). A bit field in the SD Card Register performs this selection. The SD Memory Card communication is based on a 9-pin interface (clock, command, four data and three power lines) and the MultiMedia Card on a 7-pin interface (clock, command, one data, three power lines and one reserved for future use). The SD Memory Card interface also supports MultiMedia Card operations. The main differences between SD and MultiMedia Cards are the initialization process and the bus topology. 33.2 Embedded Characteristics  Compatible with SD Memory Card Specification Version 1.0  Compatible with MultiMedia Card Specification Version 3.31  Compatible with SDIO Specification Version 1.1  Card clock rate up to Master Clock divided by 2  Embedded power management to slow down clock rate when not used  Supports 2 Multiplexed Slots ̶ Each Slot for either a MultiMediaCard Bus (Up to 30 Cards) or an SD Memory Card  Support for stream, block and multi-block data read and write  Supports Connection to Peripheral DMA Controller (PDC) ̶ Minimizes Processor Intervention for Large Buffer Transfers SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 565 33.3 Block Diagram Figure 33-1. Block Diagram APB Bridge PDC APB MCCK(1) MCCDA(1) MCDA0(1) PMC MCK MCDA1(1) MCDA2(1) MCDA3(1) MCI Interface PIO MCCDB(1) MCDB0(1) MCDB1(1) MCDB2(1) Interrupt Control MCDB3(1) MCI Interrupt Note: 566 1. When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCCDB to MCIx_CDB,MCDAy to MCIx_DAy, MCDBy to MCIx_DBy. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 33.4 Application Block Diagram Figure 33-2. Application Block Diagram Application Layer ex: File System, Audio, Security, etc. Physical Layer MCI Interface 1 2 3 4 5 6 78 1234567 9 SDCard MMC 33.5 Pin Name List Table 33-1. I/O Lines Description (1) Pin Name Pin Description Type(2) Comments MCCDA/MCCDB Command/response I/O/PP/OD CMD of an MMC or SDCard/SDIO MCCK Clock I/O CLK of an MMC or SD Card/SDIO MCDA0–MCDA3 Data 0..3 of Slot A I/O/PP DAT0 of an MMC DAT[0..3] of an SD Card/SDIO MCDB0–MCDB3 Data 0..3 of Slot B I/O/PP DAT0 of an MMC DAT[0..3] of an SD Card/SDIO Notes: 1. 2. When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCCDB to MCIx_CDB, MCDAy to MCIx_DAy, MCDBy to MCIx_DBy. I: Input, O: Output, PP: Push/Pull, OD: Open Drain SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 567 33.6 Product Dependencies 33.6.1 I/O Lines The pins used for interfacing the MultiMedia Cards or SD Cards may be multiplexed with PIO lines. The programmer must first program the PIO controllers to assign the peripheral functions to MCI pins. 33.6.2 Power Management The MCI may be clocked through the Power Management Controller (PMC), so the programmer must first configure the PMC to enable the MCI clock. 33.6.3 Interrupt The MCI interface has an interrupt line connected to the Advanced Interrupt Controller (AIC). Handling the MCI interrupt requires programming the AIC before configuring the MCI. 33.7 Bus Topology Figure 33-3. MultiMedia Memory Card Bus Topology 1234567 MMC The MultiMedia Card communication is based on a 7-pin serial bus interface. It has three communication lines and four supply lines. Table 33-2. Bus Topology Description MCI Pin Name(2) (Slot z) NC Not connected – CMD I/O/PP/OD Command/response MCCDz 3 VSS1 S Supply voltage ground VSS 4 VDD S Supply voltage VDD 5 CLK I/O Clock MCCK 6 VSS2 S Supply voltage ground VSS 7 DAT[0] I/O/PP Data 0 MCDz0 Pin Number Notes: 568 Name Type 1 RSV 2 1. 2. (1) I: Input, O: Output, PP: Push/Pull, OD: Open Drain. When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCCDB to MCIx_CDB, MCDAy to MCIx_DAy, MCDBy to MCIx_DBy. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 Figure 33-4. MMC Bus Connections (One Slot) MCI MCDA0 MCCDA MCCK Note: 1234567 1234567 1234567 MMC1 MMC2 MMC3 When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA MCDAy to MCIx_DAy. Figure 33-5. SD Memory Card Bus Topology 1 2 3 4 5 6 78 9 SD CARD The SD Memory Card bus includes the signals listed in Table 33-3. Table 33-3. SD Memory Card Bus Signals Description MCI Pin Name(2) (Slot z) I/O/PP Card detect/ Data line Bit 3 MCDz3 CMD PP Command/response MCCDz 3 VSS1 S Supply voltage ground VSS 4 VDD S Supply voltage VDD 5 CLK I/O Clock MCCK 6 VSS2 S Supply voltage ground VSS 7 DAT[0] I/O/PP Data line Bit 0 MCDz0 8 DAT[1] I/O/PP Data line Bit 1 or Interrupt MCDz1 9 DAT[2] I/O/PP Data line Bit 2 MCDz2 Pin Number Type 1 CD/DAT[3] 2 1. 2. Figure 33-6. I: input, O: output, PP: Push Pull, OD: Open Drain. When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCCDB to MCIx_CDB, MCDAy to MCIx_DAy, MCDBy to MCIx_DBy. SD Card Bus Connections with One Slot MCDA0 - MCDA3 MCCK SD CARD 9 MCCDA 1 2 3 4 5 6 78 Notes: Name (1) Note: When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA MCDAy to MCIx_DAy. SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 569 SD Card Bus Connections with Two Slots 1 2 3 4 5 6 78 Figure 33-7. MCDA0 - MCDA3 MCCK 1 2 3 4 5 6 78 9 MCCDA SD CARD 1 MCDB0 - MCDB3 9 MCCDB SD CARD 2 Note: When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK,MCCDA to MCIx_CDA, MCDAy to MCIx_DAy, MCCDB to MCIx_CDB, MCDBy to MCIx_DBy. Figure 33-8. Mixing MultiMedia and SD Memory Cards with Two Slots MCDA0 MCCDA MCCK 1234567 MMC1 MMC2 MMC3 SD CARD 9 MCCDB 1234567 1 2 3 4 5 6 78 MCDB0 - MCDB3 1234567 Note: When several MCI (x MCI) are embedded in a product, MCCK refers to MCIx_CK, MCCDA to MCIx_CDA, MCDAy to MCIx_DAy, MCCDB to MCIx_CDB, MCDBy to MCIx_DBy. When the MCI is configured to operate with SD memory cards, the width of the data bus can be selected in the MCI_SDCR. Clearing the SDCBUS bit in this register means that the width is one bit; setting it means that the width is four bits. In the case of multimedia cards, only the data line 0 is used. The other data lines can be used as independent PIOs. 570 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 33.8 MultiMedia Card Operations After a power-on reset, the cards are initialized by a special message-based MultiMedia Card bus protocol. Each message is represented by one of the following tokens:  Command: A command is a token that starts an operation. A command is sent from the host either to a single card (addressed command) or to all connected cards (broadcast command). A command is transferred serially on the CMD line.  Response: A response is a token which is sent from an addressed card or (synchronously) from all connected cards to the host as an answer to a previously received command. A response is transferred serially on the CMD line.  Data: Data can be transferred from the card to the host or vice versa. Data is transferred via the data line. Card addressing is implemented using a session address assigned during the initialization phase by the bus controller to all currently connected cards. Their unique CID number identifies individual cards. The structure of commands, responses and data blocks is described in the MultiMedia-Card System Specification. See also Table 33-4 on page 572. MultiMedia Card bus data transfers are composed of these tokens. There are different types of operations. Addressed operations always contain a command and a response token. In addition, some operations have a data token; the others transfer their information directly within the command or response structure. In this case, no data token is present in an operation. The bits on the DAT and the CMD lines are transferred synchronous to the clock MCI Clock. Two types of data transfer commands are defined:  Sequential commands: These commands initiate a continuous data stream. They are terminated only when a stop command follows on the CMD line. This mode reduces the command overhead to an absolute minimum.  Block-oriented commands: These commands send a data block succeeded by CRC bits. Both read and write operations allow either single or multiple block transmission. A multiple block transmission is terminated when a stop command follows on the CMD line similarly to the sequential read or when a multiple block transmission has a pre-defined block count (See “Data Transfer Operation” on page 574.). The MCI provides a set of registers to perform the entire range of MultiMedia Card operations. 33.8.1 Command - Response Operation After reset, the MCI is disabled and becomes valid after setting the MCIEN bit in the MCI_CR Control Register. The PWSEN bit saves power by dividing the MCI clock by 2PWSDIV + 1 when the bus is inactive. The two bits, RDPROOF and WRPROOF in the MCI Mode Register (MCI_MR) allow stopping the MCI Clock during read or write access if the internal FIFO is full. This will guarantee data integrity, not bandwidth. The command and the response of the card are clocked out with the rising edge of the MCI Clock. All the timings for MultiMedia Card are defined in the MultiMedia Card System Specification. The two bus modes (open drain and push/pull) needed to process all the operations are defined in the MCI command register. The MCI_CMDR allows a command to be carried out. For example, to perform an ALL_SEND_CID command: Host Command CMD S T Content CRC NID Cycles E Z ****** Response Z S T CID Content High Impedance State Z Z SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 Z 571 The command ALL_SEND_CID and the fields and values for the MCI_CMDR are described in Table 33-4 and Table 33-5. Table 33-4. ALL_SEND_CID Command Description CMD Index Type Argument Resp Abbreviation Command Description CMD2 bcr [31:0] stuff bits R2 ALL_SEND_CID Asks all cards to send their CID numbers on the CMD line Note: bcr means broadcast command with response. Table 33-5. Fields and Values for MCI_CMDR Command Register Field Value CMDNB (command number) 2 (CMD2) RSPTYP (response type) 2 (R2: 136 bits response) SPCMD (special command) 0 (not a special command) OPCMD (open drain command) 1 MAXLAT (max latency for command to response) 0 (NID cycles ==> 5 cycles) TRCMD (transfer command) 0 (No transfer) TRDIR (transfer direction) X (available only in transfer command) TRTYP (transfer type) X (available only in transfer command) IOSPCMD (SDIO special command) 0 (not a special command) The MCI_ARGR contains the argument field of the command. To send a command, the user must perform the following steps:  Fill the argument register (MCI_ARGR) with the command argument.  Set the command register (MCI_CMDR) (see Table 33-5). The command is sent immediately after writing the command register. The status bit CMDRDY in the status register (MCI_SR) is asserted when the command is completed. While the card maintains a busy indication (at the end of a STOP_TRANSMISSION command CMD12, for example), a new command shall not be sent. The NOTBUSY flag in the status register (MCI_SR) is asserted when the card releases the busy indication. If the command requires a response, it can be read in the MCI response register (MCI_RSPR). The response size can be from 48 bits up to 136 bits depending on the command. The MCI embeds an error detection to prevent any corrupted data during the transfer. The following flowchart shows how to send a command to the card and read the response if needed. In this example, the status register bits are polled but setting the appropriate bits in the interrupt enable register (MCI_IER) allows using an interrupt method. 572 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 Figure 33-9. Command/Response Functional Flow Diagram Set the command argument MCI_ARGR = Argument(1) Set the command MCI_CMDR = Command Read MCI_SR Wait for command ready status flag 0 CMDRDY 1 Check error bits in the status register (1) Yes Status error flags? RETURN ERROR(1) Read response if required Does the command involve a busy indication? No RETURN OK Read MCI_SR 0 NOTBUSY 1 RETURN OK Note: 1. If the command is SEND_OP_COND, the CRC error flag is always present (refer to R3 response in the MultiMedia Card specification). SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 573 33.8.2 Data Transfer Operation The MultiMedia Card allows several read/write operations (single block, multiple blocks, stream, etc.). These kind of transfers can be selected setting the Transfer Type (TRTYP) field in the MCI Command Register (MCI_CMDR). These operations can be done using the features of the Peripheral DMA Controller (PDC). If the PDCMODE bit is set in MCI_MR, then all reads and writes use the PDC facilities. In all cases, the block length (BLKLEN field) must be defined either in the mode register MCI_MR, or in the Block Register MCI_BLKR. This field determines the size of the data block. Enabling PDC Force Byte Transfer (PDCFBYTE bit in the MCI_MR) allows the PDC to manage with internal byte transfers, so that transfer of blocks with a size different from modulo 4 can be supported. When PDC Force Byte Transfer is disabled, the PDC type of transfers are in words, otherwise the type of transfers are in bytes. Consequent to MMC Specification 3.1, two types of multiple block read (or write) transactions are defined (the host can use either one at any time):  Open-ended/Infinite Multiple block read (or write): The number of blocks for the read (or write) multiple block operation is not defined. The card will continuously transfer (or program) data blocks until a stop transmission command is received.  Multiple block read (or write) with pre-defined block count (since version 3.1 and higher): The card will transfer (or program) the requested number of data blocks and terminate the transaction. The stop command is not required at the end of this type of multiple block read (or write), unless terminated with an error. In order to start a multiple block read (or write) with pre-defined block count, the host must correctly program the MCI Block Register (MCI_BLKR). Otherwise the card will start an open-ended multiple block read. The BCNT field of the Block Register defines the number of blocks to transfer (from 1 to 65535 blocks). Programming the value 0 in the BCNT field corresponds to an infinite block transfer. 33.8.3 Read Operation The following flowchart shows how to read a single block with or without use of PDC facilities. In this example (see Figure 33-10 on page 575), a polling method is used to wait for the end of read. Similarly, the user can configure the interrupt enable register (MCI_IER) to trigger an interrupt at the end of read. 574 SAM9260 [DATASHEET] Atmel-6221M-ATARM-SAM9260-Datasheet_13-Jan-16 Figure 33-10. Read Functional Flow Diagram Send SELECT/DESELECT_CARD (1) command to select the card Send SET_BLOCKLEN command(1) No Yes Read with PDC Reset the PDCMODE bit MCI_MR &= ~PDCMODE Set the block length (in bytes) MCI_MR |= (BlockLenght