AT9932
Automotive Boost-Buck LED Lamp Driver IC
Features
General Description
• Constant Output Current
• Steps Output Voltage Up or Down
• Very Low Susceptibility to Input Voltage
Transients
• Frequency Jitter
• Externally Programmable Fixed Switching
Frequency
• Temperature Foldback with External NTC
Resistor
• Internal 40V Voltage Regulator
• +/–1A MOSFET Gate Driver
• Short LED Protection
• Open LED Protection
• Input Undervoltage Lockout Protection
• Enable and PWM Dimming
• ±3% Accurate Trimmed Reference
• AEC-Q100 Compliant
The AT9932 is an advanced fixed-frequency PWM
controller IC designed to control an LED lamp driver
using a boost-buck topology that can step the input
voltage up or down automatically. The IC provides fast
output current transient response and very low
susceptibility to input voltage transients. This allows the
lamp driver to pass the rigorous electrical transient
requirements of SAE J1455 or ISO 7637-2, making the
AT9932 an ultimate solution for automobile lighting.
Capacitive isolation protects the LED Lamp from failure
of the switching MOSFET.
The AT9932 features a unique feed-forward current
control scheme, differential output current sensing, soft
start and protection from short or open LED load.
Switching frequency can be programmed with a single
external resistor.
The AT9932 includes a temperature foldback of the
output current using an external NTC resistor. This
feature allows optimization of the light output of the
LED load for safe operation over the entire operating
temperature range.
Applications
• Automobile Lighting
• Battery-Powered LED Lamps
• Other Low-Voltage AC/DC or DC/DC LED Drivers
Package Type
24-lead TSSOP
(Top view)
1
VIN
AVDD
PVDD
GATE
PGND
GND
JTR
RT
FFN
FFP
T2
T1
24
REF
UVLO
NC
NC
DRP
FB
COMP
SS
PWMD
FLT
DIV
NTC
See Table 2-1 for pin information.
2018 Microchip Technology Inc.
DS20005789A-page 1
AT9932
Functional Block Diagram
Current Mirror 2
T1
T2
IT1
-
S/D: INTC > 3IT1 + 6IT2
Recovery: INTC < 3IT1
+
+
-
POR
0.7V
+
DRP
+
FB
gm
0.7V
FLT
-
Reset
+
4 (I
- 3IT1)
30 NTC
REF
AVDD
NTC
VIN
Regulator
+
I NTC
IT2
DIV
4.25V/
4.50V
UVLO
1.05V/
1.25V
OSC
RT
Jitter
JTR
S
PVDD
R Q
GATE
+
PGND
COMP
PWMD
IN
IN - IP
15 μA
SS
Reset
GND
DS20005789A-page 2
Reset
FFN
Current
Mirror 1
FFP
IP
2018 Microchip Technology Inc.
AT9932
Typical Application Circuit
L1
CIN
VIN
RIN1
Rd
PVDD
CVDD
RIN2
RP
PWMD
FFN
UVLO
REF
RT
FLT
GND
NTC
T1
ZD1
RFB
RFLT
DIV
LED(s)
ROV
RS
FB
RDRP
CREF
DRP
CC
COMP
T2
R1
CO
D1
RREF
SS
L2
RN
PGND
RNTC
Cd
FFP
RT
CSS
R2
M1
GATE
AVDD
C1
JTR
R3
CJTR
AT9932
2018 Microchip Technology Inc.
DS20005789A-page 3
AT9932
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings†
VIN to GND ............................................................................................................................................... –0.5V to +45V
PVDD and AVDD to GND .......................................................................................................................... –0.3V to +6V
Gate to GND Voltage ............................................................................................................... –0.3V to (PVDD +0.3V)
All other pins to GND Voltage .................................................................................................... –0.3V to (AVDD +0.3V)
FFN, FFP Current .................................................................................................................................................. 2 mA
REF Current .......................................................................................................................................................... 5 mA
Junction Temperature, TJ .................................................................................................................... –40°C to +150°C
Storage Temperature, TS ..................................................................................................................... –65°C to +150°C
Continuous Power Dissipation (TA = +25°C):
24-lead TSSOP (Note 1) ...................................................................................................................... 1000 mW
† Notice: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only, and functional operation of the device at those or any other conditions above those
indicated in the operational sections of this specification is not intended. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Note 1: RJA = 125°C/W
ELECTRICAL CHARACTERISTICS
Electrical Specifications: Specifications are at TA = 25°C, VIN = 12V, VPWMD = VUVLO = VAVDD = VPVDD, Gate open,
RT = 200 kΩ, CREF = 0.1 µF, CAVDD = CPVDD = 1 µF, IT1 = IT2 = 100 µA unless otherwise noted.
Parameter
INPUT
Input DC Supply Voltage Range
Input Supply Current
Input Current, UVLO Mode
INTERNAL REGULATOR
Regulated Output Voltage
Sym.
Min.
Typ.
Max.
Unit
VIN
IINEN
IINDIS
5.3
—
—
—
—
—
40
2
100
V
mA
µA
VDD
4.65
5
5.35
V
4.25
—
4.5
250
4.85
—
V
mV
1.21
1.25
1.29
V
—
0
—
mV
VUVLO = VGND
0
—
2
mV
IREF = 0 mA–1 mA
—
—
87
20
20
90
35
35
93
ns
ns
%
CGATE = 4 nF,
VIN = VAVDD = VPVDD = 5V
VDDUV, R
VDD UVLO Upper Threshold
∆VDDUV
VDD UVLO Hysteresis
REFERENCE
Reference Output Voltage
VREF
Reference Output Voltage,
VREF, DIS
UVLO Mode
Load Regulation
∆VREF
GATE OUTPUT
Gate Output Rise Time
tr
Gate Output Fall Time
tf
Maximum Duty Cycle
DMAX
FEED-FORWARD RAMP GENERATOR
Conditions
VPWMD = VGND (Note 1)
VUVLO = VPWMD = VGND (Note 1)
IDD = 0 mA–20 mA, VIN = 6V–40V,
VPWMD = VGND (Note 1)
VDD rising (Note 1)
VDD falling
IREF = 0 mA (Note 1)
(Note 1)
IFFN = 500 μA, IFFP = 0 μA,
VCOMP = 3.5V (Note 1)
IFFN = 10 μA, IFFP = 0 μA,
Maximum Gate On-Time
tON(MAX)
6
—
13
µs
VCOMP = 3.5V (Note 1)
IFFN = 110 μA, IFFP = 10 μA,
Gate On-Time
tON
1
—
2
µs
VCOMP = 3.5V (Note 1)
IFFN = 100 μA, IFFP = 0 μA,
FFN/FFP Current Balancing
∆tON/tON
–3
—
3
%
VCOMP = 3.5V (Note 2)
Note 1: Specifications apply over the full operating ambient temperature range of –40ºC < TA < +125ºC.
2: Specifications are obtained by characterization and are not 100% tested.
Minimum Gate On-Time
DS20005789A-page 4
tON(MIN)
250
—
400
ns
2018 Microchip Technology Inc.
AT9932
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Specifications are at TA = 25°C, VIN = 12V, VPWMD = VUVLO = VAVDD = VPVDD, Gate open,
RT = 200 kΩ, CREF = 0.1 µF, CAVDD = CPVDD = 1 µF, IT1 = IT2 = 100 µA unless otherwise noted.
Parameter
Min.
Typ.
Max.
Unit
TRANSCONDUCTANCE OPERATION AMPLIFIER
Input Common Mode Range
VFB, VDRP –0.3
Input Offset Voltage
VOS
–9
Transconductance
gm
—
Open-Loop Voltage Gain
AV
65
Gain Bandwidth Product
GBW
1
COMP Sink Current
0.2
ICOMP
COMP Source Current
–0.2
—
—
0.95
—
—
—
3
9
—
—
—
—
V
mV
mA/V
dB
MHz
mA
—
—
mA
Input Bias Current
Output Voltage Range
COMP Hiccup Threshold
Output Leakage Current
OSCILLATOR
Output Frequency
Output Frequency Range
JITTER
Jitter Frequency
Sym.
Conditions
(Note 2)
(Note 1)
COMP open
CCOMP = 150 pF (Note 2)
VFB = 0.1V, VCOMP = VGND (Note 2)
VFB = –0.1V, VCOMP = VAVDD
(Note 2)
(Note 2)
(Note 2)
IBIAS, AMP
VCOMP
VCOMP, HT
ILEAK
—
0.7
—
—
0.5
—
700
0.5
1
VDD
—
1
nA
V
mV
nA
fOSC1
fOSC2
fOSC
90
427
100
105
505
—
120
583
800
kHz
kHz
kHz
RT = 1 MΩ (Note 1)
RT = 200 kΩ (Note 1)
Note 2
—
—
±4.5
50
500
—
—
—
—
Hz
Hz
kHz
CJTR = 0.1 µF
CJTR = 0.01 µF
FJTR
VPWMD = VGND (Note 2)
Change in Switching Frequency
∆F
TEMPERATURE FOLDBACK CIRCUIT
NTC Source Current Range
INTC
—
—
1
mA Note 2
DRP to NTC Current Gain
NNTC
—
0.13
—
—
INTC = 0.5 mA
NTC to T1 Current Gain
NT1
—
3
—
—
INTC = 0.5 mA
NTC to T2 Current Gain
NT2
—
6
—
—
INTC = 0.5 mA
T1 and T2 Reference Voltage
VT1, VT2
—
3.5
—
V
SOFT START
Charging Current
ISS, CHG
10
—
25
µA
Discharging Current
ISS, DIS
1
—
—
mA VSS = 5V
Reset Voltage
VSS, RST
—
—
100
mV
FAULT DETECT COMPARATOR
Trip Voltage
VFLT
–20
—
20
mV
Input Bias Current
IBIAS, FLT
—
0.5
1
nA
Note 2
INPUT UNDERVOLTAGE LOCKOUT
Undervoltage Lockout Upper
VUVLO, R
1.15
1.25
1.4
V
VUVLO rising (Note 1)
Threshold
Undervoltage Lockout Hysteresis
∆VUVLO
—
200
—
mV VUVLO falling
Input Bias Current
IBIAS, UV
—
0.5
1
nA
Note 2
PWM DIMMING
Enable Voltage Level
VPWMD(HI)
2
—
—
V
Note 1
Disable Voltage Level
VPWMD(LO)
—
—
0.8
V
Note 1
Pull-Down Resistor
RPWMD
120
—
280
kΩ
Note 1: Specifications apply over the full operating ambient temperature range of –40ºC < TA < +125ºC.
2: Specifications are obtained by characterization and are not 100% tested.
2018 Microchip Technology Inc.
DS20005789A-page 5
AT9932
TEMPERATURE SPECIFICATIONS
Parameter
Sym.
Min.
Typ.
Max.
Unit
TA
–40
—
+125
°C
Conditions
TEMPERATURE RANGE
Operating Ambient Temperature
Maximum Junction Temperature
TJ
—
—
+150
°C
Storage Temperature
TS
–65
—
+150
°C
JA
—
125
—
PACKAGE THERMAL RESISTANCE
24-lead TSSOP
°C/W Note 1
Note 1: Mounted on an FR-4 board, 25 mm x 25 mm x 1.57 mm
DS20005789A-page 6
2018 Microchip Technology Inc.
AT9932
2.0
PIN DESCRIPTION
The details on the pins of AT9932 are listed on
Table 2-1. Refer to Package Type for the location of
the pins.
TABLE 2-1:
PIN FUNCTION TABLE
Pin Number
Pin Name
Description
1
VIN
2
AVDD
This is a power supply pin for all internal circuits. It must be bypassed with a low-ESR
capacitor to GND (at least 0.1 µF).
3
PVDD
This is the power supply pin for the gate driver. It should be connected externally to
AVDD and bypassed with a low-ESR capacitor to PGND (at least 0.1 µF).
4
GATE
This pin is the output of gate driver for driving an external logic level N-channel power
MOSFET.
5
PGND
Ground return for the gate drive circuitry
6
GND
Ground return for all the low-power analog internal circuitry. This pin must be connected
to the return path from the input.
7
JTR
This pin programs the jitter of the clock by a capacitor connected from this pin to GND.
8
RT
Connecting an external resistor from this pin to GND sets the frequency of the oscillator
circuit.
9
FFN
Connecting a resistor between this pin and the negative terminal of the coupling capacitor in the boost-buck converter programs positive PWM ramp signal. The slew rate is
proportional to the current sunk from this pin. When the ramp voltage exceeds the voltage at COMP, the gate signal is terminated.
10
FFP
Connecting a resistor between this pin and GND cancels the FFN current error due to
non-zero voltage at FFN. The FFN and FFP current mirrors are internally matched.
11
T2
Connecting a resistor from this current source pin to GND programs the
overtemperature shutdown threshold temperature detected by an external NTC
resistor.
12
T1
Connecting a resistor from this current source pin to GND programs the temperature
threshold beyond which the LED current is reduced.
13
NTC
Connect an external NTC resistor from this current source pin to GND for temperature
foldback of the output current and overtemperature shutdown.
14
DIV
This is the reference input that programs the voltage at the NTC pin.
15
FLT
This pin is an input of the fault comparator. This comparator is used for open and short
LED protection. The IC shuts down and restarts after a POR delay when this comparator is triggered.
16
PWMD
When this pin is pulled to GND (or left open), the gate output is disabled. The COMP
pin becomes high-impedance and holds its voltage level. When this pin is logic-high,
the switching of gate resumes.
17
SS
Connecting a capacitor from this pin to GND programs the soft-start time of the LED
driver.
This pin is the input of a 40V high-voltage regulator.
18
COMP
This pin is the output of the error amplifier. Stable closed-loop control of the output LED
current can be achieved by connecting a compensation network between COMP and
GND. This pin is pulled to GND internally upon a startup or detection of a Fault condition.
19
FB
This pin is the high-impedance non-inverting input of the error amplifier. The output LED
current sense voltage is programmed by connecting a resistor divider between REF
and the negative terminal of the current sense resistor.
20
DRP
This is the output current sense reference voltage input at the error amplifier. Connect
this pin to GND when no NTC derating is used. Connect a resistor from this pin to GND
to program the droop of the LED current at temperature foldback.
2018 Microchip Technology Inc.
DS20005789A-page 7
AT9932
TABLE 2-1:
PIN FUNCTION TABLE (CONTINUED)
Pin Number
Pin Name
21
NC
22
NC
23
UVLO
24
REF
DS20005789A-page 8
Description
No Connection
This pin provides input undervoltage lockout protection. When voltage at this pin falls
below its lower threshold, AT9932 halts switching, and the soft-start capacitor is discharged rapidly. The voltage at the REF pin becomes 0V, and the entire IC consumes
quiescent current of less than 100 μA. The switching resumes when the UVLO pin voltage exceeds the upper threshold. Hysteresis is provided between the two thresholds.
This pin provides accurate reference voltage. It must be bypassed with a 0.01 μF
to 0.1 μF capacitor to GND.
2018 Microchip Technology Inc.
AT9932
3.0
FUNCTIONAL DESCRIPTION
3.1
Power Topology
The AT9932 is optimized to drive a Continuous
Conduction Mode (CCM) boost-buck DC/DC converter
topology commonly referred to as the Ćuk converter.
(Refer to Typical Application Circuit.) This power
converter topology offers numerous advantages useful
for driving high-brightness light-emitting diodes
(HB LED). These advantages include step-up or
step-down voltage conversion ratio and low input and
output current ripple. The output load is decoupled from
the input voltage with a capacitor, making the driver
inherently failure-safe for the output load.
The AT9932 features an optimal control method for use
with a boost-buck LED driver. This method achieves
very low susceptibility to input voltage transients, which
makes it indispensable for automotive LED lighting
applications. The AT9932 can maintain constant output
current even under vigorous input transient conditions.
Its output current control loop is inherently stable and
can be compensated using a single capacitor with the
appropriate damping at the coupling capacitor.
3.2
Regulator (VIN, AVDD) and Gate
Driver (Gate, PVDD)
The AT9932 can be powered directly from its VIN pin
that takes a voltage up to 40V. When VIN voltage is
applied, the AT9932 seeks to maintain constant voltage
at the AVDD pin. When the undervoltage upper
threshold is exceeded at AVDD, the gate driver is
enabled after a 100 μs power-on reset (POR) delay.
The output of the gate driver (GATE) controls the gate
of an external N-channel power MOSFET. The
maximum duty cycle of the gate signal is limited to 0.9
(typical). The undervoltage protection comparator
disables the gate driver when the voltage at AVDD falls
below the undervoltage lower threshold.
A separate PVDD input is provided to power the gate
output to decouple the high switching currents of the
gate driver from AVDD. Both pins (AVDD, PVDD) must
be wired together on the printed circuit board (PCB).
AVDD needs to be bypassed to GND by a low-ESR
capacitor (≥0.1 µF). PVDD needs to be bypassed to
PGND by a low-ESR capacitor (≥0.1 µF).
The input current drawn from the external power supply
(or VIN pin) is a sum of the 2 mA maximum current
drawn by the all the internal circuitry and the current
drawn by the gate driver which in turn depends on the
switching frequency and the gate charge of the external
FET. Refer to Equation 3-1.
EQUATION 3-1:
I IN = 2mA + Q G f S
2018 Microchip Technology Inc.
In Equation 3-1, fS is the switching frequency, and QG
is the gate charge of the external FET which can be
obtained from the FET data sheet.
3.3
Timing Resistor (RT)
The switching frequency fS is programmed by selecting
an external timing resistor, RT. The resistance value
can be computed as shown in Equation 3-2:
EQUATION 3-2:
1
R T = ------------------FS CT
Where CT = 9.5 pF
3.4
Jitter (JTR)
Clock frequency can be modulated by an externally
programmed saw-tooth wave signal to reduce
conducted electro-magnetic emission (EMI) from the
LED driver. The deviation of the oscillator frequency is
set internally to ±5 kHz. The modulation frequency is
programmed by connecting a capacitor from JTR to
GND. The value of the capacitor required for the jitter
frequency is calculated with Equation 3-3.
EQUATION 3-3:
5F
C JTR = -----------------------F JTR Hz
Note that the jitter frequency must be chosen to be
significantly lower than the crossover frequency of the
closed-loop control. If not, the controller will not be able
to reject the jitter frequency, and the LED current will
have a current ripple at the jitter frequency.
3.5
Reference Voltage (REF)
The AT9932 provides a 1.25V reference voltage at the
REF pin. This voltage is used to derive the various
internal voltages required by the IC and is also used to
set the LED current externally. It should be bypassed
with a low-impedance capacitor (0.01 µF–0.1 µF).
3.6
Internal 1 MHz Transconductance
Amplifier
The AT9932 includes a 1 MHz transconductance
amplifier, which can be used to close the LED current
feedback loop. The output state of the amplifier is
controlled by the signal applied to the PWMD pin.
When PWMD is high, the output of the amplifier is
connected to the COMP pin and the gate drive is
enabled. When PWMD is low, COMP is left open and
the gate drive is disabled. This enables the integrating
capacitor at the COMP pin to hold its charge when the
PWMD signal has turned off the gate drive. When the
DS20005789A-page 9
AT9932
gate drive is resumed, the voltage at COMP will be
positioned for the converter to return to its Steady State
condition.
When the voltage at COMP falls below 700 mV, the
gate output is disabled. This feature reduces power
dissipation in the Zener diode ZD1 during Open LED
string condition.
3.7
Soft Start (SS)
The soft-start feature can determine the initial ramp-up
of the error voltage at the COMP pin. Connecting a
single capacitor between SS to GND can program the
soft-start time. Upon the first application of voltage to
the AVDD pin, a current of 15 μA is supplied from the
SS pin, gradually charging the soft-start capacitor. The
COMP voltage tracks the voltage at the SS pin until
regulation of the output current is reached. When the
voltage at AVDD pin (VDD) falls below the undervoltage
lower threshold, the soft-start capacitor is discharged
rapidly.
3.8
Feed-Forward Ramp Generator
(FFP, FFN) and PWM Comparator
The heart of the AT9932 is the feed-forward circuit
having two inputs: FFN and FFP. This circuit generates
a voltage ramp proportional to the difference between
the FFN and FFP currents.
L1
CD
Q1
C1
VREF
FFN
CEFF
VCOMP - 0.7V
FIGURE 3-1:
Generator.
D1
RFFN
FFP
RFFP
L2
RD
+
-
Feed-Forward Ramp
As shown in Figure 3-1, the resistor RFFN is connected
between FFN and the negative terminal of the coupling
capacitor C1. The resistor RFFP of the same value
(RFFP = RFFN) is connected between FFP and GND.
The on-time of the gate output can be computed as
shown in Equation 3-4.
EQUATION 3-4:
R FFN C EFF V COMP – 0.7V
t ON = ------------------------------------------------------------------------------V C1
Where CEFF = 50 pF ±40%, VCOMP is the COMP voltage,
and VC1 is the voltage across the coupling capacitor C1.
The duty cycle of a Continuous Conduction mode
boost-buck converter is given as illustrated in
Equation 3-5.
EQUATION 3-5:
V OUT
V OUT
D = t ON f S = ------------- = ---------------------------V C1
V OUT + V IN
Where VIN is the input supply voltage, and VOUT is the
forward voltage of the LED string.
Since the output voltage at COMP is limited to
VCOMP = VDD, the feed-forward resistors must be
selected in accordance with Equation 3-6.
EQUATION 3-6:
V OUT
R FFN = R FFP ---------------------------------------------------------------C EFF f S V DD – 0.7V
Otherwise, the steady-state Duty Cycle D will not be
reached, and the LED driver will be unable to develop
the desired current.
The feed-forward loop provides instantaneous
response to any transient at C1 and therefore achieves
excellent rejection of the input voltage transients along
the supply line. It is inherently stable with proper
selection of the damping network Rd and Cd. Optimal
selection of Rd and Cd is complex. However, the worst
case design of the damping circuit can be performed
under the assumption that VOUT(MAX) >> VIN(MIN) for
most automotive applications of the AT9932. The
simplified equations given below produce excellent
results under this assumption. See Equation 3-7 and
Equation 3-8.
EQUATION 3-7:
2
9D MAX
L1 IO
C d = ---------------------------- -------------------- 1 – D MAX V IN MIN
EQUATION 3-8:
V IN MIN
R d = -----------------------3D MAX I O
DS20005789A-page 10
2018 Microchip Technology Inc.
AT9932
In cases where the above assumption is not valid, the
equations for Rd and Cd could still be used. However,
they may produce conservative results. Power
dissipation in the damping resistor Rd can be computed
as shown in Equation 3-9.
AT9932
AVDD
NTC
T1
DIV
T2
DRP
REF
10KΩ
R5
CREF
EQUATION 3-9:
2
V C1
P Rd = ------------------12 R d
Where:
I OUT D
V C1 = ---------------------fS C1
Output Overvoltage Protection
The AT9932 LED lamp driver supplies constant current
to the load. Therefore, an output circuit protection is
needed to prevent dramatic failures when the output
load fails to open. A simple addition of a Zener diode
(ZD1 in the Typical Application Circuit) will limit the
output voltage when the output LED connection is lost.
3.10
R6
RS
FIGURE 3-3:
Output Current Feedback
without Temperature Foldback.
is the peak-to-peak voltage ripple at the coupling
capacitor.
3.9
FB
Programming LED Current and
Temperature Foldback
The AT9932 offers a temperature foldback feature that
allows the programming of output current in
accordance
with
the
temperature
derating
characteristics provided by the LED manufacturers. A
typical derating curve is shown in Figure 3-2.
ILED
I1
When no temperature foldback is required, NTC and
T1 should be connected to AVDD. In addition, DIV and
DRP should be connected to GND. T2 still requires a
resistor to GND (10 kΩ–100 kΩ). No pins should be left
floating as shown in Figure 3-3. In this case, the output
current of the AT9932 LED driver is programmed using
Equation 3-10:
EQUATION 3-10:
V REF R 6
I 1 = ------------ -----RS
R5
Where VREF is voltage at the REF pin (VREF = 1.25V).
When temperature foldback is required, the
Equation 3-10 is also used to calculate LED current I1
at temperature below T1.
When an external NTC resistor is connected (See
Figure 3-4.), both temperatures T1 and T2, as well as
the current I2 can be accurately programmed to safely
regulate the light output of the LED lamp at the higher
temperature range between T1 and T2.
The ratio of the resistor divider R2 /(R1 + R2) programs
the voltage at the NTC pin. The voltage at T1 is
approximately 3.5V. The currents sourced by NTC and
T1 pins are mirrored into DRP in accordance with
Equation 3-11.
EQUATION 3-11:
4
I DRP = ------ I NTC – 3I T1 0
30
I2
No current is sourced from DRP when INTC < 3 x IT1.
T1
FIGURE 3-2:
of LED Current.
T2 TEMP
Temperature Derating Curve
Temperature T1 is programmed by selecting R2 such
that (See Equation 3-12.):
EQUATION 3-12:
R 2 = 3R NTC T1
Where RNTC(T1) is the resistance of the NTC resistor at
temperature T1.
2018 Microchip Technology Inc.
DS20005789A-page 11
AT9932
EQUATION 3-16:
V IN STOP = 0.84 V IN START
AT9932
NTC
RNTC
DIV
T1
DRP
T2
R1
R2
REF
FB
The hysteresis is provided to prevent oscillation.
R3
R4
R5
CREF
R6
RS
FIGURE 3-4:
Output Current Feedback
with Temperature Foldback.
At temperature higher than T1, further reduction of the
NTC resistance RNTC will create a proportional offset of
the current feedback reference voltage at DRP, and will
therefore decrease the LED current. To program the
desired LED current I2 at the temperature T2, the
resistor R4 at DRP can be calculated as shown in
Equation 3-13.
The AT9932 becomes disabled and draws less than
100 µA of current from VIN or VDD when the UVLO pin
voltage falls below the UVLO lower threshold. The
1.25V reference at the REF pin becomes 0V at this
condition. Hence, the UVLO input can also be used as
a low stand-by power disable input.
3.12
Fault Comparator (FLT)
AT9932
REF
R51
EQUATION 3-13:
FLT
R52
FB
R6
CREF
30R NTC T2 R 1 + R 2
R5
R 4 = I 1 – I 2 R S --------------------------------------------------------- ------------------4V T1 R 2 – 3R NTC T2 R 5 + R 6
Where RNTC(T2) is the resistance of the NTC resistor at the
temperature T2, and VT1 is the voltage at the T1 pin
(VT1 ≈ 3.5V).
When
the
current
from
the
NTC
pin
exceeds 3 x IT1 + 6 x IT2, overtemperature shutdown is
triggered. The voltage at T2 is approximately equal to
the voltage at T1. Selecting resistance of R3 at the T2
pin programs the desired shutdown temperature T2.
Refer to Equation 3-14.
FIGURE 3-5:
Protection.
RS
Output Short-circuit
The AT9932 also provides an internal protection
comparator that can be used for protection against
short and open LED string conditions. When the
voltage at the FLT input falls below the GND potential,
the AT9932 shuts down. The soft-start capacitor at SS
is discharged. Switching resumes automatically after a
POR delay.
Configuring the FLT input to protect against a short
LED string is illustrated in Figure 3-5. The short-circuit
current can be calculated as shown in Equation 3-17.
EQUATION 3-14:
6R NTC T2 R 1 + R 2
R 3 = -------------------------------------------------------R 2 – 3R NTC T2
The
overtemperature
recovery
threshold
is
independent of the current at T2 pin. The AT9932
recovers from thermal shutdown at the break
temperature T1, where INTC < 3 x IT1.
3.11
Input Undervoltage Lockout
(UVLO) Protection
EQUATION 3-17:
V REF R 6 + R 52
I SHORT = ------------ --------------------R 51
RS
The same resistor divider can be used to protect the
LED driver from the open LED string condition, as
shown in the Typical Application Circuit. The addition
of a Zener diode ZD1 causes the FLT comparator to trip
when VOUT > VZ.
To protect the AT9932 against excessive input current
at low input supply voltage, the undervoltage lockout
protection comparator input is provided. Connecting a
resistor divider between VIN and GND programs the
VIN start and VIN stop thresholds as indicated in
Equation 3-15 and Equation 3-16.
EQUATION 3-15:
R IN1 + R IN2 1.25V
V IN START = -------------------------------------------------------R IN2
DS20005789A-page 12
2018 Microchip Technology Inc.
AT9932
4.0
PACKAGING INFORMATION
4.1
Package Marking Information
24-lead TSSOP
XXXXXXXX
e3 YYWW
NNN
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
Example
AT9932TS
e3 1825
967
Product Code or Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
Pb-free JEDEC® designator for Matte Tin (Sn)
This package is Pb-free. The Pb-free JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for product code or customer-specific information. Package may or
not include the corporate logo.
2018 Microchip Technology Inc.
DS20005789A-page 13
AT9932
24-Lead TSSOP Package Outline (TS)
7.80x4.40mm body, 1.20mm height (max), 0.65mm pitch
D
24
θ1
E1 E
Note 1
(Index Area)
L2
L
e
1
L1
b
Top View
θ
View B
Gauge
Plane
Seating
Plane
View B
A
A A2
Seating
Plane
A1
Side View
View A-A
A
Note: For the most current package drawings, see the Microchip Packaging Specification at www.microchip.com/packaging.
Note:
1. $3LQLGHQWL¿HUPXVWEHORFDWHGLQWKHLQGH[DUHDLQGLFDWHG7KH3LQLGHQWL¿HUFDQEHDPROGHGPDUNLGHQWL¿HUDQHPEHGGHGPHWDOPDUNHURU
a printed indicator.
Symbol
Dimension
(mm)
A
A1
A2
b
D
E
E1
MIN
0.85*
0.05
0.80
0.19
7.70
6.20*
4.30
NOM
-
-
1.00
-
7.80
6.40
4.40
MAX
1.20
0.15
1.15†
0.30
7.90
6.60*
4.50
e
L
L1
L2
0.65
BSC
0.60
0.75
ș
ș
0O
0.45
1.00
REF
0.25
BSC
-
12O
REF
8O
JEDEC Registration MS-153, Variation AD, Issue F, May 2001.
7KLVGLPHQVLRQLVQRWVSHFL¿HGLQWKH-('(&GUDZLQJ
7KLVGLPHQVLRQGLIIHUVIURPWKH-('(&GUDZLQJ
Drawings are not to scale.
DS20005789A-page 14
2018 Microchip Technology Inc.
AT9932
APPENDIX A:
REVISION HISTORY
Revision A (May 2018)
• Converted Supertex Doc# DSFP-AT9932 to
Microchip DS20005789A
• Changed the package marking format
• Changed the quantity of the 24-lead TSSOP TS
package from 3000/Reel to 2500/Reel
• Made minor text changes throughout the document
2018 Microchip Technology Inc.
DS20005789A-page 15
AT9932
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, contact your local Microchip representative or sales office.
PART NO.
Device
XX
-
Package
Options
X
-
Environmental
X
Media Type
Device:
AT9932 =
Automotive Boost-Buck LED Lamp Driver
IC
Package:
TS
=
24-lead TSSOP
Environmental:
G
=
Lead (Pb)-free/RoHS-compliant Package
Media Type:
(blank)
=
2500/Reel for a TS Package
DS20005789A-page 16
Example:
a)
AT9932TS-G:
Automotive Boost-Buck LED
Lamp Driver IC, 24-lead TSSOP,
2500/Reel
2018 Microchip Technology Inc.
Note the following details of the code protection feature on Microchip devices:
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
•
There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights unless otherwise stated.
Microchip received ISO/TS-16949:2009 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperipherals, nonvolatile memory and
analog products. In addition, Microchip’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
QUALITY MANAGEMENT SYSTEM
CERTIFIED BY DNV
Trademarks
The Microchip name and logo, the Microchip logo, AnyRate, AVR,
AVR logo, AVR Freaks, BitCloud, CryptoMemory, CryptoRF,
dsPIC, FlashFlex, flexPWR, Heldo, JukeBlox, KeeLoq, Kleer,
LANCheck, LINK MD, maXStylus, maXTouch, MediaLB,
megaAVR, MOST, MOST logo, MPLAB, OptoLyzer, PIC,
picoPower, PICSTART, PIC32 logo, Prochip Designer, QTouch,
SAM-BA, SpyNIC, SST, SST Logo, SuperFlash, tinyAVR, UNI/O,
and XMEGA are registered trademarks of Microchip Technology
Incorporated in the U.S.A. and other countries.
ClockWorks, The Embedded Control Solutions Company,
EtherSynch, Hyper Speed Control, HyperLight Load, IntelliMOS,
mTouch, Precision Edge, and Quiet-Wire are registered
trademarks of Microchip Technology Incorporated in the U.S.A.
Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, BodyCom, chipKIT, chipKIT logo,
CodeGuard, CryptoAuthentication, CryptoAutomotive,
CryptoCompanion, CryptoController, dsPICDEM, dsPICDEM.net,
Dynamic Average Matching, DAM, ECAN, EtherGREEN, InCircuit Serial Programming, ICSP, INICnet, Inter-Chip
Connectivity, JitterBlocker, KleerNet, KleerNet logo, memBrain,
Mindi, MiWi, motorBench, MPASM, MPF, MPLAB Certified logo,
MPLIB, MPLINK, MultiTRAK, NetDetach, Omniscient Code
Generation, PICDEM, PICDEM.net, PICkit, PICtail, PowerSmart,
PureSilicon, QMatrix, REAL ICE, Ripple Blocker, SAM-ICE, Serial
Quad I/O, SMART-I.S., SQI, SuperSwitcher, SuperSwitcher II,
Total Endurance, TSHARC, USBCheck, VariSense, ViewSpan,
WiperLock, Wireless DNA, and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
Silicon Storage Technology is a registered trademark of Microchip
Technology Inc. in other countries.
GestIC is a registered trademarks of Microchip Technology
Germany II GmbH & Co. KG, a subsidiary of Microchip
Technology Inc., in other countries.
All other trademarks mentioned herein are property of their
respective companies.
©2018, Microchip Technology Incorporated, All Rights Reserved.
ISBN: 978-1-5224-3186-2
== ISO/TS 16949 ==
2018 Microchip Technology Inc.
DS20005789A-page 17
Worldwide Sales and Service
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ASIA/PACIFIC
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Corporate Office
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Technical Support:
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DS20005789A-page 18
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2018 Microchip Technology Inc.
10/25/17