SAMA5D2 SIP
SAMA5D2 System in Package (SIP) MPU with up to 1 Gbit
DDR2 SDRAM or 2 Gbit LPDDR2 SDRAM
Scope
This document is an overview of the main features of the SAMA5D2 SIP. The sole reference documents for product
information on the SAMA5D2 and the LPDDR2/DDR2-SDRAM memories are listed in the table below.
Introduction
The SAMA5D2 System-In-Package (SIP) integrates the Arm® Cortex®-A5 processor-based SAMA5D2 MPU with up
to 1 Gbit DDR2-SDRAM or up to 2 Gbit LPDDR2-SDRAM in a single package.
By combining the high-performance, ultra-low power SAMA5D2 with LPDDR2/DDR2-SDRAM in a single package,
PCB routing complexity, area and number of layers is reduced in the majority of cases. This makes board design
easier and more robust by facilitating design for EMI, ESD and signal integrity.
DDR2-SDRAM memory sizes and package options available
• 128 Mbit, TFBGA196
• 512 Mbit and 1 Gbit, TFBGA289
LPDDR2-SDRAM memory sizes and package options available
• 1 Gbit and 2 Gbit, TFBGA361
While the smallest option targets applications with a small OS or bare metal, the larger options are suitable for
applications using Linux®.
Reference Documents
Type
Document Title
Available
Ref. No.
Data sheet
SAMA5D2 Series
www.microchip.com
DS60001476
Data sheet
2 Mwords × 4 Banks × 16 bits
DDR2 SDRAM (128 Mbit)
www.winbond.com
W9712G6KB25I
Data sheet
8 Mwords × 4 Banks × 16 bits
DDR2 SDRAM (512 Mbit)
www.winbond.com
W9751G6KB25I
Data sheet
8 Mwords × 8 Banks × 16 bits
DDR2 SDRAM (1 Gbit)
www.winbond.com
W971GG6SB25I
Data sheet
4 Mwords × 8 Banks × 32 bits
LPDDR2-SDRAM (1 Gbit)
www.apmemory.com
AD210032F-I-AB
Data sheet
8 Mwords × 8 Banks × 32 bits
LPDDR2-SDRAM (2 Gbit)
www.apmemory.com
AD220032D-I-ED/PC/AB
© 2021 Microchip Technology Inc.
Datasheet
DS60001484D-page 1
SAMA5D2 SIP
Table of Contents
Scope............................................................................................................................................................. 1
Introduction.....................................................................................................................................................1
Reference Documents....................................................................................................................................1
1.
Features.................................................................................................................................................. 4
2.
DDR2-SDRAM Features......................................................................................................................... 7
3.
LPDDR2-SDRAM Features.....................................................................................................................8
4.
Configuration Summary.......................................................................................................................... 9
5.
Chip Identifier........................................................................................................................................ 10
6.
Package and Ballout..............................................................................................................................11
7.
Memory................................................................................................................................................. 39
8.
Electrical Characteristics.......................................................................................................................40
8.1.
8.2.
8.3.
9.
Recommended Thermal Operating Conditions.......................................................................... 40
Decoupling................................................................................................................................. 40
Power Sequences...................................................................................................................... 40
Mechanical Characteristics................................................................................................................... 45
9.1.
9.2.
9.3.
361-ball TFBGA..........................................................................................................................45
289-ball TFBGA..........................................................................................................................48
196-ball TFBGA..........................................................................................................................49
10. Ordering Information............................................................................................................................. 50
11. Revision History.................................................................................................................................... 51
11.1.
11.2.
11.3.
11.4.
DS60001484D - 03/2021............................................................................................................51
DS60001484C - 01/2020............................................................................................................51
DS60001484B - 11/2018............................................................................................................ 51
DS60001484A - 09/2017............................................................................................................51
The Microchip Website.................................................................................................................................52
Product Change Notification Service............................................................................................................52
Customer Support........................................................................................................................................ 52
Product Identification System.......................................................................................................................53
Microchip Devices Code Protection Feature................................................................................................ 53
Legal Notice................................................................................................................................................. 54
Trademarks.................................................................................................................................................. 54
Quality Management System....................................................................................................................... 55
© 2021 Microchip Technology Inc.
Datasheet
DS60001484D-page 2
SAMA5D2 SIP
Worldwide Sales and Service.......................................................................................................................56
© 2021 Microchip Technology Inc.
Datasheet
DS60001484D-page 3
SAMA5D2 SIP
Features
1.
Features
•
•
•
•
•
Arm Cortex-A5 Core
– ARMv7-A architecture
– Arm TrustZone®
™
– NEON Media Processing Engine
– Up to 500 MHz
– ETM/ETB 8 Kbytes
Memory Architecture
– Memory Management Unit
– 32-Kbyte L1 data cache, 32-Kbyte L1 instruction cache
– 128-Kbyte L2 cache configurable to be used as an internal SRAM
– DDR2-SDRAM memory up to 1 Gb
– LPDDR2-SDRAM memory up to 2 Gb
– One 128-Kbyte scrambled internal SRAM
– One 160-Kbyte internal ROM
• 64-Kbyte scrambled and maskable ROM embedding bootloader/Secure bootloader
• 96-Kbyte unscrambled, unmaskable ROM for NAND Flash BCH ECC table
– High-bandwidth scramblable 16-bit Double Data Rate (DDR) multiport dynamic RAM controller supporting
Winbond DDR2-SDRAM up to 1 Gb, including “on-the-fly” encryption/decryption path
– High-bandwidth scramblable 32-bit Double Data Rate (DDR) multiport dynamic RAM controller supporting
AP memory LPDDR2-SDRAM up to 2 Gb , including “on-the-fly” encryption/ decryption path
– 8-bit SLC/MLC NAND controller, with up to 32-bit Error Correcting Code (PMECC)
System Running up to 166 MHz
– Reset controller, shutdown controller, periodic interval timer, independent watchdog timer and secure RealTime Clock (RTC) with clock calibration
– One 600 to 1200 MHz PLL for the system and one 480 MHz PLL optimized for USB high speed
– Digital fractional PLL for audio (11.2896 MHz and 12.288 MHz)
– Internal low-power 12 MHz RC and 32 KHz typical RC
– Selectable 32.768-Hz low-power oscillator and 8 to 24 MHz oscillator
– 51 DMA Channels including two 16-channel 64-bit Central DMA Controllers
– 64-bit Advanced Interrupt Controller (AIC)
– 64-bit Secure Advanced Interrupt Controller (SAIC)
– Three programmable external clock signals
Low-Power Modes
– Ultra-Low-Power mode with fast wake-up capability
– Low-Power Backup mode with 5-Kbyte SRAM and SleepWalking™ features
• Wake-up from up to nine wake-up pins, UART reception, analog comparison
• Fast wake-up capability
• Extended Backup mode with LPDDR2/DDR2-SDRAM in Self-Refresh mode
Peripherals
– LCD TFT controller up to 1024x768, with four overlays, rotation, post-processing and alpha blending, 24-bit
parallel RGB
– ITU-R BT. 601/656/1120 Image Sensor Controller (ISC) supporting up to 5 M-pixel sensors with a parallel
12-bit interface for Raw Bayer, YCbCr, Monochrome and JPEG-compressed sensor interface
– Two Synchronous Serial Controllers (SSC), two Inter-IC Sound Controllers (I2SC), and one Stereo Class D
amplifier
– One Peripheral Touch Controller (PTC) with up to 8 X-lines and 8 Y-lines (64-channel capacitive touch)
– One Pulse Density Modulation Interface Controller (PDMIC)
© 2021 Microchip Technology Inc.
Datasheet
DS60001484D-page 4
SAMA5D2 SIP
Features
– One USB high-speed device port (UDPHS) and one USB high-speed host port or two USB high-speed host
ports (UHPHS)
– One USB high-speed host port with a High-Speed Inter-Chip (HSIC) interface
– One 10/100 Ethernet MAC (GMAC)
• Energy efficiency support (IEEE 802.3az standard)
• Ethernet AVB support with IEEE802.1AS time stamping
• IEEE®802.1Qav credit-based traffic-shaping hardware support
• IEEE1588 Precision Time Protocol (PTP)
– Two high-speed memory card hosts:
• SDMMC0: SD 3.0, eMMC 4.51, 8 bits
• SDMMC1: SD 2.0, eMMC 4.41, 4 bits only
– Two host/client Serial Peripheral Interfaces (SPI)
– Two Quad Serial Peripheral Interfaces (QSPI)
– Five FLEXCOMs (USART, SPI and TWI)
– Five UARTs
– Two host CAN-FD (MCAN) controllers with SRAM-based mailboxes, and time- and event-triggered
transmission
WARNING
•
•
•
MCAN implements the non-ISO CAN FD frame format and therefore does not pass the CAN FD
Conformance Test according to ISO 16845-1:2016.
– One Rx only UART in backup area (RXLP)
– One analog comparator (ACC) in backup area
– Two 2-wire interfaces (TWIHS) up to 400 Kbits/s supporting the I2C protocol and SMBUS (TWIHS)
– Two 3-channel 32-bit Timer/Counters (TC), supporting basic PWM modes
– One full-featured 4-channel 16-bit Pulse Width Modulation (PWM) controller
– One 12-channel, 12-bit, Analog-to-Digital Converter (ADC) with Resistive TouchScreen capability
Safety
– Zero-power Power-On Reset (POR) cells
– Main crystal clock failure detector
– Write-protected registers
– Integrity Check Monitor (ICM) based on SHA256
– Memory Management Unit
– Independent watchdog
Security
– 5 Kbytes of internal scrambled SRAM:
• 1 Kbyte non-erasable on tamper detection
• 4 Kbytes erasable on tamper detection
– 256 bits of scrambled and erasable registers
– Up to eight tamper pins for static or dynamic intrusion detections(1)
– Environmental monitors on specific versions: temperature, voltage, frequency and active die shield(2)
– Secure Boot Loader(3)
– On-the-fly AES encryption/decryption on LPDDR2/DDR2-SDRAM and QSPI memories (AESB)
– RTC including time-stamping on security intrusions
– Programmable fuse box with 544 fuse bits (including JTAG protection and BMS)
Hardware Cryptography
– SHA (SHA1, SHA224, SHA256, SHA384, SHA512): compliant with FIPS PUB 180-2
– AES: 256-, 192-, 128-bit key algorithm, compliant with FIPS PUB 197
– TDES: two-key or three-key algorithms, compliant with FIPS PUB 46-3
© 2021 Microchip Technology Inc.
Datasheet
DS60001484D-page 5
SAMA5D2 SIP
Features
•
•
– True Random Number Generator (TRNG) compliant with NIST Special Publication 800-22 Test Suite and
FIPS PUBs 140-2 and 140-3
Up to 128 I/Os
– Fully programmable through set/clear registers
– Multiplexing of up to eight peripheral functions per I/O line
– Each I/O line can be assigned to a peripheral or used as a general purpose I/O
– PIO controller features a synchronous output providing up to 32 bits of data output in one write operation
Operating Conditions
– Ambient temperature: -40°C to +85°C
Note:
1.
2.
3.
For information specific to dynamic tamper protection (PIOBU), refer to the document SAMA5D2 External
Tamper Protections (document no. 44095). Contact a Microchip sales representative for details.
For environmental monitors, refer to the document SAMA5D23 and SAMA5D28 Environmental Monitors
(document no. 44036), available under Non-Disclosure Agreement (NDA). Contact a Microchip sales
representative for details.
For secure boot strategies, refer to the document SAMA5D2 Series Secure Boot Strategy (document no.
DS00002435), available under Non-Disclosure Agreement (NDA). Contact a Microchip sales representative for
details.
© 2021 Microchip Technology Inc.
Datasheet
DS60001484D-page 6
SAMA5D2 SIP
DDR2-SDRAM Features
2.
DDR2-SDRAM Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Power Supply: DDRM_VDD, DDRM_VDDL, DDRM_VDDQ = 1.8 V ±0.1 V
Double Data Rate Architecture: Two Data Transfers per Clock Cycle
CAS Latency: 3
Burst Length: 8
Bi-Directional, Differential Data Strobes (DQS and DQSN) are Transmitted/Received with Data
Edge-Aligned with Read Data and Center-Aligned with Write Data
DLL Aligns DQ and DQS Transitions with Clock
Differential Clock Inputs (CLK and CLKN)
Data Masks (DM) for Write Data
Commands Entered on Each Positive CLK Edge, Data and Data Mask are Referenced to Both Edges of DQS
Auto-Refresh and Self-Refresh Modes
Precharged Power-Down and Active Power-Down
Write Data Mask
Write Latency = Read Latency - 1 (WL = RL - 1)
Interface: SSTL_18
© 2021 Microchip Technology Inc.
Datasheet
DS60001484D-page 7
SAMA5D2 SIP
LPDDR2-SDRAM Features
3.
LPDDR2-SDRAM Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Power Supply: DDRM_VDD18 = 1.7 to 1.9V
Power Supply: DDRM_VDD12 = 1.14 to 1.3V
Double Data Rate Architecture: Two Data Transfers per Clock Cycle
Burst Length (BL): 8
Write Latency (WL): 1
Read Latency (RL): 3
Bi-Directional, Differential Data Strobes (DQS and DQSN) are Transmitted/Received with Data
Edge-Aligned with Read Data and Center-Aligned with Write Data
Differential Clock Inputs (CLK and CLKN)
Data Masks (DM) for Write Data
Commands Entered on each Positive CLK Edge, Data and Data Mask are Referenced to Both Edges of DQS
Interface: HSUL_12
Auto-Refresh and Self-Refresh Modes
Low Power Consumption
JEDEC LPDDR2-S4B Compliance
Partial Array Self-Refresh (PASR)
Auto Temperature Compensated Self-Refresh (ATCSR) by Built-in Temperature Sensor
Deep Power-Down Mode
© 2021 Microchip Technology Inc.
Datasheet
DS60001484D-page 8
SAMA5D2 SIP
Configuration Summary
4.
Configuration Summary
Table 4-1. Configuration Summary
Feature
SAMA5D225
Package
TFBGA196
DDR2-SDRAM
LPDDR2-SDRAM
SAMA5D27
SAMA5D28
TFBGA289
TFBGA361
TFBGA289
TFBGA361
128 Mb
512 Mb
1 Gb
–
–
1 Gb
–
–
–
–
–
1 Gb
2 Gb
–
1 Gb
2 Gb
SMC
Up to 16-bit
Internal Memory Bus
Width
PIOs
16-bit
32-bit
16-bit
90
128
SRAM
128 Kbytes
QSPI
2
LCD
24-bit RGB
Camera Interface
(ISC)
1
EMAC
1
PTC
4 X-lines x 8 Ylines
8 X-lines x 8 Y-lines
CAN
1
2
USB
2
(2 Hosts or 1
Host/1 Device)
3
(2 Hosts/1 HSIC or 1 Host/1 Device/1 HSIC)
9/7/7
10 / 7 / 7
UART/SPI/I2C
SDIO/SD/MMC
2
I2S/SSC/Class
D/PDM
2/2/1/1
ADC Inputs
5
12
Timers
5
6
PWM
4 (PWM) + 5
(TC)
4 (PWM) + 6 (TC)
6
8
Tamper Pins
32-bit
AESB
Yes
Environmental
Monitors, Die Shield
–
© 2021 Microchip Technology Inc.
–
–
Datasheet
Yes
DS60001484D-page 9
SAMA5D2 SIP
Chip Identifier
5.
Chip Identifier
Table 5-1. SAMA5D2 SIP Chip ID Registers
Chip Name
CHIPID_CIDR
CHIPID_EXID
SAMA5D225C-D1M
0x00000053
SAMA5D27C-D5M
0x00000032
SAMA5D27C-D1G
0x00000033
SAMA5D27C-LD1G
SAMA5D27C-LD2G
0x8A5C08C2 or 0x8A5C08C4
0x00000061
0x00000062
SAMA5D28C-D1G
0x00000013
SAMA5D28C-LD1G
0x00000071
SAMA5D28C-LD2G
0x00000072
© 2021 Microchip Technology Inc.
Datasheet
DS60001484D-page 10
SAMA5D2 SIP
Package and Ballout
6.
Package and Ballout
The SAMA5D2 SIP is available in the packages listed below.
Important: SAMA5D2 DDR2 SIP devices are not pin-to-pin compatible with SAMA5D2 devices.
Table 6-1. Packages
Package Name
Ball Count
Ball Pitch
Package Size
TFBGA196
196
0.75 mm
11 x 11 (mm)
TFBGA289(1)
289
0.8 mm
14 x 14 (mm)
TFBGA361(2)
361
0.8 mm
16 x 16 (mm)
Notes:
1. 512 Mbit and 1 Gbit DDR2 in TFBGA289 have the same ballout.
2. 1 Gbit and 2 Gbit LPDDR2 in TFBGA361 have the same ballout.
© 2021 Microchip Technology Inc.
Datasheet
DS60001484D-page 11
© 2021 Microchip Technology Inc.
Table 6-2. Ball Description
Primary
361-ball
BGA
289-ball
BGA
196-ball
BGA
Power Rail
W11
U13
M8
VDDSDMMC
rotatethispage90
R9
W12
V11
Datasheet
W14
V10
W15
U14
T13
U15
U16
U17
L8
G8
K8
P9
P10
P11
VDDSDMMC
VDDSDMMC
VDDSDMMC
VDDSDMMC
VDDSDMMC
VDDSDMMC
VDDSDMMC
Signal
Dir
Signal
Dir
Func
Signal
Dir
IO
Set
Reset State
(Signal, Dir,
PU, PD,
HiZ, ST)(1)
GPIO_EMMC
PA0
I/O
–
–
A
SDMMC0_CK
I/O
1
PIO, I, PU, ST
B
QSPI0_SCK
O
1
GPIO_EMMC
GPIO_EMMC
GPIO_EMMC
GPIO_EMMC
GGPIO_EMMC
GPIO_EMMC
GPIO_EMMC
PA1
PA2
PA3
PA4
PA5
PA6
PA7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
–
–
–
–
–
–
–
PIO Peripheral
–
–
–
–
–
–
–
F
D0
I/O
2
A
SDMMC0_CMD
I/O
1
B
QSPI0_CS
O
1
F
D1
I/O
2
A
SDMMC0_DAT0
I/O
1
B
QSPI0_IO0
I/O
1
F
D2
I/O
2
A
SDMMC0_DAT1
I/O
1
B
QSPI0_IO1
I/O
1
F
D3
I/O
2
A
SDMMC0_DAT2
I/O
1
B
QSPI0_IO2
I/O
1
F
D4
I/O
2
A
SDMMC0_DAT3
I/O
1
B
QSPI0_IO3
I/O
1
F
D5
I/O
2
A
SDMMC0_DAT4
I/O
1
B
QSPI1_SCK
O
1
D
TIOA5
I/O
1
E
FLEXCOM2_IO0
I/O
1
DS60001484D-page 12
F
D6
I/O
2
A
SDMMC0_DAT5
I/O
1
B
QSPI1_IO0
I/O
1
D
TIOB5
I/O
1
E
FLEXCOM2_IO1
I/O
1
F
D7
I/O
2
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
SAMA5D2 SIP
R11
F7
Alternate
Package and Ballout
W16
N7
I/O
Type
© 2021 Microchip Technology Inc.
...........continued
Primary
361-ball
BGA
289-ball
BGA
196-ball
BGA
Power Rail
V12
R9
K9
VDDSDMMC
rotatethispage90
V16
V14
Datasheet
L18
T16
K18
R10
P15
N17
P16
N14
N13
L12
M14
J10
VDDSDMMC
VDDSDMMC
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
Signal
Dir
Signal
Dir
Func
Signal
Dir
IO
Set
Reset State
(Signal, Dir,
PU, PD,
HiZ, ST)(1)
GPIO_EMMC
PA8
I/O
–
–
A
SDMMC0_DAT6
I/O
1
PIO, I, PU, ST
B
QSPI1_IO1
I/O
1
GPIO_EMMC
GPIO_EMMC
GPIO
GPIO
GPIO
GPIO_QSPI
PA9
PA10
PA11
PA12
PA13
PA14
I/O
I/O
I/O
I/O
I/O
I/O
–
–
–
–
–
–
PIO Peripheral
–
–
–
–
–
–
D
TCLK5
I
1
E
FLEXCOM2_IO2
I/O
1
F
NWE/NANDWE
O
2
A
SDMMC0_DAT7
I/O
1
B
QSPI1_IO2
I/O
1
D
TIOA4
I/O
1
E
FLEXCOM2_IO3
O
1
F
NCS3
O
2
A
SDMMC0_RSTN
O
1
B
QSPI1_IO3
I/O
1
D
TIOB4
I/O
1
E
FLEXCOM2_IO4
O
1
F
A21/NANDALE
O
2
A
SDMMC0_1V8SEL
O
1
B
QSPI1_CS
O
1
D
TCLK4
I
1
F
A22/NANDCLE
O
2
A
SDMMC0_WP
I
1
B
IRQ
I
1
F
NRD/NANDOE
O
2
A
SDMMC0_CD
I
1
E
FLEXCOM3_IO1
I/O
1
F
D8
I/O
2
A
SPI0_SPCK
I/O
1
B
TK1
I/O
1
C
QSPI0_SCK
O
2
D
I2SC1_MCK
O
2
E
FLEXCOM3_IO2
I/O
1
F
D9
I/O
2
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
SAMA5D2 SIP
M17
J9
Alternate
Package and Ballout
DS60001484D-page 13
R19
P8
I/O
Type
© 2021 Microchip Technology Inc.
...........continued
Primary
361-ball
BGA
289-ball
BGA
196-ball
BGA
Power Rail
L17
N16
L14
VDDIOP1
rotatethispage90
N19
M16
M11
N14
H14
K14
VDDIOP1
VDDIOP1
I/O
Type
Signal
Dir
Signal
Dir
Func
Signal
Dir
IO
Set
Reset State
(Signal, Dir,
PU, PD,
HiZ, ST)(1)
GPIO
PA15
I/O
–
–
A
SPI0_MOSI
I/O
1
PIO, I, PU, ST
B
TF1
I/O
1
C
QSPI0_CS
O
2
D
I2SC1_CK
I/O
2
E
FLEXCOM3_IO0
I/O
1
F
D10
I/O
2
A
SPI0_MISO
I/O
1
GPIO_IO
GPIO_IO
PA16
PA17
Alternate
I/O
I/O
–
–
PIO Peripheral
–
–
Datasheet
V19
P12
VDDIOP1
VDDIOP1
GPIO_IO
GPIO_IO
PA18
PA19
I/O
I/O
–
–
–
–
O
1
I/O
2
D
I2SC1_WS
I/O
2
E
FLEXCOM3_IO3
O
1
DS60001484D-page 14
F
D11
I/O
2
A
SPI0_NPCS0
I/O
1
B
RD1
I
1
C
QSPI0_IO1
I/O
2
D
I2SC1_DI0
I
2
E
FLEXCOM3_IO4
O
1
F
D12
I/O
2
A
SPI0_NPCS1
O
1
B
RK1
I/O
1
C
QSPI0_IO2
I/O
2
D
I2SC1_DO0
O
2
E
SDMMC1_DAT0
I/O
1
F
D13
I/O
2
A
SPI0_NPCS2
O
1
1
B
RF1
I/O
C
QSPI0_IO3
I/O
2
D
TIOA0
I/O
1
E
SDMMC1_DAT1
I/O
1
F
D14
I/O
2
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
SAMA5D2 SIP
T15
L9
TD1
QSPI0_IO0
Package and Ballout
V15
T16
B
C
PIO, I, PU, ST
© 2021 Microchip Technology Inc.
...........continued
Primary
361-ball
BGA
289-ball
BGA
196-ball
BGA
Power Rail
T10
P9
H9
VDDIOP1
rotatethispage90
U19
V17
Datasheet
U18
W17
T17
T14
R17
K10
G10
P13
H10
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
VDDIOP1
Signal
Dir
Signal
Dir
GPIO_IO
PA20
I/O
–
–
GPIO_IO
GPIO_QSPI
GPIO
GPIO_IO
GPIO_IO
PA21
PA22
PA23
PA24
PA25
I/O
I/O
I/O
I/O
I/O
–
–
–
–
–
–
–
–
–
–
Func
Signal
Dir
IO
Set
Reset State
(Signal, Dir,
PU, PD,
HiZ, ST)(1)
PIO, I, PU, ST
A
SPI0_NPCS3
O
1
D
TIOB0
I/O
1
E
SDMMC1_DAT2
I/O
1
F
D15
I/O
2
A
IRQ
I
2
B
PCK2
O
3
D
TCLK0
I
1
E
SDMMC1_DAT3
I/O
1
F
NANDRDY
I
2
A
FLEXCOM1_IO2
I/O
1
B
D0
I/O
1
C
TCK
I
4
D
SPI1_SPCK
I/O
2
E
SDMMC1_CK
I/O
1
F
QSPI0_SCK
O
3
A
FLEXCOM1_IO1
I/O
1
B
D1
I/O
1
C
TDI
I
4
D
SPI1_MOSI
I/O
2
F
QSPI0_CS
O
3
A
FLEXCOM1_IO0
I/O
1
B
D2
I/O
1
C
TDO
O
4
D
SPI1_MISO
I/O
2
F
QSPI0_IO0
I/O
3
A
FLEXCOM1_IO3
O
1
B
D3
I/O
1
C
TMS
I
4
D
SPI1_NPCS0
I/O
2
F
QSPI0_IO1
I/O
3
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
SAMA5D2 SIP
R16
G9
PIO Peripheral
Package and Ballout
DS60001484D-page 15
W18
P10
Alternate
I/O
Type
© 2021 Microchip Technology Inc.
...........continued
Primary
361-ball
BGA
289-ball
BGA
196-ball
BGA
Power Rail
U14
P17
L10
VDDIOP1
rotatethispage90
M18
U13
R15
R14
P14
N12
VDDIOP1
VDDIOP1
Alternate
PIO Peripheral
U12
R13
N11
M11
VDDIOP1
VDDIOP1
VDDIOP1
O
1
PIO, I, PU, ST
D4
I/O
1
Signal
Dir
Func
Signal
GPIO_IO
PA26
I/O
–
–
A
B
GPIO_IO
GPIO
PA27
PA28
I/O
I/O
–
–
–
–
GPIO
GPIO
GPIO
PA29
PA30
PA31
I/O
I/O
I/O
–
–
–
–
–
–
C
NTRST
I
4
D
SPI1_NPCS1
O
2
F
QSPI0_IO2
I/O
3
A
TIOA1
I/O
2
B
D5
I/O
1
C
SPI0_NPCS2
O
2
D
SPI1_NPCS2
O
2
E
SDMMC1_RSTN
O
1
F
QSPI0_IO3
I/O
3
A
TIOB1
I/O
2
B
D6
I/O
1
C
SPI0_NPCS3
O
2
D
SPI1_NPCS3
O
2
E
SDMMC1_CMD
I/O
1
F
CLASSD_L0
O
1
A
TCLK1
I
2
B
D7
I/O
1
C
SPI0_NPCS1
O
2
E
SDMMC1_WP
I
1
F
CLASSD_L1
O
1
B
NWE/NANDWE
O
1
C
SPI0_NPCS0
I/O
2
D
PWMH0
O
1
E
SDMMC1_CD
I
1
F
CLASSD_L2
O
1
B
NCS3
O
1
C
SPI0_MISO
I/O
2
D
PWML0
O
1
F
CLASSD_L3
O
1
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
SAMA5D2 SIP
P13
M12
FLEXCOM1_IO4
Dir
Package and Ballout
DS60001484D-page 16
U17
P14
IO
Set
Signal
Datasheet
U16
Dir
Reset State
(Signal, Dir,
PU, PD,
HiZ, ST)(1)
I/O
Type
© 2021 Microchip Technology Inc.
...........continued
Primary
361-ball
BGA
289-ball
BGA
196-ball
BGA
Power Rail
C7
F5
E6
VDDIOP0
rotatethispage90
A9
A10
A11
Datasheet
A12
A7
C7
B8
B7
A10
C6
C5
D5
D7
C8
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
Signal
Dir
Signal
Dir
GPIO
PB0
I/O
–
–
GPIO
GPIO
GPIO
GPIO
GPIO_QSPI
GPIO
PB1
PB2
PB3
PB4
PB5
PB6
I/O
I/O
I/O
I/O
I/O
I/O
–
–
–
–
–
–
–
–
–
–
–
–
Dir
IO
Set
Reset State
(Signal, Dir,
PU, PD,
HiZ, ST)(1)
A21/NANDALE
O
1
PIO, I, PU, ST
SPI0_MOSI
I/O
2
D
PWMH1
O
1
B
A22/NANDCLE
O
1
C
SPI0_SPCK
I/O
2
D
PWML1
O
1
F
CLASSD_R0
O
1
Func
Signal
B
C
B
NRD/NANDOE
O
1
D
PWMFI0
I
1
F
CLASSD_R1
O
1
A
URXD4
I
1
B
D8
I/O
1
C
IRQ
I
3
D
PWMEXTRG1
I
1
F
CLASSD_R2
O
1
A
UTXD4
O
1
1
B
D9
I/O
C
FIQ
I
4
F
CLASSD_R3
O
1
A
TCLK2
I
1
1
B
D10
I/O
C
PWMH2
O
1
D
QSPI1_SCK
O
2
F
GTSUCOMP
O
3
A
TIOA2
I/O
1
DS60001484D-page 17
B
D11
I/O
1
C
PWML2
O
1
D
QSPI1_CS
O
2
F
GTXER
O
3
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
SAMA5D2 SIP
A9
D6
PIO Peripheral
Package and Ballout
B7
C8
Alternate
I/O
Type
© 2021 Microchip Technology Inc.
...........continued
Primary
361-ball
BGA
289-ball
BGA
196-ball
BGA
Power Rail
C5
D5
D9
VDDIOP0
rotatethispage90
B8
B6
Datasheet
G6
B5
C6
A8
A7
C9
F6
B9
B8
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
Signal
Dir
Signal
Dir
Func
Signal
Dir
IO
Set
Reset State
(Signal, Dir,
PU, PD,
HiZ, ST)(1)
GPIO_IO
PB7
I/O
–
–
A
TIOB2
I/O
1
PIO, I, PU, ST
B
D12
I/O
1
GPIO_IO
GPIO_IO
GPIO_IO
GPIO
GPIO
PB8
PB9
PB10
PB11
PB12
I/O
I/O
I/O
I/O
I/O
–
–
–
–
–
PIO Peripheral
–
–
–
–
–
C
PWMH3
O
1
D
QSPI1_IO0
I/O
2
F
GRXCK
I
3
A
TCLK3
I
1
B
D13
I/O
1
1
C
PWML3
O
D
QSPI1_IO1
I/O
2
F
GCRS
I
3
A
TIOA3
I/O
1
B
D14
I/O
1
C
PWMFI1
I
1
D
QSPI1_IO2
I/O
2
F
GCOL
I
3
A
TIOB3
I/O
1
B
D15
I/O
1
C
PWMEXTRG2
I
1
D
QSPI1_IO3
I/O
2
F
GRX2
I
3
A
LCDDAT0
O
1
B
A0/NBS0
O
1
C
URXD3
I
3
D
PDMIC_DAT
F
GRX3
I
3
A
LCDDAT1
O
1
B
A1
O
1
C
UTXD3
O
3
D
PDMIC_CLK
F
GTX2
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
2
2
O
3
PIO, I, PU, ST
SAMA5D2 SIP
B6
C7
Alternate
Package and Ballout
DS60001484D-page 18
A6
E5
I/O
Type
© 2021 Microchip Technology Inc.
...........continued
Primary
361-ball
BGA
289-ball
BGA
196-ball
BGA
Power Rail
C4
C5
B7
VDDIOP0
rotatethispage90
G4
H4
Datasheet
A4
B3
A6
E4
B5
C4
G6
B5
C4
A5
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP0
I/O
Type
Signal
Dir
Signal
Dir
Func
Signal
Dir
IO
Set
Reset State
(Signal, Dir,
PU, PD,
HiZ, ST)(1)
GPIO
PB13
I/O
–
–
A
LCDDAT2
O
1
PIO, I, PU, ST
B
A2
O
1
C
PCK1
O
3
F
GTX3
O
3
A
LCDDAT3
O
1
B
A3
O
1
C
TK1
I/O
2
D
I2SC1_MCK
O
1
E
QSPI1_SCK
O
3
F
GTXCK
I/O
3
A
LCDDAT4
O
1
GPIO_QSPI
GPIO
GPIO_IO
GPIO_IO
PB14
PB15
PB16
PB17
Alternate
I/O
I/O
I/O
I/O
–
–
–
–
PIO Peripheral
–
–
–
–
B
A4
O
1
C
TF1
I/O
2
D
I2SC1_CK
I/O
1
E
QSPI1_CS
O
3
F
GTXEN
O
3
A
LCDDAT5
O
1
B
A5
O
1
O
2
I2SC1_WS
I/O
1
E
QSPI1_IO0
I/O
3
F
GRXDV
I
3
A
LCDDAT6
O
1
B
A6
O
1
C
RD1
I
2
DS60001484D-page 19
D
I2SC1_DI0
I
1
E
QSPI1_IO1
I/O
3
F
GRXER
I
3
PIO, I, PU, ST
PIO, I, PU, ST
SAMA5D2 SIP
TD1
D
PIO, I, PU, ST
Package and Ballout
C
PIO, I, PU, ST
© 2021 Microchip Technology Inc.
...........continued
Primary
361-ball
BGA
289-ball
BGA
196-ball
BGA
Power Rail
D3
A5
B4
VDDIOP0
rotatethispage90
F4
F2
B4
A4
A6
A4
VDDIOP0
VDDIOP0
I/O
Type
Signal
Dir
Signal
Dir
Func
Signal
Dir
IO
Set
Reset State
(Signal, Dir,
PU, PD,
HiZ, ST)(1)
GPIO_IO
PB18
I/O
–
–
A
LCDDAT7
O
1
PIO, I, PU, ST
B
A7
O
1
C
RK1
I/O
2
D
I2SC1_DO0
O
1
E
QSPI1_IO2
I/O
3
F
GRX0
I
3
A
LCDDAT8
O
1
GPIO_IO
GPIO
PB19
PB20
Alternate
I/O
I/O
–
–
PIO Peripheral
–
–
Datasheet
F3
D3
VDDIOP0
VDDIOP0
GPIO
GPIO
PB21
PB22
I/O
I/O
–
–
–
–
O
1
I/O
2
D
TIOA3
I/O
2
E
QSPI1_IO3
I/O
3
F
GRX1
I
3
A
LCDDAT9
O
1
B
A9
O
1
C
TK0
I/O
1
D
TIOB3
I/O
2
E
PCK1
O
4
F
GTX0
O
3
A
LCDDAT10
O
1
B
A10
O
1
C
TF0
I/O
1
D
TCLK3
I
2
E
FLEXCOM3_IO2
I/O
3
F
GTX1
O
3
A
LCDDAT11
O
1
DS60001484D-page 20
B
A11
O
1
C
TD0
O
1
D
TIOA2
I/O
2
E
FLEXCOM3_IO1
I/O
3
F
GMDC
O
3
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
SAMA5D2 SIP
C3
A3
A8
RF1
Package and Ballout
E4
D3
B
C
PIO, I, PU, ST
© 2021 Microchip Technology Inc.
...........continued
Primary
361-ball
BGA
289-ball
BGA
196-ball
BGA
Power Rail
H2
B3
B2
VDDIOP0
rotatethispage90
A3
H1
E2
A3
E3
E2
VDDIOP0
VDDIOP0
I/O
Type
Signal
Dir
Signal
Dir
Func
Signal
Dir
IO
Set
Reset State
(Signal, Dir,
PU, PD,
HiZ, ST)(1)
GPIO
PB23
I/O
–
–
A
LCDDAT12
O
1
PIO, I, PU, ST
B
A12
O
1
GPIO
GPIO
PB24
PB25
Alternate
I/O
I/O
–
–
PIO Peripheral
–
–
Datasheet
G2
H5
G3
F4
D4
C3
VDDIOP0
VDDIOP0
GPIO
GPIO
PB26
PB27
I/O
I/O
–
–
–
–
C
RD0
I
1
D
TIOB2
I/O
2
E
FLEXCOM3_IO0
I/O
3
F
GMDIO
I/O
3
A
LCDDAT13
O
1
B
A13
O
1
C
RK0
I/O
1
D
TCLK2
I
2
E
FLEXCOM3_IO3
O
3
F
ISC_D10
I
3
A
LCDDAT14
O
1
B
A14
O
1
C
RF0
I/O
1
E
FLEXCOM3_IO4
O
3
ISC_D11
I
3
LCDDAT15
O
1
B
A15
O
1
C
URXD0
I
1
D
PDMIC_DAT
F
ISC_D0
I
3
A
LCDDAT16
O
1
B
A16
O
1
C
UTXD0
O
1
D
PDMIC_CLK
F
ISC_D1
PIO, I, PU, ST
PIO, I, PU, ST
1
3
SAMA5D2 SIP
1
I
PIO, I, PU, ST
Package and Ballout
DS60001484D-page 21
F
A
PIO, I, PU, ST
© 2021 Microchip Technology Inc.
...........continued
Primary
361-ball
BGA
289-ball
BGA
196-ball
BGA
Power Rail
J2
D2
D2
VDDIOP0
rotatethispage90
J3
A2
Datasheet
J4
T14
C2
G7
N10
F3
A2
L13
H11
VDDIOP0
VDDIOP0
VDDIOP0
VDDIOP1
VDDIOP1
Signal
Dir
Signal
Dir
Func
Signal
Dir
IO
Set
Reset State
(Signal, Dir,
PU, PD,
HiZ, ST)(1)
GPIO
PB28
I/O
–
–
A
LCDDAT17
O
1
PIO, I, PU, ST
B
A17
O
1
C
FLEXCOM0_IO0
I/O
1
D
TIOA5
I/O
2
F
ISC_D2
I
3
A
LCDDAT18
O
1
B
A18
O
1
GPIO
GPIO
GPIO
GPIO
GPIO
PB29
PB30
PB31
PC0
PC1
I/O
I/O
I/O
I/O
I/O
–
–
–
–
–
PIO Peripheral
–
–
–
–
–
C
FLEXCOM0_IO1
I/O
1
D
TIOB5
I/O
2
F
ISC_D3
I
3
A
LCDDAT19
O
1
B
A19
O
1
C
FLEXCOM0_IO2
I/O
1
D
TCLK5
I
2
F
ISC_D4
I
3
A
LCDDAT20
O
1
B
A20
O
1
C
FLEXCOM0_IO3
O
1
D
TWD0
I/O
1
F
ISC_D5
I
3
A
LCDDAT21
O
1
B
A23
O
1
C
FLEXCOM0_IO4
O
1
D
TWCK0
I/O
1
F
ISC_D6
I
3
A
LCDDAT22
O
1
B
A24
O
1
C
CANTX0
O
1
D
SPI1_SPCK
I/O
1
E
I2SC0_CK
I/O
1
F
ISC_D7
I
3
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
SAMA5D2 SIP
N11
B3
Alternate
Package and Ballout
DS60001484D-page 22
R16
G8
I/O
Type
© 2021 Microchip Technology Inc.
...........continued
Primary
361-ball
BGA
289-ball
BGA
196-ball
BGA
Power Rail
T15
N9
L11
VDDIOP1
rotatethispage90
T13
P16
M10
N15
F13
G14
VDDIOP1
VDDIOP1
I/O
Type
Signal
Dir
Signal
Dir
Func
Signal
Dir
IO
Set
Reset State
(Signal, Dir,
PU, PD,
HiZ, ST)(1)
GPIO
PC2
I/O
–
–
A
LCDDAT23
O
1
PIO, I, PU, ST
B
A25
O
1
GPIO
GPIO
PC3
PC4
Alternate
I/O
I/O
–
–
PIO Peripheral
–
–
Datasheet
L19
J13
VDDIOP1
VDDIOP1
GPIO
GPIO
PC5
PC6
I/O
I/O
–
–
–
–
I
1
SPI1_MOSI
I/O
1
E
I2SC0_MCK
O
1
F
ISC_D8
I
3
A
LCDPWM
O
1
B
NWAIT
I
1
C
TIOA1
I/O
1
D
SPI1_MISO
I/O
1
E
I2SC0_WS
I/O
1
F
ISC_D9
I
3
A
LCDDISP
O
1
B
NWR1/NBS1
O
1
C
TIOB1
I/O
1
D
SPI1_NPCS0
I/O
1
E
I2SC0_DI0
I
1
F
ISC_PCK
I
3
A
LCDVSYNC
O
1
B
NCS0
O
1
C
TCLK1
I
1
D
SPI1_NPCS1
O
1
E
I2SC0_DO0
O
1
F
ISC_VSYNC
I
3
A
LCDHSYNC
O
1
DS60001484D-page 23
B
NCS1
O
1
C
TWD1
I/O
1
D
SPI1_NPCS2
O
1
F
ISC_HSYNC
I
3
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
SAMA5D2 SIP
L11
J14
CANRX0
D
Package and Ballout
R15
M16
C
© 2021 Microchip Technology Inc.
...........continued
Primary
361-ball
BGA
289-ball
BGA
196-ball
BGA
Power Rail
N15
M15
F14
VDDIOP1
rotatethispage90
P11
B2
Datasheet
K5
C2
M13
B2
G4
A2
K13
–
–
–
VDDIOP1
VDDISC
VDDISC
VDDISC
I/O
Type
Signal
Dir
Signal
Dir
Func
Signal
Dir
IO
Set
Reset State
(Signal, Dir,
PU, PD,
HiZ, ST)(1)
GPIO_CLK
PC7
I/O
–
–
A
LCDPCK
O
1
PIO, I, PU, ST
B
NCS2
O
1
C
TWCK1
I/O
1
D
SPI1_NPCS3
O
1
E
URXD1
I
2
F
ISC_MCK
O
3
A
LCDDEN
O
1
GPIO
GPIO
GPIO
GPIO
PC8
PC9
PC10
PC11
Alternate
I/O
I/O
I/O
I/O
–
–
–
–
PIO Peripheral
–
–
–
–
B
NANDRDY
I
1
C
FIQ
I
1
D
PCK0
O
3
E
UTXD1
O
2
I
3
FIQ
I
3
B
GTSUCOMP
O
1
C
ISC_D0
I
1
D
TIOA4
I/O
2
A
LCDDAT2
O
2
B
GTXCK
I/O
1
C
ISC_D1
I
1
D
TIOB4
I/O
2
E
CANTX0
O
2
A
LCDDAT3
O
2
B
GTXEN
O
1
C
ISC_D2
I
1
D
TCLK4
I
2
DS60001484D-page 24
E
CANRX0
I
2
F
A0/NBS0
O
2
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
SAMA5D2 SIP
ISC_FIELD
Package and Ballout
F
A
PIO, I, PU, ST
© 2021 Microchip Technology Inc.
...........continued
Primary
361-ball
BGA
289-ball
BGA
196-ball
BGA
Power Rail
D2
A1
–
VDDISC
rotatethispage90
K2
K6
B1
G5
–
–
VDDISC
VDDISC
I/O
Type
Signal
Dir
Signal
Dir
Func
Signal
Dir
IO
Set
Reset State
(Signal, Dir,
PU, PD,
HiZ, ST)(1)
GPIO
PC12
I/O
–
–
A
LCDDAT4
O
2
PIO, I, PU, ST
B
GRXDV
I
1
C
ISC_D3
I
1
D
URXD3
I
1
E
TK0
I/O
2
F
A1
O
2
A
LCDDAT5
O
2
1
GPIO
GPIO
PC13
PC14
Alternate
I/O
I/O
–
–
PIO Peripheral
–
–
Datasheet
B1
K9
G2
G6
–
–
VDDISC
VDDISC
GPIO
GPIO
PC15
PC16
I/O
I/O
–
–
–
–
B
GRXER
I
C
ISC_D4
I
1
D
UTXD3
O
1
E
TF0
I/O
2
F
A2
O
2
A
LCDDAT6
O
2
B
GRX0
I
1
C
ISC_D5
I
1
E
TD0
O
2
O
2
O
2
B
GRX1
I
1
C
ISC_D6
I
1
E
RD0
I
2
F
A4
O
2
A
LCDDAT10
O
2
B
GTX0
O
1
C
ISC_D7
I
1
E
RK0
I/O
2
F
A5
O
2
PIO, I, PU, ST
PIO, I, PU, ST
SAMA5D2 SIP
A3
LCDDAT7
PIO, I, PU, ST
Package and Ballout
DS60001484D-page 25
F
A
PIO, I, PU, ST
© 2021 Microchip Technology Inc.
...........continued
Primary
361-ball
BGA
289-ball
BGA
196-ball
BGA
Power Rail
C1
C1
–
VDDISC
rotatethispage90
L9
D1
Datasheet
L8
E3
D1
H4
E1
–
–
–
–
VDDISC
VDDISC
VDDISC
VDDISC
VDDISC
Signal
Dir
Signal
Dir
Func
Signal
Dir
IO
Set
Reset State
(Signal, Dir,
PU, PD,
HiZ, ST)(1)
GPIO
PC17
I/O
–
–
A
LCDDAT11
O
2
PIO, I, PU, ST
B
GTX1
O
1
C
ISC_D8
I
1
E
RF0
I/O
2
F
A6
O
2
A
LCDDAT12
O
2
B
GMDC
O
1
GPIO
GPIO
GPIO
GPIO
GPIO
PC18
PC19
PC20
PC21
PC22
I/O
I/O
I/O
I/O
I/O
–
–
–
–
–
PIO Peripheral
–
–
–
–
–
C
ISC_D9
I
1
E
FLEXCOM3_IO2
I/O
2
F
A7
O
2
A
LCDDAT13
O
2
B
GMDIO
I/O
1
C
ISC_D10
I
1
E
FLEXCOM3_IO1
I/O
2
F
A8
O
2
A
LCDDAT14
O
2
1
B
GRXCK
I
C
ISC_D11
I
1
E
FLEXCOM3_IO0
I/O
2
F
A9
O
2
A
LCDDAT15
O
2
B
GTXER
O
1
C
ISC_PCK
I
1
E
FLEXCOM3_IO3
O
2
F
A10
O
2
A
LCDDAT18
O
2
B
GCRS
I
1
C
ISC_VSYNC
I
1
E
FLEXCOM3_IO4
O
2
F
A11
O
2
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
SAMA5D2 SIP
F1
–
Alternate
Package and Ballout
DS60001484D-page 26
E2
G9
I/O
Type
© 2021 Microchip Technology Inc.
...........continued
Primary
361-ball
BGA
289-ball
BGA
196-ball
BGA
Power Rail
L7
H9
–
VDDISC
rotatethispage90
E1
L4
D6
Datasheet
E7
J5
H8
F7
B10
F6
–
–
–
–
–
VDDISC
VDDISC
VDDIOP2
VDDIOP2
VDDIOP2
VDDIOP2
Signal
Dir
Signal
Dir
Func
Signal
Dir
IO
Set
Reset State
(Signal, Dir,
PU, PD,
HiZ, ST)(1)
GPIO
PC23
I/O
–
–
A
LCDDAT19
O
2
PIO, I, PU, ST
B
GCOL
I
1
C
ISC_HSYNC
I
1
F
A12
O
2
A
LCDDAT20
O
2
B
GRX2
I
1
C
ISC_MCK
O
1
GPIO_CLK
GPIO
GPIO
GPIO
GPIO
GPIO
PC24
PC25
PC26
PC27
PC28
PC29
I/O
I/O
I/O
I/O
I/O
I/O
–
–
–
–
–
–
PIO Peripheral
–
–
–
–
–
–
F
A13
O
2
A
LCDDAT21
O
2
B
GRX3
I
1
C
ISC_FIELD
I
1
F
A14
O
2
A
LCDDAT22
O
2
B
GTX2
O
1
D
CANTX1
O
1
F
A15
O
2
A
LCDDAT23
O
2
B
GTX3
O
1
C
PCK1
O
2
D
CANRX1
I
1
E
TWD0
I/O
2
F
A16
O
2
A
LCDPWM
O
2
B
FLEXCOM4_IO0
I/O
1
C
PCK2
O
1
E
TWCK0
I/O
2
F
A17
O
2
A
LCDDISP
O
2
B
FLEXCOM4_IO1
I/O
1
F
A18
O
2
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
SAMA5D2 SIP
B9
–
Alternate
Package and Ballout
DS60001484D-page 27
C6
G1
I/O
Type
© 2021 Microchip Technology Inc.
...........continued
Primary
361-ball
BGA
289-ball
BGA
196-ball
BGA
Power Rail
D7
E6
–
VDDIOP2
rotatethispage90
C8
J7
D8
Datasheet
J6
M3
E7
C9
D8
J1
–
–
–
–
–
VDDIOP2
VDDIOP2
VDDIOP2
VDDIOP2
VDDANA
VDDANA
Signal
Dir
Signal
Dir
GPIO
PC30
I/O
–
–
GPIO
GPIO_CLK
GPIO
GPIO_CLK
GPIO_AD
GPIO_AD
PC31
PD0
PD1
PD2
PD3
PD4
I/O
I/O
I/O
I/O
I/O
I/O
–
–
–
–
PTC_X0
PTC_X1
–
–
–
–
–
–
Func
Signal
Dir
IO
Set
Reset State
(Signal, Dir,
PU, PD,
HiZ, ST)(1)
PIO, I, PU, ST
A
LCDVSYNC
O
2
B
FLEXCOM4_IO2
I/O
1
F
A19
O
2
A
LCDHSYNC
O
2
B
FLEXCOM4_IO3
O
1
C
URXD3
I
2
F
A20
O
2
A
LCDPCK
O
2
B
FLEXCOM4_IO4
O
1
C
UTXD3
O
2
D
GTSUCOMP
O
2
F
A23
O
2
A
LCDDEN
O
2
D
GRXCK
I
2
F
A24
O
2
A
URXD1
I
1
D
GTXER
O
2
E
ISC_MCK
O
2
F
A25
O
2
A
UTXD1
O
1
DS60001484D-page 28
B
FIQ
I
2
D
GCRS
I
2
E
ISC_D11
I
2
F
NWAIT
I
2
A
TWD1
I/O
2
1
B
URXD2
I
D
GCOL
I
2
E
ISC_D10
I
2
F
NCS0
O
2
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
SAMA5D2 SIP
H7
–
PIO Peripheral
Package and Ballout
L6
A11
Alternate
I/O
Type
© 2021 Microchip Technology Inc.
...........continued
Primary
361-ball
BGA
289-ball
BGA
196-ball
BGA
Power Rail
L2
H1
–
VDDANA
rotatethispage90
J1
L5
Datasheet
K1
L3
H6
K3
J4
H5
J2
G4
C2
VDDANA
VDDANA
VDDANA
VDDANA
VDDANA
Signal
Dir
Signal
Dir
Func
Signal
Dir
IO
Set
Reset State
(Signal, Dir,
PU, PD,
HiZ, ST)(1)
GPIO_AD
PD5
I/O
PTC_X2
–
A
TWCK1
I/O
2
PIO, I, PU, ST
B
UTXD2
O
1
D
GRX2
I
2
E
ISC_D9
I
2
F
NCS1
O
2
A
TCK
I
2
B
PCK1
O
1
D
GRX3
I
2
E
ISC_D8
I
2
F
NCS2
O
2
A
TDI
I
2
C
UTMI_RXVAL
O
1
D
GTX2
O
2
E
ISC_D0
I
2
F
NWR1/NBS1
O
2
A
TDO
O
2
C
UTMI_RXERR
O
1
D
GTX3
O
2
E
ISC_D1
I
2
F
NANDRDY
I
2
GPIO_AD
GPIO_AD
GPIO_AD
GPIO_AD
GPIO_AD
PD6
PD7
PD8
PD9
PD10
I/O
I/O
I/O
I/O
I/O
PTC_X3
PTC_X4
PTC_X5
PTC_X6
PTC_X7
PIO Peripheral
–
–
–
–
–
DS60001484D-page 29
A
TMS
I
2
C
UTMI_RXACT
O
1
D
GTXCK
I/O
2
E
ISC_D2
I
2
A
NTRST
I
2
C
UTMI_HDIS
O
1
D
GTXEN
O
2
E
ISC_D3
I
2
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
SAMA5D2 SIP
J3
–
Alternate
Package and Ballout
L1
J2
I/O
Type
© 2021 Microchip Technology Inc.
...........continued
Primary
361-ball
BGA
289-ball
BGA
196-ball
BGA
Power Rail
N3
K2
F2
VDDANA
rotatethispage90
M7
N2
K9
N1
K4
C1
VDDANA
VDDANA
I/O
Type
Signal
Dir
Signal
Dir
Func
Signal
Dir
IO
Set
Reset State
(Signal, Dir,
PU, PD,
HiZ, ST)(1)
GPIO_AD
PD11
I/O
PTC_Y0
–
A
TIOA1
I/O
3
PIO, I, PU, ST
B
PCK2
O
2
C
UTMI_LS0
O
1
D
GRXDV
I
2
E
ISC_D4
I
2
F
ISC_MCK
O
4
A
TIOB1
I/O
3
GPIO_AD
GPIO_AD
PD12
PD13
Alternate
I/O
I/O
PTC_Y1
PTC_Y2
PIO Peripheral
–
–
Datasheet
M6
G2
VDDANA
VDDANA
GPIO_AD
GPIO_AD
PD14
PD15
I/O
I/O
PTC_Y3
PTC_Y4
–
–
I/O
2
UTMI_LS1
O
1
D
GRXER
I
2
E
ISC_D5
I
2
F
ISC_D4
I
4
A
TCLK1
I
3
B
FLEXCOM4_IO1
I/O
2
C
UTMI_CDRCPSEL0
I
1
D
GRX0
I
2
E
ISC_D6
I
2
F
ISC_D5
I
4
A
TCK
I
1
B
FLEXCOM4_IO2
I/O
2
C
UTMI_CDRCPSEL1
I
1
D
GRX1
I
2
E
ISC_D7
I
2
F
ISC_D6
I
4
A
TDI
I
1
DS60001484D-page 30
B
FLEXCOM4_IO3
O
2
C
UTMI_CDRCPDIVEN
I
1
D
GTX0
O
2
E
ISC_PCK
I
2
F
ISC_D7
I
4
PIO, I, PU, ST
A, PU, ST
PIO, I, PU, ST
SAMA5D2 SIP
K8
H2
FLEXCOM4_IO0
Package and Ballout
M5
K5
B
C
PIO, I, PU, ST
© 2021 Microchip Technology Inc.
...........continued
Primary
361-ball
BGA
289-ball
BGA
196-ball
BGA
Power Rail
M1
L1
J1
VDDANA
rotatethispage90
M2
M4
Datasheet
M8
N1
J7
L8
L2
G3
K2
H1
G1
VDDANA
VDDANA
VDDANA
VDDANA
VDDANA
Signal
Dir
IO
Set
Reset State
(Signal, Dir,
PU, PD,
HiZ, ST)(1)
A
TDO
O
1
PIO, I, PU, ST
B
FLEXCOM4_IO4
O
2
C
UTMI_CDRBISTEN
I
1
D
GTX1
O
2
E
ISC_VSYNC
I
2
Signal
Dir
Signal
Dir
Func
GPIO_AD
PD16
I/O
PTC_Y5
–
GPIO_AD
GPIO_AD
GPIO_AD
GPIO_AD
GPIO_AD
PD17
PD18
PD19
PD20
PD21
I/O
I/O
I/O
I/O
I/O
PTC_Y6
PTC_Y7
AD0
AD1
AD2
–
–
–
–
–
F
ISC_D8
I
4
A
TMS
I
1
C
UTMI_CDRCPSELDIV
O
1
D
GMDC
O
2
E
ISC_HSYNC
I
2
F
ISC_D9
I
4
A
NTRST
I
1
D
GMDIO
I/O
2
E
ISC_FIELD
I
2
F
ISC_D10
I
4
A
PCK0
O
1
B
TWD1
I/O
3
C
URXD2
I
3
E
I2SC0_CK
I/O
2
F
ISC_D11
I
4
A
TIOA2
I/O
3
B
TWCK1
I/O
3
C
UTXD2
O
3
E
I2SC0_MCK
O
2
F
ISC_PCK
I
4
A
TIOB2
I/O
3
B
TWD0
I/O
4
C
FLEXCOM4_IO0
I/O
3
E
I2SC0_WS
I/O
2
F
ISC_VSYNC
I
4
A, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
SAMA5D2 SIP
P1
A1
PIO Peripheral
Package and Ballout
DS60001484D-page 31
P3
K1
Alternate
I/O
Type
© 2021 Microchip Technology Inc.
...........continued
Primary
361-ball
BGA
289-ball
BGA
196-ball
BGA
Power Rail
N6
L6
F1
VDDANA
rotatethispage90
P1
N8
P8
Datasheet
P2
N5
N4
R2
L4
L5
R1
L7
L3
M2
–
–
–
–
–
–
–
VDDANA
VDDANA
VDDANA
VDDANA
VDDANA
VDDANA
VDDANA
VDDANA
Dir
IO
Set
Reset State
(Signal, Dir,
PU, PD,
HiZ, ST)(1)
TCLK2
I
3
PIO, I, PU, ST
TWCK0
I/O
4
FLEXCOM4_IO1
I/O
3
I2SC0_DI0
I
2
F
ISC_HSYNC
I
4
A
URXD2
I
2
C
FLEXCOM4_IO2
I/O
3
E
I2SC0_DO0
O
2
F
ISC_FIELD
I
4
A
UTXD2
O
2
C
FLEXCOM4_IO3
O
3
A
SPI1_SPCK
I/O
3
C
FLEXCOM4_IO4
O
3
Signal
Dir
Signal
Dir
Func
GPIO_AD
PD22
I/O
AD3
–
A
B
C
E
GPIO_AD
GPIO_AD
GPIO_AD
GPIO_AD
GPIO_AD
GPIO_AD
GPIO_AD
GPIO_AD
PD23
PD24
PD25
PD26
PD27
PD28
PD29
PD30
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
AD4
AD5
AD6
AD7
AD8
AD9
AD10
AD11
–
–
–
–
–
–
–
–
Signal
A
SPI1_MOSI
I/O
3
C
FLEXCOM2_IO0
I/O
2
A
SPI1_MISO
I/O
3
B
TCK
I
3
C
FLEXCOM2_IO1
I/O
2
A
SPI1_NPCS0
I/O
3
B
TDI
I
3
C
FLEXCOM2_IO2
I/O
2
A
SPI1_NPCS1
O
3
B
TDO
O
3
C
FLEXCOM2_IO3
O
2
D
TIOA3
I/O
3
E
TWD0
I/O
3
A
SPI1_NPCS2
O
3
B
TMS
I
3
C
FLEXCOM2_IO4
O
2
D
TIOB3
I/O
3
E
TWCK0
I/O
3
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
PIO, I, PU, ST
SAMA5D2 SIP
M9
E1
PIO Peripheral
Package and Ballout
DS60001484D-page 32
N10
T1
Alternate
I/O
Type
© 2021 Microchip Technology Inc.
...........continued
Primary
361-ball
BGA
289-ball
BGA
196-ball
BGA
Power Rail
P7
M8
–
VDDANA
rotatethispage90
I/O
Type
Alternate
PIO Peripheral
Signal
Dir
Signal
Dir
Func
Signal
Dir
IO
Set
Reset State
(Signal, Dir,
PU, PD,
HiZ, ST)(1)
GPIO
PD31
I/O
–
–
A
ADTRG
I
1
PIO, I, PU, ST
B
NTRST
I
3
C
IRQ
I
4
D
TCLK3
I
3
2
E
PCK0
O
M9
L9
L1
VDDANA
–
ADVREF
I
–
–
–
–
–
–
–
G1, H6
K4, J5
K3, L2
VDDANA
power
VDDANA
I
–
–
–
–
–
–
–
F1, G5
J6, M1
L3, K1
GNDANA
ground
GNDANA
I
–
–
–
–
–
–
–
M12, J10
J10, F11
K12,
F12
VDDIODDR
DDR
DDR_VREF
I
–
–
–
–
–
–
–
C19
-
-
Datasheet
VDDIODDR
DDR
ZQ
-
-
-
-
-
-
-
-
E11, E8, L10, L14, J8, F10, E8, E9,
H10, J13,
H10, G12,
E10, G12,
J8, L10,
E11, E8
H12, J12
P12
VDDIODDR
power
VDDIODDR
I
–
–
–
–
–
–
–
E10, F8,
K10, M14, K11, J11, F9,
G10, J9,
J9, G10,
C10, E11,
L11, M13, H12, E10, F8
F8, F11,
N12
G13, H13
GNDIODDR
ground
GNDIODDR
I
–
–
–
–
–
–
–
C3, C9, K3, H2, U3, P7, G7, H4, D14,
U9, V5,
L12, E9, D7
E14, L5
W6, K8
VDDCORE
power
VDDCORE
I
–
–
–
–
–
–
–
A1, D9,
E12, F12,
G11, E12,
J11, K4, J11, K11, K6, E13, H3, H7,
K7, V9, W1
K7
H8, J3
GNDCORE
ground
GNDCORE
I
–
–
–
–
–
–
–
F4, E4
VDDIOP0
power
VDDIOP0
I
–
–
–
–
–
–
–
E3, F2
E5, F5
GNDIOP0
ground
GNDIOP0
I
–
–
–
–
–
–
–
V13, V18
N12, P12
N9, N10
VDDIOP1
power
VDDIOP1
I
–
–
–
–
–
–
–
P13, R13,
W13, W19
M12, P11
M9, M10
GNDIOP1
ground
GNDIOP1
I
–
–
–
–
–
–
–
A8
D9
–
VDDIOP2
power
VDDIOP2
I
–
–
–
–
–
–
–
B9
D6
–
GNDIOP2
ground
GNDIOP2
I
–
–
–
–
–
–
–
T7
N8
J7
VDDSDMMC
power
VDDSDMMC
I
–
–
–
–
–
–
–
T8
R8
J8
GNDSDMMC
ground
GNDSDMMC
I
–
–
–
–
–
–
–
SAMA5D2 SIP
D4, F3
A5, D4
Package and Ballout
DS60001484D-page 33
B4, D5
© 2021 Microchip Technology Inc.
...........continued
Primary
Signal
Dir
Signal
Dir
Func
Signal
Dir
IO
Set
Reset State
(Signal, Dir,
PU, PD,
HiZ, ST)(1)
power
VDDISC
I
–
–
–
–
–
–
–
ground
GNDISC
I
–
–
–
–
–
–
–
power
VDDFUSE
I
–
–
–
–
–
–
–
power
VDDPLLA
I
–
–
–
–
–
–
–
GNDPLLA
ground
GNDPLLA
I
–
–
–
–
–
–
–
K6
VDDAUDIOPLL
power
VDDAUDIOPLL
I
–
–
–
–
–
–
–
T3
J6
GNDDPLL
ground
GNDDPLL
I
–
–
–
–
–
–
–
–
361-ball
BGA
289-ball
BGA
196-ball
BGA
G3
H3
–
VDDISC
H3
H5
–
GNDISC
U15
N13
M13
VDDFUSE
P9
R5
P4
VDDPLLA
P10
T5
L6
R6
M4
N9
rotatethispage90
Power Rail
I/O
Type
Alternate
PIO Peripheral
Datasheet
P6
T4
H6
GNDAUDIOPLL
ground
GNDAUDIOPLL
I
–
–
–
–
–
–
W2
T8
P1
VDDAUDIOPLL
–
CLK_AUDIO
O
–
–
–
–
–
–
–
W5
U9
N5
VDDOSC
–
XIN
I
–
–
–
–
–
–
–
W4
U8
P5
VDDOSC
–
XOUT
O
–
–
–
–
–
–
–
R10
N6
M7
VDDOSC
–
VDDOSC
I
–
–
–
–
–
–
–
T11
P5
N6
GNDOSC
ground
GNDOSC
I
–
–
–
–
–
–
–
R8
P6
M6
VDDUTMII
power
VDDUTMII
I
–
–
–
–
–
–
–
U7
R7
–
VDDHSIC
power
VDDHSIC
I
–
–
–
–
–
–
–
R7
M6
L7
GNDUTMII
ground
GNDUTMII
I
–
–
–
–
–
–
–
W7
U10
N7
VDDUTMII
–
HHSDPA
I/O
–
–
–
–
–
–
–
V7
T10
P7
VDDUTMII
–
HHSDMA
I/O
–
–
–
–
–
–
–
W8
U11
N8
VDDUTMII
–
HHSDPB
I/O
–
–
–
–
–
–
–
V8
T11
P8
VDDUTMII
–
HHSDMB
I/O
–
–
–
–
–
–
–
–
VDDHSIC
–
HHSDPDATC
I/O
–
–
–
–
–
–
–
–
VDDHSIC
–
HHSDMSTRC
I/O
–
–
–
–
–
–
–
T6
M7
K7
VDDUTMIC
power
VDDUTMIC
I
–
–
–
–
–
–
–
U6
R6
G5
GNDUTMIC
ground
GNDUTMIC
I
–
–
–
–
–
–
–
V6
T6
P6
VDDUTMIC
–
VBG
I
–
–
–
–
–
–
–
DS60001484D-page 34
T2
R4
D1
VDDBU
–
TST
I
–
–
–
–
–
–
–
W3
T7
J5
VDDBU
–
NRST
I
–
–
–
–
–
–
–
T3
R3
N3
VDDBU
–
JTAGSEL
I
–
–
–
–
–
–
–
U2
R2
N1
VDDBU
–
WKUP
I
–
–
–
–
–
–
–
R1
N2
–
VDDBU
–
RXD
I
–
–
–
–
–
–
–
P4
T2
B1
VDDBU
–
SHDN
O
–
–
–
–
–
–
–
SAMA5D2 SIP
T12
U12
Package and Ballout
W9
W10
© 2021 Microchip Technology Inc.
...........continued
I/O
Type
Primary
Signal
Dir
Signal
Dir
Func
Signal
Dir
IO
Set
Reset State
(Signal, Dir,
PU, PD,
HiZ, ST)(1)
VDDBU
–
PIOBU0
I/O
–
–
–
–
–
–
–
VDDBU
–
PIOBU1
I/O
–
–
–
–
–
–
–
M3
VDDBU
–
PIOBU2
I/O
–
–
–
–
–
–
–
M4
VDDBU
–
PIOBU3
I/O
–
–
–
–
–
–
–
N4
J4
VDDBU
–
PIOBU4
I/O
–
–
–
–
–
–
–
T5
M5
M5
VDDBU
–
PIOBU5
I/O
–
–
–
–
–
–
–
U5
N5
–
VDDBU
–
PIOBU6
I/O
–
–
–
–
–
–
–
P5
N3
–
VDDBU
–
PIOBU7
I/O
–
–
–
–
–
–
–
V3
U5
K5
VDDBU
power
VDDBU
I
–
–
–
–
–
–
–
U4
U4
N2
GNDBU
ground
GNDBU
I
–
–
–
–
–
–
–
U1
U2
M1
VDDBU
–
XIN32
I
–
–
–
–
–
–
–
361-ball
BGA
289-ball
BGA
196-ball
BGA
Power Rail
R4
P3
N4
R5
M3
L4
R3
P2
T4
P4
U3
rotatethispage90
Alternate
PIO Peripheral
Datasheet
T1
U1
M2
VDDBU
–
XOUT32
O
–
–
–
–
–
–
–
V1
U6
P2
VDDBU
–
COMPP
I
–
–
–
–
–
–
–
V2
U7
P3
VDDBU
–
COMPN
I
–
–
–
–
–
–
–
-
D17
D12
DDRM_VDDQ(2)
–
ODT
I
–
–
–
–
–
–
–
-
A16, B16,
C16, D16,
E15, G17,
J17, L16
B10, A12,
D10, D11
DDRM_VDD
power
DDRM_VDD
I
–
–
–
–
–
–
–
-
E16
power
I
–
–
–
–
–
–
–
-
F15, G15,
H15, J15,
K15, L15
DDRM_VDDL(2)
DDRM_VDDQ(2)
–
–
–
–
–
–
–
–
DDRM_VDDL(2)
A7, A13, A9, DDRM_VDDQ(2)
A11, B6, C12
E7
power
SAMA5D2 SIP
Package and Ballout
DS60001484D-page 35
© 2021 Microchip Technology Inc.
...........continued
Primary
361-ball
BGA
289-ball
BGA
196-ball
BGA
A14, A19,
B14, B18,
C14, C18,
D14, D18,
E14, E18,
F14, F18,
G14, G18,
H14, H18,
N14, N17,
N18, P14,
P18, R14,
R18, T18
A17, B17,
C17, D15,
E14, F17,
H17, L17
B14, A8,
C11, C14, D8
rotatethispage90
I/O
Type
Signal
Dir
Signal
Dir
Func
Signal
Dir
IO
Set
Reset State
(Signal, Dir,
PU, PD,
HiZ, ST)(1)
DDRM_VSS
ground
DDRM_VSS
–
–
–
–
–
–
–
–
Power Rail
Alternate
PIO Peripheral
Datasheet
D13
DDRM_VSSDL
ground
DDRM_VSSDL
I
–
–
–
–
–
–
–
A10, A14,
B11, B12,
B13, C13
DDRM_VSSQ
ground
DDRM_VSSQ
I
–
–
–
–
–
–
–
B15, B17,
B19, D15,
D17, D19,
F15, F17,
F19, H15,
H17, H19,
K15, K17,
K19, M15,
M17, M19,
P15, P17,
P19, T17,
T19
-
-
DDRM_VDD12(3)
power
DDRM_VDD12(3)
I
-
-
-
-
-
-
-
B11, B13,
D11, D13,
K13, K16
-
-
DDRM_VDD18(3)
power
DDRM_VDD18(3)
I
-
-
-
-
-
-
-
SAMA5D2 SIP
E17
F16, G16,
H16, J16,
K16, K17
Package and Ballout
DS60001484D-page 36
-
© 2021 Microchip Technology Inc.
...........continued
Primary
Datasheet
196-ball
BGA
Power Rail
A13, A15,
A16, A17,
A18, B10,
B12, B16,
C10, C11,
C12, C13,
C15, C16,
C17, D10,
D12, D16,
E12, E13,
E15, E16,
E17, E19,
E5, E6, E9,
F10, F11,
F12, F13,
F16, F5,
F6, F7, F9,
G11, G12,
G13, G15,
G16, G17,
G19, G7,
G8, G9,
H11, H12,
H13, H16,
H7, H8, H9,
J12, J14,
J15, J16,
J17, J18,
J19, K10,
K11, K12,
K14, L12,
L13, L14,
L15, L16,
M10, M11,
M14, N11,
N13, N16,
N7, R11,
R12, R17,
T12, T9,
U10, U11,
U8, V4
A12, A13,
A14, A15,
B11, B12,
B13, B14,
B15, C10,
C11, C12,
C13, C14,
C15, D10,
D11, D12,
D13, D14,
E13, F9,
F10, F13,
F14, G11,
G13, G14,
H11, H13,
H14, J12,
J13, J14,
K12, K13,
K14, L13,
R12, T9
–
–
rotatethispage90
I/O
Type
Alternate
PIO Peripheral
Signal
Dir
Signal
Dir
Func
Signal
Dir
IO
Set
Reset State
(Signal, Dir,
PU, PD,
HiZ, ST)(1)
NC(4)
–
–
–
–
–
–
–
–
–
SAMA5D2 SIP
289-ball
BGA
Package and Ballout
DS60001484D-page 37
361-ball
BGA
SAMA5D2 SIP
Package and Ballout
Notes:
1. Signal = ‘PIO’ if GPIO; Dir = Direction; PU = Pull-up; PD = Pull-down; HiZ = High impedance; ST = Schmitt
Trigger
2. Refer to the DDR2-SDRAM data sheet for DDRM_VDDQ and DDRM_VDDL definitions. DDRM_VDDQ/
DDRM_VDDL = 1.8V ±0.1V.
3. DDRM_VDD18 stands for VDD1, DDRM_VDD12 stands for VDD2, refer to the LPDDR2-SDRAM data sheet
for VDD1 and VDD2 definitions.
4. These balls are not internally connected, they can be left unconnected, connected to any GND, VDD or to any
slowly varying signal to avoid any EMI related issues.
© 2021 Microchip Technology Inc.
Datasheet
DS60001484D-page 38
SAMA5D2 SIP
Memory
7.
Memory
The SAMA5D2 SIP is available with 128 Mbits, 512 Mbits or 1 Gbit of DDR2-SDRAM memory, and with 1 Gbit
or 2 Gbits of LPDDR2-SDRAM memory. For the features of these memories, see DDR2-SDRAM Features and
LPDDR2-SDRAM Features.
For power consumption, electrical characteristics and timings of these memories, refer to the data sheets referenced
below on the manufacturer’s website.
Table 7-1. Memory Data Sheet References
Memory Type
DDR2-SDRAM
LPDDR2-SDRAM
Density
Manufacturer Packaged PN
Data Sheet Reference Number
128 Mbit
Winbond W9712G6KB25I
W9712G6KB
512 Mbit
Winbond W9751G6KB25I
W9751G6KB
1 Gbit
Winbond W971GG6SB25I
W971GG6SB
1 Gbit
apmemory AD210032F-I-AB
lpddr2_datasheet_1gb
2 Gbit
apmemory AD220032D-I-ED/PC/AB
lpddr2_datasheet_2gb
© 2021 Microchip Technology Inc.
Datasheet
DS60001484D-page 39
SAMA5D2 SIP
Electrical Characteristics
8.
Electrical Characteristics
8.1
Recommended Thermal Operating Conditions
Symbol
Parameter
Conditions
Min
Max
Unit
TA
Ambient temperature
–
-40
+85
°C
TJ
Junction temperature
–
-40
+125
°C
BGA196
–
30
BGA289
–
28
BGA361
–
27
TA=70°C
–
1.3
TA=85°C
–
1.0
RthJA
Junction-to-ambient thermal resistance
BGA196
PD
Allowable power dissipation
BGA289
BGA361
8.2
°C/W
W
Decoupling
100 nF (min) decoupling capacitors must be added on each power supply pin, as close as possible to the device.
8.3
Power Sequences
8.3.1
SAMA5D2 DDR2 SIP
DDRM_VDD, DDRM_VDDL and DDRM_VDDQ power rails must be connected to VDDIODDR (1.8V) on the PCB.
Refer to the sections “Power-up Considerations” and “Power-down Considerations” in the SAMA5D2 Series data
sheet, ref. no. DS60001476, available on www.microchip.com.
8.3.2
SAMA5D2 LPDDR2 SIP
The DDRM_VDD12 power rail must be connected to VDDIODDR (1.2V). The DDRM_VDD18 power rail must be
connected to a 1.8V power supply. For Backup with Self-refresh mode, these power supplies must be maintained.
Important: The sections below supersede “Recommended Power-up Sequence”, “Recommended
Power-up Sequence”, “Power Supply Sequencing at Backup Mode Entry and Exit” in the SAMA5D2 Series
data sheet.
8.3.2.1
Power-up Considerations
At power-up, from a supply sequencing perspective, the SAMA5D2 LPDDR2 SIP power supply inputs are
categorized into two groups:
•
•
Group 1 (core group) contains VDDCORE, VDDUTMIC, VDDHSIC and VDDPLLA.
Group 2 (periphery group) contains all other power supply inputs except VDDFUSE.
The figure below shows the recommended power-up sequence. Note that:
• VDDBU, when supplied from a battery, is an always-on supply input and is therefore not part of the power
supply sequencing. When no backup battery is present in the application, VDDBU is part of Group 2.
• VDDFUSE is the only power supply that may be left unpowered during operation. This is possible if and
only if the application does not access the Customer Fuse Matrix in Write mode. It is good practice to turn
© 2021 Microchip Technology Inc.
Datasheet
DS60001484D-page 40
SAMA5D2 SIP
Electrical Characteristics
on VDDFUSE only when the Customer Fuse Matrix is accessed in Write mode, and to turn off VDDFUSE
otherwise.
Figure 8-1. Recommended Power-up Sequence
Group 2
No specific order and no
specific timing required
among these channels except
DDRM_VDD12 and DDRM_VDD18
VDDBU
VDDANA
VDDOSC
VDDUTMII
VDDAUDIOPLL
VDDIOP0
VDDIOP1
VDDIOP2
VDDISC
VDDSDMMC
t5
DDRM_VDD18
DDRM_VDD12, VDDIODDR
t4
t3
VDDFUSE
Group 1
t1
VDDCORE
VDDPLLA
VDDHSIC
VDDUTMIC
t2
NRST
tRSTPU
time
Table 8-1. Power-up Timing Specification
Symbol
Parameter
Conditions
Min
Max
t1
Group 2 to Group 1 delay
Delay from the last Group 2 established(1) supply to the
first Group 1 supply turn-on
0
–
t2
Group 1 delay
Delay from the first Group 1 established supply to the
last Group 1 established supply
–
1
t3
VDDFUSE to VDDBU delay
Delay from VDDBU established to VDDFUSE turn-on
1
–
t4
DDRM_VDD18 to
DDRM_VDD12 delay
Delay from the DDRM_VDD18 established to
DDRM_VDD12 turn-on
0
–
t5
LPDDR2 power-on delay
Delay from DDRM_VDD18 turn-on to DDRM_VDD12
established
–
20
tRSTPU
Reset delay at power-up
From the last established supply to NRST high
1
–
Note:
1. An “established” supply refers to a power supply established at 90% of its final value.
© 2021 Microchip Technology Inc.
Datasheet
DS60001484D-page 41
Unit
ms
SAMA5D2 SIP
Electrical Characteristics
8.3.2.2
Power-down Considerations
The figure below shows the SAMA5D2 LPDDR2 SIP power-down sequence that starts by asserting the NRST line
to 0. Once NRST is asserted, the supply inputs can be immediately shut down without any specific timing or order
except for DDRM_VDD12 and DDRM_VDD18. VDDBU may not be shut down if the application uses a backup
battery on this supply input. In applications where VDDFUSE is powered, it is mandatory to shut down VDDFUSE
prior to removing any other supply. VDDFUSE can be removed before or after asserting the NRST signal.
Figure 8-2. Recommended Power-down Sequence
No specific order and no
specific timing required
among the channels
except DDRM_VDD12
and DDRM_VDD18
tRSTPD
t3
NRST
VDDBU
VDDANA
VDDOSC
VDDUTMII
VDDAUDIOPLL
VDDIOP0
VDDIOP1
VDDIOP2
VDDISC
VDDSDMMC
DDRM_VDD12, VDDIODDR
DDRM_VDD18
VDDFUSE
t1
t2
VDDCORE
VDDPLLA
VDDHSIC
VDDUTMIC
time
Table 8-2. Power-down Timing Specification
Symbol
Parameter
Conditions
Min
Max
Reset delay at power-down
From NRST low to the first supply turn-off
0
–
t1
VDDFUSE delay at shut-down
From VDDFUSE < 1V to the first supply turn-off
0
–
t2
DDRM_VDD12 to
DDRM_VDD18 delay
From DDRM_VDD12 zeroed to DDRM_VDD18
turn-off
0
–
t3
LPDDR2 power-off delay
From NRST low to DDRM_VDD18 zeroed
–
2000
tRSTPD
8.3.2.3
Backup Mode Entry (Shutdown)
The figure below shows the recommended power-down sequence to place the SAMA5D2 LPDDR2 SIP either in
Backup mode or in Backup mode with the LPDDR2 in self-refresh. The SHDN signal, an output of the Shutdown
Controller (SHDWC), signals the shutdown request to the power supply. This output is supplied by VDDBU that is
present in Backup mode. Placing the LPDDR2 memory in self-refresh while in Backup mode requires maintaining
VDDIODDR, DDRM_VDD18 and DDRM_VDD12 as well. One possible way to signal this additional need to the
power supply is to position one of the general-purpose I/Os supplied by VDDBU (PIOBUx) in a predefined state.
© 2021 Microchip Technology Inc.
Datasheet
DS60001484D-page 42
Unit
ms
SAMA5D2 SIP
Electrical Characteristics
Figure 8-3. Recommended Backup Mode Entry (Shutdown)
Shutdown Request
in SHDWC
tRSTPD
SHDN
PIOBUx
t2
NRST
VDDBU
VDDANA
PIOBUx signals to
maintain or shutdown
VDDIODDR
No specific order and no
specific timing required
among the channels
except DDRM_VDD12
and DDRM_VDD18
VDDOSC
VDDUTMII
VDDAUDIOPLL
VDDIOP0
VDDIOP1
VDDIOP2
VDDISC
VDDSDMMC
VDDFUSE
DDRM_VDD12, VDDIODDR
DDRM_VDD18
t1
VDDCORE
VDDPLLA
VDDHSIC
VDDUTMIC
time
Table 8-3. Shutdown Timing Specification
Symbol
Parameter
Conditions
Reset delay at power-down
t1
t2
tRSTPD
8.3.2.4
Min
Max
From NRST low to the first supply turn-off
0
–
DDRM_VDD12 to
DDRM_VDD18 delay
From DDRM_VDD12 zeroed to DDRM_VDD18
turn-off
0
–
LPDDR2 power-off delay
From NRST low to DDRM_VDD18 zeroed
–
2000
Backup Mode Exit (Wake-up)
The figure below shows the recommended power-up sequence to wake up the SAMA5D2 LPDDR2 SIP from Backup
mode. Upon a wake-up event, the Shutdown Controller toggles its SHDN output back to VDDBU to request the
power supply to restart. Except for VDDIODDR, DDRM_VDD18 and DDRM_VDD12 which may already be present if
the LPDDR2 memory was placed in Self-refresh mode, this power-up sequence is the same one as presented in the
figure “Recommended Power-up Sequence”. In particular, the definitions of Group 1 and Group 2 are the same.
© 2021 Microchip Technology Inc.
Datasheet
DS60001484D-page 43
Unit
ms
SAMA5D2 SIP
Electrical Characteristics
Figure 8-4. Recommended Backup Mode Exit (Wake-Up)
SHDN
VDDBU
Group 2
No specific order and no
specific timing required
among these channels
except DDRM_VDD12
and DDRM_VDD18
VDDANA
VDDOSC
VDDUTMII
VDDAUDIOPLL
VDDIOP0
VDDIOP1
VDDIOP2
VDDISC
VDDSDMMC
VDDFUSE
t4
DDRM_VDD18
t3
DDRM_VDD12, VDDIODDR
Group 1
t1
VDDCORE
VDDPLLA
VDDHSIC
VDDUTMIC
t2
NRST
tRSTPU
time
Table 8-4. Wake-up Timing Specification
Symbol
Parameter
Conditions
Min
Max
t1
Group 2 to Group 1 delay
Delay from the last Group 2 established(1) supply to the
first Group 1 supply turn-on
1
–
t2
Group 1 delay
Delay from the first Group 1 established supply to the
last Group 1 established supply
–
1
t3
DDRM_VDD18 to
DDRM_VDD12 delay
Delay from the DDRM_VDD18 established to
DDRM_VDD12 turn-on
0
–
t4
LPDDR2 power-on delay
Delay from DDRM_VDD18 turn-on to DDRM_VDD12
established
–
20
tRSTPU
Reset delay at power-up
From the last established supply to NRST high
1
–
Note:
1. An “established” supply refers to a power supply established at 90% of its final value.
© 2021 Microchip Technology Inc.
Datasheet
DS60001484D-page 44
Unit
ms
SAMA5D2 SIP
Mechanical Characteristics
9.
Mechanical Characteristics
9.1
361-ball TFBGA
361-Ball Thin Fine Pitch Ball Grid Array (DYB) - 16x16 mm Body [TFBGA]
Atmel Legacy Global Package Code CEP
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
361X
D
NOTE 1
A
D
4
0.15 C
0.20 C
B
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
E
4
(DATUM B)
(DATUM A)
2X
0.15 C
2X
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
V
W
E
TOP VIEW
0.15 C
A1
SEATING
C
PLANE
D1
SIDE VIEW
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
W
V
U
T
R
P
N
M
L
K
J
H
G
F
E
D
C
B
A
A
E1
NOTE 1
e
BOTTOM VIEW
361X Øb
0.15
0.08
C A B
C
Microchip Technology Drawing C04-21149-DYB Rev A Sheet 1 of 2
© 2021 Microchip Technology Inc.
Datasheet
DS60001484D-page 45
SAMA5D2 SIP
Mechanical Characteristics
361-Ball Thin Fine Pitch Ball Grid Array (DYB) - 16x16 mm Body [TFBGA]
Atmel Legacy Global Package Code CEP
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units
Dimension Limits
N
Number of Terminals
e
Pitch
Overall Height
A
Standoff
A1
Overall Length
D
Overall Pitch
D1
Overall Width
E
Overall Pitch
E1
b
Terminal Width
MIN
0.27
0.38
MILLIMETERS
NOM
361
0.80 BSC
16.00 BSC
14.40 BSC
16.00 BSC
14.40 BSC
-
MAX
1.20
0.37
0.48
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-21149-DYB Rev A Sheet 2 of 2
© 2021 Microchip Technology Inc.
Datasheet
DS60001484D-page 46
SAMA5D2 SIP
Mechanical Characteristics
361-Ball Thin Fine Pitch Ball Grid Array (DYB) - 16x16 mm Body [TFBGA]
Atmel Legacy Global Package Code CEP
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
C1
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18
19
A
B
C
D
E
F
G
H
J
C2
K
L
M
N
P
R
T
U
V
W
ØX1
SILK SCREEN
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
Contact Pitch
E
Contact Pad Spacing
C1
Contact Pad Spacing
C2
Contact Pad Width (X20)
X1
MIN
MILLIMETERS
NOM
0.80 BSC
14.40
14.40
MAX
0.45
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing C04-23149-DYB Rev A
© 2021 Microchip Technology Inc.
Datasheet
DS60001484D-page 47
SAMA5D2 SIP
Mechanical Characteristics
9.2
289-ball TFBGA
Note: For the most current package drawings, please see the Microchip Packaging Specification located at http://
www.microchip.com/packaging.
Table 9-1. 289-ball TFBGA Package Characteristics
Moisture Sensitivity Level
3
Table 9-2. Device and 289-ball TFBGA Package Weight
Device
Weight (mg)
ATSAMA5D27C-D5M (512 Mb)
390
ATSAMA5D28C-D1G (1 Gbit)
400
© 2021 Microchip Technology Inc.
Datasheet
DS60001484D-page 48
SAMA5D2 SIP
Mechanical Characteristics
Table 9-3. Package Reference
JEDEC Drawing Reference
NA
J-STD-609 Classification
e8
Table 9-4. 289-ball TFBGA Package Information
9.3
Ball Land
0.450 mm ±0.05
Nominal Ball Diameter
0.4 mm
Solder Mask Opening
0.350 mm ±0.05
Solder Mask Definition
SMD
Solder
OSP
196-ball TFBGA
For mechanical characteristics of the 196-ball TFBGA package, refer to the SAMA5D2 Series data sheet, ref. no.
DS60001476, available on www.microchip.com.
Note: The weight of the SAMA5D2 SIP is not the same as the weight of SAMA5D2. The SIP weight is given below:
Table 9-5. Device and 196-ball TFBGA Package Weight
Device
Weight (mg)
ATSAMA5D225C-D1M (128 Mb)
240
© 2021 Microchip Technology Inc.
Datasheet
DS60001484D-page 49
SAMA5D2 SIP
Ordering Information
10.
Ordering Information
Table 10-1. Ordering Information
Ordering Code
MRL
ATSAMA5D225C-D1M-CU
Package
BGA196
ATSAMA5D225C-D1M-CUR
ATSAMA5D27C-D5M-CU
BGA289
ATSAMA5D27C-D1G-CUR
ATSAMA5D28C-D1G-CU
Tray
-40°C to +85°C
Tape & Reel
Tray
BGA361
ATSAMA5D28C-LD1G-CUR
Tape & Reel
Tray
Tape & Reel
ATSAMA5D28C-LD2G-CU
Tray
ATSAMA5D28C-LD2G-CUR
© 2021 Microchip Technology Inc.
Tape & Reel
Tape & Reel
C
ATSAMA5D27C-LD2G-CU
ATSAMA5D28C-LD1G-CU
Tray
Tray
ATSAMA5D27C-LD1G-CUR
ATSAMA5D27C-LD2G-CUR
Tape & Reel
Tape & Reel
ATSAMA5D27C-D1G-CU
ATSAMA5D27C-LD1G-CU
Tray
Tray
ATSAMA5D27C-D5M-CUR
ATSAMA5D28C-D1G-CUR
Carrier Type
Operating
Temperature
Range
Tape & Reel
Datasheet
DS60001484D-page 50
SAMA5D2 SIP
Revision History
11.
Revision History
11.1
DS60001484D - 03/2021
Changes
Updated SAMA5D2 SIP Chip ID Registers.
11.2
DS60001484C - 01/2020
Changes
Reference Documents: updated memory references.
LPDDR2-SDRAM Features: updated burst, write, read latencies.
Electrical Characteristics: added 8.1 Recommended Thermal Operating Conditions.
11.3
DS60001484B - 11/2018
Changes
Added 1 Gbit and 2 Gbit LPDDR2 memory options. Added 361-ball TFBGA package option and mechanical
drawing.
Pinout: added PTC signals.
Added section Electrical Characteristics.
11.4
DS60001484A - 09/2017
Changes
First issue.
© 2021 Microchip Technology Inc.
Datasheet
DS60001484D-page 51
SAMA5D2 SIP
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Microchip provides online support via our website at www.microchip.com/. This website is used to make files and
information easily available to customers. Some of the content available includes:
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•
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Users of Microchip products can receive assistance through several channels:
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Customers should contact their distributor, representative or ESE for support. Local sales offices are also available to
help customers. A listing of sales offices and locations is included in this document.
Technical support is available through the website at: www.microchip.com/support
© 2021 Microchip Technology Inc.
Datasheet
DS60001484D-page 52
SAMA5D2 SIP
Product Identification System
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
ATSAMA5 D225 C - D1M - C U R
Architecture
Product Group
Mask Revision
Memory Type and Size
Package
Temperature Range
Carrier Type
Architecture:
ATSAMA5
= Arm Cortex-A5 CPU
Product Group:
D225
= 196-ball general-purpose
microprocessor family
D27
= 289-ball or 361-ball generalpurpose microprocessor family
D28
Memory Type and Size:
D1M
= 128-Mbit DDR2 SDRAM
D5M
= 512-Mbit DDR2 SDRAM
D1G
= 1-Gigabit DDR2 SDRAM
LD1G
= 1-Gigabit LPDDR2 SDRAM
LD2G
= 2-Gigabit LPDDR2 SDRAM
Mask Revision:
C
Package:
C
= BGA
Temperature Range:
U
= -40°C to +85°C (Industrial)
Carrier Type:
Blank
= Standard packaging (tray)
R
= Tape and Reel
Examples:
• ATSAMA5D225C-D1M-CU = ARM Cortex-A5 general-purpose microprocessor, 128-Mbit DDR2 SDRAM, 196ball, Industrial temperature, BGA Package.
Note: Tape and Reel identifier only appears in the catalog part number description. This identifier is used for
ordering purposes and is not printed on the device package
Microchip Devices Code Protection Feature
Note the following details of the code protection feature on Microchip devices:
•
•
•
Microchip products meet the specification contained in their particular Microchip Data Sheet.
Microchip believes that its family of products is one of the most secure families of its kind on the market today,
when used in the intended manner and under normal conditions.
There are dishonest and possibly illegal methods used to breach the code protection feature. All of
these methods, to our knowledge, require using the Microchip products in a manner outside the operating
specifications contained in Microchip’s Data Sheets. Most likely, the person doing so is engaged in theft of
intellectual property.
© 2021 Microchip Technology Inc.
Datasheet
DS60001484D-page 53
SAMA5D2 SIP
•
•
Microchip is willing to work with the customer who is concerned about the integrity of their code.
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code
protection does not mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection
features of our products. Attempts to break Microchip’s code protection feature may be a violation of the Digital
Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you
may have a right to sue for relief under that Act.
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ISBN: 978-1-5224-7802-7
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SAMA5D2 SIP
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For information regarding Microchip’s Quality Management Systems, please visit www.microchip.com/quality.
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