LAN9215
16-bit Non-PCI 10/100 Ethernet Controller with HP Auto-MDIX
Support
Highlights
•
•
•
•
•
Optimized for medium performance applications
Efficient architecture with low CPU overhead
Easily interfaces to most 16-bit embedded CPU’s
Integrated PHY with HP Auto-MDIX support
Supports audio & video streaming over Ethernet:
multiple standard-definition (SD) MPEG2 streams
Target Applications
•
•
•
•
•
•
•
Basic cable, satellite, and IP set-top boxes
Digital video recorders
Video-over IP solutions, IP PBX & video phones
Wireless routers & access points
Audio distribution systems
Printers, kiosks, security systems
General embedded applications
Key Benefits
• Non-PCI Ethernet controller for medium performance applications
- 16-bit interface
- Burst-mode read support
- External MII Interface
• Eliminates dropped packets
- Internal buffer memory can store over 200
packets
- Automatic PAUSE and back-pressure flow
control
• Minimizes CPU overhead
- Supports Slave-DMA
- Interrupt Pin with Programmable Hold-off
timer
• Reduces system cost and increases design flexibility
• SRAM-like interface easily interfaces to most
embedded CPU’s or SoC’s
• Reduced Power Modes
- Numerous power management modes
- Wake on LAN
- Magic packet wakeup
- Wakeup indicator event signal
- Link Status Change
2006-2017 Microchip Technology Inc.
• Single chip Ethernet controller
- Fully compliant with IEEE 802.3/802.3u standards
- Integrated Ethernet MAC and PHY
- 10BASE-T and 100BASE-TX support
- Full- and Half-duplex support
- Full-duplex flow control
- Backpressure for half-duplex flow control
- Preamble generation and removal
- Automatic 32-bit CRC generation and
checking
- Automatic payload padding and pad removal
- Loop-back modes
• Flexible address filtering modes
- One 48-bit perfect address
- 64 hash-filtered multicast addresses
- Pass all multicast
- Promiscuous mode
- Inverse filtering
- Pass all incoming with status report
- Disable reception of broadcast packets
• Integrated 10/100 Ethernet PHY
- Supports HP Auto-MDIX
- Auto-negotiation
- Supports energy-detect power down
• Host bus interface
- Simple, SRAM-like interface
- 16-bit data bus
- 16Kbyte FIFO with flexible TX/RX allocation
- One configurable host interrupt
• Miscellaneous features
- Low-profile 100-pin TQFP, or 100-ball LFBGA
RoHS Compliant package
- Integrated 1.8V regulator
- General Purpose Timer
- Optional EEPROM interface
- Support for 3 status LEDs multiplexed with
Programmable GPIO signals
• Single 3.3V Power Supply with 5V tolerant
I/O
• 0C to +70C Commercial Temperature Support
DS00002412A-page 1
LAN9215
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The last character of the literature number is the version number, (e.g., DS30000000A is version A of document DS30000000).
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DS00002412A-page 2
2006-2017 Microchip Technology Inc.
LAN9215
Table of Contents
1.0 General Description ........................................................................................................................................................................ 4
2.0 Pin Description and Configuration .................................................................................................................................................. 9
3.0 Functional Description .................................................................................................................................................................. 19
4.0 Internal Ethernet PHY ................................................................................................................................................................... 54
5.0 Register Description ...................................................................................................................................................................... 63
6.0 Timing Diagrams ......................................................................................................................................................................... 109
7.0 Operational Characteristics ......................................................................................................................................................... 120
8.0 Package Information ................................................................................................................................................................... 127
Appendix A: Data Sheet Revision History ......................................................................................................................................... 130
2006-2017 Microchip Technology Inc.
DS00002412A-page 3
LAN9215
1.0
GENERAL DESCRIPTION
The LAN9215 is a full-featured, single-chip 10/100 Ethernet controller designed for embedded applications where performance, flexibility, ease of integration and system cost control are required. The LAN9215 has been architected to
provide the best price-performance ratio for any 16-bit application with medium performance requirements. The
LAN9215 is fully IEEE 802.3 10BASE-T and 802.3u 100BASE-TX compliant, and supports HP Auto-MDIX.
The LAN9215 includes an integrated Ethernet MAC and PHY with a high-performance SRAM-like slave interface. The
simple, yet highly functional host bus interface provides a glue-less connection to most common 16-bit microprocessors
and microcontrollers as well as 32-bit microprocessors with a 16-bit external bus. The LAN9215 includes large transmit
and receive data FIFOs to accommodate high latency applications. In addition, the LAN9215 memory buffer architecture
allows highly efficient use of memory resources by optimizing packet granularity.
Applications
The LAN9215 is well suited for many medium-performance embedded applications, including:
•
•
•
•
•
Printers, kiosks, POS terminals and security systems
Audio distribution systems
General embedded systems
Basic cable, satellite and IP set-top boxes
Voice-over-IP solutions
The LAN9215 also supports features which reduce or eliminate packet loss. Its internal 16-KByte SRAM can hold over
200 received packets. If the receive FIFO gets too full, the LAN9215 can automatically generate flow control packets to
the remote node, or assert back-pressure on the remote node by generating network collisions.
The LAN9215 supports numerous power management and wakeup features. The LAN9215 can be placed in a reduced
power mode and can be programmed to issue an external wake signal via several methods, including “Magic Packet”,
“Wake on LAN” and “Link Status Change”. This signal is ideal for triggering system power-up using remote Ethernet
wakeup events. The device can be removed from the low power state via a host processor command.
DS00002412A-page 4
2006-2017 Microchip Technology Inc.
LAN9215
1.1
Block Diagram
FIGURE 1-1:
SYSTEM BLOCK DIAGRAM
System Memory
System
Peripherals
MII
Optional
Optional
External
PHY
Magnetics
Ethernet
Microprocessor/
Microcontroller
System Bus
LAN9215
Magnetics
LEDS/GPIO
25MHz
XTAL
EEPROM
(Optional)
The Microchip LAN9215 integrated 10/100 MAC/PHY controller is a peripheral chip that performs the function of translating parallel data from a host controller into Ethernet packets. The LAN9215 Ethernet MAC/PHY controller is designed
and optimized to function in an embedded environment. All communication is performed with programmed I/O transactions using the simple SRAM-like host interface bus.
The diagram shown above, describes a typical system configuration of the LAN9215 in a typical embedded environment.
The LAN9215 is a general purpose, platform independent, Ethernet controller. The LAN9215 consists of four major functional blocks. The four blocks are:
•
•
•
•
10/100 Ethernet PHY
10/100 Ethernet MAC
RX/TX FIFOs
Host Bus Interface (HBI)
2006-2017 Microchip Technology Inc.
DS00002412A-page 5
LAN9215
1.2
Compatibility with First-generation LAN9118 Family Devices
The LAN9215 is driver-, register-, and footprint-compatible with previous generation LAN9118 Family devices. Drivers
written for these products will work with the LAN9215. However, in order to support HP Auto-MDIX, other components
such as the magnetics and the passive components around the magnetics need to change, and supporting these
changes does require a minor PCB change. A reference design for the LAN9215 will be available on Microchip’s website.
1.3
Internal Block Overview
This section provides an overview of each of these functional blocks as shown in Figure 1-2, "Internal Block Diagram".
FIGURE 1-2:
INTERNAL BLOCK DIAGRAM
25MHz
+3.3V
Power
Management
Host Bus Interface
(HBI)
16-bit SRAM I/F
3.3V to 1.8V
Core Regulator
TX Status FIFO
RX Status FIFO
FIFO_SEL
Interrupt
Controller
GP Timer
1.4
3.3V to 1.8V
PLL Regulator
EEPROM
Controller
2kB to 14kB
Configurable TX FIFO
PIO
Controller
IRQ
PLL
EEPROM
(Optional)
2kB to 14kB
Configurable RX FIFO
10/100
Ethernet
MAC
MIL - RX Elastic
Buffer - 128 bytes
MIL - TX Elastic
Buffer - 2K bytes
MUX
PME
Wakup Indicator
+3.3V
10/100
Ethernet
PHY
LAN
Optional
External PHY - MII
Interface
10/100 Ethernet PHY
The LAN9215 integrates an IEEE 802.3 physical layer for twisted pair Ethernet applications. The PHY can be configured
for either 100 Mbps (100BASE-TX) or 10 Mbps (10BASE-T) Ethernet operation in either full or half duplex configurations. The PHY block supports HP Auto-MDIX and auto-negotiation.
Minimal external components are required for the utilization of the Integrated PHY.
1.5
10/100 Ethernet MAC
The transmit and receive data paths are separate within the MAC allowing the highest performance especially in full
duplex mode. The data paths connect to the PIO interface Function via separate busses to increase performance. Payload data as well as transmit and receive status is passed on these busses.
A third internal bus is used to access the MAC’s Control and Status Registers (CSR’s). This bus is accessible from the
host through the PIO interface function.
On the backend, the MAC interfaces with the internal 10/100 PHY through a MII (Media Independent Interface) port
internal to the LAN9215. The MAC CSR's also provide a mechanism for accessing the PHY’s internal registers through
the internal SMI (Serial Management Interface) bus. The Ethernet MAC can also communicate with an external PHY.
This mode however, is optional.
DS00002412A-page 6
2006-2017 Microchip Technology Inc.
LAN9215
The MAC Interface Layer (MIL), within the MAC, contains a 2K Byte transmit and a 128 Byte receive FIFO which is separate from the TX and RX FIFOs. The FIFOs within the MAC are not directly accessible from the host interface. The
differentiation between the TX/RX FIFO memory buffers and the MAC buffers is that when the transmit or receive packets are in the MAC buffers, the host no longer can control or access the TX or RX data. The MAC buffers (both TX and
RX) are in effect the working buffers of the Ethernet MAC logic. In the case of reception, the data must be moved first
to the RX FIFOs for the host to access the data. For TX operations, the MIL operates in store-and-forward mode and
will queue an entire frame before beginning transmission.
1.6
Receive and Transmit FIFOs
The Receive and Transmit FIFOs allow increased packet buffer storage to the MAC. The FIFOs are a conduit between
the host interface and the MAC through which all transmitted and received data and status information is passed. Deep
FIFOs allow a high degree of latency tolerance relative to the various transport and OS software stacks thus reducing
or minimizing overrun conditions. Like the MAC, the FIFOs have separate receive and transmit data paths. In addition,
the RX and TX FIFOs are configurable in size, allowing increased flexibility.
1.7
Interrupt Controller
The LAN9215 supports a single programmable interrupt. The programmable nature of this interrupt allows the user the
ability to optimize performance dependent upon the application requirement. Both the polarity and buffer type of the
interrupt pin are configurable for the external interrupt processing. The interrupt line can be configured as an open-drain
output to facilitate the sharing of interrupts with other devices. In addition, a programmable interrupt de-assertion interval
is provided.
1.8
GPIO Interface
A 3-bit GPIO and 2-bit GPO (Multiplexed on the EEPROM and LED Pins) interface is included in the LAN9215. It is
accessible through the host bus interface via the CSRs. The GPIO signals can function as inputs, push-pull outputs and
open drain outputs. The GPIO’s (GPO’s are not configurable) can also be configured to trigger interrupts with programmable polarity.
1.9
Serial EEPROM Interface
A serial EEPROM interface is included in the LAN9215. The serial EEPROM is optional and can be programmed with
the LAN9215 MAC address. The LAN9215 can optionally load the MAC address automatically after power-on reset,
hardware reset, or soft reset.
1.10
Power Management Controls
The LAN9215 supports comprehensive array of power management modes to allow use in power sensitive applications.
Wake on LAN, Link Status Change and Magic Packet detection are supported by the LAN9215. An external PME (Power
Management Event) interrupt is provided to indicate detection of a wakeup event.
1.11
General Purpose Timer
The general-purpose timer has no dedicated function within the LAN9215 and may be programmed to issue a timed
interrupt.
1.12
Host Bus Interface (SRAM Interface)
The host bus interface provides a FIFO interface for the transmit and receive data paths, as well as an interface for the
LAN9215 Control and Status Registers (CSR’s).
The host bus interface is the primary bus for connection to the embedded host system. This interface models an asynchronous SRAM. TX FIFO, RX FIFO, and CSR’s are accessed through this interface. Programmed I/O transactions are
supported.
The LAN9215 host bus interface supports 16-bit bus transfers. Internally, all data paths are 32-bits wide. The LAN9215
can be interfaced to either Big-Endian or Little-Endian processors.
2006-2017 Microchip Technology Inc.
DS00002412A-page 7
LAN9215
1.13
External MII Interface
The LAN9215 also supports the ability to interface to an external PHY device. This interface is compatible with all IEEE
802.3 MII compliant physical layer devices. For additional information on the MII interface and associated signals,
please refer to Section 3.11, "MII Interface - External MII Switching," on page 37 for more information.
DS00002412A-page 8
2006-2017 Microchip Technology Inc.
LAN9215
2.0
PIN DESCRIPTION AND CONFIGURATION
100-TQFP PIN CONFIGURATION (TOP VIEW)
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
RXD0
SPEED_SEL
AMDIX_EN
IRQ
NC
PME
EECLK**
EECS
EEDIO**
GND_CORE
VDD_CORE
D0
D1
D2
VDD_IO
GND_IO
D3
D4
D5
D6
VDD_IO
GND_IO
D7
D8
D9
FIGURE 2-1:
FIFO_SEL
VSS_A
(Note 1) TPO (Note 1) TPO +
VSS_A
VDD_A
(Note 1) TPI (Note 1) TPI +
NC
VDD_A
VSS_A
EXRES1
VSS_A
VDD_A
NC
NC
nRD
50
49
48
47
46
45
44
43
D10
D11
VDD_IO
GND_IO
D12
D13
D14
D15
84
85
86
87
88
89
90
91
92
93
94
95
96
42
41
40
39
38
37
36
35
34
33
32
31
30
VDD_IO
GND_IO
TX_CLK
TXD0
TXD1
TXD2
TXD3
VDD_IO
GND_IO
COL
CRS
MDC
MDIO**
97
98
29
28
RX_DV
VDD_IO
99
100
27
26
GND_IO
RX_CLK
SMSC
LAN9215
100 PIN TQFP
GND_CORE
VREG
VDD_CORE
VSS_PLL
XTAL2
XTAL1
VDD_PLL
VDD_REF
ATEST
RBIAS
VSS_REF
A7
A6
A5
A4
A3
A2
A1
GND_IO
VDD_IO
TX_EN
RXD1
RXD2
RXD3
RX_ER
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
nWR
nCS
nRESET
GND_IO
VDD_IO
GPIO0/nLED1**
GPIO1/nLED2**
GPIO2/nLED3**
76
77
78
79
80
81
82
83
**Denotes a multifunction pin
NOTE 1: When HP Auto-MDIX is activated, the TPO+/- pins function as TPI+/- and vice-versa.
2006-2017 Microchip Technology Inc.
DS00002412A-page 9
LAN9215
FIGURE 2-2:
A
B
100-LFBGA PIN CONFIGURATION (TOP VIEW)
1
2
3
4
5
6
7
8
9
10
11
12
VREG
GPIO2
nLED3
GPIO0
nLED1
nRESET
nWR
VDD_A
EXRES 1
TPI+
TPI-
TPO+
TPO-
FIFO_SEL
XTAL1
CLKIN
XTAL2
GPIO1
nLED2
VDD_IO
nCS
nRD
VDD_A
NC
VDD_IO
VDD_A
RXD0
SPEED _SEL
VDD_REF
VDD_PLL
VDD_IO
VDD_IO
AMDIX_EN
IRQ
ATEST
VDD_IO
VDD_CORE
VDD_CORE
VDD_IO
NC
A7
RBIAS
GND
GND
PME
EECLK
A5
A6
GND
GND
EECS
EEDIO
A4
A3
GND
GND
D1
D0
A2
A1
GND
GND
D3
D2
TX_EN
VDD_IO
VDD_CORE
VDD_CORE
VDD_IO
D4
RXD1
RXD2
VDD_IO
VDD_IO
D6
D5
RXD3
RX_ER
MDIO
VDD_IO
COL
TXD2
TX_CLK
D14
VDD_IO
D11
D8
D7
RX_CLK
RX_DV
MDC
CRS
TXD3
TXD1
TXD0
D15
D13
D12
D10
D9
1
2
3
4
5
6
7
8
9
10
11
12
C
D
E
F
G
H
J
M
B
C
LAN9215
100-LFBGA
TOP VIEW
GND
GND
GND
GND
K
L
A
D
E
F
G
H
J
K
DS00002412A-page 10
L
M
2006-2017 Microchip Technology Inc.
LAN9215
2.1
Pin List
TABLE 2-1:
HOST BUS INTERFACE SIGNALS
Name
Symbol
Buffer
Type
#
Pins
Host Data
D[15:0]
I/O8
16
Bi-directional data port.
Host Address
A[7:1]
IS
7
7-bit Address Port. Used to select Internal CSR’s and
TX and RX FIFOs.
Read Strobe
nRD
IS
1
Active low strobe to indicate a read cycle.
Write Strobe
nWR
IS
1
Active low strobe to indicate a write cycle. This signal,
qualified with nCS, is also used to wakeup the
LAN9215 when it is in a reduced power state.
Chip Select
nCS
IS
1
Active low signal used to qualify read and write
operations. This signal qualified with nWR is also used
to wakeup the LAN9215 when it is in a reduced power
state.
Interrupt
Request
IRQ
O8/OD8
1
Programmable Interrupt request. Programmable
polarity, source and buffer types.
FIFO Select
FIFO_SEL
IS
1
When driven high all accesses to the LAN9215 are to
the RX or TX Data FIFOs. In this mode, the A[7:3]
upper address inputs are ignored.
TABLE 2-2:
Description
DEFAULT ETHERNET SETTINGS
Default Ethernet Settings
SPEED_SEL
Speed
Duplex
Auto Neg.
0
10Mbps
Half-Duplex
Disabled
1
100Mbps
Half-Duplex
Enabled
TABLE 2-3:
LAN INTERFACE SIGNALS
Name
Symbol
Buffer
Type
# Pins
TPO+
TPO+
AO
1
Transmit Positive Output (normal)
Receive Positive Input (reversed)
TPO-
TPO-
AO
1
Transmit Negative Output (normal)
Receive Negative Input (reversed)
TPI+
TPI+
AI
1
Receive Positive Input (normal)
Transmit Positive Input (reversed)
TPI-
TPI-
AI
1
Receive Negative Input (normal)
Transmit Negative Output (reversed)
PHY External Bias
Resistor
EXRES1
AI
1
Must be connected to ground through a 12.4K
ohm 1% resistor.
2006-2017 Microchip Technology Inc.
Description
DS00002412A-page 11
LAN9215
Note:
The pin names for the twisted pair pins shown above apply to a normal connection. If HP Auto-MDIX is
enabled and a reverse connection is detected, or a reverse connection is manually selected, the input pins
become outputs, and vice-versa, as indicated in the descriptions.
TABLE 2-4:
SERIAL EEPROM INTERFACE SIGNALS
Name
Symbol
EEPROM Data,
GPO3, TX_EN,
TX_CLK
EEDIO/GPO3/
TX_EN/TX_CLK
Buffer
Type
# Pins
Description
I/O8
1
EEPROM Data: This bi-directional pin can be
connected to a serial EEPROM DIO. This is
optional.
General Purpose Output 3: This pin can also
function as a general purpose output, or it can
be configured to monitor the TX_EN or
TX_CLK signals on the internal MII port. When
configured as a GPO signal, or as a
TX_EN/TX_CLK monitor, the EECS pin is
deasserted so as to never unintentionally
access the serial EEPROM. This signal cannot
function as a general-purpose input.
EEPROM Chip
Select
EECS
O8
1
Serial EEPROM chip select.
EEPROM Clock,
GPO4 RX_DV,
RX_CLK
EECLK/GPO4/
RX_DV/RX_CLK
O8
1
EEPROM Clock: Serial EEPROM Clock pin.
General Purpose Output 4: This pin can also
function as a general-purpose output, or it can
be configured to monitor the RX_DV or
RX_CLK signals on the internal MII port. When
configured as a GPO signal, or as an
RX_DV/RX_CLK monitor, the EECS pin is
deasserted so as to never unintentionally
access the serial EEPROM. This signal cannot
function as a general-purpose input.
Note:
DS00002412A-page 12
When the EEPROM interface is not
used, the EECLK pin must be left
unconnected.
2006-2017 Microchip Technology Inc.
LAN9215
TABLE 2-5:
SYSTEM AND POWER SIGNALS
Name
Symbol
Buffer
Type
# Pins
Description
Crystal 1, Clock In
XTAL1/CLKIN
lCLK
1
External 25MHz Crystal Input. This pin can also
be connected to single-ended TTL oscillator
(CLKIN). If this method is implemented, XTAL2
should be left unconnected.
Crystal 2
XTAL2
OCLK
1
External 25MHz Crystal output.
Reset
nRESET
IS
(PU)
1
Active-low reset input. Resets all logic and
registers within the LAN9215. This signal is
pulled high with a weak internal pull-up resistor.
If nRESET is left unconnected, the LAN9215
will rely on its internal power-on reset circuitry.
Note:
The LAN9215 must always be read
at least once after power-up, reset,
or upon return from a power-saving
state or write operations will not
function. See Section 3.10, "Detailed
Reset Description," on page 36 for
additional information
Wakeup Indicator
PME
O8/OD8
1
When programmed to do so, is asserted when
the LAN9215 detects a wake event and is
requesting the system to wake up from the
associated sleep state. The polarity and buffer
type of this signal is programmable.
Note:
Detection of a Power Management
Event, and assertion of the PME signal will not wakeup the LAN9215.
The LAN9215 will only wake up
when it detects a host write cycle
(assertion of nCS and nWR).
Although any write to the LAN9215,
regardless of the data written, will
wake-up the device when it is in a
power-saving mode, it is required
that the BYTE_TEST register be
used for this purpose.
Auto-MDIX Enable
AMDIX_EN
I
(PD)
1
Enables Auto-MDIX. Pull high enable AutoMDIX, pull low or leave unconnected to disable
Auto-MDIX.
10/100 Selector
SPEED_SEL
I
(PU)
1
This signal functions as a configuration input on
power-up and is used to select the default
Ethernet settings. Upon deassertion of reset,
the value of the input is latched. This signal
functions as shown in Table 2-2, "Default
Ethernet Settings", below.
No Connect
NC
4
No Connect. These pins must be left open.
2006-2017 Microchip Technology Inc.
DS00002412A-page 13
LAN9215
TABLE 2-5:
SYSTEM AND POWER SIGNALS (CONTINUED)
Name
Symbol
Buffer
Type
General Purpose
I/O data,
nLED1 (Speed
Indicator),
nLED2 (Link &
Activity Indicator),
GPIO[2:0]/
nLED[3:1]
IS/O12/
OD12
# Pins
Description
3
General Purpose I/O data: These three
general-purpose signals are fully programmable
as either push-pull output, open-drain output or
input by writing the GPIO_CFG configuration
register in the CSR’s. They are also multiplexed
as GP LED connections.
GPIO signals are Schmitt-triggered inputs.
When configured as LED outputs these signals
are open-drain.
nLED3 (FullDuplex
Indicator).
nLED1 (Speed Indicator). This signal is driven
low when the operating speed is 100Mb. During
auto-negotiation, when the cable is
disconnected, and during 10Mbs operation, this
signal is driven high.
nLED2 (Link & Activity Indicator). This signal
is driven low (LED on) when the LAN9215
detects a valid link. This signal is pulsed high
(LED off) for 80mS whenever transmit or
receive activity is detected. This signal is then
driven low again for a minimum of 80mS, after
which time it will repeat the process if TX or RX
activity is detected. Effectively, LED2 is
activated solid for a link. When transmit or
receive activity is sensed LED2 will flash as an
activity indicator.
nLED3 (Full-Duplex Indicator). This signal is
driven low when the link is operating in fullduplex mode.
RBIAS
RBIAS
AI
1
PLL Bias: Connect to an external 12.0K ohm
1.0% resistor to ground. Used for the PLL Bias
circuit.
Test Pin
ATEST
I
1
This pin must be connected to VDD for normal
operation.
Internal Regulator
Power
VREG
P
1
3.3V input for internal voltage regulator
+3.3V I/O Power
VDD_IO
P
8
+3.3V I/O logic power supply pins
I/O Ground
GND_IO
P
8
Ground for I/O pins
(100-TQFP Package Only)
+3.3V Analog
Power
VDD_A
P
3
+3.3V analog power supply pins. See Note 2-1.
Analog Ground
VSS_A
P
4
Ground for analog circuitry
(100-TQFP Package Only)
Core Voltage
Decoupling
VDD_CORE
P
2
+1.8 V from internal core regulator. Both pins
must be connected together externally. Each
pin requires a 0.01uF decoupling capacitor. In
addition, pin 3 requires a bulk 10uF capacitor
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