LX8233ILQ-TR

LX8233 2.5A 5V E-Fuse with Bi-Directional Protection Switch and DevSleep/Disable Mode Features Description The LX8233 is a fast acting bi-directional eFuse switch designed both to protect circuitry connected to its output (VOUT) from transient input voltage surges on its input (VCC), and to protect VCC from overload current events coming from the load on VOUT. It will also block the reverse discharge current from flowing from VOUT to VCC if the input supply collapes. Voltage protection features include under-voltage lockout (UVLO), and over-voltage clamping. This clamp limits VOUT voltage allowing continued circuit operation during an input over-voltage transient condition, while UVLO ensures that VOUT remains off until VCC reaches its minimum operating threshold. On the current side, the LX8233 protects the input from a output short circuit and/or over current condtion with a 2.5A current limit circuit. Another protection feature is latching thermal shutdown of VOUT, with a fault flag output on the combined EN/FAULT pin. Once thermal shutdown threshold is reached and the eFuse switch opens, the tristate EN/FAULT pin will be pulled to about 1.6V signaling to the system and potentially other connected eFuse switches that a fault has occurred. The LX8233 latches at this level until reset by the Enable pin, DEVSLP pin, or there is a VCC power recycle.  50mΩ (typ.) Rdson Internal eFuse FET Protected From 15V  Bi-directional Current Blocking Switch  SATA DevSleep Support  SAS-DISABLE Support  Up to 15V Transient Input Range  6V Output Voltage Clamp  Continuous Operation During VCC surge  Current Limit at Overload and Short-Circuit Protection  Over-Temperature Protection  Selectable Soft-start 13ms or 1.4ms Risetime  UVLO Detection  VQFN 2mm x 3mm 13L Package Applications     Hard-Disk Drive Solid-State Drive Hot Swap PC Cards At device power up the user can initialize the DevSleep pin functionality and VOUT slew rate in one of two modes depending on the state of the FET_ON pin. In DevSleep Disabled Mode the slew rate is set to 13ms, and VOUT shutdown is engaged when the DEVSLP pin is toggled high regardless of the state of the FET_ON pin. In DevSleep Enabled Mode the slew rate is reduced to 1.4ms, and shutdown is engaged when the DEVSLP pin is toggled high and the FET_ON pin is low. January 2015 Rev. 1.0a www.microsemi.com © 2014 Microsemi Corporation 1 2.5A 5V E-Fuse with Bi-Directional Protection Switch and DevSleep/Disable Mode HOST +12V VOUT RT VCC EN/FAULT +5V 12V E-Fuse VCC 1µF VCC_12V LX8233 DEVSLP 5V Bus VOUT DEVSLP 30µF EN/FAULT DEVSLPOUTB FET_ON VCC_5V SOC/ V1P8 PMIC DEVSLPOUTB FET_ON GND DevSleep Enabled Mode Figure 1 · Typical Application of LX8233, DevSleep Enable Mode HOST +12V VOUT RT VCC EN/FAULT +5V 12V E-Fuse VCC 1µF VCC_12V LX8233 DEVSLP 5V Bus VOUT DEVSLP 30µF EN/FAULT VCC_5V SOC/ PMIC DEVSLPOUTB FET_ON GND DevSleep Disabled Mode Figure 2 · Typical Application of LX8233, DevSleep Disable Mode 2 Pin Configuration and Pinout Pin Configuration and Pinout NC 12 VCC 1 11 OUT VCC 2 10 OUT VCC 3 DEVSLP 4 EN/FAULT 5 13 GND 9 OUT 8 DEVSLPOUTB 7 FET_ON 6 GND Figure 3 · Pinout VQFN 2mm x 3mm 13L Top View Marking: Line 1 MSC Line 2 8233 Line 3 Date / Lot Code Ordering Information Ambient Temperature Type Package -40°C to 85°C RoHS Compliant, Pb-free VQFN 2mm x 3mm 13L Part Number Packaging Type LX8233ILQ Bulk / Tube LX8233ILQ-TR Tape and Reel 3 2.5A 5V E-Fuse with Bi-Directional Protection Switch and DevSleep/Disable Mode Pin Description Pin Number Pin Designator 1, 2, 3 VCC DEVSLP 4 Input/ Description Output Input Input 5 EN/FAULT Input/Output 6 GND - Input of the device. DevSleep mode input. There are two modes for the usage of DEVSLP. One operational mode is DEVSLP Enable Mode. It is selected by connecting the FET_ON pin of LX8233 to SOC during power on initalization. In this mode, only when FET_ON is low will setting DEVSLP high shut down the LX8233. This handshake feature allows the SOC to override the shutdown process initiated by the host using DevSleep allowing any necessary housekeeping functions to complete before powering off the switch. When in this mode the VOUT softstart time is programmed to 1.4 ms. The other mode is DEVSLP Disabled Mode. This is selected by letting FET_ON pin float during power on initalization. In this mode the LX8233 will shutdown by setting DEVSLP high regardless of the FET_ON state. When in this mode the VOUT softstart time is programmed to 13 ms. The two mode are summarized in the table below. DEVSLP Disabled DEVSLP Enabled FET_ON Float Connected to SOC TRISE ~13ms ~1.4ms Shutdown DEVSLP High (DEVSLP High) AND (FET_ON Low) The EN/FAULT pin is a tri−state, bidirectional interface. It can be used to disable the output of the device by pulling it to ground using an open drain or open collector device. If a thermal fault occurs, the voltage on this pin will go to an intermediate state (~1.6V)to signal a monitoring circuit that the device is in thermal shutdown. It can also be connected to another device in this family to cause a simultaneous shutdown during thermal events. See simplified schematic in Theory of Operation/ Application section. Ground Pin (Pin 6 and Pin 13 are internally connected). 7 FET_ON Input DEVSLP mode is configured by the FET_ON state during power on initializaiton. When FET_ON is floating (50pf maximum pin capacitance), the LX8233 is set to DEVSLP Disabled Mode. In this mode, the LX8233 can be shut down by setting the DEVSLP pin high. When FET_ON is connected to SOC, the LX8233 can only be shut down by setting both DEVSLP high and FET_ON low. 8 DEVSLPOUTB Output Open-drain output. A pull-up resistor is connected to the I/O supply of SOC. DEVSLPOUTB is the inversed polarity version of DEVSLP. 9, 10, 11 VOUT Output Output of the device, connect to circuitry to be protected. A 10uF capacitor is needed for over voltage protection stability. The capacitor return should be connected directly to the GND pin. 12 NC - Do Not Connect. 13 GND - Ground Pin(Pin 6 and Pin 13 are internally connected). 4 Block Diagram Block Diagram VCC UVLO Charge Pump Regulator DEVSLP DEVSLP Receiver GND Control Logic EN/FAULT DEVSLPOUTB FET_ON 50mW Bidirectional eFuse Switch Sense Device Thermal Shutdown Gate Driver VOUT dv/dt Control Reference Current limit Voltage Clamp Trim Memory GND Figure 4 · Simplified Block Diagram of LX8233 Absolute Maximum Ratings Min Max Units VCC to GND (Steady-State) -0.3 15 V VCC to GND (Transient 100ms) -0.3 15 V VOUT to GND (Steady-State) -0.3 6.5 V VOUT to GND (Transient 100ms) -0.3 7 V EN/FAULT to GND -0.3 ≤VCC V EN/FAULT to GND -0.3 6 V DEVSLPOUTB to GND -0.3 6 V DEVSLP to GND -0.3 3.6 V FET_ON to GND -0.3 3.6 V Parameter ESD (Human Body Model) 2000 V ESD (Charged Device Model) 1000 V Power Dissipation Storage Temperature -65 1.3 W 150 °C Note: Performance is not necessarily guaranteed over this entire range. These are maximum stress ratings only. Exceeding these ratings, even momentarily, can cause immediate damage, or negatively impact long-term operating reliability 5 2.5A 5V E-Fuse with Bi-Directional Protection Switch and DevSleep/Disable Mode Operating Ratings VCC Min Max Units 4.2 5.75 V 2.5 A 125 °C I(VCC) Junction Temperature -40 Note: Performance is generally guaranteed over this range as further detailed below under Electrical Characteristics. Thermal Properties Thermal Resistance θJA Typ Units 40 °C/W Note: The JA numbers assume no forced airflow. Junction Temperature is calculated using T J = TA + (PD x JA). In particular, θJA is a function of the PCB construction. The stated number above is for a four-layer board in accordance with JESD-51 (JEDEC). 6 Electrical Characteristics Electrical Characteristics Note: The following specifications apply over the operating ambient temperature of -40C ≤ TA ≤ 85C except where otherwise noted with the following test conditions: VCC = 5V. Typical parameter refers to TJ = 25°C. Symbol Parameters Test Conditions/Comments Min Typ Max Units TONDLY Turn-on Delay Time Enable by EN/FAULT with load current 100mA. 80 µs RDSON On Resistance TA = 25°C, (Note 2) 50 mΩ TJ = 80°C, (Note 1) 95 mΩ IOFF Off State Output Leakage Current VCC = 12VDC, EN/FAULT = GND, VOUT = GND Measure I(VOUT) IDC Continuous Current TA = 25°C TRISE VOUT Rise Time eFuse FET FET_ON = Float 1 2 10.4 FET_ON = GND 13 µA A 15.6 ms 1.4 ms 135 °C Thermal Shutdown TSD Shutdown Temperature VOUT is latched off once thermal shutdown is triggered. It can be reset three ways. 1) EN/FAULT is pulled low then let float. 2) DEVSLP pin is toggled high then low. 3) VCC is recycled. Under/Over Voltage Protection Output Clamping Voltage VCC = 10V Maximum Overshoot During Transient VCC transient from 5V to the higher than 12V at 100V/µs with IVOUT = 0A. COUT=33uF Minimum Undershoot During Transient VCC transient from 5V to the higher than 12V at 100V/µs with I(VOUT) = 2.5A. COUT=33uF 4.5 VUVLO_TH Under-Voltage Lock-Out Threshold Turn-on and voltage increases 3.75 VUVLO_HYS Under-Voltage Lock-Out Hysteresis 0.3 V Under-Voltage Lock-Out Response Time 2 µs 2.5 A 3 A VCLAMP 5.75 6.25 V 6.5 V V 4.2 V Current Protection ISC_LIM Short Circuit Current Limit VOUT is