MCP7951X/MCP7952X
Battery-Backed SPI Real-Time Clock/Calendar
Device Selection Table
SRAM (Bytes)
EEPROM (Kbits)
MCP79510
64
1
Blank
MCP79520
64
2
Blank
MCP79511
64
1
EUI-48™
MCP79521
64
2
EUI-48™
MCP79512
64
1
EUI-64™
MCP79522
64
2
EUI-64™
Timekeeping Features
• Real-Time Clock/Calendar (RTCC):
- Hours, minutes, seconds, hundredth of
seconds, day of week, date, month, year
- Leap year compensated to 2399
- 12/24-hour modes
• Oscillator for 32.768 kHz Crystals:
- Optimized for 6-9 pF crystals
• On-Chip Digital Trimming/Calibration:
- ±1 ppm resolution
- ±259 ppm range
• Dual Programmable Alarms
• Clock Output Function with Selectable Frequency
• Power-Fail Timestamp:
- Time logged on switchover to and from Battery
mode
Low-Power Features
• 128-Bit Protected EEPROM Area:
- Robust write unlock sequence
- EUI-48™ MAC address (MCP795X1)
- EUI-64™ MAC address (MCP795X2)
Operating Ranges
• SPI Serial Interface:
- SPI clock rate up to 5 MHz
• Temperature Range:
- Industrial (I): -40°C to +85°C
• Automotive AEC-Q100 Qualified
Packages
• 10-Lead MSOP
• 10-Lead TDFN
Package Types (not to scale)
• Wide Voltage Range:
- Operating voltage range of 1.8V to 3.6V
- Backup voltage range of 1.3V to 3.6V
• Low Typical Timekeeping Current:
- Operating from VCC: 1.2 µA at 3.0V
- Operating from VBAT: 1.0 µA at 3.0V
• Automatic Switchover to Battery Backup
MSOP/TDFN
X1 1
X2 2
VBAT
2012-2022 Microchip Technology Inc. and its subsidiaries
3
CS 4
VSS 5
User Memory
• 64-Byte Battery-Backed SRAM
• 1 Kbit or 2 Kbit EEPROM:
- Software write-protect
- Page write up to 8 bytes
- Endurance: one million erase/write cycles
Unique ID
Note:
10 VCC
MCP795XX
Part Number
9
MFP
8
SCK
7
SO
6
SI
MCP795XX is used in this document as a
generic part number for the MCP7951X
and MCP7952X devices.
DS20002300D-page 1
MCP7951X/MCP7952X
Description
The MCP795XX Real-Time Clock/Calendar (RTCC)
tracks time using internal counters for hours, minutes,
seconds, hundredth of seconds, days, months, years
and day of week. Alarms can be configured on all
counters up to and including months. For usage and
configuration, the MCP795XX supports SPI
communications up to 5 MHz.
The MCP795XX is designed to operate using a
32.768 kHz tuning fork crystal with external crystal
load capacitors. On-chip digital trimming can be used
to adjust for frequency variance caused by crystal
tolerance and temperature.
SRAM and timekeeping circuitry are powered from the
backup supply when main power is lost, allowing the
device to maintain accurate time and the SRAM
contents. The times when the device switches over to
the backup supply and when primary power returns
are both logged by the power-fail timestamp.
The MCP795XX features 128 bits of EEPROM which
is only writable after an unlock sequence, making it
ideal for storing a unique ID or other critical
information. The MCP795X1 and MCP795X2 are
preprogrammed with EUI-48 and EUI-64 addresses,
respectively. Custom programming is also available.
The MCP795XX has a shared pin for outputting a
selectable frequency square wave or alarm signals.
FIGURE 1-1:
TYPICAL APPLICATION SCHEMATIC
VCC
VCC
VCC
10
VCC
4
8
PIC® MCU
6
7
9
CS
X2
SCK
SI
CX1
1
2
32.768 KHZ
X1
CX2
MCP795XX VBAT 3
VBAT
SO
MFP
VSS
5
DS20002300D-page 2
2012-2022 Microchip Technology Inc.and its subsidiaries
MCP7951X/MCP7952X
FIGURE 1-2:
VCC
VSS
VBAT
BLOCK DIAGRAM
Power Control
and Switchover
Power-Fail
Timestamp
CS
SCK
SI
Control Logic
SPI Interface
and Addressing
SO
SRAM
EEPROM
Configuration
Hundredth of
Seconds
Seconds
X1
32.768 kHz
Oscillator
Clock Divider
X2
Minutes
Hours
Digital Trimming
MFP
Day of Week
Square Wave
Output
Date
Month
Alarms
Year
2012-2022 Microchip Technology Inc. and its subsidiaries
DS20002300D-page 3
MCP7951X/MCP7952X
1.0
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings (†)
VCC .............................................................................................................................................................................6.5V
All inputs and outputs w.r.t. VSS .......................................................................................................... -0.6V to VCC+1.0V
Storage temperature ...............................................................................................................................-65°C to +150°C
Ambient temperature under bias ...............................................................................................................-40°C to +85°C
ESD protection on all pins ..........................................................................................................................................4 kV
† NOTICE: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions above those
indicated in the operational listings of this specification is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
TABLE 1-1:
DC CHARACTERISTICS
Industrial (I):
DC CHARACTERISTICS
Param.
No.
D1
D2
Symbol
Characteristic
VIH
High-Level Input Voltage
VIL
Low-Level Input Voltage
D3
VOL
Low-Level Output Voltage
D4
VOH
High-Level Output Voltage
D5
ILI
D6
ILO
D7
D8
D9
D12
Note 1:
2:
0.7 VCC
—
VCC + 1
-0.3
—
0.3VCC
-0.3
—
0.2VCC
—
—
0.4
Test Conditions
V
V
V
VCC≥2.5V
VCC < 2.5V
IOL = 2.1 mA, VCC ≥2.5V
—
—
0.2
—
—
V
Input Leakage Current
—
—
±1
µA
CS = VCC, VIN = VSS or
VCC
Output Leakage Current
—
—
±1
µA
CS = VCC, VOUT = VSS or
VCC
CINT
Pin Capacitance
(all inputs and outputs)
—
—
7
pF
VCC = 3.6V (Note 2)
TA = +25°C, f = 1 MHz
COSC
Oscillator Pin
Capacitance (X1, X2 pins)
—
3
—
pF
Note 2
—
—
3
mA
VCC = 3.6V, FCLK = 5 MHz
SO = Open
—
—
5
mA
VCC = 3.6V
—
—
3
mA
VCC = 3.6V, FCLK = 5 MHz
SO = Open
—
—
3
mA
VCC = 3.6V, FCLK = 5 MHz
—
—
1
µA
VCC = 3.6V
—
—
1.2
µA
VCC = 1.8V, CS = VCC,
(Note 2)
—
1.2
1.8
µA
VCC = 3.0V, CS = VCC,
(Note 2)
—
—
2.6
µA
VCC = 3.6V, CS = VCC,
(Note 2)
ICCEERD
ICCREAD
ICCWRITE
D11
Minimum Typical(1) Maximum Units
VCC = 1.8V to 3.6V
VCC - 0.5
ICCEEWR
D10
TA = -40°C to +85°C
ICCDAT
ICCT
EEPROM Operating
Current
SRAM/RTCC Operating
Current
Vcc Data Retention
Current (oscillator off)
Timekeeping Current
IOL = 1.0 mA, VCC < 2.5V
IOH = -400 µA
Typical measurements taken at room temperature.
This parameter is not tested but ensured by characterization.
DS20002300D-page 4
2012-2022 Microchip Technology Inc.and its subsidiaries
MCP7951X/MCP7952X
TABLE 1-1:
DC CHARACTERISTICS (CONTINUED)
DC CHARACTERISTICS (Continued)
Industrial (I):
Param.
No.
Minimum Typical(1) Maximum Units
Symbol
Characteristic
TA = -40°C to +85°C
VCC = 1.8V to 3.6V
Test Conditions
D13
VTRIP
Power-Fail Switchover
Voltage
1.3
1.5
1.7
V
D14
VBAT
Backup Supply Voltage
Range
1.3
—
3.6
V
—
—
850
nA
VBAT = 1.3V, VCC = VSS
(Note 2)
—
1000
1200
nA
VBAT = 3.0V, VCC = VSS
(Note 2)
—
—
2300
nA
VBAT = 3.6V, VCC = VSS
(Note 2)
—
—
850
nA
VBAT = 3.6V, VCC = VSS
D15
IBATT
Timekeeping Backup
Current
VBAT Data Retention
Current (oscillator off)
D16
IBATDAT
Note 1:
2:
Typical measurements taken at room temperature.
This parameter is not tested but ensured by characterization.
2012-2022 Microchip Technology Inc. and its subsidiaries
DS20002300D-page 5
MCP7951X/MCP7952X
TABLE 1-2:
AC CHARACTERISTICS
AC CHARACTERISTICS
Industrial (I): TA = -40°C to +85°C VCC = 1.8V to 3.6V
Param.
Symbol
No.
Minimum Typical Maximum
1
FCLK
2
TCSS
3
TCSH
Characteristic
Clock Frequency
CS Setup Time
CS Hold Time
4
TCSD
CS Disable Time
5
TSU
Data Setup Time
6
THD
7
Data Hold Time
Units
Test Conditions
—
—
5
MHz
2.5V ≤Vcc < 3.6V
—
—
3
MHz
1.8V ≤Vcc < 2.5V
100
—
—
ns
2.5V ≤Vcc < 3.6V
150
—
—
ns
1.8V ≤Vcc < 2.5V
100
—
—
ns
2.5V ≤Vcc < 3.6V
150
—
—
ns
1.8V ≤Vcc < 2.5V
50
—
—
ns
20
—
—
ns
2.5V ≤Vcc < 3.6V
30
—
—
ns
1.8V ≤Vcc < 2.5V
40
—
—
ns
2.5V ≤Vcc < 3.6V
50
—
—
ns
1.8V ≤Vcc < 2.5V
TR
SCK Rise Time
—
—
100
ns
Note 1
8
TF
SCK Fall Time
—
—
100
ns
Note 1
9
THI
Clock High Time
10
TLO
Clock Low Time
100
—
—
ns
2.5V ≤Vcc < 3.6V
150
—
—
ns
1.8V ≤Vcc < 2.5V
100
—
—
ns
2.5V ≤Vcc < 3.6V
150
—
—
ns
1.8V ≤Vcc < 2.5V
11
TCLD
Clock Delay Time
50
—
—
ns
12
TCLE
Clock Enable Time
50
—
—
ns
13
TV
Output Valid from Clock
Low
—
—
100
ns
2.5V ≤Vcc < 3.6V
—
—
160
ns
1.8V ≤Vcc < 2.5V
14
THO
Output Hold Time
0
—
ns
Note 1
15
TDIS
Output Disable Time
—
—
80
ns
2.5V ≤Vcc < 3.6V (Note 1)
—
—
160
ns
1.8V ≤Vcc < 2.5V (Note 1)
—
—
5
ms
Note 2
16
TWC
17
TFVCC
VCC Fall Time
300
—
—
µs
Note 1
18
TRVCC
VCC Rise Time
0
—
—
µs
Note 1
19
FOSC
Oscillator Frequency
—
32.768
—
kHz
20
TOSF
Oscillator Timeout Period
—
1
—
Endurance
1M
—
—
21
Internal Write Cycle Time
ms
Note 1
E/W Page Mode, +25°C
cycles VCC = 3.6V (Note 1)
Note 1: This parameter is not tested but ensured by characterization.
2: TWC begins on the rising edge of CS after a valid write sequence and ends when the internal write cycle
is complete.
DS20002300D-page 6
2012-2022 Microchip Technology Inc.and its subsidiaries
MCP7951X/MCP7952X
FIGURE 1-1:
SERIAL INPUT TIMING
4
CS
12
2
7
10
SCK
3
8
9
5
SI
6
MSb In
LSb In
High-Impedance
SO
FIGURE 1-2:
11
SERIAL OUTPUT TIMING
CS
9
3
10
SCK
13
14
MSb Out
SO
15
LSb Out
Don’t Care
SI
FIGURE 1-3:
POWER SUPPLY TRANSITION TIMING
VCC
VTRIP(MAX)
VTRIP(MIN)
17
2012-2022 Microchip Technology Inc. and its subsidiaries
18
DS20002300D-page 7
MCP7951X/MCP7952X
2.0
TYPICAL PERFORMANCE CURVES
Note:
The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data represented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore, outside the warranted range.
FIGURE 2-1:
TIMEKEEPING BACKUP
CURRENT VS. BACKUP
SUPPLY VOLTAGE
FIGURE 2-2:
1.8
1.6
1.4
TA = -40°C
TA = 25°C
TA = 85°C
1.6
Ͳ40
85
1.0
0.8
0.6
0.4
ICCT Current (µA)
IBATT Current (µA)
25
1.2
TIMEKEEPING CURRENT
VS. SUPPLY VOLTAGE
1.4
1.2
25
85
1.0
0.8
0.6
0.4
0.2
0.2
0.0
1.30 1.60 1.90 2.20 2.50 2.80 3.10 3.40
VBAT Voltage (V)
0.0
1.80
DS20002300D-page 8
TA = -40°C
TA = 25°C
TA = 85°C
Ͳ40
2.10
2.40
2.70
3.00
VCC Voltage (V)
3.30
3.60
2012-2022 Microchip Technology Inc.and its subsidiaries
MCP7951X/MCP7952X
3.0
PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
TABLE 3-1:
PIN FUNCTION TABLE
10-Pin MSOP
10-Pin TDFN(1)
X1
1
1
Quartz Crystal Input, External Oscillator Input
X2
2
2
Quartz Crystal Output
VBAT
3
3
Battery Backup Supply Input
CS
4
4
Chip Select Input
VSS
5
5
Ground
SI
6
6
Serial Data Input
SO
7
7
Serial Data Output
SCK
8
8
Serial Clock Input
MFP
9
9
Multifunction Pin
10
10
Primary Power Supply
Name
VCC
Note 1:
3.1
Pin Function
Exposed pad on TDFN can be connected to Vss or left floating.
Oscillator Input/Output (X1, X2)
These pins are used as the connections for an external
32.768 kHz quartz crystal and load capacitors. X1 is
the crystal oscillator input and X2 is the output. The
MCP795XX is designed to allow for the use of external
load capacitors in order to provide additional flexibility
when choosing external crystals. The MCP795XX is
optimized for crystals with a specified load capacitance
of 6-9 pF.
3.5
Serial Output (SO)
This pin is used to transfer data out of the MCP795XX.
During a read cycle, data is shifted out on this pin after
the falling edge of the serial clock.
3.6
Serial Clock (SCK)
X1 also serves as the external clock input when the
MCP795XX is configured to use an external oscillator.
This pin is used to synchronize the communication
between a host and the MCP795XX. Instructions,
addresses or data present on the SI pin are latched on
the rising edge of the clock input, while data on the SO
pin is updated after the falling edge of the clock input.
3.2
3.7
Backup Supply (VBAT)
This is the input for a backup supply to maintain the
RTCC and SRAM registers during the time when VCC
is unavailable.
Power should be applied to VCC before VBAT.
Multifunction Pin (MFP)
The MFP pin is shared with the clock divider and the
alarms. This pin requires an external pull-up to VCC or
VBAT. The pin remains low until such time that the
interrupt flag in the register is cleared by software. This
pin has a maximum sink current of 10 mA.
If the battery backup feature is not being used, the
VBAT pin should be connected to VSS.
3.3
Chip Select (CS)
A low level on this pin selects the device, whereas a
high level deselects the device. A nonvolatile memory
programming cycle which is already initiated or in
progress will be completed, regardless of the CS input
signal. When the device is deselected, SO goes into
the high-impedance state, allowing multiple parts to
share the same SPI bus. After power-up, a high-to-low
transition on CS is required prior to any sequence
being initiated.
3.4
Serial Input (SI)
This pin is used to transfer data into the device. It
receives instructions, addresses and data. Data is
latched on the rising edge of the serial clock.
2012-2022 Microchip Technology Inc. and its subsidiaries
DS20002300D-page 9
MCP7951X/MCP7952X
4.0
SPI BUS OPERATION
The MCP795XX is designed to interface directly with
the Serial Peripheral Interface (SPI) port of many of
today’s popular microcontroller families, including
Microchip’s PIC® microcontrollers. It may also interface
with microcontrollers that do not have a built-in SPI port
by using discrete I/O lines programmed properly in
software to match the SPI protocol.
TABLE 4-1:
The MCP795XX contains an 8-bit instruction register.
The device is accessed via the SI pin, with data being
clocked in on the rising edge of SCK. The CS pin must
be low for the entire operation.
Table 4-1 contains a list of the possible instruction
bytes and format for device operation. All instructions,
addresses and data are transferred MSb first, LSb last.
Data (SI) is sampled on the first rising edge of SCK
after CS goes low.
INSTRUCTION SET SUMMARY
Instruction Name Instruction Format
Description
EEREAD
0000 0011
Read data from EEPROM array beginning at selected address
EEWRITE
0000 0010
Write data to EEPROM array beginning at selected address
EEWRDI
0000 0100
Reset the write enable latch (disable write operations)
EEWREN
0000 0110
Set the write enable latch (enable write operations)
SRREAD
0000 0101
Read STATUS register
SRWRITE
0000 0001
Write STATUS register
READ
0001 0011
Read data from RTCC/SRAM array beginning at selected address
WRITE
0001 0010
Write data to RTCC/SRAM array beginning at selected address
UNLOCK
0001 0100
Unlock the protected EEPROM block for a write operation
IDWRITE
0011 0010
Write data to the protected EEPROM block beginning at selected address
IDREAD
0011 0011
Read data from the protected EEPROM block beginning at the selected
address
CLRRAM
0101 0100
Clear all SRAM data to ‘0’
DS20002300D-page 10
2012-2022 Microchip Technology Inc.and its subsidiaries
MCP7951X/MCP7952X
5.0
FUNCTIONAL DESCRIPTION
The MCP795XX is a highly-integrated Real-Time
Clock/Calendar (RTCC). Using an on-board,
low-power oscillator, the current time is maintained in
hundredths of seconds, seconds, minutes, hours, day
of week, date, month and year. The MCP795XX also
features 64 bytes of general purpose SRAM, either
2 Kbits (MCP7952X) or 1 Kbit (MCP7951X) of
EEPROM and 16 bytes of protected EEPROM. Two
alarm modules allow interrupts to be generated at
specific times with flexible comparison options. Digital
trimming can be used to compensate for inaccuracies
inherent with crystals. Using the backup supply input
and an integrated power switch, the MCP795XX will
automatically switch to backup power when primary
power is unavailable, allowing the current time and the
SRAM contents to be maintained. The timestamp
module captures the time when primary power is lost
and when it is restored.
The RTCC configuration and STATUS registers are
used to access all of the modules featured on the
MCP795XX.
FIGURE 5-1:
5.1
Memory Organization
The MCP795XX features four different blocks of
memory: the RTCC registers, general purpose SRAM,
2 Kbit EEPROM (1 Kbit for the MCP7951X) with
software write-protect and protected EEPROM. The
RTCC registers and SRAM share the same address
space and are accessed through the READ and WRITE
instructions. The EEPROM region is accessed using
the EEREAD and EEWRITE instructions and the
protected EEPROM is accessed using the IDREAD and
IDWRITE instructions. Unused locations are not
accessible. The MCP795XX will not return valid data if
the address is out of range, as shown in the shaded
region of the memory maps in Figure 5-1 and
Figure 5-2.
The RTCC registers are contained in addresses
0x00-0x1F. Table 5-1 shows the detailed RTCC
register map. There are 64 bytes of user-accessible
SRAM, located in the address range 0x20-0x5F. The
SRAM is a separate block from the RTCC registers. All
RTCC registers and SRAM locations are maintained
while operating from backup power.
MEMORY MAP FOR MCP7951X
RTCC Registers/SRAM
EEPROM
0x00
0x00
Time and Date
0x07
0x08
0x0B
0x0C
EEPROM (128 Bytes)
Configuration and Trimming
Alarm 0
0x7F
0x80
0x11
0x12
Alarm 1
0x17
0x18
Unimplemented; mapped back to 0x00-0x7F
Power-Fail/Power-Up Timestamps
0x1F
0x20
SRAM (64 Bytes)
0xFF
Protected EEPROM
0x5F
0x60
0x00
Protected EEPROM (8 Bytes)
EUI-48/EUI-64 Node Address
Unimplemented; device does not respond
0x07
0x08
Lockable User ID (8 Bytes)
0xFF
2012-2022 Microchip Technology Inc. and its subsidiaries
0x0F
DS20002300D-page 11
MCP7951X/MCP7952X
FIGURE 5-2:
MEMORY MAP FOR MCP7952X
RTCC Registers/SRAM
EEPROM
0x00
0x00
Time and Date
0x07
0x08
0x0B
0x0C
Configuration and Trimming
Alarm 0
0x11
0x12
EEPROM (256 Bytes)
Alarm 1
0x17
0x18
Power-Fail/Power-Up Timestamps
0x1F
0x20
SRAM (64 Bytes)
0xFF
Protected EEPROM
0x5F
0x60
0x00
Protected EEPROM (8 Bytes)
EUI-48/EUI-64 Node Address
Unimplemented; device does not respond
0x07
0x08
Lockable User ID (8 Bytes)
0xFF
DS20002300D-page 12
0x0F
2012-2022 Microchip Technology Inc.and its subsidiaries
MCP7951X/MCP7952X
TABLE 5-1:
DETAILED RTCC REGISTER MAP
Addr. Register Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Section 5.3 “Timekeeping”
00h
RTCHSEC
HSECTEN3 HSECTEN2
01h
RTCSEC
ST
SECTEN2
HSECTEN1
SECTEN1
HSECTEN0 HSECONE3 HSECONE2 HSECONE1 HSECONE0
SECTEN0
SECONE3
SECONE2
SECONE1
SECONE0
02h
RTCMIN
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
03h
RTCHOUR
TRIMSIGN
12/24
AM/PM
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
04h
RTCWKDAY
—
—
OSCRUN
PWRFAIL
VBATEN
WKDAY2
WKDAY1
WKDAY0
05h
RTCDATE
—
—
DATETEN1
DATETEN0
DATEONE3
DATEONE2
DATEONE1
DATEONE0
MTHONE0
06h
RTCMTH
—
—
LPYR
MTHTEN0
MTHONE3
MTHONE2
MTHONE1
07h
RTCYEAR
YRTEN3
YRTEN2
YRTEN1
YRTEN0
YRONE3
YRONE2
YRONE1
YRONE0
08h
CONTROL
—
SQWEN
ALM1EN
ALM0EN
EXTOSC
CRSTRIM
SQWFS1
SQWFS0
09h
OSCTRIM
TRIMVAL7
TRIMVAL6
TRIMVAL5
TRIMVAL4
TRIMVAL3
TRIMVAL2
TRIMVAL1
TRIMVAL0
0Ch
ALM0SEC
—
SECTEN2
SECTEN1
SECTEN0
SECONE3
SECONE2
SECONE1
SECONE0
0Dh
ALM0MIN
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
0Eh
ALM0HOUR
—
12/24(2)
AM/PM
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
Section 5.4 “Alarms”
0Fh
ALM0WKDAY
ALM0PIN
ALM0MSK2
ALM0MSK1
ALM0MSK0
ALM0IF
WKDAY2
WKDAY1
WKDAY0
10h
ALM0DATE
—
—
DATETEN1
DATETEN0
DATEONE3
DATEONE2
DATEONE1
DATEONE0
11h
ALM0MTH
—
—
—
MTHTEN0
MTHONE3
MTHONE2
MTHONE1
MTHONE0
Section 5.4 “Alarms”
12h
ALM1HSEC
13h
ALM1SEC
—
SECTEN2
SECTEN1
SECTEN0
SECONE3
SECONE2
SECONE1
SECONE0
14h
ALM1MIN
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
15h
ALM1HOUR
—
12/24(2)
AM/PM
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
ALM1PIN
ALM1MSK2
ALM1MSK1
ALM1MSK0
ALM1IF
WKDAY2
WKDAY1
WKDAY0
—
—
DATETEN1
DATETEN0
DATEONE3
DATEONE2
DATEONE1
DATEONE0
16h
ALM1WKDAY
17h
ALM1DATE
HSECTEN3 HSECTEN2
HSECTEN1
HSECTEN0 HSECONE3 HSECONE2 HSECONE1 HSECONE0
Section 5.7.1 “Power-Fail Timestamp”
Power-Down Timestamp
18h
PWRDNMIN
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
19h
PWRDNHOUR
—
12/24
AM/PM
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
1Ah
PWRDNDATE
—
—
DATETEN1
DATETEN0
DATEONE3
DATEONE2
DATEONE1
DATEONE0
1Bh
PWRDNMTH
WKDAY2
WKDAY1
WKDAY0
MTHTEN0
MTHONE3
MTHONE2
MTHONE1
MTHONE0
Power-Up Timestamp
1Ch
PWRUPMIN
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
1Dh
PWRUPHOUR
—
12/24
AM/PM
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
1Eh
PWRUPDATE
—
—
DATETEN1
DATETEN0
DATEONE3
DATEONE2
DATEONE1
DATEONE0
1Fh
PWRUPMTH
WKDAY2
WKDAY1
WKDAY0
MTHTEN0
MTHONE3
MTHONE2
MTHONE1
MTHONE0
Note 1:
2:
Grey areas are unimplemented.
The 12/24 bits in the ALMxHOUR registers are read-only and reflect the value of the 12/24 bit in the RTCHOUR
register.
2012-2022 Microchip Technology Inc. and its subsidiaries
DS20002300D-page 13
MCP7951X/MCP7952X
5.2
Oscillator Configurations
EQUATION 5-1:
The MCP795XX can be operated in two different
oscillator configurations: using an external crystal or
using an external clock input.
5.2.1
By using external load capacitors, the MCP795XX
allows for a wide selection of crystals. Suitable crystals
have a load capacitance (CL) of 6-9 pF. Crystals with a
load capacitance of 12.5 pF are not recommended.
Figure 5-3 shows the pin connections when using an
external crystal.
FIGURE 5-3:
CRYSTAL OPERATION
MCP795XX
X1
CX1
To Internal
Logic
Quartz
Crystal
ST
X2
CX 2
Note 1: The ST bit must be set to enable the
crystal oscillator circuit.
2: Always verify oscillator performance over
the voltage and temperature range that is
expected for the application.
5.2.1.1
Choosing Load Capacitors
CL is the effective load capacitance as seen by the
crystal and includes the physical load capacitors, pin
capacitance and stray board capacitance. Equation 5-1
can be used to calculate CL.
CX1 and CX2 are the external load capacitors. They
must be chosen to match the selected crystal’s
specified load capacitance.
Note:
C X1 C X2
- + C STRAY
C L = ------------------------C X1 + C X2
EXTERNAL CRYSTAL
The crystal oscillator circuit on the MCP795XX is
designed to operate with a standard 32.768 kHz tuning
fork crystal and matching external load capacitors.
LOAD CAPACITANCE
CALCULATION
Where:
CL
=
Effective load capacitance
CX1
=
Capacitor value on X1 + COSC
CX2
=
Capacitor value on X2 + COSC
CSTRAY =
5.2.1.2
PCB stray capacitance
Layout Considerations
The oscillator circuit should be placed on the same
side of the board as the device. Place the oscillator
circuit close to the respective oscillator pins. The load
capacitors should be placed next to the oscillator
itself, on the same side of the board.
Use a grounded copper pour around the oscillator
circuit to isolate it from surrounding circuits. The
grounded copper pour should be routed directly to VSS.
Do not run any signal traces or power traces inside the
ground pour. Also, if using a two-sided board, avoid any
traces on the other side of the board where the crystal
is placed.
Layout suggestions are shown in Figure 5-4. In-line
packages may be handled with a single-sided layout
that completely encompasses the oscillator pins. With
fine-pitch packages, it is not always possible to
completely surround the pins and components. A
suitable solution is to tie the broken guard sections to a
mirrored ground layer. In all cases, the guard trace(s)
must be returned to ground.
For additional information and design guidance on
oscillator circuits, refer to these Microchip Application
Notes, available at the corporate website
(www.microchip.com):
• AN1365 – “Recommended Usage of Microchip
Serial RTCC Devices” (DS00001365)
• AN1519 – “Recommended Crystals for Microchip
Stand-Alone Real-Time Clock Calendar Devices”
(DS00001519)
If the load capacitance is not correctly
matched to the chosen crystal’s specified
value, the crystal may give a frequency
outside of the crystal manufacturer’s
specifications.
DS20002300D-page 14
2012-2022 Microchip Technology Inc.and its subsidiaries
MCP7951X/MCP7952X
FIGURE 5-4:
SUGGESTED PLACEMENT OF THE OSCILLATOR CIRCUIT
Single-Sided and In-line Layouts:
Copper Pour
(tied to ground)
Fine-Pitch (Dual-Sided) Layouts:
Oscillator
Crystal
Top Layer Copper Pour
(tied to ground)
Bottom Layer
Copper Pour
(tied to ground)
X1
X1
CX1
X2
GND
CX2
CX1
Oscillator
Crystal
GND
CX2
`
X2
DEVICE PINS
DEVICE PINS
5.2.2
EXTERNAL CLOCK INPUT
A 32.768 kHz external clock source can be connected
to the X1 pin (Figure 5-5). When using this
configuration, the X2 pin should be left floating.
Note:
The EXTOSC bit must be set to enable an
external clock source.
FIGURE 5-5:
Clock from
Ext. Source
FIGURE 5-6:
EXTERNAL CLOCK INPUT
OPERATION
X1
5.2.3
OSCILLATOR FAILURE STATUS
The MCP795XX features an oscillator failure flag,
OSCRUN, that indicates whether or not the oscillator is
running. The OSCRUN bit is automatically set after 32
oscillator cycles are detected. If no oscillator cycles are
detected for more than TOSF, then the OSCRUN bit is
automatically cleared (Figure 5-6). This can occur if the
oscillator is stopped by clearing the ST bit or due to
oscillator failure.
MCP795XX
OSCILLATOR FAILURE STATUS TIMING DIAGRAM
X1
32 Clock Cycles
< TOSF
TOSF
OSCRUN Bit
2012-2022 Microchip Technology Inc. and its subsidiaries
DS20002300D-page 15
MCP7951X/MCP7952X
TABLE 5-2:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH OSCILLATOR
CONFIGURATION
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
RTCSEC
ST
SECTEN2
SECTEN1
SECTEN0
SECONE3
SECONE2
RTCWKDAY
—
—
OSCRUN
PWRFAIL
VBATEN
WKDAY2
WKDAY1
WKDAY0
20
CONTROL
—
SQWEN
ALM1EN
ALM0EN
EXTOSC
CRSTRIM
SQWFS1
SQWFS0
29
Legend:
5.3
Bit 1
Register
on Page
Bit 7
Bit 0
SECONE1 SECONE0
18
— = unimplemented location, read as ‘0’. Shaded cells are not used by oscillator configuration.
Timekeeping
The MCP795XX maintains the current time and date
using an external 32.768 kHz crystal or clock source.
Separate registers are used for tracking hundredths of
seconds, seconds, minutes, hours, day of week, date,
month and year. The MCP795XX automatically adjusts
for months with less than 31 days and compensates for
leap years from 2001 to 2399. The year is stored as a
two-digit value.
Both 12-hour and 24-hour time formats are supported
and are selected using the 12/24 bit.
The day of week value counts from 1 to 7, increments
at midnight and the representation is user-defined (i.e.,
the MCP795XX does not require 1 to equal Sunday,
etc.).
All time and date values are stored in the registers as
binary-coded decimal (BCD) values. The MCP795XX
will continue to maintain the time and date while
operating off the backup supply.
5.3.1
DIGIT CARRY RULES
The following list explains which timer values cause a
digit carry when there is a rollover:
• Time of day: from 11:59:59.99 PM to 12:00:00.00
AM (12-hour mode) or 23:59:59.99 to 00:00:00.00
(24-hour mode), with a carry to the Date and
Weekday fields
• Date: carries to the Month field according to
Table 5-3
• Weekday: from 7 to 1 with no carry
• Month: from 12/31 to 01/01 with a carry to the
Year field
• Year: from 99 to 00 with no carry
TABLE 5-3:
DATE TO MONTH ROLLOVER
SCHEDULE
Month
Name
Maximum Date
01
January
31
When reading from the timekeeping registers, the
registers are buffered to prevent errors due to rollover
of counters. The following events cause the buffers to
be updated:
02
February
28 or 29(1)
03
March
31
04
April
30
• When a read is initiated from the RTCC registers
(addresses 0x00 to 0x1F)
• During an RTCC register read operation, when
the register address rolls over from 0x1F to 0x00
05
May
31
06
June
30
07
July
31
08
August
31
The timekeeping registers should be read in a single
operation to utilize the on-board buffers and avoid
rollover issues.
09
September
30
10
October
31
11
November
30
12
December
31
Note 1: Loading invalid values into the time and
date registers will result in undefined
operation.
Note 1:
29 during leap years, otherwise 28.
2: To avoid rollover issues when loading
new time and date values, the
oscillator/clock input should be disabled
by clearing the ST bit for External Crystal
mode and the EXTOSC bit for External
Clock Input mode. After waiting for the
OSCRUN bit to clear, the new values can
be loaded and the ST or EXTOSC bit can
then be re-enabled.
DS20002300D-page 16
2012-2022 Microchip Technology Inc.and its subsidiaries
MCP7951X/MCP7952X
5.3.2
GENERATING HUNDREDTH OF
SECONDS
A special algorithm is required to accurately generate
hundredth of seconds. The circuitry utilizes the
4.096 kHz clock signal and counts 41 clock pulses
each for 24 increments of the hundredth of seconds
count. The circuitry then counts 40 clock pulses for the
next increment of the hundredth of second count. This
results in every 25 hundredth of seconds increments
equaling exactly 250 ms. Long term, the hundredth of
seconds frequency will average the desired 100 Hz,
while jitter is minimized short term.
EQUATION 5-2:
HUNDREDTH OF
SECONDS GENERATION
--------------------------------------------------------------------------------------------------------------41 clocks 24 counts + 40 clocks 1 count = 250 ms
4,096 Hz
2012-2022 Microchip Technology Inc. and its subsidiaries
DS20002300D-page 17
MCP7951X/MCP7952X
REGISTER 5-1:
RTCHSEC: TIMEKEEPING HUNDREDTH OF SECONDS VALUE REGISTER
(ADDRESS 0x00)
R/W-0
R/W-0
HSECTEN3
HSECTEN2
R/W-0
R/W-0
R/W-0
HSECTEN1 HSECTEN0 HSECONE3
R/W-0
HSECONE2
R/W-0
R/W-0
HSECONE1 HSECONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
bit 7-4
HSECTEN: Binary-Coded Decimal Value of Hundredth of Second’s Tens Digit
Contains a value from 0 to 9
bit 3-0
HSECONE: Binary-Coded Decimal Value of Hundredth of Second’s Ones Digit
Contains a value from 0 to 9
REGISTER 5-2:
RTCSEC: TIMEKEEPING SECONDS VALUE REGISTER (ADDRESS 0x01)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
ST
SECTEN2
SECTEN1
SECTEN0
SECONE3
SECONE2
SECONE1
SECONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
bit 7
ST: Start Oscillator bit
1 = Oscillator enabled
0 = Oscillator disabled
bit 6-4
SECTEN: Binary-Coded Decimal Value of Second’s Tens Digit
Contains a value from 0 to 5
bit 3-0
SECONE: Binary-Coded Decimal Value of Second’s Ones Digit
Contains a value from 0 to 9
REGISTER 5-3:
RTCMIN: TIMEKEEPING MINUTES VALUE REGISTER (ADDRESS 0x02)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
bit 7
Unimplemented: Read as ‘0’
bit 6-4
MINTEN: Binary-Coded Decimal Value of Minute’s Tens Digit
Contains a value from 0 to 5
bit 3-0
MINONE: Binary-Coded Decimal Value of Minute’s Ones Digit
Contains a value from 0 to 9
DS20002300D-page 18
x = Bit is unknown
2012-2022 Microchip Technology Inc.and its subsidiaries
MCP7951X/MCP7952X
REGISTER 5-4:
RTCHOUR: TIMEKEEPING HOURS VALUE REGISTER (ADDRESS 0x03)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TRIMSIGN
12/24
AM/PM
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
If 12/24 = 1 (12-hour format):
bit 7
TRIMSIGN: Trim Sign bit
1 = Add clocks to correct for slow time
0 = Subtract clocks to correct for fast time
bit 6
12/24: 12 or 24 Hour Time Format bit
1 = 12-hour format
0 = 24-hour format
bit 5
AM/PM: AM/PM Indicator bit
1 = PM
0 = AM
bit 4
HRTEN0: Binary-Coded Decimal Value of Hour’s Tens Digit
Contains a value from 0 to 1
bit 3-0
HRONE: Binary-Coded Decimal Value of Hour’s Ones Digit
Contains a value from 0 to 9
If 12/24 = 0 (24-hour format):
bit 7
TRIMSIGN: Trim Sign bit
1 = Add clocks to correct for slow time
0 = Subtract clocks to correct for fast time
bit 6
12/24: 12 or 24 Hour Time Format bit
1 = 12-hour format
0 = 24-hour format
bit 5-4
HRTEN: Binary-Coded Decimal Value of Hour’s Tens Digit
Contains a value from 0 to 2.
bit 3-0
HRONE: Binary-Coded Decimal Value of Hour’s Ones Digit
Contains a value from 0 to 9
2012-2022 Microchip Technology Inc. and its subsidiaries
DS20002300D-page 19
MCP7951X/MCP7952X
REGISTER 5-5:
RTCWKDAY: TIMEKEEPING WEEKDAY VALUE REGISTER (ADDRESS 0x04)
U-0
U-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
—
—
OSCRUN
PWRFAIL
VBATEN
WKDAY2
WKDAY1
WKDAY0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘0’
bit 5
OSCRUN: Oscillator Status bit
1 = Oscillator is enabled and running
0 = Oscillator has stopped or has been disabled
bit 4
PWRFAIL: Power Failure Status bit(1,2)
1 = Primary power was lost and the power-fail timestamp registers have been loaded (must be cleared
in software). Clearing this bit resets the power-fail timestamp registers to ‘0’.
0 = Primary power has not been lost
bit 3
VBATEN: External Battery Backup Supply (VBAT) Enable bit
1 = VBAT input is enabled
0 = VBAT input is disabled
bit 2-0
WKDAY: Binary-Coded Decimal Value of Day of Week
Contains a value from 1 to 7. The representation is user-defined.
Note 1:
2:
The PWRFAIL bit must be cleared to log new timestamp data. This is to ensure previous timestamp data is
not lost.
The PWRFAIL bit can be cleared by writing a ‘0’. Once cleared, the PWRFAIL bit cannot be written to a ‘1’
in software.
REGISTER 5-6:
RTCDATE: TIMEKEEPING DATE VALUE REGISTER (ADDRESS 0x05)
U-0
U-0
R/W-0
—
—
DATETEN1
R/W-0
R/W-0
DATETEN0 DATEONE3
R/W-0
R/W-0
R/W-1
DATEONE2
DATEONE1
DATEONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
DATETEN: Binary-Coded Decimal Value of Date’s Tens Digit
Contains a value from 0 to 3
bit 3-0
DATEONE: Binary-Coded Decimal Value of Date’s Ones Digit
Contains a value from 0 to 9
DS20002300D-page 20
x = Bit is unknown
2012-2022 Microchip Technology Inc.and its subsidiaries
MCP7951X/MCP7952X
REGISTER 5-7:
RTCMTH: TIMEKEEPING MONTH VALUE REGISTER (ADDRESS 0x06)
U-0
U-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
—
—
LPYR
MTHTEN0
MTHONE3
MTHONE2
MTHONE1
MTHONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘0’
bit 5
LPYR: Leap Year bit
1 = Year is a leap year
0 = Year is not a leap year
bit 4
MTHTEN0: Binary-Coded Decimal Value of Month’s Tens Digit
Contains a value of 0 or 1
bit 3-0
MTHONE: Binary-Coded Decimal Value of Month’s Ones Digit
Contains a value from 0 to 9
REGISTER 5-8:
RTCYEAR: TIMEKEEPING YEAR VALUE REGISTER (ADDRESS 0x07)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
YRTEN3
YRTEN2
YRTEN1
YRTEN0
YRONE3
YRONE2
YRONE1
YRONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
bit 7-4
YRTEN: Binary-Coded Decimal Value of Year’s Tens Digit
Contains a value from 0 to 9
bit 3-0
YRONE: Binary-Coded Decimal Value of Year’s Ones Digit
Contains a value from 0 to 9
TABLE 5-4:
Name
RTCHSEC
RTCSEC
SUMMARY OF REGISTERS ASSOCIATED WITH TIMEKEEPING
Bit 7
Bit 6
Bit 5
HSECTEN3 HSECTEN2 HSECTEN1
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
HSECTEN0 HSECONE3 HSECONE2 HSECONE1 HSECONE0
Register
on Page
18
ST
SECTEN2
SECTEN1
SECTEN0
SECONE3
SECONE2
SECONE1
SECONE0
18
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
18
TRIMSIGN
12/24
AM/PM
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
19
RTCWKDAY
—
—
OSCRUN
PWRFAIL
VBATEN
WKDAY2
WKDAY1
WKDAY0
20
RTCDATE
—
—
DATETEN1
DATETEN0
DATEONE3
DATEONE2
DATEONE1
DATEONE0
20
RTCMTH
—
—
LPYR
MTHTEN0
MTHONE3
MTHONE2
MTHONE1
MTHONE0
21
YRTEN3
YRTEN2
YRTEN1
YRTEN0
YRONE3
YRONE2
YRONE1
YRONE0
21
RTCMIN
RTCHOUR
RTCYEAR
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used in timekeeping.
2012-2022 Microchip Technology Inc. and its subsidiaries
DS20002300D-page 21
MCP7951X/MCP7952X
5.4
Alarms
TABLE 5-6:
ALARM 1 MASKS
The MCP795XX features two independent alarms.
Each alarm can be used to either generate an interrupt
at a specific time in the future, or to generate a periodic
interrupt every second (Alarm 1 only), minute, hour,
day, day of week, or month.
ALM1MSK
Alarm 1 Asserts on Match of
000
Seconds
001
Minutes
010
Hours
There is a separate interrupt flag, ALMxIF, for each
alarm. The interrupt flags are set by hardware when the
chosen alarm mask condition matches (Table 5-5 and
Table 5-6). The interrupt flags must be cleared in
software.
011
Day of Week
100
Date
101
Hundredth of Seconds
110
Reserved
111
Seconds, Minutes, Hours, Day of
Week and Date
For alarm outputs to function, the Square Wave Output
function must be disabled. Each of the two independent
alarm signals are assigned to the MFP pin where either
can pull it low. The pin will stay low until both the alarm
flags are cleared. The alarm output to the MFP pin is
available while operating from the backup supply.
All time and date values are stored in the registers as
binary-coded decimal (BCD) values.
Note:
Note 1: The alarm interrupt flags must be cleared
by the user.
2: Loading invalid values into the alarm
registers will result in undefined
operation.
Throughout this section, references to the
register and bit names for the alarm
modules are referred to generically by the
use of ‘x’ in place of the specific module
number. Thus, “ALMxSEC” might refer to
the seconds register for Alarm 0 or
Alarm 1.
TABLE 5-5:
ALARM 0 MASKS
ALM0MSK
Alarm 0 Asserts on Match of
000
Seconds
001
Minutes
010
Hours
011
Day of Week
100
Date
101
Reserved
110
Reserved
111
Seconds, Minutes, Hours, Day of
Week, Date, and Month
DS20002300D-page 22
2012-2022 Microchip Technology Inc.and its subsidiaries
MCP7951X/MCP7952X
FIGURE 5-7:
ALARM BLOCK DIAGRAM
Timekeeping
Registers
Alarm 1
Registers
RTCHSEC
ALM1HSEC
ALM0SEC
RTCSEC
ALM1SEC
ALM0MIN
RTCMIN
ALM1MIN
ALM0HOUR
RTCHOUR
ALM1HOUR
ALM0WKDAY
RTCWKDAY
ALM1WKDAY
ALM0DATE
RTCDATE
ALM1DATE
ALM0MTH
RTCMTH
Alarm 0
Registers
Alarm 0 Mask
Comparator
Comparator
Set
ALM0IF
ALM0MSK
5.4.1
Alarm 1 Mask
Set
ALM1IF
MFP
Output Logic
MFP
ALM1MSK
CONFIGURING THE ALARM
In order to configure the alarm modules, the following
steps need to be performed:
1.
2.
3.
4.
5.
Load the timekeeping registers and enable the
oscillator.
Configure the ALMxMSK bits to select the
desired alarm mask.
Ensure the ALMxIF flag is cleared.
Based on the selected alarm mask, load the
alarm match value into the appropriate
register(s).
Enable the alarm module by setting the
ALMxEN bit.
2012-2022 Microchip Technology Inc. and its subsidiaries
DS20002300D-page 23
MCP7951X/MCP7952X
REGISTER 5-9:
ALM1HSEC: ALARM 1 HUNDREDTHS OF SECONDS VALUE REGISTER
(ADDRESS 0x12)
R/W-0
R/W-0
HSECTEN3
HSECTEN2
R/W-0
R/W-0
R/W-0
HSECTEN1 HSECTEN0 HSECONE3
R/W-0
HSECONE2
R/W-0
R/W-0
HSECONE1 HSECONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
bit 7-4
HSECTEN: Binary-Coded Decimal Value of Hundredth of Second’s Tens Digit
Contains a value from 0 to 9
bit 3-0
HSECONE: Binary-Coded Decimal Value of Hundredth of Second’s Ones Digit
Contains a value from 0 to 9
Note 1:
Hundredth of seconds matching is only available on Alarm 1.
REGISTER 5-10:
ALMxSEC: ALARM 0/1 SECONDS VALUE REGISTER (ADDRESSES 0x0C/0x13)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
SECTEN2
SECTEN1
SECTEN0
SECONE3
SECONE2
SECONE1
SECONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
bit 7
Unimplemented: Read as ‘0’
bit 6-4
SECTEN: Binary-Coded Decimal Value of Second’s Tens Digit
Contains a value from 0 to 5
bit 3-0
SECONE: Binary-Coded Decimal Value of Second’s Ones Digit
Contains a value from 0 to 9
DS20002300D-page 24
x = Bit is unknown
2012-2022 Microchip Technology Inc.and its subsidiaries
MCP7951X/MCP7952X
REGISTER 5-11:
ALMxMIN: ALARM 0/1 MINUTES VALUE REGISTER (ADDRESSES 0x0D/0x14)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6-4
MINTEN: Binary-Coded Decimal Value of Minute’s Tens Digit
Contains a value from 0 to 5
bit 3-0
MINONE: Binary-Coded Decimal Value of Minute’s Ones Digit
Contains a value from 0 to 9
REGISTER 5-12:
ALMxHOUR: ALARM 0/1 HOURS VALUE REGISTER (ADDRESSES 0x0E/0x15)
U-0
R-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
12/24
AM/PM
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
If 12/24 = 1 (12-hour format):
bit 7
Unimplemented: Read as ‘0’
bit 6
12/24: 12 or 24 Hour Time Format bit(1)
1 = 12-hour format
0 = 24-hour format
bit 5
AM/PM: AM/PM Indicator bit
1 = PM
0 = AM
bit 4
HRTEN0: Binary-Coded Decimal Value of Hour’s Tens Digit
Contains a value from 0 to 1
bit 3-0
HRONE: Binary-Coded Decimal Value of Hour’s Ones Digit
Contains a value from 0 to 9
If 12/24 = 0 (24-hour format):
bit 7
Unimplemented: Read as ‘0’
bit 6
12/24: 12 or 24 Hour Time Format bit(1)
1 = 12-hour format
0 = 24-hour format
bit 5-4
HRTEN: Binary-Coded Decimal Value of Hour’s Tens Digit
Contains a value from 0 to 2.
bit 3-0
HRONE: Binary-Coded Decimal Value of Hour’s Ones Digit
Contains a value from 0 to 9
Note 1:
This bit is read-only and reflects the value of the 12/24 bit in the RTCHOUR register.
2012-2022 Microchip Technology Inc. and its subsidiaries
DS20002300D-page 25
MCP7951X/MCP7952X
REGISTER 5-13:
ALMxWKDAY: ALARM 0/1 WEEKDAY VALUE REGISTER
(ADDRESSES 0x0F/0x16)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
—
ALMxMSK2
ALMxMSK1
ALMxMSK0
ALMxIF
WKDAY2
WKDAY1
WKDAY0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6-4
ALMxMSK: Alarm Mask bits
000 = Seconds match
001 = Minutes match
010 = Hours match (logic takes into account 12-/24-hour operation)
011 = Day of week match
100 = Date match
101 = Hundredth of Seconds(1)
110 = Reserved; do not use
111 = Seconds, Minutes, Hour, Day of Week, Date and Month(2)
bit 3
ALMxIF: Alarm Interrupt Flag bit(3)
1 = Alarm match occurred (must be cleared in software)
0 = Alarm match did not occur
bit 2-0
WKDAY: Binary-Coded Decimal Value of Day bits
Contains a value from 1 to 7. The representation is user-defined.
Note 1:
2:
3:
Hundredth of seconds matching is available on Alarm 1 only. This setting is reserved on Alarm 0.
Month matching is available on Alarm 0 only.
The ALMxIF bit can be cleared by writing a ‘0’. Once cleared, the ALMxIF bit cannot be written to a ‘1’ in
software.
REGISTER 5-14:
ALMxDATE: ALARM 0/1 DATE VALUE REGISTER (ADDRESSES 0x10/0x17)
U-0
U-0
R/W-0
—
—
DATETEN1
R/W-0
R/W-0
DATETEN0 DATEONE3
R/W-0
R/W-0
R/W-1
DATEONE2
DATEONE1
DATEONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
DATETEN: Binary-Coded Decimal Value of Date’s Tens Digit
Contains a value from 0 to 3
bit 3-0
DATEONE: Binary-Coded Decimal Value of Date’s Ones Digit
Contains a value from 0 to 9
DS20002300D-page 26
x = Bit is unknown
2012-2022 Microchip Technology Inc.and its subsidiaries
MCP7951X/MCP7952X
REGISTER 5-15:
ALM0MTH: ALARM 0 MONTH VALUE REGISTER (ADDRESS 0x11)
U-0
U-0
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-1
—
—
—
MTHTEN0
MTHONE3
MTHONE2
MTHONE1
MTHONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
bit 7-5
Unimplemented: Read as ‘0’
bit 4
MTHTEN0: Binary-Coded Decimal Value of Month’s Tens Digit
Contains a value of 0 or 1
bit 3-0
MTHONE: Binary-Coded Decimal Value of Month’s Ones Digit
Contains a value from 0 to 9
Note 1:
Month matching is only available on Alarm 0.
TABLE 5-7:
SUMMARY OF REGISTERS ASSOCIATED WITH ALARMS
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
ALM0SEC
—
SECTEN2
SECTEN1
SECTEN0
SECONE3
SECONE2
SECONE1
SECONE0
24
ALM0MIN
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
25
ALM0HOUR
—
12/24
AM/PM
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
25
Name
ALM0PIN
ALM0MSK2
ALM0MSK1
ALM0MSK0
ALM0IF
WKDAY2
WKDAY1
WKDAY0
26
ALM0DATE
—
—
DATETEN1
DATETEN0
DATEONE3
DATEONE2
DATEONE1
DATEONE0
26
ALM0MTH
—
—
—
MTHTEN0
MTHONE3
MTHONE2
MTHONE1
MTHONE0
27
HSECTEN3
HSECTEN2
HSECTEN1
HSECTEN0
ALM1SEC
—
SECTEN2
SECTEN1
SECTEN0
SECONE3
SECONE2
SECONE1
SECONE0
24
ALM1MIN
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
25
ALM1HOUR
—
12/24
AM/PM
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
25
ALM1PIN
ALM1MSK2
ALM1MSK1
ALM1MSK0
ALM1IF
WKDAY2
WKDAY1
WKDAY0
26
ALM1DATE
—
—
DATETEN1
DATETEN0
DATEONE3
DATEONE2
DATEONE1
DATEONE0
26
CONTROL
—
SQWEN
ALM1EN
ALM0EN
EXTOSC
CRSTRIM
SQWFS1
SQWFS0
29
ALM0WKDAY
ALM1HSEC
ALM1WKDAY
Legend:
HSECONE3 HSECONE2 HSECONE1 HSECONE0
24
— = unimplemented location, read as ‘0’. Shaded cells are not used by alarms.
2012-2022 Microchip Technology Inc. and its subsidiaries
DS20002300D-page 27
MCP7951X/MCP7952X
5.5
MFP Output
The MCP795XX features Square Wave Clock Output
and Alarm Interrupt Output modes through the MFP
pin. If the SQWEN bit is set, then MFP operates in
Square Wave Clock Output mode.
The alarm outputs will remain active on the MFP pin
while operating from the backup power supply. The
Square Wave Clock Output is disabled while operating
from the backup power supply.
FIGURE 5-8:
CLKOUT OUTPUT BLOCK DIAGRAM
MCP795XX
SQWFS
Oscillator
X2
ST
Postscaler
Digital
Trim
EXTOSC
8.192 kHz
4.096 kHz
1 Hz
11
10
01
00
MUX
32.768 kHz
X1
0
1
1
CRSTRIM
Alarm Flags
0
MFP
SQWEN
5.5.1
SQUARE WAVE OUTPUT MODE
The MCP795XX can be configured to generate a
square wave clock signal on MFP. The input clock
frequency, FOSC, is divided according to the
SQWFS bits as shown in Table 5-8.
The square wave output is not available when
operating from the backup power supply, but the
square wave settings can be retained by the backup
power supply so that the square wave output can
continue when VCC is restored.
Note:
All of the clock output rates are affected by
digital trimming except for the 1:1
postscaler value (SQWFS = 11).
TABLE 5-8:
CLOCK OUTPUT RATES
SQWFS
Postscaler
Nominal
Frequency
00
1:32,768
1 Hz
01
1:8
4.096 kHz
10
1:4
8.192 kHz
1:1
32.768 kHz
11
Note 1:
Nominal frequency assumes FOSC is
32.768 kHz.
DS20002300D-page 28
2012-2022 Microchip Technology Inc.and its subsidiaries
MCP7951X/MCP7952X
REGISTER 5-16:
CONTROL: RTCC CONTROL REGISTER (ADDRESS 0x08)
U-x
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
SQWEN
ALM1EN
ALM0EN
EXTOSC
CRSTRIM
SQWFS1
SQWFS0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
bit 7
Unimplemented: Read as ‘1’
bit 6
SQWEN: Square Wave Output Enable bit
1 = Enable Square Wave Clock Output mode
0 = Disable Square Wave Clock Output mode
bit 5
ALM1EN: Alarm 1 Module Enable bit
1 = Alarm 1 enabled
0 = Alarm 1 disabled
bit 4
ALM0EN: Alarm 0 Module Enable bit
1 = Alarm 0 enabled
0 = Alarm 0 disabled
bit 3
EXTOSC: External Oscillator Input bit
1 = Enable X1 pin to be driven by external 32.768 kHz source
0 = Disable external 32.768 kHz input
bit 2
CRSTRIM: Coarse Trim Mode Enable bit
Coarse Trim mode results in the MCP795XX applying digital trimming every second.
1 = Enable Coarse Trim mode. If SQWEN = 1, CLKOUT will output trimmed 1 Hz(1) nominal clock
signal.
0 = Disable Coarse Trim mode
See Section 5.6 “Digital Trimming” for details
bit 1-0
SQWFS: Square Wave Clock Output Frequency Select bits
If SQWEN = 1 and CRSTRIM = 0:
Selects frequency of clock output on CLKOUT
00 = 1 Hz(1)
01 = 4.096 kHz(1)
10 = 8.192 kHz(1)
11 = 32.768 kHz
If SQWEN = 0 or CRSTRIM = 1:
Unused
Note 1:
The 8.192 kHz, 4.096 kHz, and 1 Hz square wave clock output frequencies are affected by digital
trimming.
TABLE 5-9:
Name
CONTROL
Legend:
SUMMARY OF REGISTERS ASSOCIATED WITH CLOCK OUTPUT CONFIGURATION
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
—
SQWEN
ALM1EN
ALM0EN
EXTOSC
CRSTRIM
SQWFS1
SQWFS0
29
— = unimplemented location, read as ‘0’. Shaded cells are not used in clock output configuration.
2012-2022 Microchip Technology Inc. and its subsidiaries
DS20002300D-page 29
MCP7951X/MCP7952X
5.6
Digital Trimming
The MCP795XX features digital trimming to correct for
inaccuracies of the external crystal or clock source, up
to roughly ±259 ppm when CRSTRIM = 0. In addition
to compensating for intrinsic inaccuracies in the clock,
this feature can also be used to correct for error due to
temperature variation. This can enable the user to
achieve high levels of accuracy across a wide
temperature operating range.
Digital trimming consists of the MCP795XX periodically
adding or subtracting clock cycles, resulting in small
adjustments in the internal timing.
REGISTER 5-17:
The adjustment occurs once per minute when
CRSTRIM = 0. The TRIMSIGN bit specifies whether to
add cycles or to subtract them. The TRIMVAL bits
are used to specify by how many clock cycles to adjust.
Each step in the TRIMVAL value equates to
adding or subtracting two clock pulses to or from the
32.768 kHz clock signal. This results in a correction of
roughly 1.017 ppm per step when CRSTRIM = 0.
Setting TRIMVAL to 0x00 disables digital
trimming.
Digital trimming also occurs while operating off the
backup supply.
OSCTRIM: OSCILLATOR DIGITAL TRIM REGISTER (ADDRESS 0x09)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
TRIMVAL7
TRIMVAL6
TRIMVAL5
TRIMVAL4
TRIMVAL3
TRIMVAL2
TRIMVAL1
TRIMVAL0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
bit 7-0
x = Bit is unknown
TRIMVAL: Oscillator Trim Value bits
When CRSTRIM = 0:
11111111 = Add or subtract 510 clock cycles every minute
11111110 = Add or subtract 508 clock cycles every minute
•
•
•
00000010 = Add or subtract 4 clock cycles every minute
00000001 = Add or subtract 2 clock cycles every minute
00000000 = Disable digital trimming
When CRSTRIM = 1:
11111111 = Add or subtract 510 clock cycles every second
11111110 = Add or subtract 508 clock cycles every second
•
•
•
00000010 = Add or subtract 4 clock cycles every second
00000001 = Add or subtract 2 clock cycles every second
00000000 = Disable digital trimming
DS20002300D-page 30
2012-2022 Microchip Technology Inc.and its subsidiaries
MCP7951X/MCP7952X
5.6.1
CALIBRATION
In order to perform calibration, the number of error
clock pulses per minute must be found and the
corresponding trim value must be loaded into
TRIMVAL.
There are two methods for determining the trim value.
The first method involves measuring an output
frequency directly and calculating the deviation from
ideal. The second method involves observing the
number of seconds gained or lost over a period of time.
Once the OSCTRIM register has been loaded, digital
trimming will automatically occur every minute
(CRSTRIM = 0).
5.6.1.1
Calibration by Measuring Frequency
To calibrate the MCP795XX by measuring the output
frequency, perform the following steps:
1.
2.
3.
4.
5.
6.
Enable the crystal oscillator or external clock
input by setting the ST bit or EXTOSC bit,
respectively.
Ensure TRIMVAL is reset to 0x00.
Select an output frequency by setting
SQWFS.
Set SQWEN to enable the square wave output.
Measure the resulting output frequency using a
calibrated measurement tool, such as a
frequency counter.
Calculate the number of error clocks per minute
(see Equation 5-3).
EQUATION 5-3:
CALCULATING TRIM
VALUE FROM MEASURED
FREQUENCY
32768
F IDEAL – F MEAS ------------------- 60
IDEAL
F
TRIMVAL = -------------------------------------------------------------------------------2
5.6.1.2
To calibrate the MCP795XX by observing the deviation
over time, perform the following steps:
1.
2.
3.
4.
5.
CALCULATING ERROR
PPM
SecDeviation
PPM = ----------------------------------- 1000000
ExpectedSec
Where:
ExpectedSec = Number of seconds in chosen period
SecDeviation = Number of seconds gained or lost
• If the MCP795XX has gained time relative to
the reference clock, then the oscillator is
faster than ideal and the TRIMSIGN bit must
be cleared.
• If the MCP795XX has lost time relative to the
reference clock, then the oscillator is slower
than ideal and the TRIMSIGN bit must be set.
6. Calculate the trim value (see Equation 5-5).
EQUATION 5-5:
CALCULATING TRIM
VALUE FROM ERROR
PPM
32768 60TRIMVAL = PPM
-----------------------------------------1000000 2
F IDEAL = Ideal frequency based on SQWFS
F MEAS = Measured frequency
Note:
Ensure TRIMVAL is reset to 0x00.
Load the timekeeping registers to synchronize
the MCP795XX with a known-accurate
reference time.
Enable the crystal oscillator or external clock
input by setting the ST bit or EXTOSC bit,
respectively.
Observe how many seconds are gained or lost
over a period of time (larger time periods offer
more accuracy).
Calculate the PPM deviation (see Equation 5-4).
EQUATION 5-4:
Where:
• If the number of error clocks per minute is
negative, then the oscillator is faster than
ideal and the TRIMSIGN bit must be cleared.
• If the number of error clocks per minute is
positive, then the oscillator is slower than
ideal and the TRIMSIGN bit must be set.
7. Load the correct value into TRIMVAL.
Calibration by Observing Time
Deviation
7.
Load the correct value into TRIMVAL.
Note 1: Choosing a longer time period for
observing
deviation
will
improve
accuracy.
2: Large temperature variations during the
observation period can skew results.
Using a lower output frequency and/or
averaging the measured frequency over a
number of clock pulses will reduce the
effects of jitter and improve accuracy.
2012-2022 Microchip Technology Inc. and its subsidiaries
DS20002300D-page 31
MCP7951X/MCP7952X
5.6.2
COARSE TRIM MODE
When CRSTRIM = 1, Coarse Trim mode is enabled.
While in this mode, the MCP795XX will apply trimming
every second. If SQWEN is set, the CLKOUT pin will
output a trimmed 1 Hz nominal clock signal.
Because trimming is applied every second rather than
every minute, each step of the TRIMVAL value
has a larger effect on the resulting time deviation and
output clock frequency.
TABLE 5-10:
Name
RTCHOUR
CONTROL
OSCTRIM
Legend:
By monitoring the CLKOUT output frequency while in
this mode, the user can easily observe the
TRIMVAL value affecting the clock timing.
Note 1: The 1 Hz Coarse Trim mode square
wave output is not available while
operating from the backup power supply.
2: With Coarse Trim mode enabled, the
TRIMVAL value has a larger effect
on timing. Leaving the mode enabled
during normal operation will likely result
in inaccurate time.
SUMMARY OF REGISTERS ASSOCIATED WITH DIGITAL TRIMMING
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
TRIMSIGN
12/24
AM/PM
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
19
—
SQWEN
ALM1EN
ALM0EN
SQWFS1
SQWFS0
29
TRIMVAL1 TRIMVAL0
30
TRIMVAL7 TRIMVAL6 TRIMVAL5 TRIMVAL4
EXTOSC
CRSTRIM
TRIMVAL3
TRIMVAL2
— = unimplemented location, read as ‘0’. Shaded cells are not used by digital trimming.l
DS20002300D-page 32
2012-2022 Microchip Technology Inc.and its subsidiaries
MCP7951X/MCP7952X
5.7
Battery Backup
5.7.1
The MCP795XX features a backup power supply input
(VBAT) that can be used to provide power to the
timekeeping circuitry, RTCC registers and SRAM while
primary power is unavailable. The MCP795XX will
automatically switch to backup power when VCC falls
below VTRIP and back to VCC when it is above VTRIP.
The MCP795XX includes a power-fail timestamp
module that stores the minutes, hours, date and month
when primary power is lost and when it is restored
(Figure 5-9). The PWRFAIL bit is also set to indicate
that a power failure occurred.
Note:
The VBATEN bit must be set to enable the VBAT input.
The following functionality
operating on backup power:
•
•
•
•
•
is
maintained
while
Timekeeping
Alarms
Alarm Outputs
Digital Trimming
RTCC Register and SRAM Contents
The following features are not available while operating
on backup power:
•
•
•
•
If VCC is lost while VBAT voltage is applied,
but where VBATEN is not set to ‘1’, it
could result in undetermined behavior. If a
backup supply is not used, the VBAT pin
should be connected to VSS.
Note 1: The PWRFAIL bit must be cleared to log
new timestamp data. This is to ensure
previous timestamp data is not lost.
2: Clearing the PWRFAIL bit will clear all
timestamp registers.
5.7.1.1
Configuring Battery Backup
In order to configure the battery backup feature, the
following steps need to be performed:
1.
2.
3.
FIGURE 5-9:
Throughout this section, references to the
register and bit names for the Power-Fail
Timestamp module are referred to
generically by the use of ‘x’ in place of the
specific
module
name.
Thus,
“PWRxxMIN” might refer to the minutes
register for power-down or power-up.
To utilize the power-fail timestamp feature, a backup
power supply must be available with the VBAT input
enabled, and the oscillator should also be running to
ensure accurate functionality.
SPI Communication
Watchdog Timer
Event Detect
Square Wave Clock Output
Note:
POWER-FAIL TIMESTAMP
Enable the oscillator.
Wait for the OSCRUN bit to be set, indicating the
oscillator has started.
Enable battery backup by setting the VBATEN
bit.
POWER-FAIL TIMESTAMP TIMING
VCC
VTRIP
Power-Down
Timestamp
2012-2022 Microchip Technology Inc. and its subsidiaries
Power-Up
Timestamp
DS20002300D-page 33
MCP7951X/MCP7952X
REGISTER 5-18:
PWRxxMIN: POWER-DOWN/POWER-UP TIMESTAMP MINUTES VALUE
REGISTER (ADDRESSES 0x18/0x1C)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
bit 7
Unimplemented: Read as ‘0’
bit 6-4
MINTEN: Binary-Coded Decimal Value of Minute’s Tens Digit
Contains a value from 0 to 5
bit 3-0
MINONE: Binary-Coded Decimal Value of Minute’s Ones Digit
Contains a value from 0 to 9
REGISTER 5-19:
PWRxxHOUR: POWER-DOWN/POWER-UP TIMESTAMP HOURS VALUE
REGISTER (ADDRESSES 0x19/0x1D)
U-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
—
12/24
AM/PM
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
If 12/24 = 1 (12-hour format):
bit 7
Unimplemented: Read as ‘0’
bit 6
12/24: 12 or 24 Hour Time Format bit
1 = 12-hour format
0 = 24-hour format
bit 5
AM/PM: AM/PM Indicator bit
1 = PM
0 = AM
bit 4
HRTEN0: Binary-Coded Decimal Value of Hour’s Tens Digit
Contains a value from 0 to 1
bit 3-0
HRONE: Binary-Coded Decimal Value of Hour’s Ones Digit
Contains a value from 0 to 9
If 12/24 = 0 (24-hour format):
bit 7
Unimplemented: Read as ‘0’
bit 6
12/24: 12 or 24 Hour Time Format bit
1 = 12-hour format
0 = 24-hour format
bit 5-4
HRTEN: Binary-Coded Decimal Value of Hour’s Tens Digit
Contains a value from 0 to 2.
bit 3-0
HRONE: Binary-Coded Decimal Value of Hour’s Ones Digit
Contains a value from 0 to 9
DS20002300D-page 34
2012-2022 Microchip Technology Inc.and its subsidiaries
MCP7951X/MCP7952X
REGISTER 5-20:
PWRxxDATE: POWER-DOWN/POWER-UP TIMESTAMP DATE VALUE REGISTER
(ADDRESSES 0x1A/0x1E)
U-0
U-0
R/W-0
—
—
DATETEN1
R/W-0
R/W-0
DATETEN0 DATEONE3
R/W-0
R/W-0
R/W-0
DATEONE2
DATEONE1
DATEONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
bit 7-6
Unimplemented: Read as ‘0’
bit 5-4
DATETEN: Binary-Coded Decimal Value of Date’s Tens Digit
Contains a value from 0 to 3
bit 3-0
DATEONE: Binary-Coded Decimal Value of Date’s Ones Digit
Contains a value from 0 to 9
REGISTER 5-21:
PWRxxMTH: POWER-DOWN/POWER-UP TIMESTAMP MONTH VALUE
REGISTER (ADDRESSES 0x1B/0x1F)
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
WKDAY2
WKDAY1
WKDAY0
MTHTEN0
MTHONE3
MTHONE2
MTHONE1
MTHONE0
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
bit 7-5
WKDAY: Binary-Coded Decimal Value of Day bits
Contains a value from 1 to 7. The representation is user-defined.
bit 4
MTHTEN0: Binary-Coded Decimal Value of Month’s Ones Digit
Contains a value of 0 or 1
bit 3-0
MTHONE: Binary-Coded Decimal Value of Month’s Ones Digit
Contains a value from 0 to 9
TABLE 5-11:
Name
SUMMARY OF REGISTERS ASSOCIATED WITH BATTERY BACKUP
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Register
on Page
RTCWKDAY
—
—
OSCRUN
PWRFAIL
VBATEN
WKDAY2
WKDAY1
WKDAY0
20
PWRDNMIN
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
34
PWRDNHOUR
—
12/24
AM/PM
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
34
PWRDNDATE
—
—
DATETEN1
DATETEN0
DATEONE3
DATEONE2
DATEONE1
DATEONE0
35
PWRDNMTH
WKDAY2
WKDAY1
WKDAY0
MTHTEN0
MTHONE3
MTHONE2
MTHONE1
MTHONE0
35
PWRUPMIN
—
MINTEN2
MINTEN1
MINTEN0
MINONE3
MINONE2
MINONE1
MINONE0
34
PWRUPHOUR
—
12/24
AM/PM
HRTEN1
HRTEN0
HRONE3
HRONE2
HRONE1
HRONE0
34
PWRUPDATE
—
—
DATETEN1
DATETEN0
DATEONE3
DATEONE2
DATEONE1
DATEONE0
35
PWRUPMTH
WKDAY2
WKDAY1
WKDAY0
MTHTEN0
MTHONE3
MTHONE2
MTHONE1
MTHONE0
35
Legend:
— = unimplemented location, read as ‘0’. Shaded cells are not used with battery backup.
2012-2022 Microchip Technology Inc. and its subsidiaries
DS20002300D-page 35
MCP7951X/MCP7952X
6.0
ON-BOARD MEMORY
There is no limit to the number of bytes that can be
written in a single command. However, because the
RTCC registers and SRAM are separate blocks, writing
past the end of each block will cause the internal
Address Pointer to roll over to the beginning of the
same block. Specifically, the Address Pointer will roll
over from 0x1F to 0x00 and from 0x5F to 0x20.
The MCP7952X has 2 Kbits (256 bytes) of EEPROM,
while the MCP7951X has 1 Kbit (128 bytes) of
EEPROM. In addition, the devices have 16 bytes of
protected EEPROM for storing crucial information and
64 bytes of SRAM for general purpose usage. The
SRAM is retained when the primary power supply is
removed if a backup supply is present and enabled.
Since the EEPROM is nonvolatile, it does not require a
supply for data retention.
Each data byte is latched into memory as it is received.
Once all data bytes have been transmitted, CS is
driven high to end the operation (Figure 6-1).
6.1.2
Although the SRAM is a separate block from the RTCC
registers, they are accessed using the same
instructions, READ and WRITE. The EEPROM is
accessed using the EEREAD and EEWRITE instructions
and the protected EEPROM is accessed using the
IDREAD and IDWRITE instructions. RTCC and SRAM
can be accessed for reads or writes immediately after
starting an EEPROM write cycle.
6.1
The device is selected by pulling CS low. The 8-bit
READ instruction is transmitted to the MCP795XX
followed by an 8-bit address.
After the READ instruction and address are sent, the
data stored in the memory at the selected address is
shifted out on the SO pin. Data stored in the memory at
the next address can be read sequentially by
continuing to provide clock pulses to the client. The
internal Address Pointer automatically increments to
the next higher address after each byte of data is
shifted out. The Address Pointer allows the entire
memory block to be serially read during one operation.
The read operation is terminated by driving CS high
(Figure 6-2).
SRAM/RTCC Registers
The RTCC registers are located at addresses 0x00 to
0x1F and the SRAM is located at addresses 0x20 to
0x5F. The SRAM can be accessed while the RTCC
registers are being internally updated. The SRAM is not
initialized by a Power-on Reset (POR).
Neither the RTCC registers nor the SRAM can be
accessed when the device is operating off the backup
power supply.
6.1.1
SRAM/RTCC REGISTER READ
SEQUENCE
Because the RTCC registers and SRAM are separate
blocks, reading past the end of each block will cause
the Address Pointer to roll over to the beginning of the
same block. Specifically, the Address Pointer will roll
over from 0x1F to 0x00 and from 0x5F to 0x20.
SRAM/RTCC REGISTER WRITE
SEQUENCE
The device is selected by pulling CS low. The 8-bit
WRITE instruction is transmitted to the MCP795XX
followed by an 8-bit address. Next, the data to be
written is transmitted.
FIGURE 6-1:
SRAM/RTCC WRITE SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
Address Byte
Instruction
SI
0
0
0
1
0
0
1
Data Byte 1
0 A7 A6 A5 A4 A3 A2 A1 A0 7
6
5
4
3
2
1
0
CS
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCK
Data Byte 2
SI
7
6
DS20002300D-page 36
5
4
3
2
Data Byte 3
1
0
7
6
5
4
3
2
Data Byte n
1
0
7
6
5
4
3
2
1
0
2012-2022 Microchip Technology Inc.and its subsidiaries
MCP7951X/MCP7952X
FIGURE 6-2:
SRAM/RTCC READ SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
Instruction
SI
0
0
0
1
0
Address Byte
0
1
1 A7 A6 A5 A4 A3 A2 A1 A0
Data Out
High-Impedance
7
SO
6.1.3
CLEAR SRAM INSTRUCTION
5
4
3
2
1
0
The device is selected by pulling CS low. The 8-bit
CLRRAM instruction is transmitted to the MCP795XX
followed by an 8-bit dummy data byte. CS is driven high
to end the operation (Figure 6-3). The value of the data
byte is ignored.
The CLRRAM instruction can be used to quickly clear
the contents of SRAM to 0x00. The RTCC registers are
not affected.
FIGURE 6-3:
6
CLEAR SRAM SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
0
SCK
Instruction
SI
0
1
0
1
0
Dummy Data Byte
1
0
0
7
6
5
4
3
2
High-Impedance
SO
2012-2022 Microchip Technology Inc. and its subsidiaries
DS20002300D-page 37
MCP7951X/MCP7952X
6.2
Status Register
The STATUS register contains the BP, WEL and
WIP bits. The STATUS register is accessed using the
SRREAD and SRWRITE instructions.
The Block Protection (BP) bits are used to set the
block write protection for the EEPROM array according
to Table 6-1. These bits are set by the user issuing the
SRWRITE instruction. These bits are nonvolatile.
The WIP bit indicates whether the MCP795XX is busy
with a nonvolatile memory write operation. When set to
a ‘1’, a write is in progress. When set to a ‘0’, no write
is in progress. This bit is read-only.
TABLE 6-1:
Array Addresses
Write-Protected
BP1
BP0
0
0
None
0
1
Upper 1/4
60h-7Fh (MCP7951X)
C0h-FFh (MCP7952X)
1
0
Upper 1/2
40h-7Fh (MCP7951X)
80h-FFh (MCP7952X)
1
1
All
The Write Enable Latch (WEL) bit indicates the status
of the write enable latch. When set to a ‘1’, the latch
allows writes to the nonvolatile memory, when set to a
‘0’, the latch prohibits writes to the nonvolatile memory.
The state of this bit can be updated via the EEWREN or
EEWRDI instructions. This bit is read-only.
REGISTER 6-1:
BLOCK PROTECTION
STATUS: EEPROM WRITE PROTECTION REGISTER
U-0
U-0
U-0
U-0
R/W
R/W
R-0
R-0
—
—
—
—
BP1
BP0
WEL
WIP
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is clear
x = Bit is unknown
bit 7-4
Unimplemented: Read as ‘0’
bit 3-2
BP: EEPROM Array Block Protection bits
Selects which EEPROM region is write-protected
00 = None
01 = Upper 1/4
10 = Upper 1/2
11 = All
bit 1
WEL: Write Enable Latch bit
Indicates whether or not nonvolatile memory writes are enabled. It is automatically cleared at the end
of a nonvolatile memory write cycle.
0 = Writes to nonvolatile memory are not enabled
1 = Writes to nonvolatile memory are enabled
bit 0
WIP: Write-In-Process bit
Indicates whether or not a nonvolatile memory write cycle is in process
0 = Nonvolatile write cycle is not in process
1 = Nonvolatile write cycle is in process
6.2.1
STATUS REGISTER WRITE
SEQUENCE
The Write Status Register instruction (SRWRITE)
allows the user to write to the nonvolatile bits in the
STATUS register.
Prior to any attempt to write data to the STATUS
register, the write enable latch must be set by issuing
the EEWREN instruction. This is done by setting CS low
and then clocking out the proper instruction into the
MCP795XX.
DS20002300D-page 38
After all eight bits of the instruction are transmitted, CS
must be driven high to set the write enable latch. If the
write operation is initiated immediately after the
EEWREN instruction without CS driven high, data will not
be written to the array since the write enable latch was
not properly set. The device is selected by pulling CS
low. The 8-bit SRWRITE instruction is transmitted to the
MCP795XX followed by the 8-bit data byte. CS is
driven high to end the operation and initiate the
nonvolatile write cycle (Figure 6-4).
2012-2022 Microchip Technology Inc.and its subsidiaries
MCP7951X/MCP7952X
FIGURE 6-4:
WRITE STATUS REGISTER SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
1
0
SCK
Instruction
0
SI
0
0
0
Data to STATUS Register
0
0
0
7
1
6
5
4
3
2
High-Impedance
SO
6.2.2
STATUS REGISTER READ
SEQUENCE
The device is selected by pulling CS low. The 8-bit
SRREAD instruction is transmitted to the MCP795XX.
The STATUS register value is then shifted out on the
SO pin. The read operation is terminated by driving CS
high (Figure 6-5).
The Read Status Register instruction (SRREAD)
provides access to the STATUS register. The STATUS
register may be read at any time, even during a write
cycle. This allows the user to poll the WIP bit to
determine when a write cycle is complete.
FIGURE 6-5:
READ STATUS REGISTER SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SCK
Instruction
SI
0
0
0
0
0
1
High-Impedance
SO
2012-2022 Microchip Technology Inc. and its subsidiaries
0
1
Data from STATUS Register
7
6
5
4
3
2
1
0
DS20002300D-page 39
MCP7951X/MCP7952X
6.3
EEPROM
The following is a list of conditions under which the
write enable latch will be reset:
The MCP7952X features 2 Kbits of EEPROM and the
MCP7951X features 1 Kbit of EEPROM. It is organized
in 8-byte pages with software write protection
configurable through the STATUS register.
6.3.1
•
•
•
•
•
•
WRITE ENABLE AND WRITE
DISABLE
The MCP795XX contains a write enable latch. This
latch must be set before any write operation will be
completed internally. The EEWREN instruction will set
the latch and the EEWRDI instruction will reset the latch.
FIGURE 6-6:
Power-up
WRDI instruction successfully executed
EEWRITE instruction successfully executed
SRWRITE instruction successfully executed
IDWRITE instruction successfully executed
Unlock sequence for protected EEPROM not
followed correctly
WRITE ENABLE SEQUENCE
CS
0
1
2
3
4
5
6
7
SCK
0
SI
0
0
0
1
1
0
High-Impedance
SO
FIGURE 6-7:
0
WRITE DISABLE SEQUENCE
CS
0
1
2
3
4
5
6
7
SCK
SI
0
0
0
0
0
1
0
0
High-Impedance
SO
DS20002300D-page 40
2012-2022 Microchip Technology Inc.and its subsidiaries
MCP7951X/MCP7952X
6.3.2
EEPROM READ SEQUENCE
The device is selected by pulling CS low. The 8-bit
EEREAD instruction is transmitted to the MCP795XX
followed by an 8-bit address. See Figure 6-8 for more
details.
After the correct EEREAD instruction and address are
sent, the data stored in the EEPROM at the selected
address is shifted out on the SO pin. Data stored in the
memory at the next address can be read sequentially
by continuing to provide clock pulses to the client. The
internal Address Pointer automatically increments to
the next higher address after each byte of data is
shifted out. When the highest address is reached, the
address counter rolls over to address 00h allowing the
read cycle to be continued indefinitely. The read
operation is terminated by raising the CS pin
(Figure 6-8).
6.3.3
Additionally, a page address begins with XXXX x000
and ends with XXXX x111. If the internal address
counter reaches XXXX
x111 and clock signals
continue to be applied to the chip, the address counter
will roll back to the first address of the page and
over-write any data that previously existed in those
locations.
Note:
EEPROM WRITE SEQUENCE
Prior to any attempt to write data to the MCP795XX
EEPROM, the write enable latch must be set by issuing
the EEWREN instruction. This is done by setting CS low
and then clocking out the proper instruction into the
MCP795XX. After all eight bits of the instruction are
transmitted, CS must be driven high to set the write
enable latch. If the write operation is initiated
immediately after the EEWREN instruction without CS
driven high, data will not be written to the array since
the write enable latch was not properly set.
After setting the write enable latch, the user may
proceed by driving CS low, issuing an EEWRITE
instruction, followed by the address and then the data
to be written. Up to 8 bytes of data can be sent to the
device before a write cycle is necessary. The only
restriction is that all of the bytes must reside in the
same page.
FIGURE 6-8:
EEPROM write operations are limited to
writing bytes within a single physical page,
regardless of the number of bytes
actually being written. Physical page
boundaries start at addresses that are
integer multiples of the page buffer size
(or ‘page size’) and end at addresses that
are integer multiples of page size – 1. If an
EEWRITE command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page as might be
expected. It is therefore necessary for the
application software to prevent EEPROM
write operations that would attempt to
cross a page boundary.
For the data to be actually written to the array, the CS
must be brought high after the Least Significant bit (D0)
of the nth data byte has been clocked in. If CS is driven
high at any other time, the write operation will not be
completed. Refer to Figure 6-9 and Figure 6-10 for
more detailed illustrations on the byte write sequence
and the page write sequence respectively. While the
write is in progress, the STATUS register may be read
to check the status of the WIP, WEL, BP1 and BP0 bits.
Attempting to read a memory array location will not be
possible during a write cycle. Polling the WIP bit in the
STATUS register is recommended in order to
determine if a write cycle is in progress. When the write
cycle is completed, the write enable latch is reset.
EEPROM READ SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
Instruction
SI
0
0
0
0
0
Address Byte
0
1
1 A7 A6 A5 A4 A3 A2 A1 A0
Data Out
High-Impedance
SO
2012-2022 Microchip Technology Inc. and its subsidiaries
7
6
5
4
3
2
1
0
DS20002300D-page 41
MCP7951X/MCP7952X
FIGURE 6-9:
EEPROM BYTE WRITE SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
Instruction
SI
0
0
0
0
0
Address Byte
0
Data Byte
0 A7 A6 A5 A4 A3 A2 A1 A0
1
Twc
7
6
5
4
3
2
1
0
High-Impedance
SO
FIGURE 6-10:
EEPROM PAGE WRITE SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
Address Byte
Instruction
SI
0
0
0
0
0
0 1
Data Byte 1
0 A7 A6 A5 A4 A3 A2 A1 A0 7
6
5
4
3
2
1
0
CS
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCK
Data Byte 2
SI
6.4
7
6
5
4
3
2
Data Byte 3
1
0
7
6
Protected EEPROM
The MCP795XX features a 128-bit protected EEPROM
block, organized as two 8-byte pages, that requires a
special unlock sequence to be followed in order to write
to the memory. The protected EEPROM can be used
for storing crucial information such as a unique serial
number. The MCP795X1 and MCP795X2 include an
EUI-48 and EUI-64 node address, respectively,
preprogrammed into the protected EEPROM block.
Custom programming is also available.
The protected EEPROM block is located at addresses
0x00 to 0x0F and is accessed using the IDREAD and
IDWRITE instructions.
Note:
Attempts to access addresses outside of
0x00 to 0x0F will result in the MCP795XX
ignoring the instruction.
DS20002300D-page 42
5
4
3
Data Byte n (8 max)
2
1
6.4.1
0
7
6
5
4
3
2
1
0
PROTECTED EEPROM READ
SEQUENCE
The device is selected by pulling CS low. The 8-bit
IDREAD instruction is transmitted to the MCP795XX
followed by an 8-bit address. See Figure 6-11 for more
details.
After the correct IDREAD instruction and address are
sent, the data stored in the protected EEPROM at the
selected address is shifted out on the SO pin. Data
stored in the memory at the next address can be read
sequentially by continuing to provide clock pulses to
the client. The internal Address Pointer automatically
increments to the next higher address after each byte
of data is shifted out. When the highest address is
reached, the address counter rolls over to address 00h
allowing the read cycle to be continued indefinitely. The
read operation is terminated by raising the CS pin.
2012-2022 Microchip Technology Inc.and its subsidiaries
MCP7951X/MCP7952X
6.4.2
PROTECTED EEPROM UNLOCK
SEQUENCE
The protected EEPROM block requires a special
unlock sequence to prevent unintended writes, utilizing
the UNLOCK instruction.
Before performing the unlock sequence, the WEL bit
must first be set by executing an EEWREN instruction
(see Section 6.3.1 “Write Enable and Write Disable”
for details).
To unlock the block, the following sequence must be
followed after setting the WEL bit:
1.
2.
3.
Execute an UNLOCK instruction with a data byte
of 0x55
Execute an UNLOCK instruction with a data byte
of 0xAA
Write the desired data bytes to the protected
EEPROM using the IDWRITE instruction
Figure 6-12 illustrates the sequence.
Note 1: Diverging from any step of the unlock
sequence may result in the EEPROM
remaining locked, the write operation
being ignored and the WEL bit being
reset.
2: Unlocking the EEPROM is not required in
order to read from the memory.
An entire protected EEPROM page does not have to be
written in a single operation. However, the block is
locked after each write operation and must be unlocked
again to start a new Write command.
6.4.3
PROTECTED EEPROM WRITE
SEQUENCE
Prior to any attempt to write data to the MCP795XX
protected EEPROM block, the write enable latch must
be set by issuing the EEWREN instruction and then the
protected EEPROM unlock sequence must be
performed. The EEWREN instruction is issued by setting
CS low and then clocking out the proper instruction into
the MCP795XX. After all eight bits of the instruction are
transmitted, CS must be driven high to set the write
enable latch.
Note:
Protected EEPROM write operations are
limited to writing bytes within a single
physical page, regardless of the number
of bytes actually being written. Physical
page boundaries start at addresses that
are integer multiples of the page buffer
size (or ‘page size’) and end at addresses
that are integer multiples of page size – 1.
If an IDWRITE command attempts to write
across a physical page boundary, the
result is that the data wraps around to the
beginning of the current page (overwriting
data previously stored there), instead of
being written to the next page as might be
expected. It is therefore necessary for the
application software to prevent protected
EEPROM write operations that would
attempt to cross a page boundary.
For the data to be actually written to the array, the CS
must be brought high after the Least Significant bit (D0)
of the nth data byte has been clocked in. If CS is driven
high at any other time, the write operation will not be
completed. Refer to Figure 6-12 for more detailed
illustrations on the page write sequence. While the
write is in progress, the STATUS register may be read
to check the status of the WIP, WEL, BP1 and BP0 bits.
Attempting to read a memory array location will not be
possible during a write cycle. Polling the WIP bit in the
STATUS register is recommended in order to
determine if a write cycle is in progress. When the write
cycle is completed, the write enable latch is reset.
If an attempt is made to write to an address outside of
the 0x00 to 0x0F range, the MCP795XX will not
execute the WRITE instruction, no data will be written,
and the device will immediately accept a new
command.
After setting the write enable latch and performing the
unlock sequence, the user may proceed by driving CS
low, issuing an IDWRITE instruction, followed by the
address and then the data to be written. Up to 8 bytes
of data can be sent to the device before a write cycle is
necessary. The only restriction is that all of the bytes
must reside in the same page. Additionally, a page
address begins with XXXX x000 and ends with
XXXX x111. If the internal address counter reaches
XXXX x111 and clock signals continue to be applied to
the chip, the address counter will roll back to the first
address of the page and over-write any data that
previously existed in those locations.
2012-2022 Microchip Technology Inc. and its subsidiaries
DS20002300D-page 43
MCP7951X/MCP7952X
FIGURE 6-11:
PROTECTED EEPROM READ SEQUENCE
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
Instruction
SI
0
0
1
1
0
Address Byte
0
1
1
0
0
0 A3 A2 A1 A0
0
Data Out
High-Impedance
7
SO
FIGURE 6-12:
6
5
4
3
2
1
0
PROTECTED EEPROM UNLOCK AND PAGE WRITE SEQUENCE
1. UNLOCK
Instruction
with 0x55
Data Byte
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCK
Data Byte
Instruction
0
SI
2. UNLOCK
Instruction
with 0xAA
Data Byte
0
0
1
0
1
0
0
0
1
0
1
0
1
0
1
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
SCK
Data Byte
Instruction
0
SI
0
0
1
0
1
0
0
1
0
1
0
1
0
1
0
3. IDWRITE
Instruction
CS
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
SCK
Address Byte
Instruction
SI
0
0
1
1
0
0
1
0
0
0
0
Data Byte 1
0 A3 A2 A1 A0
7
6
5
4
3
2
1
0
CS
24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
SCK
Data Byte 2
SI
7
6
DS20002300D-page 44
5
4
3
2
Data Byte 3
1
0
7
6
5
4
3
2
Data Byte n (8 max)
1
0
7
6
5
4
3
2
1
0
2012-2022 Microchip Technology Inc.and its subsidiaries
MCP7951X/MCP7952X
6.5
Preprogrammed EUI-48™ or
EUI-64™ Node Address
6.5.1.2
The MCP795X1 and MCP795X2 are programmed at
the factory with a globally unique node address stored
in the protected EEPROM block.
6.5.1
EUI-48 NODE ADDRESS
(MCP795X1)
The 6-byte EUI-48 node address value of the
MCP795X1 is stored in protected EEPROM locations
0x02 through 0x07, as shown in Figure 6-13. The first
three bytes are the Organizationally Unique Identifier
(OUI) assigned to Microchip by the IEEE Registration
Authority. The remaining three bytes are the Extension
Identifier and are generated by Microchip to ensure a
globally-unique, 48-bit value.
6.5.1.1
Organizationally Unique Identifiers
(OUIs)
Each OUI provides roughly 16M (224) addresses. Once
the address pool for an OUI is exhausted, Microchip
will acquire a new OUI from IEEE to use for
programming this model. For more information on past
and current OUIs see “Organizationally Unique
Identifiers For Preprogrammed EUI-48 and EUI-64
Address Devices” Technical Brief (DS90003187).
Note:
The OUI will change as addresses are
exhausted. Customers are not guaranteed to receive a specific OUI and should
design their application to accept new
OUIs as they are introduced.
FIGURE 6-13:
Description
EUI-64 Support Using the
MCP795X1
The preprogrammed EUI-48 node address of the
MCP795X1 can easily be encapsulated at the
application level to form a globally unique, 64-bit node
address for systems utilizing the EUI-64 standard. This
is done by adding 0xFFFE between the OUI and the
Extension Identifier, as shown below.
Note:
6.5.2
As an alternative, the MCP795X2 features
an EUI-64 node address that can be used
in EUI-64 applications directly without the
need
for
encapsulation,
thereby
simplifying
system
software.
See
Section 6.5.2 “EUI-64 Node Address
(MCP795X2)” for details.
EUI-64 NODE ADDRESS
(MCP795X2)
The 8-byte EUI-64™ node address value of the
MCP795X2 is stored in array locations 0x00 through
0x07, as shown in Figure 6-14. The first three bytes are
the Organizationally Unique Identifier (OUI) assigned
to Microchip by the IEEE Registration Authority.
The remaining five bytes are the Extension Identifier,
and are generated by Microchip to ensure a
globally-unique, 64-bit value..
Note:
In conformance with IEEE guidelines,
Microchip will not use the values 0xFFFE
and 0xFFFF for the first two bytes of the
EUI-64 Extension Identifier. These two
values are specifically reserved to allow
applications to encapsulate EUI-48
addresses into EUI-64 addresses.
EUI-48 NODE ADDRESS PHYSICAL MEMORY MAP EXAMPLE (MCP795X1)
24-bit Organizationally
Unique Identifier
Data
00h
Array
Address
02h
04h
A3h
24-bit Extension
Identifier
12h
34h
56h
07h
Corresponding EUI-48™ Node Address: 00-04-A3-12-34-56
Corresponding EUI-64™ Node Address After Encapsulation: 00-04-A3-FF-FE-12-34-56
2012-2022 Microchip Technology Inc. and its subsidiaries
DS20002300D-page 45
MCP7951X/MCP7952X
FIGURE 6-14:
Description
EUI-64 NODE ADDRESS PHYSICAL MEMORY MAP EXAMPLE (MCP795X2)
40-bit Extension
Identifier
24-bit Organizationally
Unique Identifier
Data
00h
Array
Address
00h
04h
A3h
12h
34h
56h
78h
90h
07h
Corresponding EUI-64™ Node Address: 00-04-A3-12-34-56-78-90
DS20002300D-page 46
2012-2022 Microchip Technology Inc.and its subsidiaries
MCP7951X/MCP7952X
7.0
PACKAGING INFORMATION
7.1
Package Marking Information
10-Lead MSOP (3x3 mm)
Example
79520I
14013F
10-Lead TDFN (03x03x0.8 mm)
Example
520I
2140
13F
Part Number
MSOP
TDFN
MCP79510
79510T
510T
MCP79520
79520T
520T
MCP79511
79511T
511T
MCP79521
79521T
521T
MCP79512
79512T
512T
MCP79522
79522T
522T
Note:
Legend: XX...X
Y
YY
WW
NNN
e3
*
Note:
1st Line Marking Codes
T = Temperature grade
NN = Alphanumeric traceability code
Customer-specific information
Year code (last digit of calendar year)
Year code (last 2 digits of calendar year)
Week code (week of January 1 is week ‘01’)
Alphanumeric traceability code
JEDEC® designator for Matte Tin (Sn)
This package is RoHS compliant. The JEDEC designator ( e3 )
can be found on the outer packaging for this package.
In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
2012-2022 Microchip Technology Inc. and its subsidiaries
DS20002300D-page 47
MCP7951X/MCP7952X
10-Lead Plastic Micro Small Outline Package (MS) - 3x3 mm Body [MSOP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
0.20 H
D
D
2
A
N
E
2
E1
2
E1
E
0.20 H
1
0.25 C
2
e
B
8X b
0.13
C A B
TOP VIEW
H
C
SEATING
PLANE
A2
A
8X
A1
0.10 C
SEE DETAIL A
SIDE VIEW
END VIEW
Microchip Technology Drawing C04-021-MS Rev E Sheet 1 of 2
DS20002300D-page 48
2012-2022 Microchip Technology Inc.and its subsidiaries
MCP7951X/MCP7952X
10-Lead Plastic Micro Small Outline Package (MS) - 3x3 mm Body [MSOP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
4X Ĭ1
c
C
SEATING
PLANE
L
Ĭ
(L1)
4X Ĭ1
DETAIL A
Units
Dimension Limits
Number of Pins
N
e
Pitch
A
Overall Height
Molded Package Thickness
A2
Standoff
A1
Overall Width
E
E1
Molded Package Width
D
Overall Length
L
Foot Length
Footprint
L1
Mold Draft Angle
Ĭ
Foot Angle
Ĭ1
c
Lead Thickness
b
Lead Width
MIN
0.75
0.00
0.40
0°
5°
0.08
0.15
MILLIMETERS
NOM
10
0.50 BSC
0.85
4.90 BSC
3.00 BSC
3.00 BSC
0.60
0.95 REF
-
MAX
1.10
0.95
0.15
0.80
8°
15°
0.23
0.33
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.15mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-021-MS Rev E Sheet 2 of 2
2012-2022 Microchip Technology Inc. and its subsidiaries
DS20002300D-page 49
MCP7951X/MCP7952X
10-Lead Plastic Micro Small Outline Package (MS) - 3x3 mm Body [MSOP]
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
G
SILK SCREEN
Z
C
G1
Y1
X1
E
RECOMMENDED LAND PATTERN
Units
Dimension Limits
E
Contact Pitch
Contact Pad Spacing
C
Overall Width
Z
Contact Pad Width (X10)
X1
Contact Pad Length (X10)
Y1
Distance Between Pads (X5)
G1
Distance Between Pads (X8)
G
MIN
MILLIMETERS
NOM
0.50 BSC
4.40
MAX
5.80
0.30
1.40
3.00
0.20
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2021-MS Rev E
DS20002300D-page 50
2012-2022 Microchip Technology Inc.and its subsidiaries
MCP7951X/MCP7952X
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
2012-2022 Microchip Technology Inc. and its subsidiaries
DS20002300D-page 51
MCP7951X/MCP7952X
Note:
For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
DS20002300D-page 52
2012-2022 Microchip Technology Inc.and its subsidiaries
MCP7951X/MCP7952X
APPENDIX A:
REVISION HISTORY
Revision D (04/2022)
Updated Data Sheet with Automotive part numbers and
general fixes; Replaced terminology “Master” and
“Slave” with “Host” and “Client” respectively.
Old Bit Name
New Bit Name
CALIBRATION
TRIMVAL
ALM0C
ALM0MSK
ALM1C
ALM1MSK
Revision C (02/2018)
Added detailed description of OUIs.
Revision B (12/2016)
General rewrite of document for various corrections
and improvements throughout; Removed preliminary
status; Updated overall content for improved clarity;
Added detailed descriptions of registers; Expanded
descriptions of peripheral features; Updated block
diagram and application schematic; Defined names for
all bits and registers, and renamed the bits shown in
Table 1 for clarification; Renamed the DC
characteristics shown in Table 2 for clarification.
TABLE 1:
BIT NAME CHANGES
Old Bit Name
New Bit Name
CALSGN
TRIMSIGN
OSCON
OSCRUN
VBAT
PWRFAIL
LP
LPYR
SQWE
SQWEN
ALM0
ALM0EN
ALM1
ALM1EN
RS0
SQWFS0
RS1
SQWFS1
RS2
CRSTRIM
TABLE 2:
DC CHARACTERISTIC NAME CHANGES
Old Name
Operating Current
Old Symbol
ICC Read
New Name
New Symbol
EEPROM Operating Current
ICCEERD
IDD Write
ICCEEWR
VBAT Current
IBAT
Timekeeping Backup Current
Standby Current
ICCS
VCC Data Retention Current (oscillator off)
IBATT
ICCDAT
Revision A (04/2012)
Initial release of this document.
2012-2022 Microchip Technology Inc. and its subsidiaries
DS20002300D-page 53
MCP7951X/MCP7952X
THE MICROCHIP WEBSITE
CUSTOMER SUPPORT
Microchip provides online support via our website at
www.microchip.com. This website is used as a means
to make files and information easily available to
customers. Accessible by using your favorite Internet
browser, the website contains the following information:
Users of Microchip products can receive assistance
through several channels:
• Product Support – Data sheets and errata, application notes and sample programs, design
resources, user’s guides and hardware support
documents, latest software releases and archived
software
• General Technical Support – Frequently Asked
Questions (FAQ), technical support requests,
online discussion groups, Microchip consultant
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives
•
•
•
•
Distributor or Representative
Local Sales Office
Field Application Engineer (FAE)
Technical Support
Customers should contact their distributor, representative or Field Application Engineer (FAE) for support.
Local sales offices are also available to help customers. A listing of sales offices and locations is included in
the back of this document.
Technical support is available through the website
at: http://microchip.com/support
CUSTOMER CHANGE NOTIFICATION
SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a specified product family or development tool of interest.
To register, access the Microchip website at
www.microchip.com. Under “Support”, click on “Customer Change Notification” and follow the registration instructions.
DS20002300D-page 54
2012-2022 Microchip Technology Inc.and its subsidiaries
MCP7951X/MCP7952X
PRODUCT IDENTIFICATION SYSTEM (NON-AUTOMOTIVE)
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Not every possible ordering
combination is listed below.
PART NO.
X
Device
Memory
X
(1) –
[X](1)
X
/XX
Unique ID Tape & Reel Temperature Package
Option
Range
Device:
MCP795 = 3V SPI Serial RTCC with Battery Switchover
Memory:
1
2
=
=
1-Kbit EEPROM, 64-Byte SRAM
2-Kbit EEPROM, 64-Byte SRAM
ID/MAC
Address:
0
1
2
=
=
=
Blank
Preprogrammed EUI-48™ address
Preprogrammed EUI-64™ address
Tape & Reel
Option(1):
Blank
T
= Tube
= Tape & Reel
Temperature
Range:
I
=
Package:
MS
MN
= 10-Lead Plastic Small Outline
= 10-Lead Thin Plastic Dual Flat
(3x3x0.8 mm body)
Examples:
a)
b)
c)
d)
e)
f)
-40C to +85C
2012-2022 Microchip Technology Inc. and its subsidiares
MCP79510-I/MS:
1-Kbit
EEPROM,
Industrial Temperature, MSOP Package.
MCP79511T-I/MN: 1-Kbit EEPROM,
EUI-48™, Tape and Reel, Industrial
Temperature, TDFN Package.
MCP79512-I/MS:
1-Kbit
EEPROM,
Preprogrammed EUI-64™ address,
Industrial Temperature, MSOP Package.
MCP79520-I/MS:
2-Kbit
EEPROM,
Industrial Temperature, MSOP Package.
MCP79521T-I/MN: 2-Kbit EEPROM,
EUI-48™, Tape and Reel, Industrial
Temperature, TDFN Package.
MCP79522-I/MS:
2-Kbit
EEPROM,
EUI-64™, Industrial Temperature, MSOP
Package.
Note 1:
Tape and Reel identifier only
appears in the catalog part number
description. This identifier is used
for ordering purposes and is not
printed on the device package.
Check with your Microchip Sales
Office for package availability with
the Tape and Reel option.
DS20002300D-page 55
MCP7951X/MCP7952X
PRODUCT IDENTIFICATION SYSTEM (AUTOMOTIVE)
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. Not every possible ordering
combination is listed below.
PART NO.
(1)
[X](1)
X
X
–
X
/XX
(2,3)
/XXX
Device Memory Unique ID Tape & Reel Temperature Package Variant
Option
Range
Device:
MCP795 = 3V SPI Serial RTCC with Battery Switchover
Memory:
1
2
=
=
1-Kbit EEPROM, 64-Byte SRAM
2-Kbit EEPROM, 64-Byte SRAM
ID/MAC
Address:
0
1
2
=
=
=
Blank
Preprogrammed EUI-48™ address
Preprogrammed EUI-64™ address
Tape & Reel
Option(1):
Blank
T
= Tube
= Tape & Reel
Temperature
Range:
I
=
Package:
MS
= 10-Lead Plastic Small Outline (MSOP)
Variant(2, 3):
VAO
= Standard Automotive
DS20002300D-page 56
-40C to +85C (AEC-Q100 Grade 3)
Examples:
a) MCP79510-I/MSVAO: 1-Kbit EEPROM,
Automotive Grade 3, MSOP Package.
b) MCP79520-I/MSVAO: 2-Kbit EEPROM,
Automotive Grade 3, MSOP Package.
c) MCP79520T-I/MSVAO: 2-Kbit EEPROM,
Automotive Grade 3, Tape and Reel, MSOP
Package.
Note 1:
Tape and Reel identifier only
appears in the catalog part number
description. This identifier is used for
ordering purposes and is not printed
on the device package. Check with
your Microchip Sales Office for
package availability with the Tape
and Reel option.
2:
The VAO/VXX automotive variants
have been designed, manufactured,
tested and qualified in accordance
with AEC-Q100 requirements for
automotive applications.
3:
For customers requesting a PPAP, a
customer-specific part will be
generated and provided. A PPAP is
not provided for VAO part numbers.
2012-2022 Microchip Technology Inc. and its subsidiares
Note the following details of the code protection feature on Microchip products:
•
Microchip products meet the specifications contained in their particular Microchip Data Sheet.
•
Microchip believes that its family of products is secure when used in the intended manner, within operating specifications, and
under normal conditions.
•
Microchip values and aggressively protects its intellectual property rights. Attempts to breach the code protection features of
Microchip product is strictly prohibited and may violate the Digital Millennium Copyright Act.
•
Neither Microchip nor any other semiconductor manufacturer can guarantee the security of its code. Code protection does not
mean that we are guaranteeing the product is “unbreakable”. Code protection is constantly evolving. Microchip is committed to
continuously improving the code protection features of our products.
This publication and the information herein may be used only
with Microchip products, including to design, test, and integrate
Microchip products with your application. Use of this information in any other manner violates these terms. Information
regarding device applications is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your
specifications. Contact your local Microchip sales office for
additional support or, obtain additional support at https://
www.microchip.com/en-us/support/design-help/client-supportservices.
THIS INFORMATION IS PROVIDED BY MICROCHIP "AS IS".
MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED,
WRITTEN OR ORAL, STATUTORY OR OTHERWISE,
RELATED TO THE INFORMATION INCLUDING BUT NOT
LIMITED TO ANY IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTABILITY, AND FITNESS FOR A
PARTICULAR PURPOSE, OR WARRANTIES RELATED TO
ITS CONDITION, QUALITY, OR PERFORMANCE.
IN NO EVENT WILL MICROCHIP BE LIABLE FOR ANY INDIRECT, SPECIAL, PUNITIVE, INCIDENTAL, OR CONSEQUENTIAL LOSS, DAMAGE, COST, OR EXPENSE OF ANY
KIND WHATSOEVER RELATED TO THE INFORMATION OR
ITS USE, HOWEVER CAUSED, EVEN IF MICROCHIP HAS
BEEN ADVISED OF THE POSSIBILITY OR THE DAMAGES
ARE FORESEEABLE. TO THE FULLEST EXTENT
ALLOWED BY LAW, MICROCHIP'S TOTAL LIABILITY ON
ALL CLAIMS IN ANY WAY RELATED TO THE INFORMATION
OR ITS USE WILL NOT EXCEED THE AMOUNT OF FEES, IF
ANY, THAT YOU HAVE PAID DIRECTLY TO MICROCHIP
FOR THE INFORMATION.
Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to
defend, indemnify and hold harmless Microchip from any and
all damages, claims, suits, or expenses resulting from such
use. No licenses are conveyed, implicitly or otherwise, under
any Microchip intellectual property rights unless otherwise
stated.
Trademarks
The Microchip name and logo, the Microchip logo, Adaptec,
AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud,
CryptoMemory, CryptoRF, dsPIC, flexPWR, HELDO, IGLOO,
JukeBlox, KeeLoq, Kleer, LANCheck, LinkMD, maXStylus,
maXTouch, MediaLB, megaAVR, Microsemi, Microsemi logo,
MOST, MOST logo, MPLAB, OptoLyzer, PIC, picoPower,
PICSTART, PIC32 logo, PolarFire, Prochip Designer, QTouch,
SAM-BA, SenGenuity, SpyNIC, SST, SST Logo, SuperFlash,
Symmetricom, SyncServer, Tachyon, TimeSource, tinyAVR, UNI/O,
Vectron, and XMEGA are registered trademarks of Microchip
Technology Incorporated in the U.S.A. and other countries.
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Company, EtherSynch, Flashtec, Hyper Speed Control, HyperLight
Load, IntelliMOS, Libero, motorBench, mTouch, Powermite 3,
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TimePictra, TimeProvider, TrueTime, WinPath, and ZL are
registered trademarks of Microchip Technology Incorporated in the
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Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any
Capacitor, AnyIn, AnyOut, Augmented Switching, BlueSky,
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Programming, ICSP, INICnet, Intelligent Paralleling, Inter-Chip
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Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
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Blocker, RTAX, RTG4, SAM-ICE, Serial Quad I/O, simpleMAP,
SimpliPHY, SmartBuffer, SmartHLS, SMART-I.S., storClad, SQI,
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ViewSpan, WiperLock, XpressConnect, and ZENA are trademarks
of Microchip Technology Incorporated in the U.S.A. and other
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SQTP is a service mark of Microchip Technology Incorporated in
the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage
Technology, Symmcom, and Trusted Time are registered
trademarks of Microchip Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany
II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their
respective companies.
© 2012-2022, Microchip Technology Incorporated and its subsidiaries.
All Rights Reserved.
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality.
2012-2022 Microchip Technology Inc. and its subsidiaries
ISBN: 978-1-5224-9833-9
DS20002300D-page 57
Worldwide Sales and Service
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Tel: 91-20-4121-0141
Denmark - Copenhagen
Tel: 45-4485-5910
Fax: 45-4485-2829
China - Chongqing
Tel: 86-23-8980-9588
Japan - Osaka
Tel: 81-6-6152-7160
Finland - Espoo
Tel: 358-9-4520-820
China - Dongguan
Tel: 86-769-8702-9880
Japan - Tokyo
Tel: 81-3-6880- 3770
China - Guangzhou
Tel: 86-20-8755-8029
Korea - Daegu
Tel: 82-53-744-4301
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
China - Hangzhou
Tel: 86-571-8792-8115
Korea - Seoul
Tel: 82-2-554-7200
China - Hong Kong SAR
Tel: 852-2943-5100
Malaysia - Kuala Lumpur
Tel: 60-3-7651-7906
China - Nanjing
Tel: 86-25-8473-2460
Malaysia - Penang
Tel: 60-4-227-8870
China - Qingdao
Tel: 86-532-8502-7355
Philippines - Manila
Tel: 63-2-634-9065
China - Shanghai
Tel: 86-21-3326-8000
Singapore
Tel: 65-6334-8870
China - Shenyang
Tel: 86-24-2334-2829
Taiwan - Hsin Chu
Tel: 886-3-577-8366
China - Shenzhen
Tel: 86-755-8864-2200
Taiwan - Kaohsiung
Tel: 886-7-213-7830
Israel - Ra’anana
Tel: 972-9-744-7705
China - Suzhou
Tel: 86-186-6233-1526
Taiwan - Taipei
Tel: 886-2-2508-8600
China - Wuhan
Tel: 86-27-5980-5300
Thailand - Bangkok
Tel: 66-2-694-1351
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
China - Xian
Tel: 86-29-8833-7252
Vietnam - Ho Chi Minh
Tel: 84-28-5448-2100
Atlanta
Duluth, GA
Tel: 678-957-9614
Fax: 678-957-1455
Austin, TX
Tel: 512-257-3370
Boston
Westborough, MA
Tel: 774-760-0087
Fax: 774-760-0088
Chicago
Itasca, IL
Tel: 630-285-0071
Fax: 630-285-0075
Dallas
Addison, TX
Tel: 972-818-7423
Fax: 972-818-2924
Detroit
Novi, MI
Tel: 248-848-4000
Houston, TX
Tel: 281-894-5983
Indianapolis
Noblesville, IN
Tel: 317-773-8323
Fax: 317-773-5453
Tel: 317-536-2380
Los Angeles
Mission Viejo, CA
Tel: 949-462-9523
Fax: 949-462-9608
Tel: 951-273-7800
Raleigh, NC
Tel: 919-844-7510
New York, NY
Tel: 631-435-6000
San Jose, CA
Tel: 408-735-9110
Tel: 408-436-4270
Canada - Toronto
Tel: 905-695-1980
Fax: 905-695-2078
DS20002300D-page 58
China - Xiamen
Tel: 86-592-2388138
China - Zhuhai
Tel: 86-756-3210040
Germany - Garching
Tel: 49-8931-9700
Germany - Haan
Tel: 49-2129-3766400
Germany - Heilbronn
Tel: 49-7131-72400
Germany - Karlsruhe
Tel: 49-721-625370
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Germany - Rosenheim
Tel: 49-8031-354-560
Italy - Padova
Tel: 39-049-7625286
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Norway - Trondheim
Tel: 47-7288-4388
Poland - Warsaw
Tel: 48-22-3325737
Romania - Bucharest
Tel: 40-21-407-87-50
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
Sweden - Gothenberg
Tel: 46-31-704-60-40
Sweden - Stockholm
Tel: 46-8-5090-4654
UK - Wokingham
Tel: 44-118-921-5800
Fax: 44-118-921-5820
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09/14/21
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