1 Port PSE PoE PD69101 Controller
Introduction
DESCRIPTION
K EY F E AT UR ES
A “plug and play” device, the PD69101 executes all real time
functions as specified in the IEEE802.3af-2003 (“AF”) and
IEEE802.3at High Power (“AT”) standards, including load detection,
“AF” and “AT” classification, and using Multiple Classification
Attempts (MCA).
The PD69101 :
Is designed to detect and disable disconnected ports,
utilizing DC disconnection methods, as specified in the
IEEE 802.3af-2003 and IEEE802.3ar-2009 standards.
Can optionally detect legacy/pre-standard PD devices.
Provides PD protection such as over-load, under-load,
over-voltage, over-temperature and short-circuiting.
Supports supply voltages ranging from 44 V to 57 VDC
with no need for additional power supply sources.
Is a low power device using an internal 0.34 Ω MOSFET
and an external 0.5 Ω sense resistor.
The chip includes built-in internal thermal protection.
Two LEDs provide port state's indication and port type (AF/AT).
Fully IEEE802.3af-2003 and
IEEE802.3at-2009 compliant
Includes two-event classification
Supports pre-standard PD detection
Supports Cisco devices detection
Single DC voltage input (44 - 57 VDC)
Supports 2 Pairs and 4 Pairs (Data
and Spare Power Feeding)
VMAIN Out of Range Protection
Wide temperature range: -40° to
+85° C
Over-temperature protection
Low thermal dissipation (0.5 Ω sense
resistor)
Includes on/off command pin
2 x direct LEDs drive
Continuous port monitoring and
system data
Configurable load current setting
Configurable AT/AF modes
Configurable standard and legacy
detection mode
Power soft start mechanism
On-chip thermal protection
Voltage monitoring & protection
Built in 3.3 VDC regulator
Internal power on reset
RoHS compliant
Low Rdson FET: 0.3 Ω
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Microsemi's PD69101 is a single port, mixed-signal, high-voltage
Power over Ethernet driver. The device is utilized in Ethernet
switches and enables network devices to share power and data
over the same cable. It enables detection of IEEE802.3af-2003
compliant PDs (Powered Devices) and IEEE802.3at High Power
Devices, thus, ensuring safe power feeding and disconnection of
ports with full digital control and a minimum of external
components. Integrating power, analog and state of the art logic,
the PD69101 device fits into a single 24-pin, plastic QFN package.
IMPORTANT: For the most current data, consult MICROSEMI’s website: http://www.microsemi.com
P AC K AG E O R D ER IN FO
TA (C)
-40 to +85
Plastic 24 pin QFN 4x5
RoHS Compliant / Pb-free / MSL1
PD69101ILQ-TR
T H ERM AL D AT A
TYPICAL THERMAL RESISTANCE-JUNCTION TO AMBIENT
25° C/W
TYPICAL THERMAL RESISTANCE-JUNCTION TO CASE 4° C/W
Junction Temperature Calculation: T J = TA + (PD x JA).
The JA numbers are guidelines for the thermal
performance of the device/pc-board system. All of the
above assume no ambient airflow.
PD69101
Copyright © 2013
Microsemi
Rev. 1.7, 17-July-2013
Analog Mixed Signal Group
1 Enterprise, Aliso Viejo, CA 92656, USA; Phone (USA): (800) 713-4113, (ROW): (949) 221-7100 Fax: (949) 756-0308
1
1 Port PSE PoE PD69101 Controller
POWER DISSIPATION INFORMATION
2
Rsense Power Dissipation: 0.5 Ω x Iport
2
Rds_ON Power Dissipation: 0.3 Ω x Iport
Pport_AF = 15.4W ==> PRsense = 51 mW (320 mA)
PRds_ON = 31 mW (320 mA)
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Pport_AT = 30W
==> PRsense= 180 mW (600 mA)
PRds_ON = 108 mW (600 mA)
Typical PD69101 self power dissipation (including internal regulations) = 0.5 W (50 VDC)
Typical PD69101 @ 2 pairs AF application power dissipation = 0.5 W + 51 mW + 31 mW = 0.582 W
Typical PD69101 @ 2 pairs AT application power dissipation = 0.5 W + 180 mW + 108 mW = 0.788 W
Typical 4 pairs application, with 2 x PD69101: double the power dissipation
6
AGND
7
STD_DET / LEGACY
Master / Slave
MODE 1
MODE0
RESET_N
22
21
20
Date/Lot Code
12
VAUX5
I_REF
5
11
DRV_VAUX3P3
MSC
69101
QGND
4
10
3
PORT_SENSE
DVDD
VAUX3P3
23
2
24
1
AF/AT
9
Notes:
Exceeding these ratings can cause damage to the device. Pin Port_Sense is ESD
sensitive, pass 500V HBM. All voltages are with respect to ground. Currents are
marked positive when flowing into a specified terminal and marked negative when
flowing out of a specified terminal.
CURRENT_SET
8
-0.3 to 74 VDC
-0.3 to 74 VDC
-0.3 to 3.6 VDC
-0.3 to 0.3 VDC
-0.3V to 5.5V
-0.3 to 3.6 VDC
-40 to +85C
150 C
±2 KV HBM
-65 to +150 C
V_MAIN
Supply Input Voltage (VMAIN)
Port_Neg pin, LED0, LED1
Port_Sense Pin
QGND, AGND Pins
VAUX5
All Other Pins
Operating Ambient Temperature Range
Maximum Operating Junction Temperature
ESD Protection at all I/O Pins
Storage Temperature Range
P AC K AG E PIN O UT
PORT_NEG
AB SO L UT E M AXIM UM R AT ING S
19
DGND
18
SYNC
17
TRIM
16
N/C
15
N/C
14
LED1
13
LED0
(Top View)
RoHS / Pb-free 100% Matte Tin Finish
PD69101
Copyright © 2013
Microsemi
Rev. 1.7, 17-July-2013
Analog Mixed Signal Group
1 Enterprise, Aliso Viejo, CA 92656, USA; Phone (USA): (800) 713-4113, (ROW): (949) 221-7100 Fax: (949) 756-0308
2
1 Port PSE PoE PD69101 Controller
R O H S AN D SO L D ER R EFL OW INFO RM AT IO N
RoHS 6/6
Pb-free 100% Matte Tin Finish
Package Peak Temperature for Solder Reflow
260° C (+0° C, -5° C)
(40 seconds maximum exposure)
Notes: Exceeding these ratings can damage the device.
W W W. Microsemi .CO M
PD69101
Copyright © 2013
Microsemi
Rev. 1.7, 17-July-2013
Analog Mixed Signal Group
1 Enterprise, Aliso Viejo, CA 92656, USA; Phone (USA): (800) 713-4113, (ROW): (949) 221-7100 Fax: (949) 756-0308
3
1 Port PSE PoE PD69101 Controller
Electrical Characteristics
Unless otherwise specified, the following specifications apply to the operating ambient temperature, TAMB -40 to +85 C.
PARAMETER
SYMBOL
PD69101
CONTROLLER
MIN TYP MAX
UNIT
POWER SUPPLY
Input Voltage
VMAIN
Power Supply Current
@ Operating Mode
Supports Full IEEE802.3
functionality
44
55
VMAIN = 55 V
57
VDC
10
mA
DIGITAL I/O
Input Logic High
Threshold
Input Logic Low
Threshold
Input Hysteresis
Voltage
Input High Current
Input Low Current
VIH
2.2
VDC
VIL
0.4
0.6
0.8
VDC
0.8
VDC
IIH
-10
10
uA
IIL
-10
10
uA
Output High Voltage
VOH
For IOH = -1 mA
Output Low Voltage
VOL
IOH = 1 mA
2.4
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TEST CONDITIONS /
COMMENT
VDC
0.4
VDC
POE LOAD
CURRENTS
AT High Limit Mode
AT Medium Limit
Mode
AT Low Limit Mode
AF Limit Mode
AT_LIM_HIGH
(high current level for future use)
AT_LIM_MID
(medium current level for future use)
AT_LIM_LOW
AF_LIM
RSENSE = 0.5 Ω 1%
connected at Port_Sense
pin
1.18
1.2
1.28
A
847
874
919
mA
706
722
767
mA
410
425
448
mA
MAIN POWER
SWITCHING FET
On Resistance
Internal Thermal
Protection Threshold
RDSON
0.3
Ω
200
°C
LED0 AND LED1
DRIVERS
Current Sink
I sink (from Vmain to AGND)
3
5
mA
PD69101
Copyright © 2013
Microsemi
Rev. 1.7, 17-July-2013
Analog Mixed Signal Group
1 Enterprise, Aliso Viejo, CA 92656, USA; Phone (USA): (800) 713-4113, (ROW): (949) 221-7100 Fax: (949) 756-0308
4
1 Port PSE PoE PD69101 Controller
Dynamic Characteristics
The PD69101 utilizes three current level thresholds (Imin, Icut, Ilim) and three timers (Tmin, Tcut, Tlim).
Loads that consume Ilim current for more than Tlim are labeled as 'short circuit state' and shutdown.
Loads that dissipate more than Icut for longer than Tcut are labeled as ‘overloads’ and are shutdown.
Table 1: IEEE802.3 AF Mode Parameters
PARAMETER
CONDITIONS
Automatic Recovery from Noload Shutdown
Cutoff timers Accuracy
TUDLREC value, measured from port shutdown
point (can be modified through control port)
Typical accuracy of Tcut
Inrush Current
Output Current Operating
Range
Output Power Available
Operating Range
Off mode Current
IInrsh
Iport
TPMDO
For t=50 ms, Cload=180 uF max.
Continuous operation after startup
period.
Continuous operation after startup
period, at port output.
Must disconnect for T greater than
TUVL
May or may not disconnect where
T is greater than TUVL
Buffer period to handle transitions
Icut
Time limited to TOVL
TOVL
Trise
From 10% to 90% of Vport
Pport
Imin1
Imin2
PD Power Maintenance
Request Drop-out Time Limit
Over-load Current Detection
Range
Over Load Time Limit
Turn On Rise Time
(Specified for PD load consisting of 100 uF
capacitor in parallel to 200 ).
Turn Off Time
Time Maintain Power
Signature
Toff
TMPS
From Vport to 2.8 Vdc
DC modulation time for DC
disconnect
MIN.
TYP.
MAX.
1
UNIT
Sec
400
2
450
ms
mA
10
375
mA
0.57
15.4
W
0
5
mA
10
mA
300
400
ms
350
400
mA
50
75
ms
5
7.5
15
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If output power is below Imin for more than Tmin, the PD is labeled as ‘no-load’ and is shutdown.
Automatic recovery from over-load and no-load conditions is attempted every TOVLREC periods (typically 1 second).
Output power is limited to Ilim, which is a maximum peak current allowed at the port.
us
500
49
ms
ms
PD69101
Copyright © 2013
Microsemi
Rev. 1.7, 17-July-2013
Analog Mixed Signal Group
1 Enterprise, Aliso Viejo, CA 92656, USA; Phone (USA): (800) 713-4113, (ROW): (949) 221-7100 Fax: (949) 756-0308
5
1 Port PSE PoE PD69101 Controller
Table 2: IEEE802.3 AT Mode Parameters
CONDITIONS
TUDLREC value; measured from port shutdown
point (can be modified through control port)
Typical accuracy of Tcut
Inrush Current
IInrsh
Output Current Operating
range
Output Power Available,
Operating Range
Off Mode Current
Iport
TPMDO
For t = 50 ms, Cload = 180 uF
max.
Continuous operation after startup
period
Continuous operation after startup
period at port output
Must disconnect where T is greater
than TUVL
May or may not disconnect where
T is greater than TUVL
Buffer period to handle transitions
Icut
Time limited to TOVL
TOVL
Trise
From 10% to 90% of Vport
Pport
Imin1
Imin2
PD Power Maintenance
request drop-out time limit
Over-load Current
detection range
Over-load Time Limit
Turn on Rise Time
Turn Off Time
Time Maintain Power
Signature
Toff
TMPS
MIN.
TYP.
From Vport to 2.8 Vdc
DC modulation time for DC
disconnect
UNIT
1
s
2
ms
400
450
mA
10
725
mA
36.25
W
5
mA
10
mA
400
ms
600
mA
75
ms
0.57
0
5
7.5
300
50
(Specified for PD load consisting of 100 uF
capacitor in parallel to 200 ).
MAX.
15
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PARAMETER
Automatic Recovery from
No-load Shutdown
Cutoff Timers Accuracy
us
500
49
ms
ms
PD69101
Copyright © 2013
Microsemi
Rev. 1.7, 17-July-2013
Analog Mixed Signal Group
1 Enterprise, Aliso Viejo, CA 92656, USA; Phone (USA): (800) 713-4113, (ROW): (949) 221-7100 Fax: (949) 756-0308
6
1 Port PSE PoE PD69101 Controller
Detailed Pinout Description
PIN
PIN NAME
PIN TYPE
DESCRIPTION
Analog Gnd
1
CURRENT_SET
Digital Input
2
AF/AT
Digital Input
3
DVDD
Power In
4
VAUX3P3
Power In
5
DRV_VAUX3P3
Power Out
6
VAUX5
Power
7
AGND
Power
8
V_MAIN
Power
9
PORT_NEG
Analog I/O
10
PORT_SENSE
Analog Input
11
QGND
Power
12
I_REF
Analog I/O
Resistor reference. Connect 30.1 K 1% resistor to QGND.
13
LED0
14
LED1
Open Drain
I/O
Open Drain
I/O
Port Status Direct LED indications – see detailed table description.
This is a High voltage, Open drain, Active low (SINK) output pin.
Recommended to be connected to LED and Vmain through a
~18.2 Kohm (~3 mA) resistor
15
N/C
Analog I/O
16
N/C
Analog I/O
Test pin; for production use only.
Keep open; not connected.
17
TRIM
Analog Input
18
SYNC
Digital I/O
19
20
21
DGND
RESET_N
MODE 0
Digital I/O
Digital Input
Test I/O
22
MODE 1
Test I/O
23
Master/Slave
Digital Input
Zapping Input for IC production trimming.
Should be connected to DVDD.
Synchronization open drain IO pin between master and slave, for 4Pair applications
In ALT A 2 Pair mode (Switch) this pin should be pulled down to
DGND via a 4.7 Kohm resistor.
In 4 Pair mode, connect the SYNC pin of Master and Slave and pull it
up to the DVDD with 4.7 Kohm resistor
Digital GND.
Reset input / On-Off command (Active Low).
Configuration Input Pins: Used to set Mode of operation and Test
mode at production.
Typically connected to DGND.
See Table Below
If connected to DVDD (3.3 VDC): Master mode
If connected to GND: Slave mode (4 Pair application)
Copyright © 2013
Microsemi
Rev. 1.7, 17-July-2013
Analog Mixed Signal Group
1 Enterprise, Aliso Viejo, CA 92656, USA; Phone (USA): (800) 713-4113, (ROW): (949) 221-7100 Fax: (949) 756-0308
7
PD69101
Exposed PAD
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0
Exposed PAD; metal plate on the IC bottom side connected to
analog ground.
A high quality ground plane (about 500 mil inch over 500 mil inch)
should be deployed around this pin whenever possible.
User input to set AF / AT and maximum current limit.
Use Pull-up resistors to DVDD or Pull-Down resistors to DGND to set
mode of operation according to the detailed tables (page 4).
Regulated Input Voltage (3.3 V) for internal digital circuitry.
Should be externally connected to pin 4.
Voltage regulation in 3.3 VDC.
To be connected to pin 5.
A 4.7 uF capacitor to AGND is recommended.
Internal voltage regulator out 3.3 VDC.
To be connected externally to pin 4.
Regulated 5 VDC voltage filter.
A 1 uF capacitor to AGND is recommended.
Analog GND
Supply voltage for the internal analog circuit. Place a low ESR
bypass capacitor, not less than 1 uF, as close as possible to AGND
and this pin with low impedance traces.
Negative output of the port.
Sense resistor port input (connected to 0.5, 1% Ohm resistor to
GND).
Quiet analog ground: used for sensitive analog cells.
1 Port PSE PoE PD69101 Controller
PIN
24
PIN NAME
STD_DET / LEGACY
PIN TYPE
Digital Input
DESCRIPTION
User input pin to set chip mode of operation.
“1”: DVDD = IEEE802.3af compliant resistor detection only
“0”: DGND = AF / AT Detection and Legacy (non-standard)
line detection
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Additional Pin Description and Notes
Note:
“0” = Connect to DGND
“1” = Connect to DVDD
CURRENT_SET and AF/AT pins determine the typical PD Load output current as detailed in the following coding:
AT/AF
PIN
CURRENT_SET
PIN
CONTINUE MAX
CURRENT
I CUT [MA]
TYPICAL I
LIM
[MA]
IEEE802.3
0
1
1
0
0
0
1
1
350
600
720
1000
425
722
874
1200
AF mode (standard)
AT mode (standard)
AT mode (high power)
AT mode (extra high power)
Configuration / Mode of Operation Coding:
MODE 0
MODE 1
MODE
0
0
Normal operation Mode
0
1
Serial Monitoring Mode
1
0
Test Logic Mode
1
1
JTAG Mode
DESCRIPTION
Standard Operation POE Mode – LED0 and LED1
Outputs are used for Direct LED Drive as listed below
Standard Operation POE Mode – LED0 and LED1
are used to Continuously Streaming Out Internal
Logic Signals for POE Monitoring
Internal IC Logic Test Mode –
Used in production only
Internal IC Logic Test Mode –
Used in production only
LED I/Os Behavior
LED pin is a high voltage Open Drain output pin.
LED pin is an Active Low (SINK) pin LED is “ON” when I/O is pulled Low.
PD69101
Copyright © 2013
Microsemi
Rev. 1.7, 17-July-2013
Analog Mixed Signal Group
1 Enterprise, Aliso Viejo, CA 92656, USA; Phone (USA): (800) 713-4113, (ROW): (949) 221-7100 Fax: (949) 756-0308
8
1 Port PSE PoE PD69101 Controller
Table 3: 2 Pair Behaivor
STATUS INDICATIONS
LED1
AF Mode – Port “ON”
ON
OFF
AT Mode (Class AT was
detected) - Port “ON”
ON
ON
AF Mode – Over-load or short
Blink 1 Hz
OFF
AT Mode – Over-load or short
Blink 1 Hz
Blink 1 Hz
Vmain Voltage out of range or IC
over-temperature
Blink 4 Hz
OFF
AF Mode – Port “OFF”
OFF
ON
AT Mode – Port “OFF”
OFF
OFF
LED0
LED1
OFF
ON
ON
OFF
OFF
Blink 1 Hz
Blink 4 Hz / 1Hz
OFF
OFF
OFF
NOTES
Useful for Bicolor LED
connected from LED0 to
LED1
W W W. Microsemi .CO M
LED0
Blinking continues for
~ 2 sec
Blinking continues for
~ 2 sec
Blinking continues as long
as over-voltage or overtemperature state exists
Useful for Bicolor LED
connected from LED0 to
LED1
Table 4: 4 Pair Behavior (2 x PD69101 ICs)
STATUS INDICATIONS
Master IC “ON and Slave IC
“ON”
Only Master IC “ON
(Slave IC “OFF”)
Master and Slave ICs are both
“OFF” due to Overload or Short
Vmain Voltage out of range or IC
over-temperature
Master IC “OFF” and Slave IC
“OFF”
NOTES
Blinking continues for
~ 2 sec after overload /
short event
Master IC fail: blink 4 Hz
Slave IC fail: blink 1 Hz
Blinking continues for
~ 2 sec
PD69101
Copyright © 2013
Microsemi
Rev. 1.7, 17-July-2013
Analog Mixed Signal Group
1 Enterprise, Aliso Viejo, CA 92656, USA; Phone (USA): (800) 713-4113, (ROW): (949) 221-7100 Fax: (949) 756-0308
9
1 Port PSE PoE PD69101 Controller
PD69101 - Package Description
LQ
24-Pin QFN 4x5mm
L
D2
E
E2
b
e
K
A3
A
MILLIMETERS
MIN
MAX
INCHES
MIN
MAX
A
A1
A3
K
e
L
b
D2
E2
D
E
0.80
1.00
0.00
0.05
0.20 REF
0.20 MIN
0.50 BSC
0.30
0.50
0.18
0.30
2.50
2.75
3.50
3.75
4.00 BSC
5.00 BSC
0.031 0.039
0
0.002
0.008 REF
0.008 MIN
0.02 BSC
0.012
0.02
0.007 0.012
0.098 0.108
0.138 0.148
0.158 BSC
0.197 BSC
W W W. Microsemi .CO M
D
DIM
Note:
A1
Dimensions do not include protrusions; these shall not exceed
0.155mm (.006”) on any side. Lead dimension shall not include
solder coverage.
PD69101
Copyright © 2013
Microsemi
Rev. 1.7, 17-July-2013
Analog Mixed Signal Group
1 Enterprise, Aliso Viejo, CA 92656, USA; Phone (USA): (800) 713-4113, (ROW): (949) 221-7100 Fax: (949) 756-0308
10
1 Port PSE PoE PD69101 Controller
PD69101 - Internal Block Diagram
The PD69101 is based on two major sections (see Figure 1):
RESET_N
AF/AT
Res/ResCap
Master / Slave
V_main
Vaux5
DRV_Vaux3p3
Vaux3p3
DVDD
Clk_
block
W W W. Microsemi .CO M
SYNC
Current_SET
1. A Digital section which controls and monitors the logical PoE functions (state machines, timings etc.)
2. An Analog section which performs the Front End analog PoE functionality.
Digital
Analog
Voltage
Regulator
CLK
POR
RTP
Idle
macro
MODE 0
Dv/dt
macro
MODE 1
Main Control
Module
Parameters
i/f
POE Front End Module
Cap
det
macro
Class
macro
Classification
Voltage Generator
Analog
Mesurment
Analog
cntrl i/f
Line Detection
Generator
Thermal
Protection
Res
Det
macro
LED
cntrl
VMC
(Vmain
cntrl)
Pre
Det
macro
Adc_block
Controlled
Reference
ADC
Current Limiter
Main MOSFETs
Port_Neg
LED0
LED1
Over temp
DGND
QGND
Port_Sense
I_REF
Sense Resistor
Figure 1: PD69101 Internal Block Diagram
PD69101
Copyright © 2013
Microsemi
Rev. 1.7, 17-July-2013
Analog Mixed Signal Group
1 Enterprise, Aliso Viejo, CA 92656, USA; Phone (USA): (800) 713-4113, (ROW): (949) 221-7100 Fax: (949) 756-0308
11
1 Port PSE PoE PD69101 Controller
Logic Main Control Module
Voltage Regulator
The Logic Main Control Block includes the Digital
Timing Mechanisms and State Machines,
synchronizing and activating the PoE functions such
as:
The voltage regulator generates 3.3 VDC and 5 VDC
for the internal circuitry. These voltages are derived
from the Vmain supply.
Real Time Protection (RTP)
Start Up Macro (DVDT)
Load Signature Detection (RES DET)
Classification Macro (CLASS)
Voltage and Current Monitoring Registers
(VMC)
LEDs Stream Out Control Indications
ADC Interfacing
Direct Digital Signals with Analog Block
CLK
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CLK is an internal 8 MHz clock oscillator.
Line Detection Generator
Upon request from the Main Control Module, four
different voltage levels are generated by the Line
Detection Generator, ensuring robust AF / AT Line
Detection functionality.
Classification Generator
Upon request from the Main Control Module, the State
Machine applies a regulated Class Event and Mark
Event voltages to the ports, as required by the IEEE
standard.
Current Limiter
This circuit continuously monitors the current of
powered ports and limits the current to a specific value,
according to pre-defined limits as set by AF/AT and
Current_Set pins. In cases where the current exceeds
this specific level, the system starts measuring the
elapsed time. If this time period is greater than a
preset threshold, the port is disconnected.
Main MOSFET
Main power switching FET, used to control PoE current
into the load.
ADC
A 10-Bit Analog to Digital converter, used to convert
analog signals into digital registers for the Logic Control
module.
Power on Reset (POR)
Copyright © 2013
Microsemi
Rev. 1.7, 17-July-2013
Analog Mixed Signal Group
1 Enterprise, Aliso Viejo, CA 92656, USA; Phone (USA): (800) 713-4113, (ROW): (949) 221-7100 Fax: (949) 756-0308
PD69101
This circuit monitors the internal 3.3 V voltage DC
levels. If this voltage drops below specific thresholds, a
reset signal is generated and the PD69101s are reset.
12
1 Port PSE PoE PD69101 Controller
Line Detection
Theory of Operation
Power
“ON”
v
2 Events
Classification Phase
W W W. Microsemi .CO M
The PD69101 performs IEEE802.3af, IEEE802.3at
functionality as well as legacy (capacitor) and Cisco’s
PDs detection, as well as additional protections such
as short circuit and dV/dT protection upon startup.
The Line Detection feature detects a valid AF or AT
load, as specified in the AF / AT standard. Resistor
value should range from 19 kΩ to 26.5 kΩ. Line
detection is based on four different voltage levels
generated over the PD (the load) as illustrated in
Figure 2.
Power
“OFF”
Start-Up
(Inrush)
Detection
Phase
t
Copyright © 2013
Microsemi
Rev. 1.7, 17-July-2013
Analog Mixed Signal Group
1 Enterprise, Aliso Viejo, CA 92656, USA; Phone (USA): (800) 713-4113, (ROW): (949) 221-7100 Fax: (949) 756-0308
13
PD69101
Figure 2: Typical PoE Voltage Time Diagram
During this period current is limited to 425 mA for a
Legacy (Cap) Detection
typical duration of 65 mS, which enables the PD load to
In cases where pin 24 (LEGACY) is set to “0”, the
charge and to enter a steady state power condition.
PD69101's detection mechanism is configured to
Over-Load Detection and Port Shut Down
detect and power up LEGACY PDs, as well as AF/AT
compliant PDs.
After power up, the PD69101 automatically initializes
This mechanism detects and powers up CISCO Legacy
its internal protection mechanisms utilized to monitor
PDs as well.
and disconnect power from the load in cases where
extreme conditions such as over-current or short ports
Classification
terminals scenario occur, as specified in the
The classification process takes place right after the
IEEE802.3AF/AT standard.
resistor detection, when the resistor detection has
Disconnect Detection
completed successfully. The main goal of the
classification process is to detect the PD class, as
The PD69101 supports DC Disconnect function as per
specified in the IEEE802.3AF and AT standards.
the IEEE802.3AF/AT standard.
In the AF mode the classification mechanism is based
This mechanism continuously monitors load current
on a single voltage level (single finger).
and disconnects power in cases where load current is
below 7.5 mA (typ.) for more than 322 mS.
In the AT mode classification mechanism is based on
two voltage levels (dual finger) as defined in the
Over-temperature Protection
IEEE802.3at-2009.
The PD69101 has internal temperature sensors that
Port Start Up
continuously monitor junction temperature and
disconnect load power when the junction temperature
Upon a successful Detection and Classification
exceeds 200° C. This mechanism protects the device
process, power is applied to the load via a controlled
from extreme events, such as high ambient
Start Up mechanism.
1 Port PSE PoE PD69101 Controller
temperature or other thermo-mechanical failures that
may damage the PD69101.
valuable feature which protects the load if the main
power source is faulty or damaged.
VMAIN Out of Range Protection
W W W. Microsemi .CO M
The PD69101 automatically disconnects port power
when Vmain exceeds 60 VDC. This is an extremely
TYPICAL 2 PAIRS APPLICATION
This typical application Illustrates a simple “plug and play” Power Over Ethernet solution for a single Ethernet port
switch or hub.
“POS” and “NEG” signals should be connected to the switch RJ45 Jack.
AF and AT modes of operations are set through AF/AT and current set pins (DGND or DVDD).
44v – 57v
POS
1u
100v
1uF
VAUX5
VAUX3P3
DRV_VAUX3P3
DVDD
TRIM
4.7uF
DVDD
DGND / DVDD
DGND / DVDD
DGND / DVDD
4.7K
NEG
vmain
Pull Up
10K
Reset_N
10nF
Port_Neg
I_REF
Rref
30.1K
47nF
100v
V_MAIN
Pull Down
Port_Sense
Master / Slave
AF/AT
STD_DET
LED0
Current Set
LED1
Sync
AGND QGND DGND
0.5 ohm
1%
vmain
RES
RES
Rsense
Figure 3: Typical 2 Pair Application
* For detailed application's schematics and layout recommendations, contact sales_AMSG@microsemi.com.
PD69101
Copyright © 2013
Microsemi
Rev. 1.7, 17-July-2013
Analog Mixed Signal Group
1 Enterprise, Aliso Viejo, CA 92656, USA; Phone (USA): (800) 713-4113, (ROW): (949) 221-7100 Fax: (949) 756-0308
14
1 Port PSE PoE PD69101 Controller
TYPICAL 4 PAIRS APPLICATION
This typical application Illustrates a master / slave “plug and play” Power over Ethernet solution for 4 Pairs (date and
spare Wires) Ethernet port switch or hub.
“POS” and “NEG” signals are connected to the switch RJ45 jack via line transformers.
AF and AT modes of operations are set through AF/AT and current set pins (DGND or DVDD).
Master
Vmain
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The SYNC pins are used to synchronize the PD69101 Master to the PD69101 Slave so that line detection,
classification, power on and power off events are inline with the load.
POS
1uF
VAUX5
MAIN
DVDD
VAUX3P3
DRV_VAUX3P3
Trim
Port_Neg
IREF
Mode0
Port_Sense
Mode1
4.7 uF
30.1KΏ
47nF
NEG
0.5Ώ
Slave
LEDs
RESET_N
Master/Slave
LED0
RES/CAP
LED1
AF/AT
Current Set
GND QGND
SYNC
RES/ CAP
AF/AT
Current Set
Data Pair
Line
trans.
LEDs
1 uF
Vmain
DATA +
POWER
OUT
POS
1uF
30.1KΏ
Mode0
Mode1
47nF
Spare Pair
NEG
Port_Sense
RESET_N
Master/Slave
LED0
RES/CAP
LED1
AF/AT
Current Set
GND QGND
SYNC
0.5Ώ
LEDs
4.7 uF
VAUX5
MAIN
DVDD
VAUX3P3
DRV_VAUX3P3
Trim
Port_Neg
IREF
LEDs
I uF
Figure 4: Typical 4 Pair Application
* For detailed application's schematics and layout recommendations, contact sales_AMSG@microsemi.com.
PD69101
Copyright © 2013
Microsemi
Rev. 1.7, 17-July-2013
Analog Mixed Signal Group
1 Enterprise, Aliso Viejo, CA 92656, USA; Phone (USA): (800) 713-4113, (ROW): (949) 221-7100 Fax: (949) 756-0308
15
1 Port PSE PoE PD69101 Controller
4 PAIR TYPICAL TIMING DIAGRAM
W W W. Microsemi .CO M
SYNC
Signal
master
startup
ongoing
Class
detection
t
slave
Class
detection
slave waits for 16
consecutive clks of
sync high
(~2usec)
t
456 msec detection cycle
Figure 5: 4 Pair Timing Diagram
Serial Communication - Monitoring Mode
When Mode0 and Mode1 Input pins are configured to Serial Monitoring Mode (“01”), the PD69101 transmits out
(continuously and repeatedly) the content of 9 internal registers:
Data Out Stream is transmitted through LED1 (pin 14)
Clock Out Stream is transmitted through LED0 (pin 13)
Data stream is shifted out with a 1 MHz clock (1 µsec).
Total transaction packet length is 116 µsec.
The transmission is repeated every 1 msec.
Between transactions the clock is held low, while data stream out is stable high/low.
Note: To exploit LED1 and LED0 to communicate and monitor transmissions, use a 1 KΩ pull-up resistor to the DVDD.
Copyright © 2013
Microsemi
Rev. 1.7, 17-July-2013
Analog Mixed Signal Group
1 Enterprise, Aliso Viejo, CA 92656, USA; Phone (USA): (800) 713-4113, (ROW): (949) 221-7100 Fax: (949) 756-0308
16
PD69101
1 Port PSE PoE PD69101 Controller
Table 5: Stream Out Data Transmits 116 bits Starting from MSB to LSB
MSBYTE
I N TE RN AL
0
13 BITS
I N TE RN AL
1
10 BITS
I N TE RN AL
2
23 BITS
I N TE RN AL
3
16 BITS
I N TE RN AL
4
16 BITS
VM AI N
IPORT
10 BITS
10 BITS
Port voltage
measurement
Vmain
voltage
measurement
13 BITS
Port current
measurement
LSB = 58 mV
LSB = 58 mV
V = Decimal x
58 mV
V = Decimal
x 58 mV
LSB =
238 uA
I = Decimal x
238 uA
LSBYTE
PORT
S T ATU S
5 BITS
Real time
port status
indication
See
coding
table
below
Table 6: Port Status Coding
BINARY MSB TO LSB
DECIMAL VALUE
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01100
01011
01101
01110
01111
10000
10001
10010
10011
10100
0
1
2
3
4
5
6
7
8
9
10
12
11
13
14
15
16
17
18
19
20
DESCRIPTION
POE idle state
Searching phase
Res detection phase
W W W. Microsemi .CO M
78 internal signals used for internal tests
VPORT
Back off phase
Class phase
Wait for start up
Cap detection
Start up
On going
UDL
Overload or short circuit
Vmain out of range
116 x clk cycles
Clock Out
(Pin 13)
Data Out
(Pin 14)
9
8
1
MSB
78 x
Internal BITS
0
9
LSB
MSB
8
Vport Measure
1
0
4
LSB
MSB
3
2
1
0
LSB
Port Status
PD69101
Figure 6: Data Stream Out
Copyright © 2013
Microsemi
Rev. 1.7, 17-July-2013
Analog Mixed Signal Group
1 Enterprise, Aliso Viejo, CA 92656, USA; Phone (USA): (800) 713-4113, (ROW): (949) 221-7100 Fax: (949) 756-0308
17
1 Port PSE PoE PD69101 Controller
Clock Out
(Pin 13)
1mS
116uS
Data Packet
Idle
116uS
Data Packet
W W W. Microsemi .CO M
Figure 7: Multi Packet Idle Time (Between Packets)
Clock Out
(Pin 13)
Data Out
(Pin 14)
500nS 500nS
Typ Typ
Figure 8: Data / Clock Typical Timing
PD69101
Copyright © 2013
Microsemi
Rev. 1.7, 17-July-2013
Analog Mixed Signal Group
1 Enterprise, Aliso Viejo, CA 92656, USA; Phone (USA): (800) 713-4113, (ROW): (949) 221-7100 Fax: (949) 756-0308
18
1 Port PSE PoE PD69101 Controller
W W W. Microsemi .CO M
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PROPRIETARY AND CONFIDENTIAL information of Microsemi and cannot be copied, published, uploaded, posted,
transmitted, distributed or disclosed or used without the express duly signed written consent of Microsemi. If the
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Microsemi reserves the right to change the configuration, functionality and performance of its products at anytime
without any notice. This product has been subject to limited testing and should not be used in conjunction with lifesupport or other mission-critical equipment or applications. Microsemi assumes no liability whatsoever, and Microsemi
disclaims any express or implied warranty, relating to sale and/or use of Microsemi products including liability or
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Revision History
Revision Level / Date
Para. Affected
Description
1.0 / March 2010
Official Release
1.1 / March 2010
Added wave forms + last functionality update according to evaluation results
1.2 / June 2010
Package drawing update
1.3 / June 2010
Parameters update
1.4 / Sep 2010
Parameters update
1.5 / Dec 2010
Parameters update
1.6 / July 2013
IC marking update
1.7 / July 2013
Add TETA JC data
© 2010 Microsemi Corp.
PD69101
All rights reserved.
For support contact: sales_AMSG@microsemi.com
Visit our web site at: www.microsemi.com
Copyright © 2013
Microsemi
Rev. 1.7, 17-July-2013
Analog Mixed Signal Group
1 Enterprise, Aliso Viejo, CA 92656, USA; Phone (USA): (800) 713-4113, (ROW): (949) 221-7100 Fax: (949) 756-0308
19
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