SY88053CLMG

SY88053CL 1.0625G to 12.5G Limiting Post Amplifier with Programmable Decision Threshold Revision 1.0 General Description The SY88053CL limiting post amplifier is designed for use in fiber-optic receivers for multi-rate applications from 1.0625Gbps to 12.5Gbps. The SY88053CL contains a high-bandwidth, highsensitivity input stage with user-programmable, wide-range SD assert/LOS de-assert threshold levels, which enables optimized system reach. Typically, 4dB of electrical hysteresis is provided to minimize LOS or SD chattering caused by noisy input signals. A logic level control pin is provided to enable user selection of an open-collector, TTL-compatible LOS or SD status indication signal with an external 5kΩ to 10kΩ pull-up resistor. The SY88053CL provides fast SD assert and LOS deassert times over the entire differential input voltage range of 5mVPP to 1800mVPP. The SY88053CL input stage also provides a useradjustable decision threshold circuit to optimize BER in noisy applications such as WDM, where EDFA and Raman amplifiers contribute uneven noise levels. By applying an external control voltage, the decision threshold can typically be adjusted from 30% to 70% from the nominal 50% threshold when the circuit is disabled. The SY88053CL provides integrated 50Ω input and output impedances to optimize the high-speed signal paths and reduce component count. The post amplifier outputs have user-selectable polarity inversion control to simplify PCB layout. A TTL-compatible JAM input is provided to enable a SQUELCH function by feeding back the LOS or SD signal. The JAM input disables only the post amplifier output. The SY88053CL operates from a single +3.3V power supply, over temperatures ranging from –40°C to +85°C. Datasheets and support documentation are available on Micrel’s web site at: www.micrel.com. Features • Multi-rate operation from 1.0625Gbps to 12.5Gbps • Adjustable decision threshold level for offset compensation or BER optimization • Wide differential input range (5mVPP to 1800mVPP) • Wide SD de-assert or LOS assert threshold range − 3mVPP to 30mVPP − 4dB typical electrical hysteresis • Fast SD assert and LOS de-assert times − 75ns typical; 120ns maximum • Selectable LOS or SD status signal indicator • Selectable RXOUT+/RXOUT− polarity inversion • TTL-compatible JAM input with internal pull-up • Low-noise CML data inputs with integrated 50Ω termination impedance to internal reference VREF • Low-noise CML data outputs with integrated 50Ω termination impedance − 25ps typical rise/fall times • Wide range power supply: 3.3V ±10% • Industrial temperature range: −40°C to +85°C • Available in a tiny 3mm x 3mm QFN package Applications • • • • • • Asymmetrical/Symmetrical 10GEPON Asymmetrical/Symmetrical XGPON 10Gigabit Ethernet 8Gbps and 10Gbps Fibre Channel SONET OC192; SDH STM64 WDM/DWDM systems Markets • • • • • • PON/FTTx Datacom/Enterprise Storage area networks High-performance computing Telecom 8G+ Optical transceivers . Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com July 3, 2013 Revision 1.0 FOMhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY88053CL Typical Application Circuit – Fixed Decision Threshold Typical Application Circuit – Adjustable Decision Threshold July 3, 2013 2 Revision 1.0 FOMhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY88053CL Ordering Information Part Number SY88053CLMG (1) SY88053CLMG TR Package Type Operating Range Package Marking Lead Finish 3mm x 3mm QFN-16 Industrial 053C with Pb-Free bar line indicator NiPdAu Pb-Free 3mm x 3mm QFN-16 Industrial 053C with Pb-Free bar line indicator NiPdAu Pb-Free Note: 1. Tape and reel. Pin Configuration 16-Pin 3mm x 3mm QFN (Top View) July 3, 2013 3 Revision 1.0 FOMhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY88053CL Pin Description Pin # Pin Name Pin Type Functional Description 1 GND Negative Supply Rail 2 RXIN+ High-Speed Data Input Differential noninverting data input. LVPECL/CML compatible. AC-coupled with 100nF (high-frequency, low-ESR capacitor is recommended). Internally terminated with 50Ω to VCC – 1.2V. AC-coupled only. 3 RXIN− High-Speed Data Input Differential inverting data input. LVPECL/CML-compatible. AC-coupled with 100nF (high-frequency, low-ESR capacitor is recommended). Internally terminated by 50Ω to VCC – 1.2V. AC-coupled only. 4 GND Negative Supply Rail Negative supply rail. Connect to the PCB negative power supply plane that is also connected to the ePAD. 5 VTHN Analog Voltage Input Analog control input. Connect to VTH_REF for crossing threshold adjustment using VTHP (pin 16). Connect to GND to disable crossing point adjustment capability. 6 VTH_REF Analog Current Output Reference voltage. 1.25V reference with respect to GND for crossing point decision threshold adjustment. 7 SD/LOS Open Collector Logic Output Output status indicator. Loss of signal (LOS) or signal detect (SD) open collector output externally terminated with 5kΩ to 10kΩ resistor to VCC. TTLcompatible logic levels. Negative supply rail. Connect to the PCB negative power supply plane that is also connected to the ePAD. LOS = High when RXIN+/RXIN− amplitude falls below the threshold set at the SD/LOSLVL pin. SD = Low when RXIN+/RXIN− amplitude falls below the threshold set at the SD/LOSLVL pin. 8 SD/LOSLVL Analog Input 9, 12 VCC Positive Supply Rail 10 RXOUT− High-Speed Data Output Differential inverting data output (default). CML-compatible and internally terminated by 50Ω to VCC. Can be AC or DC-coupled to downstream devices. Can be inverted using the RXOUT_INV control pin. 11 RXOUT+ High-Speed Data Output Differential noninverting data output (default). CML-compatible and internally terminated by 50Ω to VCC. Can be AC or DC-coupled to downstream devices. Can be inverted using the RXOUT_INV control pin. 13 RXOUT_INV Logic Level Input Input control signal. TTL-compatible logic input signal to invert the polarity of the RXOUT+/− signals. Internal ~18kΩ pull-up to VCC. Analog control input. Sets the trigger threshold for the LOS or SD status indicator signals. If SD/LOS_SEL = High (LOS selected), connect a resistor from the SD/LOSLVL pin (loss of signal threshold level) to VCC to adjust the LOS_Assert threshold for the RXIN+/RXIN− data inputs. If SD/LOS_SEL = Low (SD selected), connect a resistor from the SD/LOSLVL pin (signal select level) to VCC to adjust the SD_de-assert threshold for the RXIN+/RXIN− data inputs. Positive power supply input. Bypass with a 0.1µF capacitor in parallel with a 0.01µF low-ESR capacitor to GND as close as possible to the VCC pin. Default = High (NC): Pin10 = RXOUT− and pin11 = RXOUT+ RXOUT_INV = Low: Pin10 = RXOUT+ and pin11 = RXOUT−. 14 July 3, 2013 SD/LOS_SEL Logic Level Input Input control signal. TTL-compatible logic input signal to select LOS or SD as the output signal. Internal ~18kΩ pull-up to VCC. Default = High (NC): LOS selected – normal operation LOS/SD_SEL = Low: SD selected and JAM operation is inverted 4 Revision 1.0 FOMhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY88053CL Pin # Pin Name Pin Type 15 JAM Logic Level Input Functional Description Input control signal. TTL-compatible input signal that enables or disables the RXOUT+/− output signals. Internal 27kΩ pull-up resistor to VCC. Can be connected to SD/LOS to form a SQUELCH function. When SD/LOS_SEL = High Default = High and RXOUT+/− outputs are disabled. Low = RXOUT+ and RXOUT− outputs are enabled Operation is inverted when SD/LOS_SEL = Low and SD is selected. 16 VTHP Analog Voltage Input Analog control voltage input that typically adjusts the crossing point threshold from 30% to 70%. Threshold crossing adjustment control. Apply a DC-control voltage from 0V to 2.4V to adjust the crossing point. VTHN (pin 6) must be connected to VTH_REF (pin 7). Nominal 50% midpoint decision threshold occurs with VTHP = 1.25V. Connect to ground to disable decision threshold (crossing point) adjust capability. ePAD GND Negative Supply Rail Exposed thermal pad. Must be soldered to PCB plane connected to the negative supply rail. The recommended via array is needed to remove heat from the device. July 3, 2013 5 Revision 1.0 FOMhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY88053CL Absolute Maximum Ratings(2) Operating Ratings(3) Supply Voltage (VCC) ......................................... 0V to +4.0V Input Voltage (RXIN+, RXIN−) ................. VCC – 1.5V to VCC CML Output Voltage (VOUT)……....VCC − 1.0V to VCC + 0.5V VVTH_REF Current ..................................... −800µA to +500µA JAM Voltage ........................................................... 0 to VCC SD/LOSLVL Voltage ................................ VCC – 1.3V to VCC Lead Temperature (soldering, 20s) ............................ 260°C Storage Temperature (Ts) ......................... –65°C to +150°C Supply Voltage (VCC) .................................... +3.0V to +3.6V Ambient Temperature (TA) .......................... –40°C to +85°C Junction Temperature (TJ) ........................ –40°C to +125°C (4) Package Thermal Resistance .........3mm x 3mm QFN-16 (θJA) Still-air ........................................................ 60°C/W (ψJB) ................................................................... 33°C/W DC Electrical Characteristics VCC = 3.0 to 3.6V; TA = –40°C to +85°C, typical values at VCC = 3.3V, TA = 25°C. Symbol Parameter Condition Min. ICC Power Supply Current Note 5 SD/LOSLVL SD or LOS Threshold Voltage VOH RXOUT+/RXOUT− High Voltage VCC − 0.020 VOL RXOUT+/RXOUT− Low Voltage VCC − 0.400 VOFFSET Differential Output Offset VVTH_REF Decision Threshold Reference Voltage Typ. Max. Units 58 75 mA VCC V VCC − 0.005 VCC V VCC − 0.350 VCC − 0.300 V ±80 mV VCC − 1.3 VTHP and VTHN tied to GND 1.25 V Z0 Single-Ended Output Impedance 45 50 55 Ω ZI Single-Ended Input Impedance 45 50 55 Ω Notes: 2. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this datasheet. Exposure to absolute maximum ratings conditions may affect device reliability. 3. The datasheet limits are not guaranteed if the device is operated beyond the recommended operating conditions. 4. Package thermal resistance assumes that the exposed pad is soldered (or equivalent) to the devices most negative potential on the PCB. ψJB and θJA assumes still air and a 4-layer PCB, unless otherwise stated. It also assumes that the recommended via pattern and via sizes on the PCB are used. 5. Outputs RXOUT+ and RXOUT− are loaded with external 50Ω loads and the outputs are enabled. July 3, 2013 6 Revision 1.0 FOMhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY88053CL TTL DC Electrical Characteristics VCC = 3.0 to 3.6V; TA = –40°C to +85°C, typical values at VCC = 3.3V, TA = 25°C. Symbol Parameter Condition Min. Typ. 30 40 CPALOW Output Signal Crossing Range Lower Limit VTHN connected to VTH_REF and 0V to 2.4V applied to VTHP. CPAHIGH Output signal Crossing Range Upper Limit 10 ≤ VID ≤ 60mVPP, see “Crossing Point Adjustment Waveforms.” Note 6. VIH Input High Voltage JAM, RXOUT_INV, SD/LOS_SEL VIL Input Low Voltage JAM, RXOUT_INV, SD/LOS_SEL 0.8 V IIH JAM, RXOUT_INV, SD/LOS_SEL Input High Current VIN = 2.7V 20 µA VIN = VCC 100 IIL JAM, RXOUT_INV, SD/LOS_SEL Input Low Current VIN = 0.4V −0.3 mA VOH SD or LOS Output High Level Sourcing 100µA 2.4 V VOL SD or LOS Output Low Level Sinking 2mA 60 Max. Units % 70 2.0 % V 0.4 V Note: 6. Crossing point adjust functionality is limited to small input amplitude swing levels, as noted. Crossing point adjust range is reduced outside of the noted input amplitude swing levels. July 3, 2013 7 Revision 1.0 FOMhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY88053CL AC Electrical Characteristics VCC = 3.3V ±10%, TA = –40°C to +85°C. Typical values at VCC = 3.3V, TA = 25°C; RLOAD = 50Ω to VCC. Symbol Parameter VOH Min. Typ. Max. Units RXOUT+, RXOUT− High Voltage VCC − 0.020 VCC − 0.005 VCC V VOL RXOUT+, RXOUT− Low Voltage VCC − 0.400 VCC − 0.350 VCC − 0.300 V tr , tf Output Rise/Fall Time (20% to 80%) Note 7 25 40 ps Deterministic Note 8 10 Random Note 9 1 VID_11.3G Differential Input Voltage Swing Note 10. See Figure 1. 5 1800 mVPP VID_12.5G Differential Input Voltage Swing Note 11. See Figure 1. 10 1800 mVPP VOD Differential Output Voltage Swing Note 7 600 700 800 mVPP tLOS_D; tLOS_A tSD_D; tSD_A LOS De-assert, LOS Assert Time \SD De-assert, SD Assert Time Note 12 75 120 ns LOSAL_20k Low LOS Assert Level RLOSLVL = 20kΩ, Note 13 3 mVPP LOSDL_20k Low LOS De-assert Level RLOSLVL = 20kΩ, Note 13 5 mVPP HYSL_20k Low LOS Hysteresis RLOSLVL = 20kΩ, Note 14 LOSAM_10k Medium LOS Assert Level RLOSLVL = 10kΩ, Note 13 4.5 mVPP LOSDM_10k Medium LOS De-assert Level RLOSLVL = 10kΩ, Note 13 7.3 mVPP HYSM_10k Medium LOS Hysteresis RLOSLVL = 10kΩ, Note 14 LOSAH1_1k High1 LOS Assert Level RLOSLVL = 1kΩ, Note 13 18.6 mVPP LOSDH1_1k High1 LOS De-assert Level RLOSLVL = 1kΩ, Note 13 28.3 mVPP HYSH1_1k High1 LOS Hysteresis RLOSLVL = 1kΩ, Note 14 LOSAH2_100 High2 LOS Assert Level RLOSLVL = 100Ω, Note 13 29.7 mVPP LOSDH2_100 High2 LOS De-assert Level RLOSLVL = 100Ω, Note 13 44.6 mVPP HYSH2_100 High2 LOS Hysteresis RLOSLVL = 100Ω, Note 14 AV(Diff)_053C Differential Voltage Gain S21_053C Single-Ended Small-Signal Gain tJITTER Condition 2 2 2 2 32 4.4 4.1 3.6 3.5 ps 6 6 6 6 dB dB dB dB 44 dB 38 dB Note: 7. Amplifier is in limiting mode. Input is a 200MHz square wave. 8. Deterministic jitter is measured using 10Gbps K28.5 pattern, VID = 20mVPP. 9. Random jitter is measured using 10Gbps K28.7 pattern, VID = 20mVPP. 10. Differential input swing amplitude for data rates up to 11.3Gbps. 11. Differential input swing amplitude for data rates between 11.3Gbps and 12.5Gbps. 12. In real world applications, the LOS de-assert/assert time can be strongly influenced by the RC time constant of the AC-coupling capacitor and the 50Ω input termination. To keep this time low, use a decoupling capacitor with the lowest value that is allowed by the data rate and the number of consecutive identical bits in the application (typical values are in the range of 0.001µF to 0.1µF). 13. See “Typical Operating Characteristics” for a graph showing how to choose a particular RLOSLVL for a particular LOS assert and its associated deassert amplitude. 14. This specification defines electrical hysteresis as 20log (LOS de-assert/LOS assert). The ratio between optical hysteresis and electrical hysteresis is found to vary between 1.5 and 2, depending on the level of received optical power and ROSA characteristics. July 3, 2013 8 Revision 1.0 FOMhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY88053CL Crossing Point Adjustment Waveforms Waveform 1: Nominal Crossing Point Adjustment (50% Decision Threshold) – 20mVPP Signal Input (VTHN is tied to VTH_REF; VTHP = 1.25V) Waveform 2: Minimum Crossing Point Adjustment (~30% Decision Threshold) – 20mVPP Signal Input VTHN is tied to VTH_REF; VTHP is approximately 0.75V Note: Although the crossing point adjustment circuit has sufficient range to move the decision point threshold to 20%, it is recommended that the minimum adjustment be limited to ~30%. Waveform 3: Minimum Crossing Point Adjustment (~70% Decision Threshold) – 20mVPP Signal Input VTHN is tied to VTH_REF; VTHP is approximately 1.75V Note: Although the crossing point adjustment circuit has sufficient range to move the decision point threshold to 80%, it is recommended that the maximum adjustment be limited to ~70%. July 3, 2013 9 Revision 1.0 FOMhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY88053CL Typical Operating Characteristics VCC = 3.3V, TA = 25°C, RLOAD = 50Ω to VCC, unless otherwise stated. VID(LOS Assert) and VID(LOS De-Assert) vs. RSD/LOSLVL LOS Hysteresis vs. SD/LOSLVL Resistor 6 5 HYSTERESIS (dB) INPUT SIGNAL AMPLITUDE (mVPP) 100 10 4 3 2 1 1 10 100 1000 10000 0 100000 SD/LOSLVL RESISTOR (Ω) 10 100 1000 10000 100000 SD/LOSLVL RESISTOR (Ω) Typical Linear Mode 10.3G Output with 5mVPP Differential Input Signal July 3, 2013 10 Revision 1.0 FOMhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY88053CL Functional Block Diagram July 3, 2013 11 Revision 1.0 FOMhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY88053CL Functional Description Signal Detect / Loss of Signal The SY88053CL generates a user-selectable (SD/LOS_SEL pin) signal detect (SD) or loss of signal (LOS) open-collector TTL output, as shown in Figure 4. LOS is used to determine whether the input amplitude is too small to be considered as a valid input. LOS asserts high if the input amplitude falls below the threshold set by SD/LOSLVL and de-asserts low otherwise. LOS can be fed back to the JAM input to perform the SQUELCH function and to maintain output stability under a LOS condition. JAM de-asserts the true output signal low without removing the input signals. Typically, 4dB LOS hysteresis is provided to prevent chattering. The SY88053CL is a high-sensitivity, high-bandwidth limiting post amplifier. It operates from a single +3.3V power supply across the entire industrial temperature range of –40°C to +85°C. Signals with data rates from 1.0625Gbps to 12.5Gbps and amplitudes as small as 5mVpp are supported. Figure 1 shows the allowed input voltage swing. When SD/LOSLVL is used to select the SD output on the SD/LOS pin, SD is asserted when the differential input signal amplitude exceeds the level set by the SD/LOSLVL resistor. The JAM operation is inverted when SD is selected. Signal Detect / Loss of Signal Level Setting A programmable SD/LOS level set pin (SD/LOSLVL) sets the threshold of the input amplitude detection. Connecting an external resistor between VCC and SD/LOSLVL sets the threshold voltage. This voltage ranges from VCC to VCC − 1.3V. The external resistor creates a voltage divider between VCC and VCC − 1.3V, as shown in Figure 5. Figure 1. VIS and VID Definition The SY88053CL has a selectable SD or LOS status output signal that can be fed back to the JAM input to perform the SQUELCH function for output stability if there is no signal at the input. SD/LOSLVL sets the sensitivity of the input amplitude detection. Hysteresis The SY88053CL provides typically 4dB LOS electrical hysteresis, which is defined as 20log (VINLOS_De-Assert ÷ VINLOS_Assert). Because the relationship of the voltage output of the ROSA to optical power at its input is linear, the optical hysteresis is typically half of the electrical hysteresis reported in the datasheet. In practice the ratio between electrical and optical hysteresis is found to be between 1.5 and 1.8. Thus, 4dB electrical hysteresis corresponds to an optical hysteresis within the range of 2dB to 2.4dB. In applications where the noise is not evenly distributed between the high and the low levels of the signal, such as links using EDFA amplifiers, the zero crossing point (decision threshold) of the signal can be adjusted, using the VTHN and VTHP pins to optimize the performance of the link. Input Amplifier/Buffer Figure 2 shows a simplified schematic of the input stage. The high sensitivity of the input amplifier allows signals as small as 5mVpp to be detected and amplified. The input amplifier allows input signals as large as 1800mVpp. Input signals are amplified with a typical 44dB differential voltage gain. The user will need to select the appropriate AC coupling capacitor value for their application. Signal Crossing Point Adjustment To optimize the decision threshold level, and so the BER of the optical link where the noise is unevenly distributed between the high and the low levels, the SY88053CL provides two pins for output signal crossing point adjustment (decision threshold) control. The output signal crossing can be adjusted by connecting VTHN (pin 5) to VTH_REF (pin 6), and applying a DC signal at VTHP (pin 16). By varying the DC signal at VTHP from 0V to 2.5V while the input signal to the post amplifier is less than 60mVPP, the crossing point of the output signal changes from approximately 30% to 70%, reaching 50% when VTHP = VTH_REF = 1.25V. If the crossing point control function is not needed, VTHN and VTHP must be connected to GND. Output Buffer The SY88053CL CML output buffer is designed to drive 50Ω impedance transmission lines and is internally terminated with 50Ω to VCC. Figure 3 shows a simplified schematic of the output stage. The user will need to select the appropriate AC coupling capacitor value for their application. July 3, 2013 12 Revision 1.0 FOMhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY88053CL Functional Circuit Structure Figure 2. Typical Input Structure Figure 3. Typical Output Structure July 3, 2013 13 Revision 1.0 FOMhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY88053CL Figure 4. Typical SD/LOS Output Structure Figure 5. Typical SD/LOSLVL Setting Circuit Related Product and Support Documentation Document Number Title Application Note Link AN-45 Notes on Sensitivity and Hysteresis in Micrel Post Amplifiers www.micrel.com/_PDF/HBW/App-Notes/an-45.pdf July 3, 2013 14 Revision 1.0 FOMhelp@micrel.com or (408) 955-1690 Micrel, Inc. SY88053CL Package Information(15) 16-Pin (3mm x 3mm) QFN-16 Note: 15. Package information is correct as of the publication date. For updates and most current information, go to www.micrel.com. MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http://www.micrel.com Micrel makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data sheet. This information is not intended as a warranty and Micrel does not assume responsibility for its use. Micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. No license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Micrel’s terms and conditions of sale for such products, Micrel assumes no liability whatsoever, and Micrel disclaims any express or implied warranty relating to the sale and/or use of Micrel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright or other intellectual property right. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser’s use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser’s own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. © 2013 Micrel, Incorporated. July 3, 2013 15 Revision 1.0 FOMhelp@micrel.com or (408) 955-1690