Dual, 12-/14-/16-Bit nanoDACs® with
5 ppm/°C On-Chip Reference, I2C® Interface
AD5627R/AD5647R/AD5667R, AD5627/AD5667
FEATURES
FUNCTIONAL BLOCK DIAGRAMS
APPLICATIONS
VDD
VREFIN/VREFOUT
1.25V/2.5V REF
BUFFER
ADDR
SCL
INPUT
REGISTER
DAC
REGISTER
STRING
DAC A
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
VOUTA
BUFFER
VOUTB
SDA
POWER-DOWN
LOGIC
06342-001
POWER-ON
RESET
LDAC CLR
Figure 1. AD5627R/AD5647R/AD5667R
VDD
GND
VREFIN
AD5627/AD5667
BUFFER
ADDR
SCL
Process control
Data acquisition systems
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
GND
AD5627R/AD5647R/AD5667R
INTERFACE
LOGIC
Low power, smallest pin-compatible, dual nanoDACs
AD5627R/AD5647R/AD5667R
12-/14-/16-bit
On-chip 1.25 V/2.5 V, 5 ppm/°C reference
AD5627/AD5667
12-/16-bit
External reference only
3 mm x 3 mm LFCSP and 10-lead MSOP
2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to zero scale
Per channel power-down
Hardware LDAC and CLR functions
I2C-compatible serial interface supports standard (100 kHz),
fast (400 kHz), and high speed (3.4 MHz) modes
INTERFACE
LOGIC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC A
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
VOUTA
BUFFER
VOUTB
SDA
POWER-ON
RESET
POWER-DOWN
LOGIC
06342-002
Data Sheet
LDAC CLR
Figure 2. AD5627/AD5667
GENERAL DESCRIPTION
The AD5627R/AD5647R/AD5667R, AD5627/AD5667 members
of the nanoDAC family are low power, dual, 12-, 14-, 16-bit
buffered voltage-out digital-to-analog converters (DACs)
with/without on-chip reference. All devices operate from a single
2.7 V to 5.5 V supply, are guaranteed monotonic by design, and
have an I2C-compatible serial interface.
The AD5627R/AD5647R/AD5667R have an on-chip reference.
The AD5627RBCPZ, AD5647RBCPZ, and AD5667RBCPZ have a
1.25 V, 5 ppm/°C reference, giving a full-scale output range of 2.5 V;
the AD5627RBRMZ and AD5667RBRMZ have a 2.5 V, 5 ppm/°C
reference, giving a full-scale output range of 5 V. The on-chip
reference is off at power-up, allowing the use of an external
reference. The internal reference is enabled via a software write.
The AD5667 and AD5627 require an external reference voltage
to set the output range of the DAC.
The AD5627R/AD5647R/AD5667R, AD5627/AD5667
incorporate a power-on reset circuit that ensures the DAC
output powers up to 0 V, and remains there until a valid write
takes place.
Rev. B
The device contains a per-channel power-down feature that
reduces the current consumption of the device to 480 nA at 5 V
and provides software-selectable output loads while in powerdown mode. The low power consumption of this device in
normal operation makes it ideally suited to portable batteryoperated equipment. The on-chip precision output amplifier
enables rail-to-rail output swing.
The AD5627R/AD5647R/AD5667R, AD5627/AD5667 use a
2-wire I2C-compatible serial interface that operates in standard
(100 kHz), fast (400 kHz), and high speed (3.4 MHz) modes.
Table 1. Related Devices
Part No.
AD5663
AD5623R/AD5643R/AD5663R
AD5625R/AD5645R/AD5665R,
AD5625/AD5665
Description
2.7 V to 5.5 V, dual 16-bit DAC,
external reference, I2C interface
2.7 V to 5.5 V, dual 12-, 14-, 16bit DACs, internal reference,
I2C interface
2.7 V to 5.5 V, quad 12-, 14-, 16bit DACs, with/without internal
reference, I2C interface
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AD5627R/AD5647R/AD5667R, AD5627/AD5667
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Write Operation.......................................................................... 21
Applications ....................................................................................... 1
Read Operation........................................................................... 21
Functional Block Diagrams ............................................................. 1
High Speed Mode ....................................................................... 21
General Description ......................................................................... 1
Input Shift Register .................................................................... 23
Revision History ............................................................................... 2
Multiple Byte Operation ............................................................ 23
Specifications..................................................................................... 3
Broadcast Mode .......................................................................... 23
AC Characteristics ........................................................................ 5
LDAC Function .......................................................................... 23
I C Timing Specifications ............................................................ 6
Power-Down Modes .................................................................. 25
Absolute Maximum Ratings ............................................................ 8
Power-On Reset and Software Reset........................................ 26
ESD Caution .................................................................................. 8
Clear Pin (CLR) .......................................................................... 26
Pin Configuration and Function Descriptions ............................. 9
Internal Reference Setup (R Versions) .................................... 26
Typical Performance Characteristics ........................................... 10
Application Information ................................................................ 28
Terminology .................................................................................... 18
Using a Reference as a Power Supply for the
AD5627R/AD5647R/AD5667R, AD5627/AD5667 .................. 28
2
Theory of Operation ...................................................................... 20
D/A Section ................................................................................. 20
Resistor String ............................................................................. 20
Output Amplifier ........................................................................ 20
Internal Reference ...................................................................... 20
External Reference...................................................................... 20
Bipolar Operation Using the AD5627R/AD5647R/AD5667R,
AD5627/AD5667 ......................................................................... 28
Power Supply Bypassing and Grounding ................................ 28
Outline Dimensions ....................................................................... 29
Ordering Guide .......................................................................... 30
Serial Interface ............................................................................ 21
REVISION HISTORY
9/2016—Rev. A to Rev. B
Changed SPI to I2C ........................................................ Throughout
2/2016—Rev. 0 to Rev. A
Changes to Internal Reference Section ............................................. 20
Changes to Power-On Reset and Software Reset Section ........... 26
Updated Outline Dimensions .............................................................. 29
Changes to Ordering Guide .................................................................. 30
1/2007—Revision 0: Initial Version
Rev. B | Page 2 of 30
Data Sheet
AD5627R/AD5647R/AD5667R, AD5627/AD5667
SPECIFICATIONS
VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
STATIC PERFORMANCE 2
AD5667R/AD5667
Resolution
Relative Accuracy
Differential Nonlinearity
AD5647R
Resolution
Relative Accuracy
Differential Nonlinearity
AD5627R/AD5627
Resolution
Relative Accuracy
Differential Nonlinearity
Zero-Code Error
Offset Error
Full-Scale Error
Gain Error
Zero-Code Error Drift
Gain Temperature Coefficient
DC Power Supply Rejection Ratio
DC Crosstalk (External Reference)
Min
DC Output Impedance
Short-Circuit Current
Power-Up Time
REFERENCE INPUTS
Reference Current
Reference Input Range
Reference Input Impedance
REFERENCE OUTPUT
(LFCSP_WD PACKAGE)
Output Voltage
Reference TC3
Output Impedance
REFERENCE OUTPUT (MSOP PACKAGE)
Output Voltage
Reference TC3
Output Impedance
Max
Unit
Test Conditions/Comments 1
±8
±12
±1
Bits
LSB
LSB
Guaranteed monotonic by design
±4
±0.5
Bits
LSB
LSB
Guaranteed monotonic by design
16
14
±2
12
±2
±2.5
−100
15
Bits
LSB
LSB
mV
mV
% of FSR
% of FSR
µV/°C
ppm
dB
µV
10
8
25
µV/mA
µV
µV
20
10
µV/mA
µV
±0.5
2
±1
−0.1
DC Crosstalk (Internal Reference)
OUTPUT CHARACTERISTICS 3
Output Voltage Range
Capacitive Load Stability
Typ
0
±1
±0.25
10
±10
±1
±1.5
VDD
2
10
0.5
30
4
110
0.75
±5
7.5
Of FSR/°C
DAC code = midscale ; VDD = 5 V ± 10%
Due to full-scale output change,
RL = 2 kΩ to GND or 2 kΩ to VDD
Due to load current change
Due to powering down (per channel)
Due to full-scale output change,
RL = 2 kΩ to GND or 2 kΩ to VDD
Due to load current change
Due to powering down (per channel)
RL = ∞
RL = 2 kΩ
VDD = 5 V
Coming out of power-down mode; VDD = 5 V
µA
V
kΩ
VREF = VDD = 5.5 V
1.253
V
ppm/°C
kΩ
At ambient
2.505
±10
V
ppm/°C
kΩ
At ambient
±10
7.5
2.495
All 1s loaded to DAC register
130
VDD
50
1.247
V
nF
nF
Ω
mA
µs
Guaranteed monotonic by design
All 0s loaded to DAC register
Rev. B | Page 3 of 30
AD5627R/AD5647R/AD5667R, AD5627/AD5667
Parameter
LOGIC INPUTS (ADDR, CLR, LDAC)3
IIN, Input Current
VINL, Input Low Voltage
VINH, Input High Voltage
CIN, Pin Capacitance
Min
VHYST, Input Hysteresis
LOGIC INPUTS (SDA, SCL)
IIN, Input Current
VINL, Input Low Voltage
VINH, Input High Voltage
CIN, Pin Capacitance
VHYST, Input Hysteresis
LOGIC OUTPUTS (OPEN-DRAIN)
VOL, Output Low Voltage
0.1 × VDD
Floating-State Leakage Current
Floating-State Output Capacitance
POWER REQUIREMENTS
VDD
IDD (Normal Mode) 4
VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 3.6 V
VDD = 4.5 V to 5.5 V
VDD = 2.7 V to 3.6 V
IDD (All Power-Down Modes) 5
Typ
Max
Unit
±1
0.15 × VDD
µA
V
V
pF
pF
V
0.85 × VDD
2
20
±1
0.3 × VDD
µA
V
V
pF
V
0.4
0.6
±1
V
V
µA
pF
5.5
V
0.5
0.45
1.15
0.95
1
mA
mA
mA
mA
µA
0.7 × VDD
2
0.1 × VDD
2
2.7
0.4
0.35
0.95
0.8
0.48
Data Sheet
Test Conditions/Comments 1
ADDR
CLR, LDAC
ISINK = 3 mA
ISINK = 6 mA
VIH = VDD, VIL = GND
Internal reference off
Internal reference off
Internal reference on
Internal reference on
VIH = VDD, VIL = GND
Temperature range: B grade: −40°C to +105°C.
Linearity calculated using a reduced code range: AD5667R/AD5667 (Code 512 to Code 65,024); AD5647R (Code 128 to Code 16,256); AD5627R/AD5627 (Code 32 to Code 4064).
Output unloaded.
3
Guaranteed by design and characterization, not production tested.
4
Interface inactive. All DACs active. DAC outputs unloaded.
5
All DACs powered down.
1
2
Rev. B | Page 4 of 30
Data Sheet
AD5627R/AD5647R/AD5667R, AD5627/AD5667
AC CHARACTERISTICS
VDD = 2.7 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; VREFIN = VDD; all specifications TMIN to TMAX, unless otherwise noted. 1
Table 3.
Parameter 2
Output Voltage Settling Time
AD5627R/AD5627
AD5647R
AD5667R/AD5667
Slew Rate
Digital-to-Analog Glitch Impulse
Digital Feedthrough
Reference Feedthrough
Digital Crosstalk
Analog Crosstalk
DAC to DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
Output Noise Spectral Density
Output Noise
Min
Typ
Max
Unit
Test Conditions/Comments 3
3
3.5
4
1.8
15
0.1
−90
0.1
1
4
1
4
340
−80
120
100
15
4.5
5
7
µs
µs
µs
V/µs
nV-s
nV-s
dB
nV-s
nV-s
nV-s
nV-s
nV-s
kHz
dB
nV/√Hz
nV/√Hz
µV p-p
¼ to ¾ scale settling to ±0.5 LSB
¼ to ¾ scale settling to ±0.5 LSB
¼ to ¾ scale settling to ±2 LSB
Guaranteed by design and characterization, not production tested.
See the Terminology section.
3
Temperature range is −40°C to +105°C, typical at 25°C.
1
2
Rev. B | Page 5 of 30
1 LSB change around major carry transition
VREF = 2 V ± 0.1 V p-p, frequency 10 Hz to 20 MHz
External reference
Internal reference
External reference
Internal reference
VREF = 2 V ± 0.1 V p-p
VREF = 2 V ± 0.1 V p-p, frequency = 10 kHz
DAC code = midscale, 1 kHz
DAC code = midscale, 10 kHz
0.1 Hz to 10 Hz
AD5627R/AD5647R/AD5667R, AD5627/AD5667
Data Sheet
I2C TIMING SPECIFICATIONS
VDD = 2.7 V to 5.5 V; all specifications TMIN to TMAX, fSCL = 3.4 MHz, unless otherwise noted. 1
Table 4.
Parameter
fSCL 3
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t11A
Test Conditions/Comments 2
Standard mode
Fast mode
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Standard mode
Fast mode
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Standard mode
Fast mode
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Standard mode
Fast mode
High speed mode
Standard mode
Fast mode
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Standard mode
Fast mode
High speed mode
Standard mode
Fast mode
High speed mode
Standard mode
Fast mode
Standard mode
Fast mode
High speed mode
Standard mode
Fast mode
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Standard mode
Fast mode
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Standard mode
Fast mode
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Standard mode
Fast mode
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Min
4
0.6
60
120
4.7
1.3
160
320
250
100
10
0
0
0
0
4.7
0.6
160
4
0.6
160
4.7
1.3
4
0.6
160
10
20
10
20
10
20
10
20
Max
100
400
3.4
1.7
1000
300
80
160
300
300
80
160
1000
300
40
80
1000
Unit
kHz
kHz
MHz
MHz
μs
μs
ns
ns
μs
μs
ns
ns
ns
ns
ns
μs
μs
ns
ns
μs
μs
ns
μs
μs
ns
μs
μs
μs
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
300
80
160
ns
ns
ns
3.45
0.9
70
150
Description
Serial clock frequency
tHIGH, SCL high time
tLOW, SCL low time
tSU;DAT, data setup time
tHD;DAT, data hold time
tSU;STA, setup time for a repeated start condition
tHD;STA, hold time (repeated) start condition
tBUF, bus free time between a stop and a start condition
tSU;STO, setup time for a stop condition
tRDA, rise time of SDA signal
tFDA, fall time of SDA signal
tRCL, rise time of SCL signal
tRCL1, rise time of SCL signal after a repeated start condition and after
an acknowledge bit
Rev. B | Page 6 of 30
Data Sheet
Parameter
t12
t13
t14
t15
tSP 4
AD5627R/AD5647R/AD5667R, AD5627/AD5667
Test Conditions/Comments 2
Standard mode
Fast mode
High speed mode, CB = 100 pF
High speed mode, CB = 400 pF
Standard mode
Fast mode
High speed mode
Standard mode
Min
10
20
10
10
10
300
Fast mode
High speed mode
Standard mode
Fast mode
High speed mode
Fast mode
High speed mode
300
30
20
20
20
0
0
Max
300
300
40
80
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
50
10
Description
tFCL, fall time of SCL signal
LDAC pulse width low
Falling edge of 9th SCL clock pulse of last byte of valid write to LDAC
falling edge
CLR pulse width low
Pulse width of spike suppressed
See Figure 3. High speed mode timing specification applies only to the AD5627RBRMZ-2/AD5627BRMZ-2REEL7 and AD5667RBRMZ-2/AD5667BRMZ-2REEL7.
CB refers to the capacitance on the bus line.
3
The SDA and SCL timing is measured with the input filters enabled. Switching off the input filters improves the transfer rate but has a negative effect on EMC behavior
of the device.
4
Input filtering on the SCL and SDA inputs suppresses noise spikes that are less than 50 ns for fast mode or 10 ns for high speed mode.
1
2
t11
t12
t6
t2
SCL
t1
t6
t4
t5
t8
t10
t3
t9
SDA
t7
P
S
S
P
t14
t15
CLR
*ASYNCHRONOUS LDAC UPDATE MODE.
Figure 3. 2-Wire Serial Interface Timing Diagram
Rev. B | Page 7 of 30
06342-003
t13
LDAC*
AD5627R/AD5647R/AD5667R, AD5627/AD5667
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Parameter
VDD to GND
VOUT to GND
VREFIN/VREFOUT to GND
Digital Input Voltage to GND
Operating Temperature Range, Industrial
Storage Temperature Range
Junction Temperature (TJ maximum)
Power Dissipation
θJA Thermal Impedance
LFCSP_WD Package (4-Layer Board)
MSOP Package
Reflow Soldering Peak Temperature, Pb-Free
Rating
−0.3 V to +7 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−0.3 V to VDD + 0.3 V
−40°C to +105°C
−65°C to +150°C
150°C
(TJ max − TA)/θJA
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
61°C/W
150.4°C/W
260°C ± 5°C
Rev. B | Page 8 of 30
Data Sheet
AD5627R/AD5647R/AD5667R, AD5627/AD5667
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
LDAC 4
CLR 5
TOP VIEW
(Not to Scale)
10 VREFIN
VOUTA 1
9
VDD
VOUTB 2
8
SDA
GND 3
7
SCL
LDAC 4
6
ADDR
EXPOSED PAD TIED TO GND
ON LFCSP PACKAGE.
CLR 5
AD5627R/
AD5647R/
AD5667R
TOP VIEW
(Not to Scale)
10 VREFIN/VREFOUT
9
VDD
8
SDA
7
SCL
6
ADDR
EXPOSED PAD TIED TO GND
ON LFCSP PACKAGE.
Figure 4. AD5627/AD5667 Pin Configuration
06342-102
GND 3
AD5627/
AD5667
06342-101
VOUTA 1
VOUTB 2
Figure 5. AD5627R/AD5647R/AD5667R Pin Configuration
Table 6. Pin Function Descriptions
Pin
No.
1
2
3
4
Mnemonic
VOUTA
VOUTB
GND
LDAC
5
CLR
6
7
8
ADDR
SCL
SDA
9
VDD
10
VREFIN/VREFOUT
Description
Analog Output Voltage from DAC A. The output amplifier has rail-to-rail operation.
Analog Output Voltage from DAC B. The output amplifier has rail-to-rail operation.
Ground reference point for all circuitry on the device.
Pulsing this pin low allows any or all DAC registers to be updated if the inputs have new data. This allows
simultaneous updates of all DAC outputs. Alternatively, this pin can be tied permanently low.
Asynchronous Clear Input. The CLR input is falling-edge sensitive. While CLR is low, all LDAC pulses are ignored.
When CLR is activated, zero scale is loaded to all input and DAC registers. This clears the output to 0 V. The device exits
clear code mode on the falling edge of the 9th clock pulse of the last byte of valid write. If CLR is activated during a
write sequence, the write is aborted. If CLR is activated during high speed mode the device will exit high speed mode.
Three-State Address Input. Sets the two least significant bits (Bit A1, Bit A0) of the 7-bit slave address.
Serial Clock Line. This is used in conjunction with the SDA line to clock data into or out of the 24-bit input register.
Serial Data Line. This is used in conjunction with the SCL line to clock data into or out of the 24-bit input register. It is
a bidirectional, open-drain data line that should be pulled to the supply with an external pull-up resistor.
Power Supply Input. These devices can be operated from 2.7 V to 5.5 V, and the supply should be decoupled with a
10 μF capacitor in parallel with a 0.1 μF capacitor to GND.
The AD5627R/AD5647R/AD5667R have a common pin for reference input and reference output. When using the
internal reference, this is the reference output pin. When using an external reference, this is the reference input pin.
The default for this pin is as a reference input. (The internal reference and reference output are only available on R
suffix versions.) The AD5627/AD5667 have a reference input pin only.
Rev. B | Page 9 of 30
AD5627R/AD5647R/AD5667R, AD5627/AD5667
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
8
0.6
4
0.4
DNL ERROR (LSB)
6
2
0
–2
–4
0.2
0
–0.2
–0.4
–6
–0.6
–8
–0.8
–10
0
VDD = VREF = 5V
TA = 25°C
0.8
5k 10k 15k 20k 25k 30k 35k 40k 45k 50k 55k 60k 65k
CODE
–1.0
06342-005
INL ERROR (LSB)
1.0
VDD = VREF = 5V
TA = 25°C
0
30k
CODE
40k
50k
60k
0.5
VDD = VREF = 5V
TA = 25°C
3
20k
Figure 9. AD5667 DNL, External Reference
Figure 6. AD5667 INL, External Reference
4
10k
06342-007
10
VDD = VREF = 5V
TA = 25°C
0.4
0.3
DNL ERROR (LSB)
INL ERROR (LSB)
2
1
0
–1
–2
0.2
0.1
0
–0.1
–0.2
–0.3
–3
0
2500
5000
7500
10000
CODE
12500
15000
–0.5
0
2500
5000
7500
10000
CODE
12500
15000
06342-008
–0.4
06342-006
–4
Figure 10. DNL AD5647R, External Reference
Figure 7. AD5647R INL, External Reference
0.20
1.0
VDD = VREF = 5V
0.8 TA = 25°C
VDD = VREF = 5V
TA = 25°C
0.15
0.6
0.10
DNL ERROR (LSB)
0.2
0
–0.2
–0.4
0.05
0
–0.05
–0.10
–0.6
–1.0
0
500
1000
1500
2000
2500
CODE
3000
3500
4000
–0.20
0
500
1000
1500
2000 2500
CODE
3000
3500
Figure 11. AD5627 DNL, External Reference
Figure 8. AD5627 INL, External Reference
Rev. B | Page 10 of 30
4000
06342-009
–0.15
–0.8
06342-100
INL ERROR (LSB)
0.4
Data Sheet
AD5627R/AD5647R/AD5667R, AD5627/AD5667
10
1.0
VDD = 5V
VREFOUT = 2.5V
TA = 25°C
8
0.6
6
4
DNL ERROR (LSB)
2
0
–2
0.4
0.2
0
–0.2
–0.4
–4
–0.6
–6
–0.8
–8
65000
CODE
Figure 12. AD5667R INL, 2.5 V Internal Reference
06342-013
60000
55000
50000
45000
40000
35000
30000
25000
20000
15000
0
65000
06342-010
60000
55000
50000
45000
40000
35000
30000
25000
20000
15000
10000
0
5000
CODE
10000
–1.0
–10
5000
INL ERROR (LSB)
VDD = 5V
VREFOUT = 2.5V
TA = 25°C
0.8
Figure 15. AD5667R DNL, 2.5 V Internal Reference
4
0.5
VDD = 5V
VREFOUT = 2.5V
TA = 25°C
3
VDD = 5V
VREFOUT = 2.5V
TA = 25°C
0.4
0.3
DNL ERROR (LSB)
INL ERROR (LSB)
2
1
0
–1
0.2
0.1
0
–0.1
–0.2
–2
–0.3
–3
–0.4
16250
15000
13750
11250
12500
8750
10000
7500
6250
5000
3750
2500
1250
0
CODE
Figure 13. AD5647R INL, 2.5 V Internal Reference
06342-014
CODE
06342-011
16250
15000
13750
–0.5
12500
11250
10000
8750
7500
6250
5000
3750
2500
0
1250
–4
Figure 16. AD5647R DNL, 2.5 V Internal Reference
0.20
1.0
VDD = 5V
VREFOUT = 2.5V
TA = 25°C
0.8
VDD = 5V
VREFOUT = 2.5V
TA = 25°C
0.15
0.6
DNL ERROR (LSB)
0.2
0
–0.2
0.05
0
–0.05
–0.4
–0.10
–0.6
–1.0
0
500
1000
1500
2000 2500
CODE
3000
3500
4000
Figure 14. AD5627R INL, 2.5 V Internal Reference
–0.20
0
500
1000
1500
2000 2500
CODE
3000
3500
Figure 17. AD5627R DNL, 2.5 V Internal Reference
Rev. B | Page 11 of 30
4000
06342-015
–0.15
–0.8
06342-012
INL ERROR (LSB)
0.10
0.4
AD5627R/AD5647R/AD5667R, AD5627/AD5667
Data Sheet
1.0
0.6
–0.2
65000
CODE
Figure 18. AD5667R INL,1.25 V Internal Reference
06342-019
60000
55000
50000
0
65000
CODE
06342-016
60000
55000
50000
45000
40000
35000
30000
25000
20000
15000
–1.0
5000
–0.8
–10
10000
–0.6
–8
0
–6
45000
–0.4
40000
–4
0
35000
–2
0.2
30000
0
0.4
25000
2
20000
4
DNL ERROR (LSB)
INL ERROR (LSB)
6
VDD = 3V
VREFOUT = 1.25V
TA = 25°C
0.8
15000
8
5000
VDD = 3V
VREFOUT = 1.25V
TA = 25°C
10000
10
Figure 21. AD5667R DNL,1.25 V Internal Reference
4
0.5
VDD = 3V
VREFOUT = 1.25V
TA = 25°C
3
VDD = 3V
VREFOUT = 1.25V
TA = 25°C
0.4
0.3
DNL ERROR (LSB)
INL ERROR (LSB)
2
1
0
–1
0.2
0.1
0
–0.1
–0.2
–2
–0.3
–3
–0.4
CODE
Figure 19. AD5647R INL, 1.25 V Internal Reference
06342-020
16250
15000
13750
12500
11250
10000
8750
7500
6250
5000
3750
2500
1250
0
16250
CODE
06342-017
15000
13750
12500
11250
8750
10000
7500
6250
5000
3750
2500
1250
–0.5
0
–4
Figure 22. AD5647R DNL,1.25 V Internal Reference
1.0
0.20
VDD = 3V
VREFOUT = 1.25V
TA = 25°C
0.8
0.6
VDD = 3V
VREFOUT = 1.25V
TA = 25°C
0.15
DNL ERROR (LSB)
0.2
0
–0.2
–0.4
0.05
0
–0.05
–0.10
–0.6
–1.0
0
500
1000
1500
2000 2500
CODE
3000
3500
4000
Figure 20. AD5627R INL,1.25 V Internal Reference
–0.20
0
500
1000
1500
2000 2500
CODE
3000
3500
Figure 23. AD5627R DNL, 1.25 V Internal Reference
Rev. B | Page 12 of 30
4000
06342-021
–0.15
–0.8
06342-018
INL ERROR (LSB)
0.10
0.4
Data Sheet
AD5627R/AD5647R/AD5667R, AD5627/AD5667
8
0
6
VDD = VREF = 5V
VDD = 5V
–0.02
MAX INL
–0.04
GAIN ERROR
4
ERROR (% FSR)
2
MAX DNL
0
MIN DNL
–2
–0.08
–0.10
–0.12
–0.14
–4
FULL-SCALE ERROR
–0.16
MIN INL
–6
–0.18
–20
0
20
40
60
TEMPERATURE (°C)
80
100
–0.20
–40
06342-022
–8
–40
Figure 24. INL Error and DNL Error vs. Temperature
–20
0
20
40
60
TEMPERATURE (°C)
80
100
06342-025
ERROR (LSB)
–0.06
Figure 27. Gain Error and Full-Scale Error vs. Temperature
10
1.5
MAX INL
8
1.0
ZERO-SCALE ERROR
6
0.5
VDD = 5V
TA = 25°C
ERROR (mV)
ERROR (LSB)
4
2
MAX DNL
0
MIN DNL
–2
0
–0.5
–1.0
–4
–1.5
–6
OFFSET ERROR
MIN INL
1.25
1.75
2.25
2.75
3.25
VREF (V)
3.75
4.25
4.75
–2.5
–40
Figure 25. INL and DNL Error vs. VREF
0
20
40
60
TEMPERATURE (°C)
80
100
Figure 28. Zero-Scale Error and Offset Error vs. Temperature
8
1.0
6
MAX INL
TA = 25°C
0.5
4
ERROR (% FSR)
GAIN ERROR
2
MAX DNL
0
MIN DNL
–2
0
FULL-SCALE ERROR
–0.5
–1.0
–4
MIN INL
–8
2.7
3.2
3.7
4.2
VDD (V)
4.7
5.2
Figure 26. INL and DNL Error vs. Supply
–2.0
2.7
3.2
3.7
4.2
VDD (V)
4.7
5.2
Figure 29. Gain Error and Full-Scale Error vs. Supply
Rev. B | Page 13 of 30
06342-027
–1.5
–6
06342-024
ERROR (LSB)
–20
06342-026
–10
0.75
–2.0
06342-023
–8
AD5627R/AD5647R/AD5667R, AD5627/AD5667
Data Sheet
0.5
1.0
TA = 25°C
0.4
ZERO-SCALE ERROR
ERROR VOLTAGE (V)
–0.5
–1.0
–1.5
0.2
0.1
VDD = 3V
VREFOUT = 1.25V
0
–0.1
–0.2
VDD = 5V
VREFOUT = 2.5V
–0.3
–2.0
OFFSET ERROR
3.2
3.7
4.2
VDD (V)
4.7
5.2
–0.4
–0.5
–10
06342-028
–2.5
2.7
Figure 30. Zero-Scale Error and Offset Error vs. Supply
18
–8
–6
–4
–2
0
2
CURRENT (mA)
4
6
8
10
Figure 33. Headroom at Rails vs. Source and Sink
6
VDD = 3.6V
16
DAC LOADED WITH
ZERO-SCALE
SINKING CURRENT
0.3
0
ERROR (mV)
DAC LOADED WITH
FULL-SCALE
SOURCING CURRENT
06342-031
0.5
VDD = 5.5V
5
VDD = 5V
VREFOUT = 2.5V
TA = 25°C
FULL SCALE
3/4 SCALE
4
12
VOUT (V)
NUMBER OF DEVICES
14
10
8
3
MIDSCALE
2
1/4 SCALE
6
1
4
0
0.32
0.34
0.36
0.38
IDD (mA)
0.40
0.42
0.44
Figure 31. IDD Histogram with External Reference
14
–1
–30
3
8
VOUT (V)
VREFOUT = 2.5V
6
3/4 SCALE
2
MIDSCALE
1
1/4 SCALE
0
2
Figure 32. IDD Histogram with Internal Reference
–1
–30
06342-030
IDD (mA)
30
FULL SCALE
4
0
20
VDD = 3V
VREFOUT = 1.25V
TA = 25°C
10
0.74
0.75
0.76
0.77
0.78
0.79
0.80
0.81
0.82
0.83
0.84
0.85
0.86
0.87
0.88
0.89
0.90
0.91
0.92
0.93
0.94
0.95
0.96
0.97
0.98
0.99
1.00
1.01
1.02
1.03
1.04
NUMBER OF DEVICES
0
10
CURRENT (mA)
4
VDD = 5.5V
12
–10
Figure 34. AD5627R/AD5647R/AD5667R with 2.5 V Reference, Source and
Sink Capability
VDD = 3.6V
VREFOUT = 1.25V
–20
ZERO SCALE
–20
–10
0
10
CURRENT (mA)
20
30
06342-047
0.30
06342-029
0
ZERO SCALE
06342-046
2
Figure 35. AD5627R/AD5647R/AD5667R with 1.25 V Reference, Source and
Sink Capability
Rev. B | Page 14 of 30
Data Sheet
AD5627R/AD5647R/AD5667R, AD5627/AD5667
0.9
TA = 25°C
0.8
VDD = 5V, VREFOUT = 2.5V
0.7
VDD = VREF = 5V
TA = 25°C
FULL-SCALE CODE CHANGE
0x0000 TO 0xFFFF
OUTPUT LOADED WITH 2kΩ
AND 200pF TO GND
IDD (mA)
0.6
0.5
VDD = VREF = 5V
0.4
0.3
VOUT = 909mV/DIV
0.2
1
10512
20512
30512
40512
CODE
50512
60512
06342-048
0
512
06342-060
0.1
TIME BASE = 4µs/DIV
Figure 36. Supply Current vs. Code
Figure 39. Full-Scale Settling Time, 5 V
0.40
VDD = VREF = 5V
TA = 25°C
0.35
0.30
0.20
VDD
1
0.15
0.10
MAX(C2)
420.0mV
2
0.05
3.7
4.2
4.7
SUPPLY VOLTAGE (V)
3.2
CH1 2.0V
06342-061
0
2.7
5.2
Figure 37. Supply Current vs. Supply Voltage
M100µs 125MS/s
A CH1
1.28V
8.0ns/pt
Figure 40. Power-On Reset to 0 V
0.45
SYNC
VDD = VREFIN = 5V
0.40
1
0.35
SLCK
3
VDD = VREFIN = 3V
0.30
0.25
0.20
0.15
VOUT
0.10
0.05
0
–40
VDD = 5V
2
–20
0
20
40
60
TEMPERATURE (°C)
80
100
06342-063
IDD (mA)
CH2 500mV
06342-049
VOUT
TA = 25°C
Figure 38. Supply Current vs. Temperature
CH1 5.0V
CH3 5.0V
CH2 500mV
M400ns
A CH1
Figure 41. Exiting Power-Down to Midscale
Rev. B | Page 15 of 30
1.4V
06342-050
IDD (mA)
0.25
VDD = VREF = 5V
TA = 25°C
DAC LOADED WITH MIDSCALE
VDD = VREF = 5V
TA = 25°C
5ns/SAMPLE NUMBER
GLITCH IMPULSE = 9.494nV
1LSB CHANGE AROUND
MIDSCALE (0x8000 TO 0x7FFF)
0
50
100
150
200 250 300 350
SAMPLE NUMBER
400
450
512
4s/DIV
Figure 42. Digital-to-Analog Glitch Impulse (Negative)
2.498
1
Figure 45. 0.1 Hz to 10 Hz Output Noise Plot, External Reference
VDD = 5V
VREFOUT = 2.5V
TA = 25°C
DAC LOADED WITH MIDSCALE
VDD = VREF = 5V
TA = 25°C
5ns/SAMPLE NUMBER
ANALOG CROSSTALK = 0.424nV
2.497
06342-051
2µV/DIV
2.538
2.537
2.536
2.535
2.534
2.533
2.532
2.531
2.530
2.529
2.528
2.527
2.526
2.525
2.524
2.523
2.522
2.521
Data Sheet
06342-058
VOUT (V)
AD5627R/AD5647R/AD5667R, AD5627/AD5667
10µV/DIV
VOUT (V)
2.496
2.495
2.494
1
2.493
50
100
150
200 250 300 350
SAMPLE NUMBER
400
450
512
VDD = 3V
VREFOUT = 1.25V
TA = 25°C
DAC LOADED WITH MIDSCALE
5µV/DIV
2.496
2.494
2.492
2.490
2.488
2.486
2.484
2.482
2.480
2.478
2.476
2.474
2.472
2.470
2.468
2.466
2.464
2.462
2.460
2.458
2.456
Figure 46. 0.1 Hz to 10 Hz Output Noise Plot, 2.5 V Internal Reference
VDD = 5V
VREFOUT = 2.5V
TA = 25°C
5ns/SAMPLE NUMBER
ANALOG CROSSTALK = 4.462nV
0
50
100
150
200 250 300 350
SAMPLE NUMBER
400
450
Figure 44. Analog Crosstalk, Internal Reference
512
06342-062
VOUT (V)
Figure 43. Analog Crosstalk, External Reference
5s/DIV
06342-052
0
1
4s/DIV
06342-053
2.491
06342-059
2.492
Figure 47. 0.1 Hz to 10 Hz Output Noise Plot,1.25 V Internal Reference
Rev. B | Page 16 of 30
Data Sheet
AD5627R/AD5647R/AD5667R, AD5627/AD5667
800
16
TA = 25°C
MIDSCALE LOADED
VREF = VDD
TA = 25°C
14
600
VDD = 3V
12
TIME (µs)
500
400
300
6
VDD = 3V
VREFOUT = 1.25V
0
100
1k
10k
FREQUENCY (Hz)
100k
1M
4
0
Figure 48. Noise Spectral Density, Internal Reference
–20
–30
3
4
5
6
7
CAPACITANCE (nF)
5
VDD = 5V
TA = 25°C
DAC LOADED WITH FULL SCALE
VREF = 2V ± 0.3V p-p
8
9
10
VDD = 5V
TA = 25°C
0
–5
–10
(dB)
–50
–60
–70
–15
–20
–25
–80
–30
–90
–35
2k
4k
6k
FREQUENCY (Hz)
8k
10k
06342-055
(dB)
2
Figure 50. Settling Time vs. Capacitive Load
–40
–100
1
Figure 49. Total Harmonic Distortion
–40
10k
100k
1M
FREQUENCY (Hz)
Figure 51. Multiplying Bandwidth
Rev. B | Page 17 of 30
10M
06342-057
100
VDD = 5V
06342-056
200
10
8
VDD = 5V
VREFOUT = 2.5V
06342-054
OUTPUT NOISE (nV/√Hz)
700
AD5627R/AD5647R/AD5667R, AD5627/AD5667
Data Sheet
TERMINOLOGY
Relative Accuracy or Integral Nonlinearity (INL)
For the DAC, relative accuracy or integral nonlinearity is a
measurement of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer function.
Differential Nonlinearity (DNL)
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent codes.
A specified differential nonlinearity of ±1 LSB maximum ensures
monotonicity. This DAC is guaranteed monotonic by design.
Zero-Code Error
Zero-code error is a measurement of the output error when
zero scale (0x0000) is loaded to the DAC register. Ideally, the
output should be 0 V. The zero-code error is always positive in
the AD5667R because the output of the DAC cannot go below
0 V due to a combination of the offset errors in the DAC and
the output amplifier. Zero-code error is expressed in mV.
Full-Scale Error
Full-scale error is a measurement of the output error when fullscale code (0xFFFF) is loaded to the DAC register. Ideally, the
output should be VDD − 1 LSB. Full-scale error is expressed in %
of full-scale range (FSR).
Gain Error
Gain error is a measure of the span error of the DAC. It is the
deviation in slope of the DAC transfer characteristic from ideal
expressed in % of FSR.
Zero-Code Error Drift
Zero-code error drift is a measurement of the change in zerocode error with a change in temperature. It is expressed in µV/°C.
Gain Temperature Coefficient
Gain temperature coefficient is a measurement of the change in
gain error with changes in temperature. It is expressed in ppm
of FSR/°C.
Offset Error
Offset error is a measure of the difference between VOUT (actual)
and VOUT (ideal) expressed in mV in the linear region of the
transfer function. Offset error is measured on the AD5667R
with code 512 loaded in the DAC register. It can be negative or
positive.
DC Power Supply Rejection Ratio (PSRR)
DC PSRR indicates how the output of the DAC is affected by
changes in the supply voltage. PSRR is the ratio of the change in
VOUT to a change in VDD for full-scale output of the DAC. It is
measured in dB. VREF is held at 2 V and VDD is varied by ±10%.
Output Voltage Settling Time
Output voltage settling time is the amount of time it takes for
the output of a DAC to settle to a specified level for a ¼ to ¾
full-scale input change and is measured from the rising edge of
the stop condition.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV-s, and is
measured when the digital input code is changed by 1 LSB at
the major carry transition (0x7FFF to 0x8000) (see Figure 42).
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into
the analog output of the DAC from the digital inputs of the
DAC, but is measured when the DAC output is not updated. It
is specified in nV-s, and measured with a full-scale code change
on the data bus, that is, from all 0s to all 1s and vice versa.
Reference Feedthrough
Reference feedthrough is the ratio of the amplitude of the signal
at the DAC output to the reference input when the DAC output
is not being updated. It is expressed in dB.
Output Noise Spectral Density
Output noise spectral density is a measurement of the internally
generated random noise. Random noise is characterized as a
spectral density. It is measured by loading the DAC to midscale
and measuring noise at the output. It is measured in nV/√Hz. A
plot of noise spectral density can be seen in Figure 48.
DC Crosstalk
DC crosstalk is the dc change in the output level of one DAC in
response to a change in the output of another DAC. It is measured
with a full-scale output change on one DAC (or soft power-down
and power-up) while monitoring another DAC kept at midscale.
It is expressed in μV.
DC crosstalk due to load current change is a measure of the
impact that a change in load current on one DAC has to
another DAC kept at midscale. It is expressed in µV/mA.
Digital Crosstalk
Digital crosstalk is the glitch impulse transferred to the output
of one DAC at midscale in response to a full-scale code change
(all 0s to all 1s and vice versa) in the input register of another
DAC. It is measured in standalone mode and is expressed in nV-s.
Rev. B | Page 18 of 30
Data Sheet
AD5627R/AD5647R/AD5667R, AD5627/AD5667
Analog Crosstalk
Analog crosstalk is the glitch impulse transferred to the output
of one DAC due to a change in the output of another DAC. It is
measured by loading one of the input registers with a full-scale
code change (all 0s to all 1s and vice versa), then executing a
software LDAC and monitoring the output of the DAC whose
digital code was not changed. The area of the glitch is expressed
in nV-s.
DAC-to-DAC Crosstalk
DAC-to-DAC crosstalk is the glitch impulse transferred to the
output of one DAC due to a digital code change and subsequent
analog output change of another DAC. It is measured by loading
the attack channel with a full-scale code change (all 0s to all 1s
and vice versa) with LDAC low while monitoring the output of
the victim channel that is at midscale. The energy of the glitch is
expressed in nV-s.
Multiplying Bandwidth
The multiplying bandwidth is a measure of the finite bandwidth
of the amplifiers within the DAC. A sine wave on the reference
(with full-scale code loaded to the DAC) appears on the output.
The multiplying bandwidth is the frequency at which the output
amplitude falls to 3 dB below the input.
Total Harmonic Distortion (THD)
THD is the difference between an ideal sine wave and the
attenuated version using the DAC. The sine wave is used as the
reference for the DAC, and the THD is a measurement of the
harmonics present on the DAC output. It is measured in dB.
Rev. B | Page 19 of 30
AD5627R/AD5647R/AD5667R, AD5627/AD5667
Data Sheet
THEORY OF OPERATION
D/A SECTION
R
The AD5627R/AD5647R/AD5667R, AD5627/AD5667 DACs are
fabricated on a CMOS process. The architecture consists of a
string DAC followed by an output buffer amplifier. Figure 52
shows a block diagram of the DAC architecture.
REF (+)
DAC
REGISTER
TO OUTPUT
AMPLIFIER
R
OUTPUT
AMPLIFIER
GAIN = +2
RESISTOR
STRING
REF (–)
GND
VOUT
R
06342-032
VDD
R
R
06342-033
Figure 52. DAC Architecture
Because the input coding to the DAC is straight binary, the ideal
output voltage when using an external reference is given by
Figure 53. Resistor String
INTERNAL REFERENCE
D
VOUT = VREFIN × N
2
The ideal output voltage when using the internal reference is
given by
D
VOUT = 2 × VREFOUT × N
2
where:
D is the decimal equivalent of the binary code that is loaded to
the DAC register:
0 to 4095 for AD5627R/AD5627 (12-bit).
0 to 16,383 for AD5647R (14-bit).
0 to 65,535 for AD5667R/AD5667 (16-bit).
N is the DAC resolution.
RESISTOR STRING
The resistor string is shown in Figure 53. It is simply a string of
resistors, each of value R. The code loaded to the DAC register
determines at which node on the string the voltage is tapped off
to be fed into the output amplifier. The voltage is tapped off by
closing one of the switches connecting the string to the amplifier.
Because it is a string of resistors, it is guaranteed monotonic.
OUTPUT AMPLIFIER
The output buffer amplifier can generate rail-to-rail voltages on
the output, which gives an output range of 0 V to VDD. It can drive a
load of 2 kΩ in parallel with 1000 pF to GND. The source and
sink capabilities of the output amplifier can be seen in Figure 33
and Figure 34. The slew rate is 1.8 V/µs with a ¼ to ¾ full-scale
settling time of 7 µs.
The AD5627R/AD5647R/AD5667R feature an on-chip reference.
Versions without the R suffix require an external reference. The
on-chip reference is off at power-up and enabled via a write to a
control register. See the Internal Reference Setup section for details.
Versions packaged in a 10-lead LFCSP package have a 1.25 V
reference, giving a full-scale output of 2.5 V. These devices can
operate with a VDD supply of 2.7 V to 5.5 V. Versions packaged
in a 10-lead MSOP package have a 2.5 V reference, giving a fullscale output of 5 V. The devices are functional with a VDD supply
of 4.5 V to 5.5 V, but with a VDD supply of less than 5 V, the output
is clamped to VDD. See the Ordering Guide for a full list of
models. The internal reference associated with each device is
available at the VREFOUT pin.
A buffer is required if the reference output drives external loads.
When using the internal reference, it is recommended that a
100 nF capacitor be placed between the reference output and
GND for reference stability.
EXTERNAL REFERENCE
The AD5627/AD5667 require an external reference, which is
applied at the VREFIN pin. The VREFIN pin on the AD5627R/
AD5647R/AD5667R allows the use of an external reference if
the application requires it. The default condition of the on-chip
reference is off at power-up. All devices can be operated from a
single 2.7 V to 5.5 V supply.
Rev. B | Page 20 of 30
Data Sheet
AD5627R/AD5647R/AD5667R, AD5627/AD5667
SERIAL INTERFACE
WRITE OPERATION
The AD5627R/AD5647R/AD5667R, AD5627/AD5667 have 2wire I2C-compatible serial interfaces (refer to I2C-Bus
Specification, Version 2.1, January 2000, available from Philips
Semiconductor). The AD5627R/AD5647R/AD5667R,
AD5627/AD5667 can be connected to an I2C bus as a slave
device, under the control of a master device. See Figure 3 for a
timing diagram of a typical write sequence.
When writing to the AD5627R/AD5647R/AD5667R,
AD5627/AD5667, the user must begin with a start command
followed by an address byte (R/W= 0), after which the DAC
acknowledges that it is prepared to receive data by pulling SDA
low. The AD5627R/AD5647R/AD5667R, AD5627/AD5667
requires two bytes of data for the DAC and a command byte
that controls various DAC functions. Three bytes of data must
therefore be written to the DAC, the command byte followed by
the most significant data byte and the least significant data byte,
as shown in Figure 54. All these data bytes are acknowledged by
the AD5627R/AD5647R/AD5667R, AD5627/AD5667. A stop
condition follows.
The AD5627R/AD5647R/AD5667R, AD5627/AD5667 support
standard (100 kHz), fast (400 kHz), and high speed (3.4 MHz)
data transfer modes. High speed operation is only available on
select models. See the Ordering Guide for a full list of models.
Support is not provided for 10-bit addressing and general call
addressing.
The AD5627R/AD5647R/AD5667R, AD5627/AD5667 each have
a 7-bit slave address. The five MSBs are 00011 and the two LSBs
(A1, A0) are set by the state of the ADDR address pin. The
facility to make hardwired changes to ADDR allows the user to
incorporate up to three of these devices on one bus, as outlined
in Table 7.
Table 7. Device Address Selection
ADDR Pin Connection
VDD
No Connection
GND
A1
0
1
1
2.
3.
When reading data back from the AD5627R/AD5647R/AD5667R,
AD5627/AD5667, the user begins with a start command
followed by an address byte (R/W = 1), after which the DAC
acknowledges that it is prepared to transmit data by pulling
SDA low. Three bytes of data are then read from the DAC,
which are acknowledged by the master, as shown in Figure 55.
A stop condition follows.
HIGH SPEED MODE
A0
0
0
1
The AD5627RBRMZ and the AD5667RBRMZ offer high speed
serial communication with a clock frequency of 3.4 MHz. See
the Ordering Guide for details.
The 2-wire serial bus protocol operates as follows:
1.
READ OPERATION
The master initiates data transfer by establishing a start
condition when a high-to-low transition on the SDA line
occurs while SCL is high. The following byte is the address
byte, which consists of the 7-bit slave address. The slave
address corresponding to the transmitted address responds
by pulling SDA low during the 9th clock pulse (this is termed
the acknowledge bit). At this stage, all other devices on the
bus remain idle while the selected device waits for data to
be written to, or read from, the shift register.
Data is transmitted over the serial bus in sequences of nine
clock pulses (eight data bits followed by an acknowledge
bit). The transitions on the SDA line must occur during the
low period of SCL and remain stable during the high
period of SCL.
When all data bits have been read or written, a stop
condition is established. In write mode, the master pulls
the SDA line high during the 10th clock pulse to establish a
stop condition. In read mode, the master issues a no
acknowledge for the 9th clock pulse (that is, the SDA line
remains high). The master then brings the SDA line low
before the 10th clock pulse, and then high during the 10th
clock pulse to establish a stop condition.
High speed mode communication commences after the master
addresses all devices connected to the bus with the Master Code
00001XXX to indicate that a high speed mode transfer is to begin
(see Figure 56). No device connected to the bus is permitted to
acknowledge the high speed master code. Therefore, the code is
followed by a no acknowledge. The master must then issue a
repeated start followed by the device address. The selected
device then acknowledges the address.
All devices continue to operate in high speed mode until the
master issues a stop condition. When the stop condition is
issued, the devices return to standard/fast mode. The device
also returns to standard/fast mode when CLR is activated while
the device is in high speed mode.
Rev. B | Page 21 of 30
AD5627R/AD5647R/AD5667R, AD5627/AD5667
1
9
Data Sheet
1
9
SCL
0
SDA
0
0
1
1
A1
A0
DB23
R/W
DB22 DB21 DB20 DB19 DB18
DB17
DB16
ACK. BY
AD56x7
START BY
MASTER
ACK. BY
AD56x7
FRAME 1
SLAVE ADDRESS
FRAME 2
COMMAND BYTE
1
9
1
9
SCL
(CONTINUED)
DB15 DB14
DB13 DB12
DB11 DB10
DB9
DB7
DB8
DB6
DB5
DB4
ACK. BY
AD56x7
FRAME 3
MOST SIGNIFICANT
DATA BYTE
DB3
DB2
DB1
DB0
ACK. BY STOP BY
AD56x7 MASTER
FRAME 4
LEAST SIGNIFICANT
DATA BYTE
06342-103
SDA
(CONTINUED)
Figure 54. I2C Write Operation
1
9
1
9
SCL
0
SDA
0
0
1
1
A1
A0
DB23
R/W
DB22 DB21 DB20 DB19 DB18
DB17
ACK. BY
AD56x7
START BY
MASTER
DB16
ACK. BY
MASTER
FRAME 1
SLAVE ADDRESS
FRAME 2
COMMAND BYTE
1
9
1
9
SCL
(CONTINUED)
DB15 DB14
DB13 DB12
DB11 DB10
DB9
DB7
DB8
DB6
DB5
DB4
ACK. BY
MASTER
FRAME 3
MOST SIGNIFICANT
DATA BYTE
DB3
DB2
DB1
DB0
NO ACK. STOP BY
MASTER
FRAME 4
LEAST SIGNIFICANT
DATA BYTE
Figure 55. I2C Read Operation
FAST MODE
HIGH-SPEED MODE
1
9
1
9
SCL
0
START BY
MASTER
0
0
0
1
X
X
X
0
NO ACK
0
0
1
1
SR
HS-MODE
MASTER CODE
A0
R/W
ACK. BY
AD56x7
SERIAL BUS
ADDRESS BYTE
Figure 56. Placing the AD5627RBRMZ-2/AD5667RBRMZ-2 in High Speed Mode
Rev. B | Page 22 of 30
A1
06342-105
SDA
06342-104
SDA
(CONTINUED)
Data Sheet
AD5627R/AD5647R/AD5667R, AD5627/AD5667
INPUT SHIFT REGISTER
Table 9. DAC Address Command
The input shift register is 24 bits wide. Data is loaded into the
device as a 24-bit word under the control of a serial clock input,
SCL. The timing diagram for this operation is shown in Figure 3.
The 8 MSBs make up the command byte. DB23 is reserved and
should always be set to 0 when writing to the device. DB22 (S)
selects multiple byte operation The next three bits are the
command bits (C2, C1, C0) that control the mode of operation of
the device. See Table 8 for details. The last 3 bits of first byte are
the address bits (A2, A1, A0). See Table 9 for details. The rest of
the bits are the 16-, 14-, 12-bit data word. The data word
comprises the 16-, 14-, 12-bit input code followed by two or four
don’t cares for the AD5647R and the AD5627R/AD5627,
respectively (see Figure 59 through Figure 61).
A2
0
0
1
MULTIPLE BYTE OPERATION
Multiple byte operation is supported on the AD5627R/AD5647R/
AD5667R, AD5627/AD5667. A 2-byte operation is useful for
applications that require fast DAC updating and do not need to
change the command byte. The S bit (DB22) in the command
register can be set to 1 for 2-byte mode of operation (see Figure 57).
For standard 3-byte and 4-byte operation, the S bit (DB22) in
the command byte should be set to 0 (see Figure 58).
BROADCAST MODE
Broadcast addressing is supported on the AD5627R/AD5647R/
AD5667R, AD5627/AD5667. Broadcast addressing can be
synchronously update or power down multiple AD5627R/
AD5647R/AD5667R, AD5627/AD5667 devices. Using the
broadcast address, the AD5627R/AD5647R/AD5667R, AD5627/
AD5667 responds regardless of the states of the address pins.
Broadcast is supported only in write mode. The AD5627R/
AD5647R/AD5667R, AD5627/AD5667 broadcast address is
00010000.
Table 8. Command Definition
C2
0
0
0
0
1
1
1
1
C1
0
0
1
1
0
0
1
1
C0
0
1
0
1
0
1
0
1
Command
Write to input register n
Update DAC register n
Write to input register n, update all (software LDAC)
Write to and update DAC channel n
Power up/power down
Reset
LDAC register setup
Internal reference setup (on/off )
A1
0
0
1
A0
0
1
1
ADDRESS (n)
DAC A
DAC B
Both DACs
LDAC FUNCTION
The AD5627R/AD5647R/AD5667R, AD5627/AD5667 DACs
have double-buffered interfaces consisting of two banks of
registers, input registers and DAC registers. The input registers
are connected directly to the input shift register, and the digital
code is transferred to the relevant input register on completion
of a valid write sequence. The DAC registers contain the digital
codes used by the resistor strings.
Access to the DAC registers is controlled by the LDAC pin.
When the LDAC pin is high, the DAC registers are latched and
the input registers can change state without affecting the contents
of the DAC registers. When LDAC is brought low, however, the
DAC registers become transparent and the contents of the input
registers are transferred to them. The double-buffered interface
is useful if the user requires simultaneous updating of all DAC
outputs. The user can write to one of the input registers
individually and then, by bringing LDAC low when writing to
the other DAC input register, all outputs update simultaneously.
These devices each contain an extra feature whereby a DAC register
is not updated unless the input register has been updated since
the last time LDAC was brought low. Normally, when LDAC is
brought low, the DAC registers are filled with the contents of the
input registers. In the case of the AD5627R/AD5647R/AD5667R,
AD5627/AD5667, the DAC register updates only if the input
register has changed since the last time the DAC register was
updated, thereby removing unnecessary digital crosstalk.
The outputs of all DACs can be simultaneously updated, using
the hardware LDAC pin.
Rev. B | Page 23 of 30
AD5627R/AD5647R/AD5667R, AD5627/AD5667
BLOCK 2
S=1
BLOCK n
S=1
S=1
SLAVE
COMMAND MOST SIGNIFICANT LEAST SIGNIFICANT MOST SIGNIFICANT LEAST SIGNIFICANT
ADDRESS
BYTE
DATA BYTE
DATA BYTE
DATA BYTE
DATA BYTE
MOST SIGNIFICANT LEAST SIGNIFICANT STOP
DATA BYTE
DATA BYTE
06342-106
BLOCK 1
Data Sheet
Figure 57. Multiple Block Write with Initial Command Byte Only (S = 1)
BLOCK 2
S=0
BLOCK n
S=0
S=0
SLAVE
COMMAND MOST SIGNIFICANT LEAST SIGNIFICANT COMMAND MOST SIGNIFICANT LEAST SIGNIFICANT
ADDRESS
BYTE
DATA BYTE
DATA BYTE
BYTE
DATA BYTE
DATA BYTE
COMMAND MOST SIGNIFICANT LEAST SIGNIFICANT STOP
DATA BYTE
BYTE
DATA BYTE
Figure 58. Multiple Block Write with Command Byte in Each Block (S = 0)
S
BYTE
SELECTION
C2
C1
C0
COMMAND
A2
A1
A0
D15
D14
D13
DAC ADDRESS
COMMAND BYTE
D12
D11
D10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
DAC DATA
DAC DATA
DATA HIGH BYTE
DATA LOW BYTE
06342-108
R
RESERVED
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
Figure 59. AD5667R/AD5667 Input Shift Register (16-Bit DAC)
S
BYTE
SELECTION
C2
C1
C0
COMMAND
A2
A1
A0
D13
D12
D11
DAC ADDRESS
COMMAND BYTE
D10
D9
D8
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
D7
D6
D5
D4
D3
D2
D1
D0
X
X
DAC DATA
DAC DATA
DATA HIGH BYTE
DATA LOW BYTE
06342-109
R
RESERVED
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
R
S
RESERVED
BYTE
SELECTION
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
C2
C1
C0
COMMAND
COMMAND BYTE
A2
A1
A0
DAC ADDRESS
D11
D10
D9
D8
D7
D6
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
D5
D4
D3
D2
D1
D0
X
X
X
X
DAC DATA
DAC DATA
DATA HIGH BYTE
DATA LOW BYTE
Figure 61. AD5627R/AD5627 Input Shift Register (12-Bit DAC)
Rev. B | Page 24 of 30
06342-110
Figure 60. AD5647R Input Shift Register (14-Bit DAC)
06342-107
BLOCK 1
Data Sheet
AD5627R/AD5647R/AD5667R, AD5627/AD5667
Synchronous LDAC
POWER-DOWN MODES
The DAC registers are updated after new data is read in. LDAC
can be permanently low or pulsed.
Command 100 is reserved for the power-up/down function.
The power-up/down modes are programmed by setting Bit DB5
and Bit DB4. This defines the output state of the DAC amplifier,
as shown in Table 11. Bit DB1and Bit DB0 determine to which
DAC or DACs the power-up/down command is applied. Setting
one of these bits to 1 applies the power-up/down state defined by
DB5 and DB4 to the corresponding DAC. If a bit is 0, the state
of the DAC is unchanged. Figure 65 shows the contents of the
input shift register for the power up/down command.
Asynchronous LDAC
The outputs are not updated at the same time that the input
registers are written to. When LDAC goes low, the DAC
registers are updated with the contents of the input register.
The LDAC register gives the user full flexibility and control over
the hardware LDAC pin. This register allows the user to select
which combination of channels to simultaneously update when
the hardware LDAC pin is executed. Setting the LDAC bit
register to 0 for a DAC channel means that the update of this
channel is controlled by the LDAC pin. If this bit is set to 1, this
channel synchronously updates, that is, the DAC register is
updated after new data is read in, regardless of the state of the
LDAC pin. It effectively sees the LDAC pin as being pulled low.
See Table 10 for the LDAC register mode of operation. This
flexibility is useful in applications when the user wants to
simultaneously update select channels while the rest of the
channels are synchronously updating.
When Bit DB5 and Bit DB4 are set to 0, the deice works normally
with the normal power consumption of 400 μA at 5 V. However,
for the three power-down modes, the supply current falls to 480 nA
at 5 V. Not only does the supply current fall, but the output stage is
also internally switched from the output of the amplifier to a
resistor network of known values. This allows the output
impedance of the device to be known while the device is in
power-down mode. The outputs can either be connected
internally to GND through a 1 kΩ or 100 kΩ resistor, or left
open-circuited (three-state) as shown in Figure 62.
Table 11. Modes of Operation for the
AD5627R/AD5647R/AD5667R, AD5627/AD5667
Table 10. LDAC Register Mode of Operation:
Load DAC Register
LDAC Bits
(DB1 to DB0)
0
LDAC Pin
LDAC Operation
1/0
Determined by LDAC pin.
1
x = don’t care
The DAC registers are updated
after new data is read in.
DB5
0
DB4
0
0
1
1
1
0
1
Operating Mode
Normal operation
Power-down modes
1 kΩ pull-down to GND
100 kΩ pull-down to GND
Three-state, high impedance
RESISTOR
STRING DAC
AMPLIFIER
VOUT
POWER-DOWN
CIRCUITRY
RESISTOR
NETWORK
06342-038
Writing to the DAC using Command 110 loads the 2-bit LDAC
register [DB1:DB0]. The default for each channel is 0, that is,
the LDAC pin works normally. Setting the bits to 1 means the
DAC register is updated, regardless of the state of the LDAC
pin. See Figure 63 for contents of the input shift register during
the LDAC register setup command.
Figure 62. Output Stage During Power-Down
S
C2
C1
C0
A2
A1
A0
0
X
1
1
0
A2
A1
A0
DON’T
CARE
COMMAND
DAC ADDRESS
(DON’T CARE)
DB15 DB14 DB13 DB12 DB11 DB10
X
X
X
X
X
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
X
X
X
X
X
X
X
X
X
DON’T CARE
DB1
DB0
DACB DACA
DON’T CARE
DAC SELECT
(0 = LDAC PIN ENABLED)
Figure 63. LDAC Setup Command
Rev. B | Page 25 of 30
06342-111
R
RESERVED
The bias generator, the output amplifier, the resistor string, and
other associated linear circuitry are shut down when powerdown mode is activated. However, the contents of the DAC
register are unaffected when in power-down. The time to exit
power-down is typically 4 μs for VDD = 5 V.
AD5627R/AD5647R/AD5667R, AD5627/AD5667
Data Sheet
POWER-ON RESET AND SOFTWARE RESET
CLEAR PIN (CLR)
The AD5627R/AD5647R/AD5667R, AD5627/AD5667 contain a
power-on reset circuit that controls the output voltage during
power-up. The device powers up to 0 V and the output remains
powered up at this level until a valid write sequence is made to
the DAC. This is useful in applications where it is important to
know the state of the output of the DAC while it is in the process
of powering up. Any events on LDAC or CLR during power-on
reset are ignored.
The AD5627R/AD5647R/AD5667R, AD5627/AD5667 has an
asynchronous clear input. The CLR input is falling edge sensitive.
While CLR is low, all LDAC pulses are ignored. When CLR is
activated, zero scale is loaded to all input and DAC registers.
This clears the output to 0 V. The device exits clear code mode
on the on the falling edge of the ninth clock pulse of the last
byte of valid write. If CLR is activated during a write sequence,
the write is aborted. If CLR is activated during high speed mode,
the device exits high speed mode to standard/fast mode.
There is also a software reset function. Command 101 is the
software reset command. The software reset command contains
two reset modes that are software programmable by setting Bit DB0
in the input shift register.
Table 12 shows how the state of the bit corresponds to the
software reset modes of operation of the devices. Figure 64
shows the contents of the input shift register during the
software reset mode of operation.
After a full software reset (DB0 = 1), there must be a short time
delay, approximately 5 µs, to complete the reset. During the
reset, a low pulse can be observed on the CLR line. If the next
I2C transaction commences before the CLR line returns high,
that I2C transaction is ignored.
INTERNAL REFERENCE SETUP (R VERSIONS)
The on-chip reference is off at power-up by default. It can be
turned on by sending the reference setup command (111) and
setting DB0 in the input shift register. Table 13 shows how the
state of the bit corresponds to the mode of operation. See Figure 66
for the contents of the input shift register during the internal
reference setup command.
Table 13. Reference Setup Command
DB0
0
1
Table 12. Software Reset Modes for the
AD5627R/AD5647R/AD5667R, AD5627/AD5667
DB0
0
1 (Power-On Reset)
Registers Reset to Zero
DAC register
Input shift register
DAC register
Input shift register
LDAC register
Power-down register
Internal reference setup register
Rev. B | Page 26 of 30
Action
Internal reference off (default)
Internal reference on
C2
C1
C0
A2
A1
A0
X
1
0
1
X
X
X
DB15 DB14 DB13 DB12 DB11 DB10
X
X
X
DAC ADDRESS
(DON’T CARE)
COMMAND
X
X
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
X
X
X
X
X
X
X
X
X
RST
X
DON’T CARE
DON’T CARE
06342-113
S
0
RESET
MODE
X
DON’T
CARE
AD5627R/AD5647R/AD5667R, AD5627/AD5667
RESERVED
Data Sheet
S
C2
C1
C0
A2
A1
A0
0
X
1
0
0
X
X
X
DON’T
CARE
DB15 DB14 DB13 DB12 DB11 DB10
X
X
X
X
DAC ADDRESS
(DON’T CARE)
COMMAND
X
X
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
X
X
X
X
PD1
PD0
X
X
DON’T CARE
DON’T CARE
DB1
DB0
DACB DACA
POWERDON’T CARE
DOWN MODE
DAC SELECT
(1 = DAC SELECTED)
06342-112
R
RESERVED
Figure 64. Software Reset Command
C2
C1
C0
A2
A1
A0
X
1
1
1
X
X
X
DON’T
CARE
COMMAND
DAC ADDRESS
(DON’T CARE)
DB15 DB14 DB13 DB12 DB11 DB10
X
X
X
X
X
X
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
X
X
X
X
X
X
X
X
X
REF
DON’T CARE
Figure 66. Reference Setup Command
Rev. B | Page 27 of 30
DON’T CARE
06342-114
S
0
REFERENCE
MODE
R
RESERVED
Figure 65. Power Up/Down Command
AD5627R/AD5647R/AD5667R, AD5627/AD5667
Data Sheet
APPLICATION INFORMATION
Because the supply current required by the AD5627R/AD5647R/
AD5667R, AD5627/AD5667 is extremely low, an alternative option
is to use a voltage reference to supply the required voltage to the
device (see Figure 67). This is especially useful if the power supply
is quite noisy, or if the system supply voltages are at some value
other than 5 V or 3 V, for example, 15 V. The voltage reference
outputs a steady supply voltage for the AD5627R/AD5647R/
AD5667R, AD5627/AD5667. If the low dropout REF195 is used, it
must supply 450 µA of current to the AD5627R/AD5647R/
AD5667R, AD5627/AD5667 with no load on the output of the
DAC. When the DAC output is loaded, the REF195 must also
supply the current to the load. The total current required (with
a 5 kΩ load on the DAC output) is
This is an output voltage range of ±5 V, with 0x0000 corresponding to a −5 V output, and 0xFFFF corresponding to a
+5 V output.
R2 = 10kΩ
+5V
R1 = 10kΩ
AD820/
OP295
10µF
15V
REF195
5V
VDD
SCL
SDA
AD5627R/
AD5647R/
AD5667R/
AD5627/
AD5667
VOUT = 0V TO 5V
GND
06342-043
2-WIRE
SERIAL
INTERFACE
Figure 67. REF195 as Power Supply to the AD5627R/AD5647R/AD5667R,
AD5627/AD5667
BIPOLAR OPERATION USING THE
AD5627R/AD5647R/AD5667R, AD5627/AD5667
The AD5627R/AD5647R/AD5667R, AD5627/AD5667 has been
designed for single-supply operation, but a bipolar output range
is also possible using the circuit in Figure 68. The circuit gives an
output voltage range of ±5 V. Rail-to-rail operation at the amplifier
output is achieved using an AD820 or an OP295 as the output
amplifier.
The output voltage for any input code can be calculated as
follows:
D R1 + R2
R2
VO = V DD ×
×
− V DD ×
65
,
R1
536
R1
where D represents the input code in decimal (0 to 65535).
With VDD = 5 V, R1 = R2 = 10 kΩ,
10 × D
VO =
−5 V
65,536
0.1µF
VOUT
AD5627R/
AD5647R/
AD5667R/
AD5627/
AD5667
GND SCL
–5V
SDA
2-WIRE
SERIAL
INTERFACE
450 µA + (5 V/5 kΩ) = 1.45 mA
The load regulation of the REF195 is typically 2 ppm/mA,
resulting in a 2.9 ppm (14.5 µV) error for the 1.45 mA current
drawn from it. This corresponds to a 0.191 LSB error.
VDD
+5V
VO
±5V
06342-044
USING A REFERENCE AS A POWER SUPPLY FOR THE
AD5627R/AD5647R/AD5667R, AD5627/AD5667
Figure 68. Bipolar Operation with the AD5627R/AD5647R/AD5667R,
AD5627/AD5667
POWER SUPPLY BYPASSING AND GROUNDING
When accuracy is important in a circuit, it is helpful to carefully
consider the power supply and ground return layout on the board.
The printed circuit board containing the AD5627R/AD5647R/
AD5667R, AD5627/AD5667 should have separate analog and
digital sections, each having its own area of the board. If the
AD5627R/AD5647R/AD5667R, AD5627/AD5667 are in a system
where other devices require an AGND to DGND connection, the
connection should be made at one point only. This ground point
should be as close as possible to the AD5627R/AD5647R/
AD5667R, AD5627/AD5667.
The power supply to the AD5627R/AD5647R/AD5667R,
AD5627/AD5667 should be bypassed with 10 µF and 0.1 µF
capacitors. The capacitors should be located as close as possible
to the device, with the 0.1 µF capacitor ideally right up against the
device. The 10 µF capacitor should be the tantalum bead type. It
is important that the 0.1 µF capacitor have low effective series
resistance (ESR) and effective series inductance (ESI), for example,
common ceramic types of capacitors. This 0.1 µF capacitor
provides a low impedance path to ground for high frequencies
caused by transient currents due to internal logic switching.
The power supply line itself should have as large a trace as
possible to provide a low impedance path and to reduce glitch
effects on the supply line. Clocks and other fast switching
digital signals should be shielded from other devices of the
board by digital ground. Avoid crossover of digital and analog
signals if possible. When traces cross on opposite sides of the
board, ensure that they run at right angles to each other to
reduce feedthrough effects through the board. The best board
layout technique is the microstrip technique where the
component side of the board is dedicated to the ground plane
only and the signal traces are placed on the solder side.
However, this is not always possible with a two-layer board.
Rev. B | Page 28 of 30
Data Sheet
AD5627R/AD5647R/AD5667R, AD5627/AD5667
OUTLINE DIMENSIONS
2.48
2.38
2.23
3.10
3.00 SQ
2.90
0.50 BSC
10
6
PIN 1 INDEX
AREA
1.74
1.64
1.49
EXPOSED
PAD
0.50
0.40
0.30
PIN 1
INDICATOR
(R 0.15)
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.30
0.25
0.20
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
02-05-2013-C
0.80
0.75
0.70
SEATING
PLANE
0.20 MIN
1
5
TOP VIEW
0.20 REF
Figure 69. 10-Lead Lead Frame Chip Scale Package [LFCSP_WD]
3 mm x 3 mm Body, Very Very Thin, Dual Lead
(CP-10-9)
Dimensions shown in millimeters
3.10
3.00
2.90
10
3.10
3.00
2.90
1
5.15
4.90
4.65
6
5
PIN 1
IDENTIFIER
0.50 BSC
0.95
0.85
0.75
15° MAX
1.10 MAX
0.30
0.15
6°
0°
0.23
0.13
0.70
0.55
0.40
COMPLIANT TO JEDEC STANDARDS MO-187-BA
Figure 70. 10-Lead Mini Small Outline Package [MSOP]
(RM-10)
Dimensions shown in millimeters
Rev. B | Page 29 of 30
091709-A
0.15
0.05
COPLANARITY
0.10
AD5627R/AD5647R/AD5667R, AD5627/AD5667
Data Sheet
ORDERING GUIDE
Model 1
AD5627BCPZ-R2
AD5627BCPZ-REEL7
AD5627BRMZ
AD5627BRMZ-REEL7
AD5627RBCPZ-R2
AD5627RBCPZ-REEL7
AD5627RBRMZ-1
AD5627RBRMZ-1REEL7
AD5627RBRMZ-2
AD5627RBRMZ-2REEL7
AD5647RBCPZ-R2
AD5647RBCPZ-REEL7
AD5647RBRMZ
AD5647RBRMZ-REEL7
AD5667BCPZ-R2
AD5667BCPZ-REEL7
AD5667BRMZ
AD5667BRMZ-REEL7
AD5667RBCPZ-R2
AD5667RBCPZ-REEL7
AD5667RBRMZ-1
AD5667RBRMZ-1REEL7
AD5667RBRMZ-2
AD5667RBRMZ-2REEL7
EVAL-AD5667RSDZ
1
Temperature
Range
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
−40°C to +105°C
Accuracy
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±1 LSB INL
±4 LSB INL
±4 LSB INL
±4 LSB INL
±4 LSB INL
±12 LSB INL
±12 LSB INL
±12 LSB INL
±12 LSB INL
±12 LSB INL
±12 LSB INL
±12 LSB INL
±12 LSB INL
±12 LSB INL
±12 LSB INL
On-Chip
Reference
None
None
None
None
1.25 V
1.25 V
2.5 V
2.5 V
2.5 V
2.5 V
1.25 V
1.25 V
2.5 V
2.5 V
None
None
None
None
1.25 V
1.25 V
2.5 V
2.5 V
2.5 V
2.5 V
Max I2C
Speed
400 kHz
400 kHz
400 kHz
400 kHz
400 kHz
400 kHz
400 kHz
400 kHz
3.4 MHz
3.4 MHz
400 kHz
400 kHz
400 kHz
400 kHz
400 kHz
400 kHz
400 kHz
400 kHz
400 kHz
400 kHz
400 kHz
400 kHz
3.4 MHz
3.4 MHz
Package
Description
10-Lead LFCSP_WD
10-Lead LFCSP_WD
10-Lead MSOP
10-Lead MSOP
10-Lead LFCSP_WD
10-Lead LFCSP_WD
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead LFCSP_WD
10-Lead LFCSP_WD
10-Lead MSOP
10-Lead MSOP
10-Lead LFCSP_WD
10-Lead LFCSP_WD
10-Lead MSOP
10-Lead MSOP
10-Lead LFCSP_WD
10-Lead LFCSP_WD
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
10-Lead MSOP
Evaluation Board
Z = RoHS Compliant Part.
I2C refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors).
©2007–2016 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06342-0-9/16(B)
Rev. B | Page 30 of 30
Package
Option
CP-10-9
CP-10-9
RM-10
RM-10
CP-10-9
CP-10-9
RM-10
RM-10
RM-10
RM-10
CP-10-9
CP-10-9
RM-10
RM-10
CP-10-9
CP-10-9
RM-10
RM-10
CP-10-9
CP-10-9
RM-10
RM-10
RM-10
RM-10
Branding
DA1
DA1
DA1
DA1
D9J
D9J
DA7
DA7
DA8
DA8
D9G
D9G
D9G
D9G
D9Z
D9Z
D9Z
D9Z
D8X
D8X
DA5
DA5
DA6
DA6
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