14-Bit, 3 GSPS, JESD204B,
Dual Analog-to-Digital Converter
AD9208
Data Sheet
FEATURES
2 integrated, wideband digital processors per channel
48-bit NCO
4 cascaded half-band filters
Phase coherent NCO switching
Up to 4 channels available
Serial port control
Integer clock with divide by 2 and divide by 4 options
Flexible JESD204B lane configurations
On-chip dither
JESD204B (Subclass 1) coded serial digital outputs
Support for lane rates up to 16 Gbps per lane
1.65 W total power per channel at 3 GSPS (default settings)
Performance at −2 dBFS amplitude, 2.6 GHz input
SFDR = 70 dBFS
SNR = 57.2 dBFS
Performance at −9 dBFS amplitude, 2.6 GHz input
SFDR = 78 dBFS
SNR = 59.5 dBFS
Integrated input buffer
Noise density = −152 dBFS/Hz
0.975 V, 1.9 V, and 2.5 V dc supply operation
9 GHz analog input full power bandwidth (−3 dB)
Amplitude detect bits for efficient AGC implementation
APPLICATIONS
Diversity multiband and multimode digital receivers
3G/4G, TD-SCDMA, W-CDMA, and GSM, LTE, LTE-A
Electronic test and measurement systems
Phased array radar and electronic warfare
DOCSIS 3.0 CMTS upstream receive paths
HFC digital reverse path receivers
FUNCTIONAL BLOCK DIAGRAM
ADC
CORE
VREF
ADC
CORE
BUFFER
DRVDD2
(1.9V)
SPIVDD
(1.9V)
14
DIGITAL DOWNCONVERTER
DIGITAL DOWNCONVERTER
JESD204B
LINK
AND
Tx
OUTPUTS
SYNCINB±
PDWN/STBY
SYSREF±
8
SERDOUT0±
SERDOUT1±
SERDOUT2±
SERDOUT3±
SERDOUT4±
SERDOUT5±
SERDOUT6±
SERDOUT7±
JESD204B
SUBCLASS 1
CONTROL
CLOCK
DISTRIBUTION
FD_A/GPIO_A0
GPIO MUX
CLK+
CLK–
÷2
SPI AND
CONTROL
REGISTERS
AD9208
÷4
AGND
GPIO_A1
FD_B/GPIO_B0
GPIO_B1
SDIO SCLK
CSB
DRGND
DGND
15547-001
VIN+B
VIN–B
DRVDD1
(0.975V)
14
SIGNAL
MONITOR
FAST
DETECT
DVDD
(0.975V)
CROSSBAR MUX
BUFFER
AVDD3 AVDD1_SR
(0.975V)
(2.5V)
CROSSBAR MUX
VIN+A
VIN–A
AVDD2
(1.9V)
PROGRAMMABLE
FIR FILTER
AVDD1
(0.975V)
Figure 1.
Rev. 0
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AD9208
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
DDC Complex to Real Conversion ......................................... 57
Applications ....................................................................................... 1
DDC Mixed Decimation Settings ............................................ 58
Functional Block Diagram .............................................................. 1
DDC Example Configurations ................................................. 59
Revision History ............................................................................... 3
DDC Power Consumption ........................................................ 63
General Description ......................................................................... 4
Signal Monitor ................................................................................ 64
Specifications..................................................................................... 5
SPORT over JESD204B .............................................................. 65
DC Specifications ......................................................................... 5
Digital Outputs ............................................................................... 67
AC Specifications.......................................................................... 6
Introduction to the JESD204B Interface ................................. 67
Digital Specifications ................................................................... 7
JESD204B Overview .................................................................. 67
Switching Specifications .............................................................. 9
Functional Overview ................................................................. 68
Timing Specifications ................................................................ 10
JESD204B Link Establishment ................................................. 68
Absolute Maximum Ratings.......................................................... 12
Physical Layer (Driver) Outputs .............................................. 70
Thermal Resistance .................................................................... 12
fS × 4 Mode .................................................................................. 71
ESD Caution ................................................................................ 12
Setting Up the AD9208 digital interface .................................. 72
Pin Configuration and Function Descriptions ........................... 13
Deterministic Latency.................................................................... 78
Typical Performance Characteristics ........................................... 16
Subclass 0 Operation.................................................................. 78
Equivalent Circuits ......................................................................... 22
Subclass 1 Operation.................................................................. 78
Theory of Operation ...................................................................... 24
Multichip Synchronization............................................................ 80
ADC Architecture ...................................................................... 24
Normal Mode.............................................................................. 80
Analog Input Considerations.................................................... 24
Timestamp Mode ....................................................................... 80
Voltage Reference ....................................................................... 28
SYSREF Input .............................................................................. 82
DC Offset Calibration ................................................................ 29
SYSREF± Setup/Hold Window Monitor ................................. 84
Clock Input Considerations ...................................................... 29
Latency ............................................................................................. 86
Power-Down/Standby Mode..................................................... 31
End to End Total Latency .......................................................... 86
Temperature Diode .................................................................... 31
Example Latency Calculations.................................................. 86
ADC Overrange and Fast Detect .................................................. 33
LMFC Referenced Latency........................................................ 86
ADC Overrange .......................................................................... 33
Test Modes ....................................................................................... 88
Fast Threshold Detection (FD_A and FD_B) ........................ 33
ADC Test Modes ........................................................................ 88
ADC Application Modes and JESD204B Tx Converter Mapping
........................................................................................................... 34
JESD204B Block Test Modes .................................................... 89
Serial Port Interface ........................................................................ 91
Programmable FIR filters .............................................................. 36
Configuration Using the SPI ..................................................... 91
Supported Modes........................................................................ 36
Hardware Interface..................................................................... 91
Programming Instructions ........................................................ 38
SPI Accessible Features .............................................................. 91
Digital Downconverter (DDC) ..................................................... 40
Memory Map .................................................................................. 92
DDC I/Q Input Selection .......................................................... 40
Reading the Memory Map Register Table............................... 92
DDC I/Q Output Selection ....................................................... 40
Memory Map Register Details .................................................. 93
DDC General Description ........................................................ 40
Applications Information ............................................................ 134
DDC Frequency Translation ..................................................... 43
Power Supply Recommendations........................................... 134
DDC Decimation Filters............................................................ 51
Layout Guidelines..................................................................... 135
DDC Gain Stage ......................................................................... 57
AVDD1_SR (Pin E7) and AGND (Pin E6 and Pin E8) ........... 135
Rev. 0 | Page 2 of 136
Data Sheet
AD9208
Outline Dimensions ..................................................................... 136
Ordering Guide ........................................................................ 136
REVISION HISTORY
4/2017—Revision 0: Initial Version
Rev. 0 | Page 3 of 136
AD9208
Data Sheet
GENERAL DESCRIPTION
The AD9208 is a dual, 14-bit, 3 GSPS analog-to-digital converter
(ADC). The device has an on-chip buffer and a sample-andhold circuit designed for low power, small size, and ease of use.
This product is designed to support communications applications
capable of direct sampling wide bandwidth analog signals of up
to 5 GHz. The −3 dB bandwidth of the ADC input is 9 GHz.
The AD9208 is optimized for wide input bandwidth, high sampling
rate, excellent linearity, and low power in a small package.
capability. The signal monitoring block provides additional
information about the signal being digitized by the ADC.
The dual ADC cores feature a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth inputs supporting a variety of
user-selectable input ranges. An integrated voltage reference
eases design considerations. The analog input and clock signals
are differential inputs. The ADC data outputs are internally
connected to four digital downconverters (DDCs) through a
crossbar mux. Each DDC consists of up to five cascaded signal
processing stages: a 48-bit frequency translator (numerically
controlled oscillator (NCO)), and up to four half-band decimation
filters. The NCO has the option to select preset bands over the
general-purpose input/output (GPIO) pins, which enables the
selection of up to three bands. Operation of the AD9208 between
the DDC modes is selectable via SPI-programmable profiles.
The AD9208 has flexible power-down options that allow
significant power savings when desired. All of these features can
be programmed using a 3-wire serial port interface (SPI).
In addition to the DDC blocks, the AD9208 has several functions
that simplify the automatic gain control (AGC) function in a
communications receiver. The programmable threshold detector
allows monitoring of the incoming signal power using the fast
detect control bits in Register 0x0245 of the ADC. If the input
signal level exceeds the programmable threshold, the fast detect
indicator goes high. Because this threshold indicator has low
latency, the user can quickly turn down the system gain to avoid
an overrange condition at the ADC input. In addition to the fast
detect outputs, the AD9208 also offers signal monitoring
The user can configure the Subclasss 1 JESD204B-based high
speed serialized output in a variety of one-lane, two-lane, fourlane, and eight-lane configurations, depending on the DDC
configuration and the acceptable lane rate of the receiving logic
device. Multidevice synchronization is supported through the
SYSREF± and SYNCINB± input pins.
The AD9208 is available in a Pb-free, 196-ball BGA, specified
over the −40°C to +85°C ambient temperature range. This
product is protected by a U.S. patent.
Note that throughout this data sheet, multifunction pins, such
as FD_A/GPIO_A0, are referred to either by the entire pin
name or by a single function of the pin, for example, FD_A,
when only that function is relevant.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
6.
7.
Rev. 0 | Page 4 of 136
Wide, input −3 dB bandwidth of 9 GHz supports direct radio
frequency (RF) sampling of signals up to about 5 GHz.
Four integrated, wideband decimation filter and NCO
blocks supporting multiband receivers.
Fast NCO switching enabled through the GPIO pins.
A SPI controls various product features and functions to
meet specific system requirements.
Programmable fast overrange detection and signal
monitoring.
On-chip temperature diode for system thermal management.
12 mm × 12 mm, 196-ball BGA.
Data Sheet
AD9208
SPECIFICATIONS
DC SPECIFICATIONS
AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.9 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.9 V,
SPIVDD = 1.9 V, specified maximum sampling rate, 1.7 V p-p full-scale differential input, input amplitude (AIN) = −2.0 dBFS, L = 8, M = 2,
F = 1, −10°C ≤ TJ ≤ +120°C,1 unless otherwise noted. Typical specifications represent performance at TJ = 70°C (TA = 25°C).
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Offset Matching
Gain Error
Gain Matching
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
Gain Error
INTERNAL VOLTAGE REFERENCE
INPUT-REFERRED NOISE
ANALOG INPUTS
Differential Input Voltage Range
Common-Mode Voltage(VCM)
Differential Input Resistance
Differential Input Capacitance
Differential Input Return Loss at 2.1 GHz2
−3 dB Bandwidth
POWER SUPPLY
AVDD1
AVDD2
AVDD3
AVDD1_SR
DVDD
DRVDD1
DRVDD2
SPIVDD
IAVDD1
IAVDD2
IAVDD3
IAVDD1_SR
IDVDD
IDRVDD13
IDRVDD2
ISPIVDD
POWER CONSUMPTION
Total Power Dissipation (Including Output Drivers)4
Power-Down Dissipation
Standby5
Min
14
−5.89
−2.9
−0.63
−26
1.32
0.95
1.85
2.44
0.95
0.95
0.95
1.85
1.85
Typ
%FSR
%FSR
%FSR
%FSR
LSB
LSB
±15
440
0.5
5.6
ppm/°C
ppm/°C
V
LSB rms
1.7
1.35
200
0.25
−7
9
0.975
1.9
2.5
0.975
0.975
0.975
1.9
1.9
640
790
110
24
480
320
30
1
The junction temperature (TJ) range of −10°C to +120°C translates to an ambient temperature (TA) range of −40°C to +85°C.
For more information, see the Analog Input Considerations section.
All lanes running. Power dissipation on DRVDD1 changes with lane rate and number of lanes used.
4
Default mode. No DDCs used.
5
Can be controlled by the SPI.
2
3
Rev. 0 | Page 5 of 136
Unit
Bits
Guaranteed
0
0
±1
+5.89
±0.2
+2.9
±0.4
+0.74
±6
+21
3.3
300
1.65
1
Max
1.52
1.0
1.95
2.56
1.0
1.0
1.0
1.95
1.95
765
885
120
50
1020
590
35
5
V p-p
V
Ω
pF
dB
GHz
V
V
V
V
V
V
V
V
mA
mA
mA
mA
mA
mA
mA
mA
W
mW
mW
AD9208
Data Sheet
AC SPECIFICATIONS
AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.9 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.9 V,
SPIVDD = 1.9 V, specified maximum sampling rate, 1.7 V p-p full-scale differential input, default SPI settings, −10°C ≤ TJ ≤ +120°C,1
unless otherwise noted. Typical specifications represent performance at TJ = 70°C (TA = 25°C).
Table 2.
Parameter2
NOISE DENSITY3
1.7 V p-p Setting
2.04 V p-p Setting
NOISE FIGURE
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 255 MHz
fIN = 255 MHz (2.04 V p-p Setting)
fIN = 765 MHz
fIN = 900 MHz
fIN = 1800 MHz
fIN = 2100 MHz
fIN = 2600 MHz
fIN = 3950 MHz
SIGNAL-TO-NOISE-AND-DISTORTION RATIO (SINAD)
fIN = 255 MHz
fIN = 255 MHz (2.04 V p-p Setting)
fIN = 765 MHz
fIN = 900 MHz
fIN = 1800 MHz
fIN = 2100 MHz
fIN = 2600 MHz
fIN = 3950 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 255 MHz
fIN = 765 MHz
fIN = 900 MHz
fIN = 1800 MHz
fIN = 2100 MHz
fIN = 2600 MHz
fIN = 3950 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR), SECOND OR THIRD HARMONIC
fIN = 255 MHz
fIN = 255 MHz (2.04 V p-p Setting)
fIN = 765 MHz
fIN = 900 MHz
fIN = 1800 MHz
fIN = 2100 MHz
fIN = 2600 MHz
fIN = 3950 MHz
Rev. 0 | Page 6 of 136
AIN = −2 dBFS
Min Typ
Max
52.1
46.6
7.5
51
AIN = −9 dBFS
Min Typ
Max
Unit
−152
−154
24.5
−152
−154
24.5
dBFS/Hz
dBFS/Hz
dB
60.2
61.4
59.8
59.5
58.7
58.2
57.2
55.1
60.2
61.8
60.2
60.2
60.0
59.8
59.5
58.6
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
59.7
60.0
58.8
58.6
57.4
56.7
56.1
52.8
60.0
61.5
60.0
59.9
59.7
59.4
59.2
58.2
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
9.6
9.5
9.4
9.2
9.1
9.0
8.5
9.7
9.7
9.7
9.6
9.6
9.5
9.4
Bits
dBFS
Bits
Bits
Bits
Bits
Bits
71
65
71
71
69
67
70
58
78
83
79
78
81
73
78
73
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
Data Sheet
AD9208
Parameter2
WORST OTHER, EXCLUDING SECOND OR THIRD HARMONIC
fIN = 255 MHz
fIN = 255 MHz (2.04 V p-p Setting)
fIN = 765 MHz
fIN = 900 MHz
fIN = 1800 MHz
fIN = 2100 MHz
fIN = 2600 MHz
fIN = 3950 MHz
TWO-TONE, THIRD-ORDER INTERMODULATION DISTORTION (IMD3)
fIN1 = 1.842 GHz, fIN2 = 1.847 GHz, AIN1 and AIN2 = −8.0 dBFS
fIN1 = 1.842 GHz, fIN2 = 1.847 GHz, AIN1 and AIN2 = −15.0 dBFS
fIN1 = 2.62 GHz, fIN2 = 2.69 GHz, AIN1 and AIN2 = −8.0 dBFS
fIN1 = 2.62 GHz, fIN2 = 2.69 GHz, AIN1 and AIN2 = −15.0 dBFS
fIN1 = 2.62 GHz, fIN2 = 2.69 GHz, AIN1 and AIN2 = −8.0 dBFS; Full-Scale Voltage
(VFS) = 1.13 V p-p
fIN1 = 2.62 GHz, fIN2 = 2.69 GHz, AIN1 and AIN2 = −15.0 dBFS; VFS = 1.13 V p-p
CROSSTALK4
Overrange Condition5
ANALOG INPUT BANDWIDTH, FULL POWER6
AIN = −2 dBFS
Min Typ
Max
−75
−89
−90
−90
−89
−81
−80
−84
−80
AIN = −9 dBFS
Min Typ
Max
−90
−90
−89
−90
−94
−98
−90
−90
−73
−87
−69
−88
−75
−111
>90
>90
5
>90
>90
5
Unit
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
dB
dB
GHz
1
The junction temperature (TJ) range of −10°C to +120°C translates to an ambient temperature (TA) range of −40°C to+ 85°C.
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed.
3
Noise density is measured at a low analog input frequency (30 MHz).
4
Crosstalk is measured at 950 MHz with a −1.0 dBFS analog input on one channel, and no input on the adjacent channel.
5
The overrange condition is specified with 3 dB of the full-scale input range.
6
Full power bandwidth is the bandwidth of operation in which proper ADC performance can be achieved.
2
DIGITAL SPECIFICATIONS
AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.9 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.9 V,
SPIVDD = 1.9 V, specified maximum sampling rate, 1.7 V p-p full-scale differential input, AIN = −2.0 dBFS, L = 8, M = 2, F = 1, −10°C ≤
TJ ≤ +120°C,1 unless otherwise noted. Typical specifications represent performance at TJ = 70°C (TA = 25°C).
Table 3.
Parameter
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Differential Input Voltage
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
Differential Input Return Loss at 3 GHz2
SYSTEM REFERENCE (SYSREF) INPUTS (SYSREF+, SYSREF−)
Logic Compliance
Differential Input Voltage
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance (Differential)
LOGIC INPUTS (SDIO, SCLK, CSB, PDWN/STBY, FD_A/GPIO_A0,
FD_B/GPIO_B0, GPIO_A1, GPIO_B1)
Logic Compliance
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Min
300
400
Typ
LVDS/LVPECL
800
0.675
106
0.9
−9.4
LVDS/LVPECL
800
0.675
18
1
Max
Unit
1800
mV p-p
V
Ω
pF
dB
1800
2.0
mV p-p
V
kΩ
pF
CMOS
0.65 × SPIVDD
0
0.35 × SPIVDD
30
Rev. 0 | Page 7 of 136
V
V
kΩ
AD9208
Parameter
LOGIC OUTPUTS (SDIO, FD_A, FD_B)
Logic Compliance
Logic 1 Voltage (IOH = 4 mA)
Logic 0 Voltage (IOL = 4 mA)
SYNCIN INPUT (SYNCINB+/SYNCINB−)
Logic Compliance
Differential Input Voltage
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
SYNCINB+ INPUT
Logic Compliance
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
DIGITAL OUTPUTS (SERDOUTx±, x = 0 TO 7)
Logic Compliance
Differential Output Voltage
Differential Termination Impedance
1
2
Data Sheet
Min
Typ
Max
Unit
0.45
V
V
CMOS
SPIVDD − 0.45V
0
400
LVDS/LVPECL
800
0.675
18
1
1800
2.0
mV p-p
V
kΩ
pF
CMOS
0.9 × DRVDD1
2 × DRVDD1
0.1 × DRVDD1
2.6
V
V
kΩ
SST
360
80
560
100
The junction temperature (TJ) range of −10°C to +120°C translates to an ambient temperature (TA) range of −40°C to+85°C.
Reference impedance = 100 Ω.
Rev. 0 | Page 8 of 136
770
120
mV p-p
Ω
Data Sheet
AD9208
SWITCHING SPECIFICATIONS
AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.9 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.9 V,
SPIVDD = 1.9 V, specified maximum sampling rate, 1.7 V p-p full-scale differential input, AIN = −2.0 dBFS, default SPI settings, −10°C ≤
TJ ≤ +120°C,1 unless otherwise noted. Typical specifications represent performance at TJ = 70°C (TA = 25°C).
Table 4.
Parameter
CLOCK
Clock Rate (at CLK+/CLK− Pins)
Sample Rate2
Clock Pulse Width High
Clock Pulse Width Low
OUTPUT PARAMETERS
Unit Interval (UI)3
Rise Time (tR) (20% to 80% into 100 Ω Load)
Fall Time (tF) (20% to 80% into 100 Ω Load)
Phase-Locked Loop (PLL) Lock Time
Data Rate per Channel (Nonreturn to Zero)4
LATENCY5
Pipeline Latency6
Fast Detect Latency
WAKE-UP TIME
Standby
Power-Down
NCO CHANNEL SELECTION TO OUTPUT
APERTURE
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
Out of Range Recovery Time
Min
Typ
Max
Unit
2500
161.29
161.29
3
3000
166.67
166.67
6
3100
192.31
192.31
GHz
MSPS
ps
ps
66.67
26
26
5
15
592.6
ps
ps
ps
ms
Gbps
62.5
1.6875
16
75
26
Clock cycles
Clock cycles
400
15
μs
ms
Clock cycles
8
250
55
1
1
The junction temperature (TJ) range of −10°C to +120°C translates to an ambient temperature (TA) range of −40°C to +85°C.
The maximum sample rate is the clock rate after the divider.
3
Baud rate = 1/UI. A subset of this range can be supported.
4
Default L = 8. This number can be changed based on the sample rate and decimation ratio.
5
No DDCs used. L = 8, M = 2, and F = 1.
6
Refer to the Latency section for more details.
2
Rev. 0 | Page 9 of 136
ps
fs rms
Clock cycles
AD9208
Data Sheet
TIMING SPECIFICATIONS
Table 5.
Parameter
CLK+ to SYSREF+ TIMING REQUIREMENTS
tSU_SR
tH_SR
SPI TIMING REQUIREMENTS
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tACCESS
Description
Min
Device clock to SYSREF+ setup time
Device clock to SYSREF+ hold time
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the SCLK
Setup time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK must be in a logic high state
Minimum period that SCLK must be in a logic low state
Maximum time delay between the falling edge of SCLK and
output data valid for a read operation
Time required for the SDIO pin to switch from an output to an
input, relative to the SCLK rising edge (not shown in Figure 4)
tDIS_SDIO
10
N – 75
N+1
N – 73
SAMPLE N
N – 72
N–1
CLK–
CLK+
CLK–
SERDOUT0–
SERDOUT1–
SERDOUT1+
SERDOUT2–
SERDOUT2+
SERDOUT3–
SERDOUT3+
SERDOUT4–
SERDOUT4+
SERDOUT5–
SERDOUT5+
SERDOUT6–
SERDOUT6+
SERDOUT7–
SERDOUT7+
A
B
C
D
E
F
G
H
I
J
CONVERTER0
SAMPLE N – 75 MSB
A
B
C
D
E
F
G
H
I
J
CONVERTER0
SAMPLE N – 75 LSB
A
B
C
D
E
F
G
H
I
J
CONVERTER0
SAMPLE N – 74 MSB
A
B
C
D
E
F
G
H
I
J
CONVERTER0
SAMPLE N – 74 LSB
A
B
C
D
E
F
G
H
I
J
CONVERTER1
SAMPLE N – 75 MSB
A
B
C
D
E
F
G
H
I
J
CONVERTER1
SAMPLE N – 75 LSB
A
B
C
D
E
F
G
H
I
J
CONVERTER1
SAMPLE N – 74 MSB
A
B
C
D
E
F
G
H
I
J
CONVERTER1
SAMPLE N – 74 LSB
SAMPLE N – 75 AND N – 74
ENCODED INTO ONE
8-BIT/10-BIT SYMBOL
Figure 2. Data Output Timing Diagram
Rev. 0 | Page 10 of 136
15547-002
CLK+
SERDOUT0+
Unit
−65
95
ps
ps
6
ns
ns
ns
ns
ns
ns
ns
ns
10
ns
APERTURE DELAY
N – 74
Max
2
2
40
2
2
10
10
Timing Diagrams
ANALOG
INPUT
SIGNAL
Typ
Data Sheet
AD9208
CLK–
CLK+
tSU_SR
tH_SR
15547-003
SYSREF–
SYSREF+
Figure 3. SYSREF± Setup and Hold Timing Diagram
tDS
tS
tDH
tHIGH
tCLK
tACCESS
tH
tLOW
CSB
SCLK DON’T CARE
R/W
A14
A13
A12
A11
A10
A9
A8
A7
D5
Figure 4. SPI Interface Timing Diagram
Rev. 0 | Page 11 of 136
D4
D3
D2
D1
D0
DON’T CARE
15547-004
SDIO DON’T CARE
DON’T CARE
AD9208
Data Sheet
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 6.
Parameter
Electrical
AVDD1 to AGND
AVDD1_SR to AGND
AVDD2 to AGND
AVDD3 to AGND
DVDD to DGND
DRVDD1 to DRGND
DRVDD2 to DRGND
SPIVDD to DGND
AGND to DRGND
AGND to DGND
DGND to DRGND
VIN±x to AGND
CLK± to AGND
SCLK, SDIO, CSB to DGND
PDWN/STBY to DGND
SYSREF± to AGND
SYNCINB± to DRGND
Junction Temperature Range (TJ)
Storage Temperature Range,
Ambient (TA)
Rating
1.05 V
1.05 V
2.0 V
2.70 V
1.05 V
1.05 V
2.0 V
2.0 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
−0.3 V to +0.3 V
AGND − 0.3 V to AVDD3 + 0.3 V
AGND − 0.3 V to AVDD1 + 0.3 V
DGND − 0.3 V to SPIVDD + 0.3 V
DGND − 0.3 V to SPIVDD + 0.3 V
2.5 V
2.5 V
−40°C to +125°C
−65°C to +150°C
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Close attention to
PCB thermal design is required. θJA is the natural convection
junction-to-ambient thermal resistance measured in a one cubic
foot sealed enclosure. θJC is the junction to case thermal resistance.
Table 7. Thermal Resistance
Package Type
BP-196-41
1
θJA
16.26
θJC_TOP
1.4
ΨJB
5.44
ΨJT
1.68
Unit
°C/W
Test Condition 1: Thermal impedance simulated values are based on JEDEC
2S2P thermal test board with 190 thermal vias. See JEDEC JESD51.
ESD CAUTION
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. 0 | Page 12 of 136
Data Sheet
AD9208
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD9208
1
2
3
4
5
6
7
8
9
10
11
12
13
14
A
AVDD2
AVDD2
AVDD1
AVDD1 1
AVDD1 1
AGND1
CLK+
CLK–
AGND1
AVDD1 1
AVDD1 1
AVDD1
AVDD2
AVDD2
B
AVDD2
AVDD2
AVDD1
AVDD1 1
AGND
AGND1
AGND1
AGND1
AGND1
AGND
AVDD1 1
AVDD1
AVDD2
AVDD2
C
AVDD2
AVDD2
AVDD1
AGND
AGND
AGND1
AGND1
AGND1
AGND1
AGND
AGND
AVDD1
AVDD2
AVDD2
D
AVDD3
AGND
AGND
AGND
AGND
AGND
AGND1
AGND1
AGND
AGND
AGND
AGND
AGND
AVDD3
E
VIN–B
AGND
AGND
AGND
AGND
AGND2
AVDD1_SR
AGND2
AGND
AGND
AGND
AGND
AGND
VIN–A
F
VIN+B
AGND
AGND
AGND
AGND
AGND
SYSREF+
SYSREF–
AGND
AGND
AGND
AGND
AGND
VIN+A
G
AVDD3
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AVDD3
H
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
VREF
AGND
AGND
AGND
AGND
J
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
AGND
K
AGND3
AGND3
AGND3
AGND3
AGND3
AGND3
AGND3
AGND3
AGND3
AGND3
AGND3
AGND3
AGND3
AGND3
L
DGND
GPIO_B1
SPIVDD
FD_B/
GPIO_B0
CSB
SCLK
SDIO
PDWN/
STBY
FD_A/
GPIO_A0
SPIVDD
GPIO_A1
DGND
DGND
DGND
M
DGND
DGND
DRGND
DRGND
DRVDD1
DRVDD1
DRVDD1
DRVDD1
DRGND
DRGND
DRVDD1
DRGND
DRVDD2
DVDD
N
DVDD
DVDD
DRGND
SERDOUT7+ SERDOUT6+ SERDOUT5+ SERDOUT4+ SERDOUT3+ SERDOUT2+ SERDOUT1+ SERDOUT0+
DRGND
SYNCINB+
DVDD
P
DVDD
DVDD
DRGND
SERDOUT7– SERDOUT6– SERDOUT5– SERDOUT4– SERDOUT3– SERDOUT2– SERDOUT1– SERDOUT0–
DRGND
SYNCINB–
DVDD
15547-005
1DENOTES CLOCK DOMAIN.
2DENOTES SYSREF± DOMAIN.
3DENOTES ISOLATION DOMAIN.
Figure 5. Pin Configuration (Top View)
Rev. 0 | Page 13 of 136
AD9208
Data Sheet
Table 8. Pin Function Descriptions1
Pin No.
Power Supplies
A3, A12, B3, B12, C3, C12
A4, A5, A10, A11, B4, B11
A1, A2, A13, A14, B1, B2, B13, B14,
C1, C2, C13, C14
D1, D14, G1, G14
E7
L3, L10
M14, N1, N2, N14, P1, P2, P14
M5 to M8, M11
M13
B5, B10, C4, C5, C10, C11, D2 to D6,
D9 to D13, E2 to E5, E9 to E13,
F2 to F6, F9 to F13, G2 to G13,
H1 to H9, H11 to H14, J1 to J14
A6, A9, B6 to B9, C6 to C9, D7, D8
E6, E8
K1 to K14
L1, L12 to L14, M1, M2
M3, M4, M9, M10, M12, N3, N12,
P3, P12
Analog
E1, F1
E14, F14
A7, A8
H10
CMOS Inputs/Outputs
L2
L4
L9
L11
Digital Inputs
F7, F8
N13
P13
Data Outputs
N4, P4
N5, P5
N6, P6
N7, P7
N8, P8
N9, P9
N10, P10
N11, P11
Mnemonic
Type
Description
AVDD1
AVDD12
Power
Power
AVDD2
Power
Analog Power Supply (0.975 V Nominal).
Analog Power Supply for the Clock Domain (0.975 V
Nominal).
Analog Power Supply (1.9 V Nominal).
AVDD3
AVDD1_SR
SPIVDD
DVDD
DRVDD1
DRVDD2
AGND
Power
Power
Power
Power
Power
Power
Ground
Analog Power Supply (2.5 V Nominal).
Analog Power Supply for SYSREF± (0.975 V Nominal).
Digital Power Supply for SPI (1.9 V Nominal).
Digital Power Supply (0.975 V Nominal).
Digital Driver Power Supply (0.975 V Nominal).
Digital Driver Power Supply (1.9 V Nominal).
Analog Ground. These pins connect to the analog
ground plane.
AGND2
AGND3
AGND4
DGND
Ground
Ground
Ground
Ground
DRGND
Ground
Ground Reference for the Clock Domain.
Ground Reference for SYSREF±.
Isolation Ground.
Digital Control Ground Supply. These pins connect to
the digital ground plane.
Digital Driver Ground Supply. These pins connect to
the digital driver ground plane.
VIN−B, VIN+B
VIN−A, VIN+A
CLK+, CLK−
VREF
Input
Input
Input
Input/DNC
ADC B Analog Input Complement/True.
ADC A Analog Input Complement/True.
Clock Input True/Complement.
0.50 V Reference Voltage Input/Do Not Connect. This
pin is configurable through the SPI as a no connect or
an input. Do not connect this pin if using the internal
reference. This pin requires a 0.50 V reference voltage
input if using an external voltage reference source.
GPIO_B1
FD_B/GPIO_B0
FD_A/GPIO_A0
GPIO_A1
Input/output
Input/output
Input/output
Input/output
GPIO B1.
Fast Detect Outputs for Channel B/GPIO B0.
Fast Detect Outputs for Channel A/GPIO A0.
GPIO A1.
SYSREF+, SYSREF−
Input
SYNCINB+
SYNCINB−
Input
Input
Active High JESD204B LVDS System Reference Input
True/Complement.
Active Low JESD204B LVDS/CMOS Sync Input True.
Active Low JESD204B LVDS Sync Input Complement.
SERDOUT7+, SERDOUT7−
SERDOUT6+, SERDOUT6−
SERDOUT5+, SERDOUT5−
SERDOUT4+, SERDOUT4−
SERDOUT3+, SERDOUT3−
SERDOUT2+, SERDOUT2−
SERDOUT1+, SERDOUT1−
SERDOUT0+, SERDOUT0−
Output
Output
Output
Output
Output
Output
Output
Output
Lane 7 Output Data True/Complement.
Lane 6 Output Data True/Complement.
Lane 5 Output Data True/Complement.
Lane 4 Output Data True/Complement.
Lane 3 Output Data True/Complement.
Lane 2 Output Data True/Complement.
Lane 1 Output Data True/Complement.
Lane 0 Output Data True/Complement.
Rev. 0 | Page 14 of 136
Data Sheet
Pin No.
Digital Controls
L8
L5
L6
L7
AD9208
Mnemonic
Type
Description
PDWN/STBY
Input
CSB
SCLK
SDIO
Input
Input
Input/output
Power-Down Input (Active High). The operation of
this pin depends on the SPI mode and can be
configured as power-down or standby.
SPI Chip Select (Active Low).
SPI Serial Clock.
SPI Serial Data Input/Output.
1
See the Theory of Operation section and the Applications Information section for more information on isolating the planes for optimal performance.
Denotes clock domain.
Denotes SYSREF± domain.
4
Denotes isolation domain.
2
3
Rev. 0 | Page 15 of 136
AD9208
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD1 = 0.975 V, AVDD1_SR = 0.975 V, AVDD2 = 1.9 V, AVDD3 = 2.5 V, DVDD = 0.975 V, DRVDD1 = 0.975 V, DRVDD2 = 1.9 V,
SPIVDD = 1.9 V, sampling rate = 3000 MHz, 1.7 V p-p full-scale differential input, DDC decimation rate = 8, default buffer current settings,
TA = 25°C, 128,000 fast Fourier transform (FFT) sample, unless otherwise noted. See Table 10 for the recommended settings.
0
–40
–60
–80
–100
–40
–60
–80
0
150
300
450
600
750
900
1050 1200 1350 1500
FREQUENCY (MHz)
–120
0
0
–60
–80
300
450
600
750
900
1050 1200 1350 1500
–40
1050 1200 1350 1500
–60
–80
–120
0
0
300
450
600
750
900
1050 1200 1350 1500
AIN = –2dBFS
SNR = 58.0dBFS
SFDR = 67dBFS
ENOB = 9.2BITS
NSD = –149.7dBFS/Hz
BUFFER CURRENT = 500µA
–20
AMPLITUDE (dBFS)
–40
150
Figure 10. Single-Tone FFT at fIN = 1807 MHz, AIN = −9 dBFS
AIN = –2dBFS
SNR = 59.9dBFS
SFDR = 71dBFS
ENOB = 9.6BITS
NSD = –151.6dBFS/Hz
BUFFER CURRENT = 500µA
–20
0
FREQUENCY (MHz)
Figure 7. Single-Tone FFT at fIN = 765 MHz
–60
–80
–40
–60
–80
–100
0
150
300
450
600
750
900
1050 1200 1350 1500
FREQUENCY (MHz)
Figure 8. Single-Tone FFT at fIN = 905 MHz
–120
0
150
300
450
600
750
900
1050 1200 1350 1500
FREQUENCY (MHz)
Figure 11. Single-Tone FFT at fIN = 2100 MHz
Rev. 0 | Page 16 of 136
15547-011
–100
15547-008
AMPLITUDE (dBFS)
900
15547-010
150
15547-007
0
FREQUENCY (MHz)
–120
750
–100
–100
–120
600
AIN = –9dBFS
SNR = 60.4dBFS
SFDR = 81dBFS
ENOB = 9.7BITS
NSD = –152.1dBFS/Hz
BUFFER CURRENT = 500µA
–20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
–40
450
Figure 9. Single-Tone FFT at fIN = 1807 MHz
AIN = –2dBFS
SNR = 60dBFS
SFDR = 71dBFS
ENOB = 9.6BITS
NSD = –151.8dBFS/Hz
BUFFER CURRENT = 500µA
–20
300
FREQUENCY (MHz)
Figure 6. Single-Tone FFT at fIN = 255 MHz
0
150
15547-009
–100
15547-006
–120
AIN = –2dBFS
SNR = 57.9dBFS
SFDR = 69dBFS
ENOB = 9.2BITS
NSD = –149.7dBFS/Hz
BUFFER CURRENT = 500µA
–20
AMPLITUDE (dBFS)
–20
AMPLITUDE (dBFS)
0
AIN = –2dBFS
SNR = 60.2dBFS
SFDR = 71dBFS
ENOB = 9.6BITS
NSD = –152.0dBFS/Hz
BUFFER CURRENT = 400µA
Data Sheet
0
0
AIN = –9dBFS
SNR = 50.2dBFS
SFDR = 75dBFS
ENOB = 9.7BITS
NSD = –152.0dBFS/Hz
BUFFER CURRENT = 500µA
–40
–60
–80
–40
–60
–80
–100
150
300
450
600
750
900
1050 1200 1350 1500
FREQUENCY (MHz)
–120
15547-012
0
0
150
0
–60
–80
1050 1200 1350 1500
–40
–60
–80
–100
150
300
450
600
750
900
1050 1200 1350 1500
–120
15547-013
0
FREQUENCY (MHz)
0
300
450
600
750
900
1050 1200 1350 1500
61
60
59
SNR (dBFS)
–40
150
Figure 16. Single-Tone FFT at fIN = 3957 MHz, AIN = −9 dBFS
AIN = –9dBFS
SNR = 59.9dBFS
SFDR = 78dBFS
ENOB = 9.7BITS
NSD = –151.7dBFS/Hz
BUFFER CURRENT = 500µA
–20
0
FREQUENCY (MHz)
Figure 13. Single-Tone FFT at fIN = 2600 MHz
–60
58
57
–80
56
–100
55
–120
0
150
300
450
600
750
900
1050 1200 1350 1500
FREQUENCY (MHz)
Figure 14. Single-Tone FFT at fIN = 2600 MHz, AIN = −9 dBFS
54
155
455
755 1055 1355 1655 1955 2255 2555 2855 3155 3455 3755
INPUT FREQUENCY (MHz)
Figure 17. SNR vs. Input Frequency (fIN); AIN = −2 dBFS and −9 dBFS
Rev. 0 | Page 17 of 136
15547-017
–9dBFS
–2dBFS
15547-014
AMPLITUDE (dBFS)
900
15547-016
–100
–120
750
AIN = –9dBFS
SNR = 58.2dBFS
SFDR = 73dBFS
ENOB = 9.34BITS
NSD = –150dBFS/Hz
BUFFER CURRENT = 700µA
–20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
–40
600
Figure 15. Single-Tone FFT at fIN = 3957 MHz
AIN = –2dBFS
SNR = 57.2dBFS
SFDR = 70dBFS
ENOB = 9.1BITS
NSD = –149.0dBFS/Hz
BUFFER CURRENT = 700µA
–20
450
FREQUENCY (MHz)
Figure 12. Single-Tone FFT at fIN = 2100 MHz, AIN = −9 dBFS
0
300
15547-015
–100
–120
AIN = –2dBFS
SNR = 54.9dBFS
SFDR = 58dBFS
ENOB = 8.4BITS
NSD = –146.7dBFS/Hz
BUFFER CURRENT = 700µA
–20
AMPLITUDE (dBFS)
–20
AMPLITUDE (dBFS)
AD9208
AD9208
Data Sheet
90
0
AIN1 AND AIN2 = –8dBFS
SFDR = 72dBFS
IMD2 = 72dBFS
IMD3 = 73dBFS
BUFFER CURRENT = 500µA
80
–20
AMPLITUDE (dBFS)
70
SFDR (dBFS)
60
50
40
30
–40
–60
–80
20
–9dBFS
–2dBFS
155
455
755 1055 1355 1655 1955 2255 2555 2855 3205 3505 3805
INPUT FREQUENCY (MHz)
–120
15547-018
0
–10
0
–20
AMPLITUDE (dBFS)
HD2 (dBc)
–50
450
600
750
900
1050 1200 1350 1500
AIN1 AND AIN2 = –15dBFS
SFDR = 75dBFS
IMD2 = 75dBFS
IMD3 = 87dBFS
BUFFER CURRENT = 500µA
–20
–40
300
Figure 21. Two-Tone FFT; fIN1 = 1821.5 MHz, fIN2 = 1831.5 MHz;
AIN1 and AIN2 = −8 dBFS
–9dBFS
–2dBFS
–30
150
FREQUENCY (MHz)
Figure 18. SFDR vs. Input Frequency (fIN); AIN = −2 dBFS and −9 dBFS
0
0
15547-021
–100
10
–40
–60
–80
–60
–100
155
455
755 1055 1355 1655 1955 2255 2555 2855 3205 3505 3805
INPUT FREQUENCY (MHz)
–120
15547-019
–80
–10
150
300
450
600
750
1050 1200 1350 1500
Figure 22. Two-Tone FFT; fIN1 = 1821.5 MHz, fIN2 = 1831.5 MHz;
AIN1 and AIN2 = −15 dBFS
0
–9dBFS
–2dBFS
AIN1 AND AIN2 = –8dBFS
SFDR = 67dBFS
IMD2 = 67dBFS
IMD3 = 69dBFS
BUFFER CURRENT = 600µA
–20
AMPLITUDE (dBFS)
–20
–30
HD3 (dBc)
900
FREQUENCY (MHz)
Figure 19. HD2 vs. Input Frequency (fIN); AIN = −2 dBFS and −9 dBFS
0
0
15547-022
–70
–40
–50
–60
–70
–40
–60
–80
–100
155
455
755 1055 1355 1655 1955 2255 2555 2855 3205 3505 3805
INPUT FREQUENCY (MHz)
–120
0
150
300
450
600
750
900
1050 1200 1350 1500
FREQUENCY (MHz)
Figure 23. Two-Tone FFT; fIN1 = 2621.5 MHz, fIN2 = 2631.5 MHz;
AIN1 and AIN2 = −8 dBFS
Figure 20. HD3 vs. Input Frequency (fIN); AIN = −2 dBFS and −9 dBFS
Rev. 0 | Page 18 of 136
15547-023
–90
15547-020
–80
Data Sheet
AD9208
0
AIN1 AND AIN2 = –15dBFS
SFDR = 75dBFS
IMD2 = 75dBFS
IMD3 = 88dBFS
BUFFER CURRENT = 600µA
–30
AMPLITUDE (dBFS)
–40
–60
–80
–100
150
300
450
600
750
900
1050 1200 1350 1500
Figure 24. Two-Tone FFT; fIN1 = 2621.5 MHz, fIN2 = 2631.5 MHz;
AIN1 and AIN2 = −15 dBFS
0
–37.5
0
37.5
75.0
112.5
150.0
187.5
FREQUENCY (MHz)
AIN1 AND AIN2 = –15dBFS
NCO FREQUENCY = 2176.9MHz
SFDR = 94dBFS
–10
–30
AMPLITUDE (dBFS)
–40
–60
–80
–50
–70
–90
0
150
300
450
600
750
900
1050 1200 1350 1500
FREQUENCY (MHz)
15547-025
–110
Figure 25. Two-Tone FFT; fIN1 = 2621.5 MHz, fIN2 = 2631.5 MHz;
Full-Scale Voltage = 1.1 V p-p; AIN1 and AIN2 = −8 dBFS
0
–187.5 –150.0 –112.5 –75.0
–37.5
0
37.5
75.0
112.5
150.0
187.5
FREQUENCY (MHz)
Figure 28. Two-Tone FFT; fIN1 = 1800 MHz, fIN2 = 2100 MHz
fCLK = 2.94912 GHz; Decimation Ratio = 8, NCO Frequency = 2176.92 MHz
0
AIN1 AND AIN2 = –15dBFS
SFDR = 86dBFS
IMD2 = 106dBFS
IMD3 = 111dBFS
BUFFER CURRENT = 800µA
IMD3 (dBFS)
IMD3 (dBc)
SFDR (dBFS)
SFDR (dBc)
–20
SFDR/IMD3 (dBc AND dBFS)
–20
–130
15547-228
AMPLITUDE (dBFS)
–187.5 –150.0 –112.5 –75.0
Figure 27. Two-Tone FFT; fIN1 = 1800 MHz, fIN2 = 2100 MHz
fCLK = 2.94912 GHz; Decimation Ratio = 8, NCO Frequency = 1874.28 MHz
–100
–40
–60
–80
–100
–40
–60
–80
–100
0
150
300
450
600
750
900
1050 1200 1350 1500
FREQUENCY (MHz)
15547-026
AMPLITUDE (dBFS)
–130
AIN1 AND AIN2 = –8dBFS
SFDR = 67dBFS
IMD2 = 67dBFS
IMD3 = 75dBFS
BUFFER CURRENT = 600µA
–20
–120
–90
15547-227
0
FREQUENCY (MHz)
–120
–70
–110
15547-024
–120
–50
Figure 26. Two-Tone FFT; fIN1 = 2621.5 MHz, fIN2 = 2631.5 MHz;
Full-Scale Voltage = 1.1 V p-p; AIN1 and AIN2 = −15 dBFS
–120
–95 –89 –83 –77 –71 –65 –59 –53 –47 –41 –35 –29 –23 –17 –11 –7
INPUT AMPLITUDE (dBFS)
Figure 29. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with
fIN1 = 1821.5 MHz, fIN2 = 1831.5 MHz
Rev. 0 | Page 19 of 136
15547-229
AMPLITUDE (dBFS)
–20
AIN1 AND AIN2 = –15dBFS
NCO FREQUENCY = 1842.5MHz
SFDR = 80dBFS
–10
AD9208
Data Sheet
0
–20
SNR (dBFS)
SFDR (dBFS)
75
–40
SNR/SFDR (dBFS)
–60
–80
–100
70
65
60
–120
–95 –89 –83 –77 –71 –65 –59 –53 –47 –41 –35 –29 –23 –17 –11 –7
INPUT AMPLITUDE (dBFS)
15547-230
55
Figure 30. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with
fIN1 = 2621.5 MHz, fIN2 = 2631.5 MHz
50
–10
0
10
20
30
40
50
60
70
80
90 100 110 120
TJ (°C)
15547-030
SFDR/IMD3 (dBc AND dBFS)
80
IMD3 (dBFS)
IMD3 (dBc)
SFDR (dBFS)
SFDR (dBc)
Figure 33. SNR/SFDR vs. Junction Temperature (TJ), fIN = 950 MHz, AIN = −9 dBFS
110
4.0
100
3.5
80
3.0
70
60
POWER (W)
50
40
30
20
10
0
2.5
2.0
1.5
TOTAL POWER (W)
AVDD1 + AVDD2 + AVDD3 POWER (W)
DVDD + SPIVDD POWER (W)
DRVDD1 + DRVDD2 POWER (W)
1.0
SNR (dBc)
SNR (dBFS)
SFDR (dBc)
SFDR (dBFS)
–20
–30
–40
–95 –89 –83 –77 –71 –65 –59 –53 –47 –41 –35 –29 –23 –17 –11 –5 –1
INPUT AMPLITUDE (dBFS)
0.5
0
–10
0
10
20
30
40
50
60
70
80
90 100 110 120
TJ (°C)
Figure 31. SNR/SFDR vs. Input Amplitude (AIN), fIN = 950 MHz
15547-031
–10
15547-027
SNR/SFDR (dBc AND dBFS)
90
Figure 34. Power vs. Junction Temperature (TJ), fIN = 950 MHz
60
110
100
59
80
58
SNR (dBFS)
60
50
40
30
20
10
0
57
56
55
54
–10
SNR (dBc)
SNR (dBFS)
SFDR (dBc)
SFDR (dBFS)
–20
–30
–40
–95 –89 –83 –77 –71 –65 –59 –53 –47 –41 –35 –29 –23 –17 –11 –5 –1
INPUT AMPLITUDE (dBFS)
Figure 32. SNR/SFDR vs. Input Amplitude (AIN), fIN = 1800 MHz
53
52
255
200mV p-p
500mV p-p
1000mV p-p
1200mV p-p
1500mV p-p
1800mV p-p
2000mV p-p
655
1055
1455
1855
2255
2655
3055
ANALOG INPUT FREQUENCY (MHz)
3455
3855
15547-032
70
15547-028
SNR/SFDR (dBc AND dBFS)
90
Figure 35. SNR vs. Analog Input Frequency (fIN) vs. Various Clock Amplitude in
Differential Voltages, AIN = −2dBFS
Rev. 0 | Page 20 of 136
Data Sheet
AD9208
61
–3
–9dBFS
–2dBFS
–4
–5
60
–6
AMPLITUDE (dB)
SNR (dBFS)
59
58
57
–7
–8
–9
–10
–11
–12
–13
56
2600
2700
2800
2900
3000
3100
SAMPLE FREQUENCY (MHz)
–15
100
15547-033
2500
Figure 36. SNR vs. Sample Frequency (fS), fIN = 1.8 GHz; AIN = −2 dBFS and −9 dBFS
2100
4100
6100
8100
10100
12100
FREQUENCY (MHz)
15547-035
–14
55
2400
Figure 39. Input Bandwidth (See Figure 55 for the Input Configuration)
90
80000
80
70000
70
60000
NUMBER OF HITS
5.6LSB rms
SFDR (dBFS)
60
50
40
30
50000
40000
30000
20000
20
10000
2600
2700
2800
2900
3000
3100
SAMPLE FREQUENCY (MHz)
0
Figure 37. SFDR vs. Sample Frequency (fS), fIN = 1.8 GHz; AIN = −2 dBFS and
−9 dBFS
4.0
POWER DISSIPATION (W)
3.5
3.0
2.5
2.0
ANALOG POWER
DIGITAL POWER
DRIVER POWER
TOTAL POWER
1.5
1.0
0
2400
2500
2600
2700
2800
2900
SAMPLE FREQUENCY (MHz)
3000
3100
15547-034
0.5
Figure 38. Power Dissipation vs. Sample Frequency (fS), fIN = 1.8 GHz; AIN = −2 dBFS
Rev. 0 | Page 21 of 136
OUTPUT CODE
Figure 40. Input Referred Noise Histogram
15547-036
2500
15547-238
0
2400
–9dBFS
–2dBFS
N – 25
N – 23
N – 21
N – 19
N – 17
N – 15
N – 13
N – 10
N–8
N–6
N–4
N–2
N
N+2
N+4
N+6
N+8
N + 10
N + 12
N + 14
N + 16
N + 18
N + 20
N + 22
N + 24
10
AD9208
Data Sheet
EQUIVALENT CIRCUITS
AVDD1_SR
AVDD3
AVDD3
SYSREF+
100Ω
VIN+x
10kΩ
1.9pF
0.3pF
130kΩ
100Ω
AVDD3
LEVEL
TRANSLATOR VCM = 0.65V
VCM
BUFFER
AVDD3
100Ω
AVDD3
130kΩ
AVDD1_SR
AIN
CONTROL
(SPI)
SYSREF–
100Ω
15547-037
0.3pF
10kΩ
15547-039
VIN–x
1.9pF
Figure 43. SYSREF± Inputs
Figure 41. Analog Inputs
AVDD1
EMPHASIS/SWING
CONTROL (SPI)
CLK+
DRVDD
SERDOUTx+
DATA+
x = 0, 1, 2, 3, 4, 5, 6, 7
106Ω
AVDD1
VCM = 0.65V
SERDOUTx–
DATA–
x = 0, 1, 2, 3, 4, 5, 6, 7
DRGND
Figure 42. Clock Inputs
Figure 44. Digital Outputs
DRVDD1
2.6kΩ
SYNCINB+
SYNCINB PIN
CONTROL (SPI)
DRGND
100Ω
CMOS PATH
DRVDD1
10kΩ
1.9pF
130kΩ
DRGND
DRGND
LEVEL
TRANSLATOR VCM = 0.65V
130kΩ
DRVDD1
SYNCINB–
100Ω
10kΩ
1.9pF
DRGND
DRGND
Figure 45. SYNCINB± Inputs
Rev. 0 | Page 22 of 136
15547-041
16kΩ
15547-040
16kΩ
15547-038
CLK–
DRGND
DRVDD
OUTPUT
DRIVER
Data Sheet
AD9208
SPIVDD
SPIVDD
ESD
PROTECTED
SPIVDD
ESD
PROTECTED
SDI
SPIVDD
SCLK
DGND
SDIO
SPIVDD
56kΩ
DGND
15547-042
DGND
DGND
SDO
ESD
PROTECTED
DGND
DGND
Figure 46. SCLK Input
DGND
15547-044
56kΩ
ESD
PROTECTED
Figure 48. SDIO Input
SPIVDD
SPIVDD
ESD
PROTECTED
ESD
PROTECTED
56kΩ
PDWN/STBY
56kΩ
DGND
ESD
PROTECTED
15547-043
ESD
PROTECTED
DGND
DGND
PDWN
CONTROL (SPI)
DGND
DGND
Figure 47. CSB Input
15547-045
CSB
Figure 49. PDWN/STBY Input
VCM OUTPUT
TEMPERATURE DIODE
VOLTAGE OUTPUT
AVDD2
VREF PIN
CONTROL (SPI)
AGND
Figure 50. VREF Input/Output
SPIVDD
SPIVDD
ESD
PROTECTED
NCO BAND SELECT
DGND
FD_A/GPIO_A0,
FD_B/GPIO_B0
SPIVDD
FD
JESD204B LMFC
56kΩ
ESD
PROTECTED
DGND
DGND
FD PIN CONTROL (SPI)
15547-047
JESD204B SYNC~
DGND
Figure 51. FD_A/GPIO_A0, FD_B/GPIO_B0
SPIVDD
ESD
PROTECTED
SPIVDD
NCO BAND SELECT
SDI
GPIO_A1/GPIO_B1
56kΩ
DGND
DGND
CHIP TRANSFER
DGND
GPIO_A1/GPIO_B1
PIN CONTROL (SPI)
Figure 52. GPIO_A1/GPIO_B1
Rev. 0 | Page 23 of 136
15547-048
ESD
PROTECTED
15547-046
EXTERNAL REFERENCE
VOLTAGE INPUT
VREF
AD9208
Data Sheet
THEORY OF OPERATION
The dual ADC cores feature a multistage, differential pipelined
architecture with integrated output error correction logic. Each
ADC features wide bandwidth inputs supporting a variety of
user-selectable input ranges. An integrated voltage reference
eases design considerations.
The AD9208 has several functions that simplify the AGC
function in a communications receiver. The programmable
threshold detector allows monitoring of the incoming signal
power using the fast detect output bits of the ADC. If the input
signal level exceeds the programmable threshold, the fast detect
indicator goes high. Because this threshold indicator has low
latency, the user can quickly turn down the system gain to avoid
an overrange condition at the ADC input.
The Subclass 1 JESD204B-based high speed serialized output data
lanes can be configured in one-lane (L = 1), two-lane (L = 2),
four-lane (L = 4), and eight-lane (L = 8) configurations, depending
on the sample rate and the decimation ratio. Multiple device
synchronization is supported through the SYSREF± and
SYNCINB± input pins. The SYSREF± pin in the AD9208 can
also be used as a timestamp of data as it passes through the
ADC and out of the JESD204B interface.
Either a differential capacitor or two single-ended capacitors (or
a combination of both) can be placed on the inputs to provide a
matching passive network. These capacitors ultimately create a
low-pass filter that limits unwanted broadband noise. For more
information, refer to the Analog Dialogue article “TransformerCoupled Front-End for Wideband A/D Converters”
(Volume 39, April 2005). In general, the precise front-end
network component values depend on the application.
Figure 53 shows the differential input return loss curve for the
analog inputs across a frequency range of 100 MHz to 10 GHz.
The reference impedance is 100 Ω.
1.0
m5
5.0
m1
m3
0
0
m2
–5.0
–0.2
–0.5
–2.0
The input buffer provides a linear high input impedance (for
ease of drive) and reduces kickback from the ADC. The
quantized outputs from each stage are combined into a final
14-bit result in the digital correction logic. The pipelined
architecture permits the first stage to operate with a new input
sample; at the same time, the remaining stages operate with the
preceding samples. Sampling occurs on the rising edge of the clock.
m1
FREQUENCY = 100MHz
SDD11 = 0.301/–8.069
IMPEDANCE= Z0 × (1.838 – j0.171)
m4
FREQUENCY = 4GHz
SDD11 = 0.500/136.667
IMPEDANCE = Z0 × (0.379 – j0.347)
m2
FREQUENCY = 1GHz
SDD11 = 0.352/–73.534
IMPEDANCE= Z0 × (0.947 – j0.731)
m5
FREQUENCY = 5GHz
SDD11 = 0.475/79.360
IMPEDANCE= Z0 × (0.737 – j0.889)
m3
FREQUENCY = 3GHz
SDD11 = 0.496/175.045
IMPEDANCE= Z0 × (0.337 – j0.038)
15547-254
–1.0
FREQUENCY (100MHz TO 10GHz)
The architecture of the AD9208 consists of an input buffered
pipelined ADC. The input buffer provides a termination
impedance to the analog input signal. This termination
impedance is set to 200 Ω. The equivalent circuit diagram of the
analog input termination is shown in Figure 29. The input
buffer is optimized for high linearity, low noise, and low power
across a wide bandwidth.
The analog input to the AD9208 is a differential buffer. The
internal common-mode voltage of the buffer is 1.35 V. The
clock signal alternately switches the input circuit between
sample mode and hold mode.
m4
0.2
ADC ARCHITECTURE
ANALOG INPUT CONSIDERATIONS
2.0
0.5
SDD11
The AD9208 has two analog input channels and up to eight
JESD204B output lane pairs. The ADC samples wide bandwidth
analog signals of up to 5 GHz. The actual −3 dB roll-off of the
analog inputs is 9 GHz. The AD9208 is optimized for wide input
bandwidth, high sampling rate, excellent linearity, and low
power in a small package.
Figure 53. Differential Input Return Loss
For best dynamic performance, the source impedances driving
VIN+x and VIN−x must be matched such that common-mode
settling errors are symmetrical. These errors are reduced by the
common-mode rejection of the ADC. An internal reference
buffer creates a differential reference that defines the span of the
ADC core.
Maximum SNR performance is achieved by setting the ADC to
the largest span in a differential configuration. For the AD9208,
the available span is programmable through the SPI port from
1.13 V p-p to 2.04 V p-p differential, with 1.7 V p-p differential
being the default.
Rev. 0 | Page 24 of 136
Data Sheet
AD9208
Differential Input Configurations
in the second or third Nyquist zones, it is recommended to
remove some of the front-end passive components to ensure
wideband operation (see Figure 55 and Table 9).
There are several ways to drive the AD9208, either actively or
passively. Optimum performance is achieved by driving the
analog input differentially.
C2
R1
C3
R2
MARKI
BAL-0006
C4
C1
R2
R1
C2
C3
200Ω
ADC
R3
NOTES:
1. SEE TABLE 9 FOR COMPONENT VALUES
For low to midrange frequencies, a double balun or double
transformer network (see Figure 54 and Table 9) is recommended
for optimum performance of the AD9208. For higher frequencies
Figure 54. Differential Transformer Coupled Configuration for the AD9208
0.1µF
25Ω
R3
15547-050
For applications where SNR and SFDR are key parameters,
differential transformer coupling is the recommended input
configuration (see Figure 54 and Table 9) because the noise
performance of most amplifiers is not adequate to achieve the
true performance of the AD9208.
10Ω
25Ω
MARKI
BAL-0009
200Ω
0.1µF
ADC
25Ω
15547-331
25Ω
10Ω
0.1µF
Figure 55. Input Network Configuration for Frequencies > 5 GHz
Table 9. Differential Transformer-Coupled Input Configuration Component Values
Frequency Range
3000 MHz
Register 0x1A4C and Register 0x1A4D
400 μA/500 μA
500 μA
500 μA/700 μA
Dither
The AD9208 has internal on-chip dither circuitry that improves
the ADC linearity and SFDR, particularly at smaller signal
levels. A known but random amount of white noise is injected
into the input of the AD9208. This dither improves the small
signal linearity within the ADC transfer function and is
precisely subtracted out digitally. The dither is turned on by
default and does not reduce the ADC input dynamic range. The
data sheet specifications and limits are obtained with the dither
turned on.
The dither is on by default. It is not recommended to turn it off.
0.21
Absolute Maximum Input Swing
0.2
0.19
500
600
BUFFER CURRENT SETTING (µA)
700
15547-053
0.18
0.17
400
Table 10 shows the recommended values for the buffer current
for various Nyquist zones.
The absolute maximum input swing allowed at the inputs of the
AD9208 is 5.8 V p-p differential. Signals operating near or at
this level can cause permanent damage to the ADC. See Table 6
for more information.
Figure 58. AVDD3 Current (IAVDD3) vs. Buffer Current Setting (Buffer Control 1
Setting in Register 0x1A4C and Buffer Control 2 Setting in Register 0x1A4D)
Rev. 0 | Page 27 of 136
AD9208
Data Sheet
VIN+A/VIN+B
VIN–A/VIN–B
INTERNAL
0.5V
REFERENCE
GENERATOR
ADC
CORE
VFS
ADJUST
INPUT FULL SCALE
RANGE ADJUST
SPI REGISTER
(0x1910)
VREF
15547-054
VREF PIN
CONTROL SPI
REGISTER
(0x18A6)
Figure 59. Internal Reference Configuration and Controls
INTERNAL
0.5V
REFERENCE
GENERATOR
ADR130
NC
NC
ADC
GND SET
INPUT
VIN VOUT
0.1µF
VFS
ADJUST
VREF
0.1µF
15547-056
VREF PIN
AND VFS
CONTROL
Figure 60. External Reference Using the ADR130
The SPI Register 0x18A6 enables the user to either use this
internal 0.5 V reference, or to provide an external 0.5 V
reference. When using an external voltage reference, provide a
0.5 V reference. The full-scale adjustment is made using the SPI,
irrespective of the reference voltage. For more information on
adjusting the full-scale level of the AD9208, refer to the Memory
Map section.
0.5060
0.5055
3.
Set Register 0x18E3 to 0x00 to turn off the VCM export.
Set Register 0x18E6 to 0x00 to turn off the temperature
diode export.
Set Register 0x18A6 to 0x01 to turn on the external voltage
reference.
0.5045
0.5040
0.5035
0.5030
–10
The SPI writes required to use the external voltage reference, in
order, are as follows:
1.
2.
0.5050
10
30
50
70
90
JUNCTION TEMPERATURE (°C)
110
130
15547-055
A stable and accurate 0.5 V voltage reference is built into the
AD9208. This internal 0.5 V reference sets the full-scale input
range of the ADC. The full-scale input range can be adjusted via
the ADC input full-scale control register (Register 0x1910). For
more information on adjusting the input swing, see Table 46.
Figure 59 shows the block diagram of the internal 0.5 V reference
controls.
The use of an external reference may be necessary, in some
applications, to enhance the gain accuracy of the ADC or to
improve thermal drift characteristics. Figure 61 shows the
typical drift characteristics of the internal 0.5 V reference.
BAND GAP VOLTAGE (V)
VOLTAGE REFERENCE
Figure 61. Typical VREF Drift
The external reference must be a stable 0.5 V reference. The
ADR130 is a sufficient option for providing the 0.5 V reference.
Figure 60 shows how the ADR130 can be used to provide the
external 0.5 V reference to the AD9208. The dashed lines show
unused blocks within the AD9208 while using the ADR130 to
provide the external reference.
Rev. 0 | Page 28 of 136
Data Sheet
AD9208
CLOCK INPUT CONSIDERATIONS
For optimum performance, drive the AD9208 sample clock
inputs (CLK+ and CLK−) with a differential signal. This signal is
ac-coupled to the CLK+ and CLK− pins via a transformer or clock
drivers. These pins are biased internally and require no
additional biasing.
CLK+
CLOCK INPUT
ADC
1:2Z
15547-058
The AD9208 contains a digital filter to remove the dc offset
from the output of the ADC. For ac-coupled applications, this
filter can be enabled by writing 0x86 to Register 0x0701. The
filter computes the average dc signal and it is digitally subtracted
from the ADC output. As a result, the dc offset is improved to
better than 70 dBFS at the output. Because the filter does not
distinguish between the source of dc signals, this feature can be
used when the signal content at dc is not of interest. The filter
corrects dc up to ±512 codes and saturates beyond that.
Figure 63 shows a preferred method for clocking the AD9208.
The low jitter clock source is converted from a single-ended
signal to a differential signal using an RF transformer.
CLK–
Figure 63. Transformer-Coupled Differential Clock
Another option is to ac couple a differential CML or LVPECL
signal to the sample clock input pins, as shown in Figure 64 and
Figure 65.
Figure 62 shows the differential input return loss curve for the
clock inputs across a frequency range of 100 MHz to 6 GHz.
The reference impedance is 100 Ω.
1.0
CLK+
100Ω
DIFFERENTIAL
TRACE
LVDS
DRIVER
150Ω
ADC
CLOCK
INPUT
CLK–
15547-059
DC OFFSET CALIBRATION
150Ω
Figure 64. Differential LVPECL Sample Clock
2.0
0.5
CLK+
m2
5.0
m4
15547-060
0.2
DIFFERENTIAL
TRACE
m1
0
Figure 65. Differential CML Sample Clock
0
–5.0
–0.2
–0.5
–2.0
m3
FREQUENCY = 3.104GHz
SDD11 = 0.332/165.502
IMPEDANCE = Z0 × (0.508 – j0.095)
m2
FREQUENCY = 2.996GHz
SDD11 = 0.337/169.383
IMPEDANCE = Z0 × (0.499 – j0.070)
m4
FREQUENCY = 6GHz
SDD11 = 0.271/54.790
IMPEDANCE = Z0 × (1.218 – j0.581)
CLKOUT–
CLK–
Figure 66. Clock Output Clocking the AD9208
–1.0
FREQUENCY (100MHz TO 6GHz)
m1
FREQUENCY = 2.503GHz
SDD11 = 0.313/–173.307
IMPEDANCE = Z0 × (0.524 – j0.042)
DAC
CLOCK
INPUT
CLK+
ADC
CLOCK
INPUT
15547-061
ADC
CLKOUT+
15547-057
SDD11
ADC
CLOCK
INPUT
CLK–
CML
DRIVER
Figure 62. Differential Input Return Loss for the CLK± Inputs
Rev. 0 | Page 29 of 136
AD9208
Data Sheet
Clock Duty Cycle Considerations
Clock Fine Delay and Superfine Delay Adjust
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. The AD9208 contains an
internal clock divider and a duty cycle stabilizer comprised of
DCS1 and DCS2, which is enabled by default. In applications
where the clock duty cycle cannot be guaranteed to be 50%, a
higher multiple frequency clock along with the usage of the
clock divider is recommended.
Adjust the AD9208 sampling edge instant by writing to
Register 0x0110, Register 0x0111, and Register 0x0112. Bits[2:0]
of Register 0x0110 enable the selection of the fine delay, or the
fine delay with superfine delay. The fine delay allows the user to
delay the clock edges with 16 step or 192 step delay options. The
superfine delay is an unsigned control to adjust the clock delay
in superfine steps of 0.25 ps each.
When it is not possible to provide a higher frequency clock, it is
recommended to turn on the DCS using Register 0x011C and
Register 0x011E. Figure 67 shows the different controls to the
AD9208 clock inputs. The output of the divider offers a 50%
duty cycle, high slew rate (fast edge) clock signal to the internal
ADC. See the Memory Map section for more details on using
this feature.
Register 0x0112, Bits[7:0] offer the user the option to delay
the clock in 192 delay steps. Register 0x0111, Bits[7:0] offer the
user the option to delay the clock in 128 superfine steps. These
values can be programmed individually for each channel. To
use the superfine delay option, set the clock delay control in
Register 0x0110, Bits[2:0] to 0x2 or 0x6. Figure 68 shows the
controls available to the clock dividers within AD9208. It is
recommended to apply the same delay settings to the digital
delay circuits as are applied to the analog delay circuits to
maintain sample accuracy through the pipe.
The AD9208 contains an input clock divider with the ability to
divide the input clock by 1, 2, or 4. Select the divider ratios
using Register 0x0108 (see Figure 67).
The maximum frequency at the CLK± inputs is 6 GHz, which is
the limit of the divider. In applications where the clock input is
a multiple of the sample clock, take care to program the appropriate
divider ratio into the clock divider before applying the clock
signal; this ensures that the current transients during device
startup are controlled.
CHANNEL A
PHASE
CH. A
CLK INPUT
PHASE
CH. B
0x0108
REG 0x011C,
0x011E
0x0109
CLK+
÷2
÷4
REG 0x0108
FINE DELAY
0x0110,
0x0111,
0x0112
CHANNEL B
Figure 68. Clock Divider Phase and Delay Controls
15547-062
CLK–
CLK_DIV
15547-063
Input Clock Divider
Figure 67. Clock Divider Circuit
The AD9208 clock divider can be synchronized using the
external SYSREF± input. A valid SYSREF± signal causes the
clock divider to reset to a programmable state. This synchronization feature allows multiple devices to have their clock
dividers aligned to guarantee simultaneous input sampling. See
the Memory Map Register Details section for more information.
Input Clock Divider ½ Period Delay Adjust
The input clock divider in the AD9208 provides phase delay in
increments of ½ the input clock cycle. Program Register 0x0109
to enable this delay independently for each channel. Changing
this register does not affect the stability of the JESD204B link.
The clock delay adjustment takes effect immediately when it is
enabled via SPI writes. Enabling the clock fine delay adjust in
Register 0x0110 causes a datapath reset. However, the contents
of Register 0x0111 and Register 0x0112 can be changed without
affecting the stability of the JESD204B link.
Clock Coupling Considerations
The AD9208 has many different domains within the analog
supply that control various aspects of the data conversion. The
clock domain is supplied by Pin A4, Pin A5, Pin A10, Pin A11,
Pin B4, and Pin B11 on the analog supply, AVDD1 (0.975 V)
and Pin A6, Pin A9, Pin B6, Pin B7, Pin B8, Pin B9, Pin C6,
Pin C7, Pin C8, Pin C9, Pin D7, and Pin D8 on the ground
(AGND) side. To minimize coupling between the clock supply
domain and the other analog domains, it is recommended to
add a supply Q factor reduction circuitry (de-Q) for Pin A4 and
Pin A11, as well as Pin B4 and Pin B11, as shown in Figure 69.
Rev. 0 | Page 30 of 136
Data Sheet
AD9208
FERRITE BEAD
220Ω AT
100MHz
DCR ≤ 0.5Ω
A4
SNR JITTER
SNR ADC
10
10
SNR (dBFS) = −10log10 10
10
B4
100nF
10Ω
AVDD1
PLANE
61
FERRITE BEAD
59
57
B11
15547-064
100nF
10Ω
Figure 69. De-Q Network Recommendation for the Clock Domain Supply
55
53
Clock Jitter Considerations
51
High speed, high resolution ADCs are sensitive to the quality of
the clock input. Calculate the degradation in SNR at a given
input frequency (fA) due only to aperture jitter (tJ) by
49
47
45
100
SNRJITTER = -20 × log10 (2 × π × fA × tJ)
12.5fS
25fS
50fS
100fS
200fS
400fS
800fS
110
SNR (dB)
100
90
10000
Figure 71. Estimated SNR Degradation for the AD9208 vs. Input Frequency
and RMS Jitter
IF undersampling applications are particularly sensitive to jitter
(see Figure 70).
120
1000
INPUT FREQUENCY (MHz)
In this equation, the rms aperture jitter represents the root
mean square of all jitter sources, including the clock input,
analog input signal, and ADC aperture jitter specifications.
130
25fS
50fS
75fS
100 fS
125 fS
150 fS
175 fS
200 fS
15547-066
A11
SNR (dBFS)
220Ω AT
100MHz
DCR ≤ 0.5Ω
POWER-DOWN/STANDBY MODE
The AD9208 has a PDWN/STBY pin that can be used to
configure the device in power-down or standby mode. The
default operation is PDWN. The PDWN/STBY pin is a logic
high pin. When in power-down mode, the JESD204B link is
disrupted. The power-down option can also be set via
Register 0x003F and Register 0x0040.
70
In standby mode, the JESD204B link is not disrupted and transmits
zeros for all converter samples. Change this transmission using
Register 0x0571, Bit 7 to select /K/ characters.
60
TEMPERATURE DIODE
50
The AD9208 contains diode-based temperature sensors. The
diodes output voltages commensurate to the temperature of the
silicon. There are multiple diodes on the die, but the results
established using the temperature diode at the central location
of the die can be regarded as representative of the entire die.
However, in applications where only one channel is used (the
other channel being in a power-down state), it is recommended
to read the temperature diode corresponding to the channel
that is on. The Figure 72 shows the locations of the diodes in
the AD9208 with voltages that can be output to the VREF pin.
In each location, there is a pair of diodes, one of which is 20×
the size of the other. It is recommended to use both diodes in a
location to obtain an accurate estimate of the die temperature.
For more information, see the AN-1432 Application Note, Practical
Thermal Modeling and Measurements in High Power ICs.
80
30
10
100
1000
ANALOG INPUT FREQUENCY (MHz)
10000
15547-065
40
Figure 70. Ideal SNR vs. Input Frequency and Jitter
Treat the clock input as an analog signal when aperture jitter
may affect the dynamic range of the AD9208. Separate power
supplies for clock drivers from the ADC output driver supplies
to avoid modulating the clock signal with digital noise. If the
clock is generated from another type of source (by gating,
dividing, or other methods), retime the clock by the original clock
at the last step. Refer to the AN-501 Application Note and the
AN-756 Application Note for more in depth information about
jitter performance as it relates to ADCs.
Figure 71 shows the estimated SNR of the AD9208 across input
frequency for different clock induced jitter values. Estimate the
SNR by using the following equation:
Rev. 0 | Page 31 of 136
AD9208
Data Sheet
0.80
JESD204B DRIVER
CHANNEL A, CENTRAL,
CHANNEL B
Figure 72. Temperature Diode Locations in the Die
The temperature diode voltages can be exported to the VREF pin
using the SPI. Use Register 0x18E6 to enable or disable diodes.
It is important to note that other voltages may be exported to
the VREF pin at the same time, which can result in undefined
behavior. To ensure a proper readout, switch off all other voltage
exporting circuits as described in this section. Figure 73 shows
the block diagram of the controls that are required to enable the
diode voltage readout.
VREF PIN
CONTROL
SPI REGISTER
(0x18A6)
VREF
–20
0
20
40
60
80
100
The relationship between the measured delta voltage (ΔV) and
the junction temperature in °C is shown in Figure 75.
150
140
130
120
110
100
90
80
70
60
50
40
30
20
10
0
–10
–20
–30
–40
60
TJ (°C)
15547-068
The SPI writes required to export the central temperature diode
are as follows (see Table 46 for more information):
5.
0.55
Figure 74. Typical Voltage Response of the 1× Temperature Diode
Figure 73. Register Controls to Output Temperature Diode Voltage on the
VREF Pin
4.
0.60
JUNCTION TEMPERATURE (°C)
CHANNEL B
1.
2.
3.
0.65
0.50
–40
CHANNEL A
CENTRAL
TEMPERATURE DIODE
LOCATION SELECT
SPI REGISTER (0x18E6)
0.70
15547-069
DIGITAL
TEMPERATURE DIODE
LOCATIONS
0.75
Set Register 0x0008 to 0x03 to select both channels.
Set Register 0x18E3 to 0x00 to turn off VCM export.
Set Register 0x18A6 to 0x00 to turn off voltage reference
export.
Set Register 0x18E6 to 0x01 to turn on voltage export of
the central 1× temperature diode. The typical voltage
response of the temperature diode is shown in Figure 74.
Although this voltage represents the die temperature, it is
recommended to take measurements from a pair of diodes
for improved accuracy. The following step explains how to
enable the 20× diode.
Set Register 0x18E6 to 0x02 to turn on the second central
temperature diode of the pair, which is 20× the size of the
first. For the method using two diodes simultaneously to
achieve a more accurate result, see the AN-1432 Application
Note, Practical Thermal Modeling and Measurements in
High Power ICs.
Rev. 0 | Page 32 of 136
65
70
75
80
85
90
95
100
105
DELTA VOLTAGE (mV)
Figure 75. Junction Temperature vs. ΔV (mV)
110
15547-070
VREF
15547-067
ADC
B
TEMPERATURE DIODE VOLTAGE (V)
ADC
ADC
A
Data Sheet
AD9208
ADC OVERRANGE AND FAST DETECT
The operation of the upper threshold and lower threshold
registers, along with the dwell time registers, is shown in
Figure 76.
In receiver applications, it is desirable to have a mechanism to
reliably determine when the converter is about to be clipped.
The standard overrange bit in the JESD204B outputs provides
information on the state of the analog input that is of limited
usefulness. Therefore, it is helpful to have a programmable
threshold below full scale that allows time to reduce the gain
before the clip actually occurs. In addition, because input
signals can have significant slew rates, the latency of this
function is of major concern. Highly pipelined converters can
have significant latency. The AD9208 contains fast detect
circuitry for individual channels to monitor the threshold and
assert the FD_A and FD_B pins.
The FD indicator is asserted if the input magnitude exceeds the
value programmed in the fast detect upper threshold registers,
located at Register 0x0247 and Register 0x0248. The selected
threshold register is compared with the signal magnitude at the
output of the ADC. The fast upper threshold detection has a
latency of 28 clock cycles (maximum). The approximate upper
threshold magnitude is defined by
Upper Threshold Magnitude (dBFS) = 20log(Threshold
Magnitude/213)
ADC OVERRANGE
The FD indicators are not cleared until the signal drops below
the lower threshold for the programmed dwell time. The lower
threshold is programmed in the fast detect lower threshold
registers, located at Register 0x0249 and Register 0x024A. The
fast detect lower threshold register is a 13-bit register that is
compared with the signal magnitude at the output of the ADC.
This comparison is subject to the ADC pipeline latency, but is
accurate in terms of converter resolution. The lower threshold
magnitude is defined by
The ADC overrange indicator is asserted when an overrange is
detected on the input of the ADC. The overrange indicator can
be embedded within the JESD204B link as a control bit (when
CSB > 0). The latency of this overrange indicator matches the
sample latency.
The AD9208 also records any overrange condition in any of the
eight virtual converters. For more information on the virtual
converters, refer to Figure 84. The overrange status of each virtual
converter is registered as a sticky bit in Register 0x0563. The
contents of Register 0x0563 can be cleared using Register 0x0562,
by toggling the bits corresponding to the virtual converter to set
and reset position.
Lower Threshold Magnitude (dBFS) = 20log(Threshold
Magnitude/213)
For example, to set an upper threshold of −6 dBFS, write 0xFFF
to Register 0x0247 and Register 0x0248. To set a lower threshold of
−10 dBFS, write 0xA1D to Register 0x0249 and Register 0x024A.
FAST THRESHOLD DETECTION (FD_A AND FD_B)
The FD_A or FD_B pin is immediately set whenever the
absolute value of the input signal exceeds the programmable
upper threshold level. The FD bit is only cleared when the
absolute value of the input signal drops below the lower
threshold level for greater than the programmable dwell time.
This feature provides hysteresis and prevents the FD bit from
excessively toggling.
The dwell time can be programmed from 1 to 65,535 sample
clock cycles by placing the desired value in the fast detect dwell
time registers, located at Register 0x024B and Register 0x024C.
See Register 0x0040 and Register 0x0245 to Register 0x024C in
the Memory Map section (see Table 46) for more details.
UPPER THRESHOLD
DWELL TIME
TIMER RESET BY
RISE ABOVE
LOWER
THRESHOLD
DWELL TIME
FD_A OR FD_B
Figure 76. Threshold Settings for the FD_A and FD_B Signals
Rev. 0 | Page 33 of 136
TIMER COMPLETES BEFORE
SIGNAL RISES ABOVE
LOWER THRESHOLD
15547-071
MIDSCALE
LOWER THRESHOLD
AD9208
Data Sheet
ADC APPLICATION MODES AND JESD204B Tx CONVERTER MAPPING
Table 11 shows the number of virtual converters required and
the transport layer mapping when channel swapping is disabled.
Figure 77 shows the virtual converters and their relationship to
the DDC outputs when complex outputs are used.
The AD9208 contains a configurable signal path that allows
different features to be enabled for different applications. These
features are controlled using the chip application mode register,
Register 0x0200. The chip operating mode is controlled by Bits[3:0]
in this register, and the chip Q ignore is controlled by Bit 5.
Each DDC channel outputs either two sample streams (I/Q) for
the complex data components (real + imaginary), or one sample
stream for real (I) data. The AD9208 can be configured to use up to
eight virtual converters, depending on the DDC configuration.
The AD9208 contains the following modes:
Full bandwidth mode: two 14-bit ADC cores running at
full sample rate.
DDC mode: up to four digital downconverter (DDC)
channels.
The I/Q samples are always mapped in pairs with the I samples
mapped to the first virtual converter and the Q samples mapped
to the second virtual converter. With this transport layer mapping,
the number of virtual converters are the same whether a single
real converter is used along with a digital downconverter block
producing I/Q outputs, or whether an analog downconversion
is used with two real converters producing I/Q outputs.
After the chip application mode is selected, the output
decimation ratio is set using the chip decimation ratio in
Register 0x0201, Bits[3:0]. The output sample rate = ADC
sample rate/the chip decimation ratio.
To support the different application layer modes, the AD9208
treats each sample stream (real, I, or Q) as originating from
separate virtual converters.
Figure 78 shows a block diagram of the two scenarios described
for I/Q transport layer mapping.
Table 11. Virtual Converter Mapping
1
2
2
4
4
8
Chip Operating
Mode
(Reg. 0x0200,
Bits[3:0])
Full bandwidth
mode (0x0)
One DDC mode
(0x1)
One DDC mode
(0x1)
Two DDC mode
(0x2)
Two DDC mode
(0x2)
Four DDC mode
(0x3)
Four DDC mode
(0x3)
Virtual Converter Mapping
Chip Q Ignore
(0x0200, Bit 5)
Real or
complex (0x0)
Real (I only)
(0x1)
Complex (I/Q)
(0x0)
Real (I only)
(0x1)
Complex (I/Q)
(0x0)
Real (I only)
(0x1)
Complex (I/Q)
(0x0)
REAL/I
0
ADC A
samples
DDC0 I
samples
DDC0 I
samples
DDC0 I
samples
DDC0 I
samples
DDC0 I
samples
DDC0 I
samples
1
ADC B
samples
Unused
2
Unused
3
Unused
4
Unused
5
Unused
6
Unused
7
Unused
Unused
Unused
Unused
Unused
Unused
Unused
DDC0 Q
samples
DDC1 I
samples
DDC0 Q
samples
DDC1 I
samples
DDC0 Q
samples
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
DDC1 I
samples
DDC2 I
samples
DDC1 I
samples
DDC1 Q
samples
DDC3 I
samples
DDC1 Q
samples
Unused
Unused
Unused
Unused
Unused
Unused
Unused
Unused
DDC2 I
samples
DDC2 Q
samples
DDC3 I
samples
DDC3 Q
samples
REAL/I
ADC A
SAMPLING
AT fS
REAL/Q
REAL/I
I/Q
CROSSBAR
MUX
REAL/Q
REAL/I
REAL/Q
REAL/Q
ADC B
SAMPLING
AT fS
REAL/I
REAL/Q
DDC 0
I
REAL/I
CONVERTER 0
Q
Q
CONVERTER 1
I
Q
DDC 1
I
REAL/I
CONVERTER 2
Q
Q
CONVERTER 3
I
Q
DDC 2
I
OUTPUT
INTERFACE
REAL/I
CONVERTER 4
Q
Q
CONVERTER 5
I
Q
DDC 3
I
Q
REAL/I
CONVERTER 6
Q
Q
CONVERTER 7
I
Figure 77. DDCs and Virtual Converter Mapping
Rev. 0 | Page 34 of 136
15547-072
Number of
Virtual
Converters
Supported
1 to 2
Data Sheet
AD9208
DIGITAL DOWNCONVERSION
M=2
I
CONVERTER 0
ADC
REAL
I
REAL
DIGITAL
DOWN
CONVERSION
L LANES
JESD204B
Tx
L LANES
I/Q ANALOG MIXING
M=2
I
CONVERTER 0
ADC
90°
PHASE
Q
JESD204B
Tx
Q
CONVERTER 1
ADC
Q
CONVERTER 1
Figure 78. I/Q Transport Layer Mapping
Rev. 0 | Page 35 of 136
15547-073
REAL
AD9208
Data Sheet
PROGRAMMABLE FIR FILTERS
SUPPORTED MODES
The AD9208 supports the following modes of operation (the
asterisk symbol (*) denotes convolution):
PROGRAMMABLE FILTER (PFILT)
I (REAL)
ADC A
CORE
DINI [n]
48-TAP FIR
FILTER
xyI [n]
DOUTI [n]
I′ (REAL)
SIGNAL
PROCESSING
BLOCKS
Q (IMAG)
ADC B
CORE
DINQ [n]
48-TAP FIR
FILTER
xyQ [n]
DOUTQ [n]
JESD204B
INTERFACE
Q′ (IMAG)
15547-074
Real 48-tap filter for each I/Q channel (see Figure 79)
DOUT_I[n] = DIN_I[n] * XY_I[n]
DOUT_Q[n] = DIN_Q[n] * XY_Q[n]
Real 96-tap filter for on either I or Q channel (see Figure 80)
DOUT_I[n] = DIN_I[n] * XY_I[n]
DOUT_Q[n] = DIN_Q[n] * XY_Q[n]
Real set of two cascaded 24-tap filters for each I/Q channel
(see Figure 81)
DOUT_I[n] = DIN_I[n] * X_I[n] * Y_I[n]
DOUT_Q[n] = DIN_Q[n] * X_Q[n] * Y_Q[n]
Figure 79. Real 48-Tap Filter Configuration
PROGRAMMABLE FILTER (PFILT)
I (REAL)
ADC A
CORE
DINI [n]
96-TAP FIR
FILTER
xIyIxQyQ [n]
DOUTI [n]
I′ (REAL)
SIGNAL
PROCESSING
BLOCKS
Q (IMAG)
ADC B
CORE
DINQ [n]
DOUTQ [n]
Q′ (IMAG)
Figure 80. Real 96-Tap Filter Configuration
Rev. 0 | Page 36 of 136
JESD204B
INTERFACE
15547-075
Half complex filter using two real 48-tap filters for the I/Q
channels (see Figure 82)
DOUT_I[n] = DIN_I[n]
DOUT_Q[n] = DIN_Q[n] * XY_Q[n] + DIN_I[n] *
XY_I[n]
Full complex filter using four real 24-tap filters for the I/Q
channels (see Figure 83)
DOUT_I[n] = DIN_I[n] * X_I[n] + DIN_Q[n] *
Y_Q[n]
DOUT_Q[n] = DIN_Q[n] * X_Q[n] + DIN_I[n] *
Y_I[n]
Data Sheet
AD9208
PROGRAMMABLE FILTER (PFILT)
I (REAL)
ADC A
CORE
DINI [n]
24-TAP FIR
FILTER
xI [n]
DOUTI [n]
24-TAP FIR
FILTER
yI [n]
I′ (REAL)
SIGNAL
PROCESSING
BLOCKS
JESD204B
INTERFACE
24-TAP FIR
FILTER
yQ [n]
ADC B
CORE
DINQ [n]
24-TAP FIR
FILTER
xQ [n]
DOUTQ [n]
Q′ (IMAG)
15547-076
Q (IMAG)
Figure 81. Real, Two Cascaded, 24-Tap Filter Configuration
PROGRAMMABLE FILTER (PFILT)
I (REAL)
ADC A
CORE
DINI [n]
DOUTI [n]
0 TO 47
DELAY TAPS
48-TAP FIR
FILTER
xyI [n]
I′ (REAL)
SIGNAL
PROCESSING
BLOCKS
JESD204B
INTERFACE
+
ADC B
CORE
DINQ [n]
48-TAP FIR
FILTER
xyQ [n]
+
DOUTQ [n]
Q′ (IMAG)
15547-077
Q (IMAG)
Figure 82. 48-Tap Half Complex Filter Configuration
PROGRAMMABLE FILTER (PFILT)
I (REAL)
ADC A
CORE
DINI [n]
24-TAP FIR
FILTER
xI [n]
DOUTI [n]
+
I′ (REAL)
+
24-TAP FIR
FILTER
yI [n]
SIGNAL
PROCESSING
BLOCKS
JESD204B
INTERFACE
24-TAP FIR
FILTER
yQ [n]
ADC B
CORE
DINQ [n]
24-TAP FIR
FILTER
xQ [n]
+
DOUTQ [n]
Q′ (IMAG)
Figure 83. 24-Tap Full Complex Filter Configuration.
Rev. 0 | Page 37 of 136
15547-078
+
Q (IMAG)
AD9208
Data Sheet
PROGRAMMING INSTRUCTIONS
Table 12. Register 0x0DF8 Definition
Use the following procedure to set up the programmable FIR filter:
Bit(s)
[7:3]
[2:0]
1.
2.
3.
4.
5.
6.
7.
Enable the sample clock to the device.
Configure the mode registers as follows:
a. Set the device index to Channel A (I path)
(Register 0x0008 = 0x01).
b. Set the I path mode (I mode) and gain in
Register 0x0DF8 and Register 0x0DF9 (see Table 12
and Table 13).
c. Set the device index to Channel B (Q path)
(Register 0x0008 = 0x02).
d. Set the Q path mode (Q mode) and gain in
Register 0x0DF8 and Register 0x0DF9.
Wait at least 5 μs to allow the programmable filter to power up.
Program the I path coefficients to the internal shadow
registers as follows:
a. Set the device index to Channel A (I path)
(Register 0x0008 = 0x01).
b. Program the XI coefficients in Register 0x0E00 to
Register 0x0E2F (see Table 14 and Table 15).
c. Program the YI coefficients in Register 0x0F00 to
Register 0x0F2F (see Table 14 and Table 15).
d. Program the tapped delay in Register 0x0F30 (note
that this step is optional).
Program the Q path coefficients to the internal shadow
registers as follows:
a. Set the device index to Channel B (Q path)
(Register 0x0008 = 0x02).
b. Set the Q path mode and gain in Register 0x0DF8 and
Register 0x0DF9 (see Table 12 and Table 13).
c. Program the XQ coefficients in Register 0x0E00 to
Register 0x0E2F (see Table 14 and Table 15)
d. Program the YQ coefficients in Register 0x0F00 to
Register 0x0F2F (see Table 14 and Table 15)
e. Program the tapped delay in Register 0x0F30 (note
that this step is optional).
Set the chip transfer bit using either of the following
methods (note that setting the chip transfer bit applies the
programmed shadow coefficients to the filter):
a. Via the register map using the write the chip transfer
bit (Register 0x000F = 0x01).
b. Via a GPIO pin, as follows:
i. Configure one of the GPIO pins as the chip
transfer bit in Register 0x0040 to Register 0x0042.
ii. Toggle the GPIO pin to initiate the chip transfer
(the rising edge is triggered).
When the I or Q path mode register changes in
Register 0x0DF8, all coefficients must be reprogrammed.
Description
Reserved
Filter mode (I mode or Q mode)
000: filters bypassed
001: real 24-tap filter (X only)
010: real 48-tap filter (X and Y together)
100: real set of two cascaded 24-tap filters (X then Y
cascaded)
101: full complex filter using four real 24-tap filters for the
A/B channels (opposite channel must also be set to 101)
110: half complex filter using two real 48-tap filters +
48-tap delay line (X and Y together) (opposite channel
must also be set to 010)
111: real 96-tap filter (XI, YI, XQ, and YQ together)
(opposite channel must be set to 000)
Table 13. Register 0x0DF9 Definition
Bit(s)
7
[6:4]
3
[2:0]
Description
Reserved
Y filter gain
110: −12 dB loss
111: −6 dB loss
000: 0 dB gain
001: 6 dB gain
010: 12 dB gain
Reserved
X filter gain
110: −12 dB loss
111: −6 dB loss
000: 0 dB gain
001: 6 dB gain
010: 12 dB gain
Table 14 and Table 15 show the coefficient tables in
Register 0x0E00 to Register 0x0F30. Note that all coefficients
are Q1.15 format (sign bit + 15 fractional bits).
Rev. 0 | Page 38 of 136
Data Sheet
AD9208
Table 14. I Coefficient Table (Device Selection = 0x1)1
Addr.
0x0E00
0x0E01
0x0E02
0x0E03
…
0x0E2E
0x0E2F
0x0F00
0x0F01
0x0F02
0x0F03
…
0x0F2E
0x0F2F
0x0F30
Single 24-Tap
Filter (I Mode
[2:0] = 0x1)
XI C0 [7:0]
XI C0 [15:8]
XI C1 [7:0]
XI C1 [15:8]
…
XI C23 [7:0]
XI C23 [15:0]
Unused
Unused
Unused
Unused
…
Unused
Unused
Unused
Single 48-Tap
Filter (I Mode
[2:0] = 0x2)
XI C0 [7:0]
XI C0 [15:8]
XI C1 [7:0]
XI C1 [15:8]
…
XI C23 [7:0]
XI C23 [15:0]
YI C24 [7:0]
YI C24 [15:8]
YI C25 [7:0]
YI C25 [15:8]
…
YI C47 [7:0]
YI C47 [15:0]
Unused
Two Cascaded
24-Tap Filters (I
Mode [2:0] = 0x4)
XI C0 [7:0]
XI C0 [15:8]
XI C1 [7:0]
XI C1 [15:8]
…
XI C23 [7:0]
XI C23 [15:0]
YI C0 [7:0]
YI C0 [15:8]
YI C1 [7:0]
YI C1 [15:8]
…
YI C23 [7:0]
YI C23 [15:0]
Unused
Full Complex
24-Tap Filters (I
Mode [2:0] = 0x5
and Q Mode
[2:0] = 0x5)
XI C0 [7:0]
XI C0 [15:8]
XI C1 [7:0]
XI C1 [15:8]
…
XI C23 [7:0]
XI C23 [15:0]
YI C0 [7:0]
YI C0 [15:8]
YI C1 [7:0]
YI C1 [15:8]
…
YI C23 [7:0]
YI C23 [15:0]
Unused
Half Complex
48-Tap Filters (I
Mode [2:0] = 0x6
and Q Mode
[2:0] = 0x2)2
XI C0 [7:0]
XI C0 [15:8]
XI C1 [7:0]
XI C1 [15:8]
…
XI C23 [7:0]
XI C23 [15:0]
YI C24 [7:0]
YI C24 [15:8]
YI C25 [7:0]
YI C25 [15:8]
…
YI C47 [7:0]
YI C47 [15:0]
I path tapped delay
0: 0 tapped delay
(matches C0 in the
filter)
1: 1 tapped delays
…
47: 47 tapped delays
I Path 96-Tap
Filter (I Mode[2:0] =
0x7 and Q Mode
[2:0] = 0x0)3
XI C0 [7:0]
XI C0 [15:8]
XI C1 [7:0]
XI C1 [15:8]
…
XI C23 [7:0]
XI C23 [15:0]
YI C24 [7:0]
YI C24 [15:8]
YI C25 [7:0]
YI C25 [15:8]
…
YI C47 [7:0]
YI C47 [15:0]
Unused
Q Path 96-Tap
Filter (I Mode
[2:0] = 0x0 and Q
Mode [2:0] = 0x7)3
XQ C48 [7:0]
XQ C48 [15:8]
XQ C49 [7:0]
XQ C49 [15:8]
…
XQ C71 [7:0]
XQ C71 [15:0]
YQ C72 [7:0]
YQ C72 [15:8]
YQ C73 [7:0]
YQ C73 [15:8]
…
YQ C95 [7:0]
YQ C95 [15:0]
Unused
I Path 96-Tap
Filter (Q Mode
[2:0] = 0x0 and I
Mode [2:0] = 0x7)3
XI C48 [7:0]
XI C48 [15:8]
XI C49 [7:0]
XI C49 [15:8]
…
XI C71 [7:0]
XI C71 [15:0]
YI C72 [7:0]
YI C72 [15:8]
YI C73 [7:0]
YI C73 [15:8]
…
YI C95 [7:0]
YI C95 [15:0]
Unused
Q Path 96-Tap
Filter (Q Mode
[2:0] = 0x7 and I
Mode [2:0] = 0x0)3
XQ C0 [7:0]
XQ C0 [15:8]
XQ C1 [7:0]
XQ C1 [15:8]
…
XQ C23 [7:0]
XQ C23 [15:0]
YQ C24 [7:0]
YQ C24 [15:8]
YQ C25 [7:0]
YQ C25 [15:8]
…
YQ C47 [7:0]
YQ C47 [15:0]
Unused
1
XI Cn means I Path X Coefficient n. YI Cn means I Path Y Coefficient n.
When using the I path in half-complex 48-tap filter mode, the Q path must be in single 48-tap filter mode.
3
When using the I path in 96-tap filter mode, the Q path must be in bypass mode.
2
Table 15. Q Coefficient Table (Device Selection = 0x2)1
Addr.
0x0E00
0x0E01
0x0E02
0x0E03
…
0x0E2E
0x0E2F
0x0F00
0x0F01
0x0F02
0x0F03
…
0x0F2E
0x0F2F
0x0F30
Single 24-Tap
Filter (Q Mode
[2:0] = 0x1)
XQ C0 [7:0]
XQ C0 [15:8]
XQ C1 [7:0]
XQ C1 [15:8]
…
XQ C23 [7:0]
XQ C23 [15:0]
Unused
Unused
Unused
Unused
…
Unused
Unused
Unused
Single 48-Tap
Filter (Q Mode
[2:0] = 0x2)
XQ C0 [7:0]
XQ C0 [15:8]
XQ C1 [7:0]
XQ C1 [15:8]
…
XQ C23 [7:0]
XQ C23 [15:0]
YQ C24 [7:0]
YQ C24 [15:8]
YQ C25 [7:0]
YQ C25 [15:8]
…
YQ C47 [7:0]
YQ C47 [15:0]
Unused
Two Cascaded
24-Tap Filters (Q
Mode [2:0] = 0x4)
XQ C0 [7:0]
XQ C0 [15:8]
XQ C1 [7:0]
XQ C1 [15:8]
…
XQ C23 [7:0]
XQ C23 [15:0]
YQ C0 [7:0]
YQ C0 [15:8]
YQ C1 [7:0]
YQ C1 [15:8]
…
YQ C23 [7:0]
YQ C23 [15:0]
Unused
Full Complex
24-Tap Filters (Q
Mode [2:0] = 0x5
and I Mode
[2:0] = 0x5)
XQ C0 [7:0]
XQ C0 [15:8]
XQ C1 [7:0]
XQ C1 [15:8]
…
XQ C23 [7:0]
XQ C23 [15:0]
YQ C0 [7:0]
YQ C0 [15:8]
YQ C1 [7:0]
YQ C1 [15:8]
…
YQ C23 [7:0]
YQ C23 [15:0]
Unused
1
Half Complex
48-Tap Filters (Q
Mode [2:0] = 0x6
and I Mode
[2:0] = 0x2)2
XQ C0 [7:0]
XQ C0 [15:8]
XQ C1 [7:0]
XQ C1 [15:8]
…
XQ C23 [7:0]
XQ C23 [15:0]
YQ C24 [7:0]
YQ C24 [15:8]
YQ C25 [7:0]
YQ C25 [15:8]
…
YQ C47 [7:0]
YQ C47 [15:0]
Q Path Tapped
Delay
0: 0 tapped delay
(matches C0 in the
filter)
1: 1 tapped delays
…
47: 47 tapped
delays
XQ Cn means Q Path X Coefficient n. YQ Cn means Q Path Y Coefficient n.
When using the I path in half-complex 48-tap filter mode, the Q path must be in single 48-tap filter mode.
3
When using the I path in 96-tap filter mode, the Q path must be in bypass mode.
2
Rev. 0 | Page 39 of 136
AD9208
Data Sheet
DIGITAL DOWNCONVERTER (DDC)
The AD9208 includes four digital downconverters (DDC0 to
DDC3) that provide filtering and reduce the output data rate.
This digital processing section includes an NCO, multiple
decimating FIR filters, a gain stage, and a complex to real
conversion stage. Each of these processing blocks has control lines
that allow it to be independently enabled and disabled to provide
the desired processing function. The digital downconverter can be
configured to output either real data or complex output data.
The DDCs output a 16-bit stream. To enable this operation, the
converter number of bits, N, is set to a default value of 16, even
though the analog core only outputs 14 bits. In full bandwidth
operation, the ADC outputs are the 14-bit word followed by two
zeros, unless the tail bits are enabled.
DDC I/Q INPUT SELECTION
The AD9208 has two ADC channels and four DDC channels.
Each DDC channel has two input ports that can be paired to
support both real and complex inputs through the I/Q crossbar
mux. For real signals, both DDC input ports must select the
same ADC channel (that is, DDC Input Port I = ADC Channel A
and DDC Input Port Q = ADC Channel A). For complex
signals, each DDC input port must select different ADC
channels (that is, DDC Input Port I = ADC Channel A and
DDC Input Port Q = ADC Channel B).
The inputs to each DDC are controlled by the DDC input selection registers (Register 0x0311, Register 0x0331, Register 0x0351,
and Register 0x0371). See Table 46 for information on how to
configure the DDCs.
DDC I/Q OUTPUT SELECTION
Each DDC channel has two output ports that can be paired to
support both real and complex outputs. For real output signals,
only the DDC Output Port I is used (the DDC Output Port Q is
invalid). For complex I/Q output signals, both DDC Output
Port I and DDC Output Port Q are used.
The I/Q outputs to each DDC channel are controlled by the
DDC complex to real enable bit, Bit 3, in the DDC control
registers (Register 0x0310, Register 0x0330, Register 0x0350,
and Register 0x0370).
The chip Q ignore bit in the chip mode register (Register 0x0200,
Bit 5) controls the chip output muxing of all the DDC channels.
When all DDC channels use real outputs, set this bit high to
ignore all DDC Q output ports. When any of the DDC channels
are set to use complex I/Q outputs, the user must clear this bit
to use both DDC Output Port I and DDC Output Port Q. For
more information, see Figure 101.
DDC GENERAL DESCRIPTION
The four DDC blocks are used to extract a portion of the full
digital spectrum captured by the ADC(s). They are intended for
IF sampling or oversampled baseband radios requiring wide
bandwidth input signals.
Each DDC block contains the following signal processing
stages:
Frequency translation stage (optional)
Filtering stage
Gain stage (optional)
Complex to real conversion stage (optional)
DDC Frequency Translation Stage (Optional)
This stage consists of a phase coherent NCO and quadrature
mixers that can be used for frequency translation of both real or
complex input signals. The phase coherent NCO allows an
infinite number of frequency hops that are all referenced back
to a single synchronization event. It also includes 16 shadow
registers for fast switching applications. This stage shifts a
portion of the available digital spectrum down to baseband.
DDC Filtering Stage
After shifting down to baseband, this stage decimates the
frequency spectrum using multiple low-pass finite impulse
response (FIR) filters for rate conversion. The decimation
process lowers the output data rate, which in turn reduces the
output interface rate.
DDC Gain Stage (Optional)
Because of losses associated with mixing a real input signal
down to baseband, this stage compensates by adding an
additional 0 dB or 6 dB of gain.
DDC Complex to Real Conversion Stage (Optional)
When real outputs are necessary, this stage converts the
complex outputs back to real by performing an fS/4 mixing
operation plus a filter to remove the complex component of the
signal.
Figure 84 shows the detailed block diagram of the DDCs
implemented in the AD9208.
Figure 85 shows an example usage of one of the four DDC
channels with a real input signal and four half-band filters
(HB4 + HB3 + HB2 + HB1) used. It shows both complex
(decimate by 16) and real (decimate by 8) output options.
Rev. 0 | Page 40 of 136
Data Sheet
AD9208
COMPLEX TO REAL
CONVERSION (OPTIONAL)
COMPLEX TO REAL
CONVERSION (OPTIONAL)
Q CONVERTER 1
Q
REAL/I
I
DECIMATION
FILTERS
REAL/I
CONVERTER 2
Q CONVERTER 3
DDC 2
REAL/I
Q
REAL/I
I
DECIMATION
FILTERS
REAL/I
CONVERTER 4
JESD204B TRANSMIT INTERFACE
I/Q CROSSBAR MUX
REAL/I
ADC B
SAMPLING
AT fS
L
JESD204B
LANES
AT UP TO
16Gbps
Q CONVERTER 5
DDC 3
DECIMATION
FILTERS
Q
SYSREF
REAL/I
CONVERTER 6
Q CONVERTER 7
SYSREF
DCM = DECIMATION
15547-079
NCO CHANNEL
SELECTION
CIRCUITS
DECIMATION
FILTERS
REAL/I
CONVERTER 0
DDC 1
REAL/I
GPIO PINS
COMPLEX TO REAL
CONVERSION (OPTIONAL)
I
NCO
+
MIXER
(OPTIONAL)
REGISTER MAP
CONTROLS
COMPLEX TO REAL
CONVERSION (OPTIONAL)
REAL/I
NCO
+
MIXER
(OPTIONAL)
SYNCHRONIZATION
CONTROL CIRCUITS
GAIN = 0 OR +6dB
Q
NCO
+
MIXER
(OPTIONAL)
SYSREF
PIN
GAIN = 0 OR +6dB
REAL/I
ADC A
SAMPLING
AT fS
REAL/Q
GAIN = 0 OR +6dB
I
NCO
+
MIXER
(OPTIONAL)
REAL/I
GAIN = 0 OR +6dB
DDC 0
REAL/I
NCO CHANNEL SELECTION
Figure 84. DDC Detailed Block Diagram
Rev. 0 | Page 41 of 136
AD9208
Data Sheet
ADC
–fS/2
–fS/3
ADC
SAMPLING
AT fS
REAL
REAL INPUT—SAMPLED AT fS
BANDWIDTH OF
INTEREST IMAGE
–fS/4
REAL
BANDWIDTH OF
INTEREST
fS/32
–fS/32
DC
–fS/16
fS/16
–fS/8
fS/8
fS/4
fS/3
fS/2
FREQUENCY TRANSLATION STAGE (OPTIONAL)
I
DIGITAL MIXER + NCO
FOR fS/3 TUNING, THE FREQUENCY TUNING WORD = ROUND
((fS/3)/fS × 248) = +9.382513
(0x5555_5555_5555)
NCO TUNES CENTER OF
BANDWIDTH OF INTEREST
TO BASEBAND
cos(ωt)
REAL
48-BIT
NCO
90°
0°
–sin(ωt)
Q
DIGITAL FILTER
RESPONSE
–fS/3
–fS/4
fS/32
–fS/32
DC
–fS/16
fS/16
–fS/8
FILTERING STAGE
HB4 FIR
4 DIGITAL HALF-BAND FILTERS
(HB4 + HB3 + HB2 + HB1)
I
HALFBAND
FILTER
Q
HALFBAND
FILTER
HB3 FIR
2
HALFBAND
FILTER
2
HALFBAND
FILTER
HB4 FIR
fS/8
2
2
HALFBAND
FILTER
HB3 FIR
fS/3
fS/2
HB1 FIR
HB2 FIR
HALFBAND
FILTER
fS/4
2
HALFBAND
FILTER
2
HALFBAND
FILTER
2
I
HB1 FIR
HB2 FIR
2
Q
6dB GAIN TO
COMPENSATE FOR
NCO + MIXER LOSS
DIGITAL FILTER
RESPONSE
0dB OR 6dB GAIN
I
GAIN STAGE (OPTIONAL)
Q
0dB OR 6dB GAIN
COMPLEX TO REAL
CONVERSION STAGE (OPTIONAL)
fS/32
–fS/32
DC
–fS/16
fS/16
–fS/8
COMPLEX (I/Q) OUTPUTS
DECIMATE BY 16
GAIN STAGE (OPTIONAL)
fS/8
fS/4 MIXING + COMPLEX FILTER TO REMOVE Q
2
+6dB
2
+6dB
I
Q
fS/32
–fS/32
DC
–fS/16
fS/16
DOWNSAMPLE BY 2
I
REAL (I) OUTPUTS
+6dB
I
DECIMATE BY 8
Q
+6dB
Q
COMPLEX REAL/I
TO
REAL
6dB GAIN TO
COMPENSATE FOR
NCO + MIXER LOSS
–fS/8
fS/32
–fS/32
DC
–fS/16
fS/16
fS/8
Figure 85. DDC Theory of Operation Example (Real Input)
Rev. 0 | Page 42 of 136
15547-080
–fS/2
BANDWIDTH OF
INTEREST IMAGE
(–6dB LOSS DUE TO
NCO + MIXER)
BANDWIDTH OF INTEREST
(–6dB LOSS DUE TO
NCO + MIXER)
Data Sheet
AD9208
DDC FREQUENCY TRANSLATION
Variable IF Mode
DDC Frequency Translation General Description
In this mode, the NCO and mixers are enabled. NCO output
frequency can be used to digitally tune the IF frequency.
Frequency translation is accomplished by using a 48-bit
complex NCO with a digital quadrature mixer. This stage
translates either a real or complex input signal from an IF to a
baseband complex digital output (carrier frequency = 0 Hz).
0 Hz IF (ZIF) Mode
In this mode, the mixers are bypassed, and the NCO is disabled.
fS/4 Hz IF Mode
The frequency translation stage of each DDC can be controlled
individually and supports four different IF modes using Bits[5:4]
of the DDC control registers (Register 0x0310, Register 0x0330,
Register 0x0350, and Register 0x0370). These IF modes are
Test Mode
In this mode, input samples are forced to 0.999 to positive full
scale. The NCO is enabled. This test mode allows the NCOs to
directly drive the decimation filters.
Variable IF mode
0 Hz IF or zero IF (ZIF) mode
fS/4 Hz IF mode
Test mode
Figure 86 and Figure 87 show examples of the frequency
translation stage for both real and complex inputs.
NCO FREQUENCY TUNING WORD (FTW) SELECTION
48-BIT NCO FTW = MIXING FREQUENCY/ADC SAMPLE RATE × 4096
I
ADC + DIGITAL MIXER + NCO
REAL INPUT—SAMPLED AT fS
REAL
cos(ωt)
ADC
SAMPLING
AT fS
REAL
48-BIT
NCO
90°
0°
COMPLEX
–sin(ωt)
Q
BANDWIDTH OF
INTEREST
BANDWIDTH OF
INTEREST IMAGE
–fS/2
–fS/3
–fS/4
–fS/8
–fS/32
fS/32
DC
–fS/16
fS/16
fS/8
fS/4
fS/3
fS/2
–6dB LOSS DUE TO
NCO + MIXER
48-BIT NCO FTW =
ROUND ((fS/3)/fS × 248) = +9.382513
(0x5555_5555_5555)
POSITIVE FTW VALUES
–fS/32
DC
fS/32
48-BIT NCO FTW =
ROUND (( fS/3)/fS × 248) = –9.3825 13
(0xAAAA_AAAA_AAAA)
NEGATIVE FTW VALUES
–fS/32
DC
fS/32
Figure 86. DDC NCO Frequency Tuning Word Selection—Real Inputs
Rev. 0 | Page 43 of 136
15547-081
In this mode, the mixers and the NCO are enabled in
downmixing by fS/4 mode to save power.
AD9208
Data Sheet
NCO FREQUENCY TUNING WORD (FTW) SELECTION
48-BIT NCO FTW = MIXING FREQUENCY/ADC SAMPLE RATE × 248
QUADRATURE ANALOG MIXER +
2 ADCs + QUADRATURE DIGITAL
MIXER + NCO
QUADRATURE MIXER
ADC
SAMPLING
AT fS
I
+
I
I
Q
Q
REAL
90°
PHASE
48-BIT
NCO
90°
0°
COMPLEX INPUT—SAMPLED AT fS
Q
Q
ADC
SAMPLING
AT fS
Q
Q
I
I
–
–sin(ωt)
I
I
+
COMPLEX
Q
+
BANDWIDTH OF
INTEREST
IMAGE DUE TO
ANALOG I/Q
MISMATCH
–fS/3
–fS/4
–fS/8
–fS/32
fS/32
–fS/16
fS/16
DC
fS/8
fS/4
fS/3
fS/2
48-BIT NCO FTW =
ROUND ((fS/3)/fS × 248) = +9.382513
(0x5555_5555_5555)
POSITIVE FTW VALUES
–fS/32
fS/32
DC
Figure 87. DDC NCO Frequency Tuning Word Selection—Complex Inputs
Rev. 0 | Page 44 of 136
15547-082
–fS/2
Data Sheet
AD9208
DDC NCO Description
DDC NCO Coherent Mode
Each DDC contains one NCO. Each NCO enables the
frequency translation process by creating a complex exponential
frequency (e-jωct), which can be mixed with the input spectrum
to translate the desired frequency band of interest to dc, where
it can be filtered by the subsequent low-pass filter blocks to
prevent aliasing.
This mode allows an infinite number of frequency hops where the
phase is referenced to a single synchronization event at time 0.
This mode is useful when phase coherency must be maintained
when switching between different frequency bands. In this mode,
the user can switch to any tuning frequency without the need to
reset the NCO. Although only one FTW is required, the NCO
contains 16 shadow registers for fast-switching applications.
Selection of the shadow registers is controlled by the CMOS
GPIO pins or through the register map of the SPI. In this mode,
the NCO can be set up by providing the following:
When placed in variable IF mode, the NCO supports two
different additional modes.
DDC NCO Programmable Modulus Mode
This mode supports >48-bit frequency tuning accuracy for
applications that require exact rational (M/N) frequency
synthesis at a single carrier frequency. In this mode, the NCO is
set up by providing the following:
Figure 88 shows a block diagram of one NCO and its connection to
the rest of the design. The coherent phase accumulator block
contains the logic that allows an infinite number of frequency
hops. The gray lines in Figure 88 represent SPI control lines.
48-bit frequency tuning word (FTW)
48-bit Modulus A word (MAW)
48-bit Modulus B word (MBW)
48-bit phase offset word (POW)
NCO
NCO CHANNEL
SELECTION
FTW/POW
WRITE INDEX
SYNCHRONIZATION
CONTROL CIRCUITS
I/O
CROSSBAR
MUX
0
48-BIT
FTW/POW
0
1
48-BIT
FTW/POW
1
48-BIT
FTW/POW
15
15
COHERENT
PHASE
ACCUMULATOR
BLOCK
COS/SIN
GENERATOR
SYSREF
I
I
Q
Q
DIGITAL
QUADRATURE
MIXER
FTW = FREQUENCY TUNING WORD
POW = PHASE OFFSET WORD
MAW = MODULUS A WORD (NUMERATOR)
MBW = MODULUS B WORD (DENOMINATOR)
Figure 88. NCO + Mixer Block Diagram
Rev. 0 | Page 45 of 136
DECIMATION
FILTERS
15547-083
FTW/POW
REGISTER
MAP
MODULUS
ERROR
48-BIT
MAW/MBW
–sin(x)
MAW/MBW
cos(x)
NCO
CHANNEL
SELECTION
CIRCUITS
Up to sixteen 48-bit FTWs.
Up to sixteen 48-bit POWs.
The 48-bit MAW must be set to zero in coherent mode.
AD9208
Data Sheet
NCO FTW/POW/MAW/MAB Description
The NCO frequency value is determined by the following settings:
48-bit twos complement number entered in the FTW
48-bit unsigned number entered in the MAW
48-bit unsigned number entered in the MBW
M and N are integers reduced to their lowest terms. MAW and
MBW are integers reduced to their lowest terms. When MAW is
set to zero, the programmable modulus logic is automatically
disabled.
Frequencies between −fS/2 and +fS/2 (fS/2 excluded) are
represented using the following values:
Note that Equation 1 to Equation 4 apply to the aliasing of
signals in the digital domain (that is, aliasing introduced when
digitizing analog signals).
FTW = 0x8000_0000_0000 and MAW = 0x0000_0000_0000
represents a frequency of –fS/2.
FTW = 0x0000_0000_0000 and MAW = 0x0000_0000_0000
represents dc (frequency is 0 Hz).
FTW = 0x7FFF_FFFF_FFFF and MAW = 0x0000_0000_0000
represents a frequency of +fS/2.
For example, if the ADC sampling frequency (fS) is 3000 MSPS
and the carrier frequency (fC) is 1001.5 MHz, then,
mod(1001.5, 3000)
3000
FTW floor(248
In programmable modulus mode, the FTW, MAW, and MBW
must satisfy the following four equations (for a detailed
description of the programmable modulus feature, see the DDS
architecture described in the AN-953 Application Note):
mod( f c , f s ) M
fs
N
FTW floor(2
48
2 48
mod( fc , f s )
fs
)
mod(1001.5, 3000)
)
MAW = mod(248 × 2003, 6000) = 0x0000_0000_0F80
For programmable modulus mode, the MAW must be set to a
nonzero value (not equal to 0x0000_0000_0000). This mode is
only needed when frequency accuracy of >48 bits is required.
One example of a rational frequency synthesis requirement that
requires >48 bits of accuracy is a carrier frequency of 1/3 the
sample rate. When frequency accuracy of ≤48 bits is required,
coherent mode must be used (see the NCO FTW/POW/
MAW/MAB Coherent Mode section).
MAW
MBW
M 2003
N 6000
3000
0x5576_19F0_FB38
NCO FTW/POW/MAW/MAB Programmable Modulus
Mode
FTW
MBW = 0x0000_0000_1770
The actual carrier frequency can be calculated based on the
following equation:
f C _ ACTUAL
MAW = mod(248 × M,N)
(3)
MBW = N
(4)
where:
fC is the desired carrier frequency.
fS is the ADC sampling frequency.
M is the integer representing the rational numerator of the
frequency ratio.
N is the integer representing the rational denominator of the
frequency ratio.
FTW is the 48-bit twos complement number representing the
NCO FTW.
MAW is the 48-bit unsigned number representing the NCO
MAW (must be B
Figure 102. Signal Monitor Block
The peak detector captures the largest signal within the
observation period. The detector only observes the magnitude
of the signal. The resolution of the peak detector is a 13-bit
value, and the observation period is 24 bits and represents
converter output samples. The peak magnitude can be derived
by using the following equation:
The magnitude of the input port signal is monitored over a
programmable time period, which is determined by the signal
monitor period register (SMPR). The peak detector function is
enabled by setting Bit 1 in the signal monitor control register
(Register 0x0270). The 24-bit SMPR must be programmed
before activating this mode.
After enabling peak detection mode, the value in the SMPR is
loaded into a monitor period timer, which decrements at the
decimated clock rate. The magnitude of the input signal is
compared with the value in the internal magnitude storage
register (not accessible to the user), and the greater of the two
is updated as the current peak level. The initial value of the
magnitude storage register is set to the current ADC input signal
magnitude. This comparison continues until the monitor period
timer reaches a count of 1.
When the monitor period timer reaches a count of 1, the 13-bit
peak level value is transferred to the signal monitor holding
register, which can be read through the memory map or output
through the SPORT over the JESD204B interface. The monitor
period timer is reloaded with the value in the SMPR, and the
countdown restarts. In addition, the magnitude of the first
input sample is updated in the magnitude storage register, and
the comparison and update procedure, as explained previously,
continues.
Peak Magnitude (dBFS) = 20log(Peak Detector Value/213)
Rev. 0 | Page 64 of 136
Data Sheet
AD9208
is to be inserted (CS = 1), only the most significant control bit is
used (see Example Configuration 1 and Example Configuration 2
in Figure 103). To select the SPORT over JESD204B option,
program Register 0x0559, Register 0x055A, and Register 0x058F.
See Table 46 for more information on setting these bits.
SPORT OVER JESD204B
The signal monitor data can also be serialized and sent over the
JESD204B interface as control bits. These control bits must be
deserialized from the samples to reconstruct the statistical data.
The signal control monitor function is enabled by setting Bits[1:0]
of Register 0x0279 and Bit 1 of Register 0x027A. Figure 103 shows
two different example configurations for the signal monitor
control bit locations inside the JESD204B samples. A maximum
of three control bits can be inserted into the JESD204B samples;
however, only one control bit is required for the signal monitor.
Control bits are inserted from MSB to LSB. If only one control bit
Figure 104 shows the 25-bit frame data that encapsulates the
peak detector value. The frame data is transmitted MSB first
with five 5-bit subframes. Each subframe contains a start bit
that can be used by a receiver to validate the deserialized data.
Figure 105 shows the SPORT over JESD204B signal monitor
data with a monitor period timer set to 80 samples.
16-BIT JESD204B SAMPLE SIZE (N' = 16)
EXAMPLE
CONFIGURATION 1
(N' = 16, N = 15, CS = 1)
1-BIT
CONTROL
BIT
(CS = 1)
15-BIT CONVERTER RESOLUTION (N = 15)
15
S[14]
X
14
S[13]
X
13
S[12]
X
12
11
S[11]
X
10
S[10]
X
9
S[9]
X
8
S[8]
X
7
S[7]
X
6
S[6]
X
5
S[5]
X
S[4]
X
4
S[3]
X
3
S[2]
X
2
S[1]
X
1
0
S[0]
X
CTRL
[BIT 2]
X
SERIALIZED SIGNAL MONITOR
FRAME DATA
16-BIT JESD204B SAMPLE SIZE (N' = 16)
14-BIT CONVERTER RESOLUTION (N = 14)
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
S[13]
X
S[12]
X
S[11]
X
S[10]
X
S[9]
X
S[8]
X
S[7]
X
S[6]
X
S[5]
X
S[4]
X
S[3]
X
S[2]
X
S[1]
X
S[0]
X
CTRL
[BIT 2]
X
TAIL
X
SERIALIZED SIGNAL MONITOR
FRAME DATA
Figure 103. Signal Monitor Control Bit Locations
5-BIT SUBFRAMES
5-BIT IDLE
SUBFRAME
(OPTIONAL)
25-BIT
FRAME
IDLE
1
IDLE
1
IDLE
1
IDLE
1
IDLE
1
5-BIT IDENTIFIER START
0
SUBFRAME
ID[3]
0
ID[2]
0
ID[1]
0
ID[0]
1
5-BIT DATA
MSB
SUBFRAME
START
0
P[12]
P[11]
P[10]
P[9]
5-BIT DATA
SUBFRAME
START
0
P[8]
P[7]
P[6]
P5]
5-BIT DATA
SUBFRAME
START
0
P[4]
P[3]
P[2]
P1]
5-BIT DATA
LSB
SUBFRAME
START
0
P[0]
0
0
0
P[x] = PEAK MAGNITUDE VALUE
15547-099
EXAMPLE
CONFIGURATION 2
(N' = 16, N = 14, CS = 1)
Figure 104. SPORT over JESD204B Signal Monitor Frame Data
Rev. 0 | Page 65 of 136
15547-098
1
CONTROL
1 TAIL
BIT
BIT
(CS = 1)
AD9208
Data Sheet
SMPR = 80 SAMPLES (0x0271 = 0x50; 0x0272 = 0x00; 0x0273 = 0x00)
80 SAMPLE PERIOD
PAYLOAD
25-BIT FRAME (N)
IDENT.
DATA
MSB
DATA
DATA
DATA
LSB
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
IDLE
80 SAMPLE PERIOD
PAYLOAD
25-BIT FRAME (N + 1)
IDENT.
DATA
MSB
DATA
DATA
DATA
LSB
IDLE
IDLE
IDLE
IDLE
IDLE
80 SAMPLE PERIOD
IDENT.
DATA
MSB
DATA
DATA
DATA
LSB
IDLE
IDLE
IDLE
IDLE
IDLE
Figure 105. SPORT over JESD204B Signal Monitor Example with Period = 80 Samples
Rev. 0 | Page 66 of 136
15547-100
PAYLOAD
25-BIT FRAME (N + 2)
Data Sheet
AD9208
DIGITAL OUTPUTS
INTRODUCTION TO THE JESD204B INTERFACE
The AD9208 digital outputs are designed to the JEDEC standard
JESD204B, serial interface for data converters. JESD204B is a
protocol to link the AD9208 to a digital processing device over a
serial interface with lane rates of up to 16 Gbps. The benefits of
the JESD204B interface over LVDS include a reduction in
required board area for data interface routing and an ability to
enable smaller packages for converter and logic devices.
JESD204B OVERVIEW
The JESD204B data transmit block assembles the parallel data
from the ADC into frames and uses 8-bit/10-bit encoding as
well as optional scrambling to form serial output data. Lane
synchronization is supported through the use of separate
control characters during the initial establishment of the link.
Additional control characters are embedded in the data stream
to maintain synchronization thereafter. A JESD204B receiver is
required to complete the serial link. For additional details on
the JESD204B interface, refer to the JESD204B standard.
The AD9208 JESD204B data transmit block maps up to two
physical ADCs or up to eight virtual converters (when DDCs are
enabled) over a link. A link can be configured to use one, two,
four, or eight JESD204B lanes. The JESD204B specification refers
to a number of parameters to define the link, and these parameters
must match between the JESD204B transmitter (the AD9208
output) and the JESD204B receiver (the logic device input).
The JESD204B link is described according to the following
parameters:
L is the number of lanes per converter device (lanes per
link); AD9208 value = 1, 2, 4, or 8.
M is the number of converters per converter device (virtual
converters per link); AD9208 value = 1, 2, 4, or 8.
F is the octets per frame; AD9208 value = 1, 2, 4, 8, or 16.
N΄ is the number of bits per sample (JESD204B word size);
AD9208 value = 8 or 16.
N is the converter resolution; AD9208 value = 7 to 16.
CS is the number of control bits per sample;
AD9208 value = 0, 1, 2, or 3.
Figure 106 shows a simplified block diagram of the AD9208
JESD204B link. By default, the AD9208 is configured to use
two converters and four lanes. Converter A data is output to
SERDOUT0± and/or SERDOUT1±, and Converter B is output
to SERDOUT2± and/or SERDOUT3±. The AD9208 allows
other configurations such as combining the outputs of both
converters onto a single lane, or changing the mapping of the
A and B digital output paths. These modes are set up via a quick
configuration register in the SPI register map, along with
additional customizable options.
By default in the AD9208, the 14-bit converter word from each
converter is broken into two octets (eight bits of data). Bit 13
(MSB) through Bit 6 are in the first octet. The second octet
contains Bit 5 through Bit 0 (LSB) and two tail bits. The tail bits
can be configured as zeros or as a pseudorandom number
sequence. The tail bits can also be replaced with control bits
indicating overrange, SYSREF±, or fast detect output.
The two resulting octets can be scrambled. Scrambling is
optional; however, it is recommended to avoid spectral peaks
when transmitting similar digital data patterns. The scrambler
uses a self synchronizing, polynomial-based algorithm defined
by the equation 1 + x14 + x15. The descrambler in the receiver is
a self synchronizing version of the scrambler polynomial.
The two octets are then encoded with an 8-bit/10-bit encoder. The
8-bit/10-bit encoder works by taking eight bits of data (an octet)
and encoding them into a 10-bit symbol. Figure 107 shows how
the 14-bit data is taken from the ADC, how the tail bits are added,
how the two octets are scrambled, and how the octets are encoded
into two 10-bit symbols. Figure 107 shows the default data format.
CONVERTER 0
CONVERTER A
INPUT
ADC A
SERDOUT0±
MUX/
FORMAT
(SPI
REGISTERS
0x0561,
0x0564)
CONVERTER B
INPUT
JESD204B LINK
CONTROL
(L, M, F)
(SPI REGISTER
0x058B,
0x058E, 0x058C)
ADC B
CONVERTER 1
LANE MUX
AND
MAPPING
(SPI
REGISTERS
0x05B0,
0x05B2,
0x05B3,
0x05B5,
0x05B6)
SERDOUT1±
SERDOUT2±
SERDOUT3±
SERDOUT4±
SERDOUT5±
SERDOUT6±
SERDOUT7±
15547-101
K is the number of frames per multiframe;
AD9208 value = 4, 8, 12, 16, 20, 24, 28, or 32.
S is the samples transmitted per single converter per frame
cycle; AD9208 value is set automatically based on L, M, F,
and N΄.
HD is the high density mode; the AD9208 mode is set
automatically based on L, M, F, and N΄.
CF is the number of control words per frame clock cycle
per converter device; AD9208 value = 0.
SYSREF±
SYNCINB±
Figure 106. Transmit Link Simplified Block Diagram Showing Full Bandwidth Mode (Register 0x0200 = 0x00)
Rev. 0 | Page 67 of 136
AD9208
Data Sheet
JESD204B DATA
LINK LAYER TEST
PATTERNS
0x0574[2:0]
JESD204B
INTERFACE TEST
PATTERN
(0x0573,
0x0551 TO 0x0558)
MSB A13
A12
A11
A10
A9
A8
ADC
A7
A6
A5
A4
A3
A2
A1
LSB A0
OCTET1
TAIL BITS
0x0571[6]
OCTET0
JESD204B SAMPLE
CONSTRUCTION
MSB A13
A12
A11
A10
A9
A8
A7
LSB A6
A5
A4
A3
A2
A1
A0
C2
T
SCRAMBLER
1 + x14 + x15
(OPTIONAL)
MSB S7
S6
S5
S4
S3
S2
S1
LSB S0
S7
S6
S5
S4
S3
S2
S1
S0
8-BIT/
10-BIT
ENCODER
SERIALIZER
a b
i j a b
SERDOUT0±
SERDOUT1±
SERDOUT2±
SERDOUT3±
i j
SYMBOL0 SYMBOL1
a b c d e f g h i j
a b c d e f g h i j
C2
C1
C0
15547-102
CONTROL BITS
FRAME
CONSTRUCTION
OCTET1
ADC TEST PATTERNS
(0x0550,
0x0551 TO 0x0558)
OCTET0
JESD204B LONG
TRANSPORT TEST
PATTERN
0x0571[5]
Figure 107. ADC Output Datapath Showing Data Framing
TRANSPORT
LAYER
SAMPLE
CONSTRUCTION
FRAME
CONSTRUCTION
SCRAMBLER
ALIGNMENT
CHARACTER
GENERATION
8-BIT/10-BIT
ENCODER
PHYSICAL
LAYER
CROSSBAR
MUX
SERIALIZER
Tx
OUTPUT
15547-103
PROCESSED
SAMPLES
FROM ADC
DATA LINK
LAYER
SYSREF±
SYNCINB±
Figure 108. Data Flow
FUNCTIONAL OVERVIEW
Physical Layer
The block diagram in Figure 108 shows the flow of data through
the JESD204B hardware from the sample input to the physical
output. The processing can be divided into layers that are
derived from the open source initiative (OSI) model widely
used to describe the abstraction layers of communications
systems. These layers are the transport layer, data link layer,
and physical layer (serializer and output driver).
The physical layer consists of the high speed circuitry clocked at
the serial clock rate. In this layer, parallel data is converted into
one, two, or four lanes of high speed differential serial data.
Transport Layer
The transport layer handles packing the data (consisting of
samples and optional control bits) into JESD204B frames that
are mapped to 8-bit octets. These octets are sent to the data link
layer. The transport layer mapping is controlled by rules derived
from the link parameters. Tail bits are added to fill gaps where
required. The following equation can be used to determine the
number of tail bits within a sample (JESD204B word):
T = N΄ – N – CS
Data Link Layer
The data link layer is responsible for the low level functions
of passing data across the link. These functions include optionally
scrambling the data, inserting control characters for multichip
synchronization/lane alignment/monitoring, and encoding
8-bit octets into 10-bit symbols. The data link layer is also
responsible for sending the initial lane alignment sequence
(ILAS), which contains the link configuration data used by the
receiver to verify the settings in the transport layer.
JESD204B LINK ESTABLISHMENT
The AD9208 JESD204B transmitter (Tx) interface operates in
Subclass 1 as defined in the JEDEC Standard 204B (July 2011
specification). The link establishment process is divided into the
following steps: code group synchronization and SYNCINB±,
initial lane alignment sequence, and user data and error correction.
Code Group Synchronization (CGS) and SYNCINB±
The CGS is the process by which the JESD204B receiver finds
the boundaries between the 10-bit symbols in the stream of
data. During the CGS phase, the JESD204B transmit block
transmits /K28.5/ characters. The receiver must locate /K28.5/
characters in its input data stream using clock and data recovery
(CDR) techniques.
The receiver issues a synchronization request by asserting the
SYNCINB± pin of the AD9208 low. The JESD204B Tx then begins
sending /K/ characters. After the receiver synchronizes, it waits for
the correct reception of at least four consecutive /K/ symbols. It
then deasserts SYNCINB±. The AD9208 then transmits an ILAS
on the following LMFC boundary.
For more information on the code group synchronization
phase, refer to the JEDEC Standard JESD204B, July 2011,
Section 5.3.3.1.
Rev. 0 | Page 68 of 136
Data Sheet
AD9208
User Data and Error Detection
The SYNCINB± pin operation can also be controlled by the
SPI. The SYNCINB± signal is a differential dc-coupled LVDS
mode signal by default, but it can also be driven single-ended.
For more information on configuring the SYNCINB± pin
operation, refer to Register 0x0572.
After the initial lane alignment sequence is complete, the user
data is sent. Normally, within a frame, all characters are considered
user data. However, to monitor the frame clock and multiframe
clock synchronization, there is a mechanism for replacing
characters with /F/ or /A/ alignment characters when the data
meets certain conditions. These conditions are different for
unscrambled and scrambled data. The scrambling operation is
enabled by default; however, it can be disabled using the SPI.
The SYNCINB± pins can also be configured to run in CMOS
(single-ended) mode, by setting Bit 4 in Register 0x0572. When
running SYNCINB± in CMOS mode, connect the CMOS
SYNCINB signal to Pin N13 (SYNCINB+) and leave Pin R13
(SYNCINB−) floating.
For scrambled data, any 0xFC character at the end of a frame
is replaced by an /F/, and any 0x7C character at the end of a
multiframe is replaced by an /A/. The JESD204B receiver (Rx)
checks for /F/ and /A/ characters in the received data stream
and verifies that they only occur in the expected locations. If an
unexpected /F/ or /A/ character is found, the receiver handles
the situation by using dynamic realignment or asserting the
SYNCINB± signal for more than four frames to initiate a
resynchronization. For unscrambled data, if the final character
of two subsequent frames is equal, the second character is
replaced with an /F/ if it is at the end of a frame, and an /A/ if
it is at the end of a multiframe.
Initial Lane Alignment Sequence (ILAS)
The ILAS phase follows the CGS phase and begins on the next
LMFC boundary. The ILAS consists of four multiframes, with
an /R/ character marking the beginning and an /A/ character
marking the end. The ILAS begins by sending an /R/ character
followed by 0 to 255 ramp data for one multiframe. On the
second multiframe, the link configuration data is sent, starting
with the third character. The second character is a /Q/ character
to confirm that the link configuration data is to follow. All
undefined data slots are filled with ramp data. The ILAS
sequence is never scrambled.
Insertion of alignment characters can be modified using the
SPI. The frame alignment character insertion (FACI) is enabled
by default. More information on the link controls is available in
the Memory Map section, Register 0x0571.
The ILAS sequence construction is shown in Figure 109. The
four multiframes include the following:
Multiframe 1 begins with an /R/ character (/K28.0/) and
ends with an /A/ character (/K28.3/).
Multiframe 2 begins with an /R/ character followed by a
/Q/ character (/K28.4/), followed by link configuration
parameters over 14 configuration octets (see Table 30) and
ends with an /A/ character. Many of the parameter values
are of the value − 1 notation.
Multiframe 3 begins with an /R/ character (/K28.0/) and
ends with an /A/ character (/K28.3/).
Multiframe 4 begins with an /R/ character (/K28.0/) and
ends with an /A/ character (/K28.3/).
K
K
R
D
●●●
D
A
R
Q
C
●●●
C
D
●●●
8-Bit/10-Bit Encoder
The 8-bit/10-bit encoder converts 8-bit octets into 10-bit symbols
and inserts control characters into the stream when needed.
The control characters used in JESD204B are shown in Table 30.
The 8-bit/10-bit encoding ensures that the signal is dc balanced by
using the same number of ones and zeros across multiple symbols.
The 8-bit/10-bit interface has options that can be controlled via the
SPI. These operations include bypass and invert. These options are
troubleshooting tools for the verification of the digital front end
(DFE). See the Memory Map section, Register 0x0572, Bits[2:1]
for information on configuring the 8-bit/10-bit encoder.
D
A
R
D
●●●
D
A
R
D
●●●
D
A
D
END OF
MULTIFRAME
START OF
ILAS
●●●
●●●
●●●
START OF LINK
CONFIGURATION DATA
●●●
START OF
USER DATA
Figure 109. Initial Lane Alignment Sequence
Table 30. AD9208 Control Characters used in JESD204B
Abbreviation
/R/
/A/
/Q/
/K/
/F/
1
Control Symbol
/K28.0/
/K28.3/
/K28.4/
/K28.5/
/K28.7/
8-Bit Value
000 11100
011 11100
100 11100
101 11100
111 11100
10-Bit Value,
RD1 = −1
001111 0100
001111 0011
001111 0100
001111 1010
001111 1000
RD means running disparity.
Rev. 0 | Page 69 of 136
10-Bit Value,
RD1 = +1
110000 1011
110000 1100
110000 1101
110000 0101
110000 0111
Description
Start of multiframe
Lane alignment
Start of link configuration data
Group synchronization
Frame alignment
15547-104
●●●
AD9208
Data Sheet
DRVDD
0.1µF
SERDOUTx+
100Ω
DIFFERENTIAL
TRACE PAIR
RECEIVER
100Ω
0.1µF
SERDOUTx–
15547-105
OUTPUT SWING = 0.85 × DRVDD1 V p-p DIFFERENTIAL
ADJUSTABLE TO
1 × DRVDD1, 0.75 × DRVDD1
Figure 110. AC-Coupled Digital Output Termination Example
16 Gbps
PHYSICAL LAYER (DRIVER) OUTPUTS
Digital Outputs, Timing, and Controls
Place a 100 Ω differential termination resistor at each receiver
input to result in a nominal 0.85 × DRVDD1 V p-p swing at the
receiver (see Figure 110). The swing is adjustable through the
SPI registers. AC coupling is recommended to connect to the
receiver. See the Memory Map section (Register 0x05C0 to
Register 0x05C3 in Table 46) for more details.
The AD9208 digital outputs can interface with custom ASICs
and field programmable gate array (FPGA) receivers, providing
superior switching performance in noisy environments. Single
point-to-point network topologies are recommended with a
single differential 100 Ω termination resistor placed as close to
the receiver inputs as possible.
If there is no far end receiver termination, or if there is poor
differential trace routing, timing errors can result. To avoid such
timing errors, it is recommended that the trace length be less
than six inches, and that the differential output traces be close
together and at equal lengths.
Figure 111 to Figure 113 show an example of the digital output
data eye, jitter histogram, and bathtub curve for one AD9208
lane running at 16 Gbps. The format of the output data is twos
complement by default. To change the output data format, see
the Memory Map section (Register 0x0561 in Table 46).
15547-108
The AD9208 physical layer consists of drivers that are defined in
the JEDEC Standard JESD204B, July 2011. The differential digital
outputs are powered up by default. The drivers use a dynamic
100 Ω internal termination to reduce unwanted reflections.
Figure 113. Digital Outputs Bathtub Curve, External 100 Ω Terminations at
16 Gbps
De-Emphasis
De-emphasis enables the receiver eye diagram mask to be met
in conditions where the interconnect insertion loss does not
meet the JESD204B specification. Use the de-emphasis feature
only when the receiver is unable to recover the clock due to
excessive insertion loss. Under normal conditions, it is disabled
to conserve power. Additionally, enabling and setting too high a
de-emphasis value on a short link can cause the receiver eye
diagram to fail. Use the de-emphasis setting with caution
because it can increase electromagnetic interference (EMI). See
the Memory Map section (Register 0x05C4 to Register 0x05CB
in Table 46) for more details.
Phase-Locked Loop (PLL)
The PLL generates the serializer clock, which operates at the
JESD204B lane rate. The status of the PLL lock can be checked
in the PLL locked status bit (Register 0x056F, Bit 7). This read
only bit notifies the user if the PLL achieved a lock for the
specific setup. Register 0x056F also has a loss of lock (LOL)
sticky bit (Bit 3) that notifies the user that a loss of lock is
detected. The sticky bit can be reset by issuing a JESD204B link
restart (Register 0x0571 = 0x15, followed by Register 0x0571 =
0x14). Refer to Table 32 for the reinitialization of the link
following a link power cycle.
15547-106
The JESD204B lane rate control, Bits[7:4] of Register 0x056E,
must be set to correspond with the lane rate. Table 31 shows the
lane rates supported by the AD9208 using Register 0x056E.
Figure 111. Digital Outputs Data Eye, External 100 Ω Terminations at 16 Gbps
15547-107
Table 31. AD9208 Register 0x056E Supported Lane Rates
Value
0x00
0x10
0x30
0x50
Figure 112. Digital Outputs Jitter Histogram, External 100 Ω Terminations at
Rev. 0 | Page 70 of 136
Lane Rate
Lane rate = 6.75 Gbps to 13.5 Gbps
Lane rate = 3.375 Gbps to 6.75 Gbps
Lane rate = 13.5 Gbps to 15.5 Gbps (default for AD9208)
Lane rate = 1.6875 Gbps to 3.375 Gbps
Data Sheet
AD9208
fS × 4 MODE
fS × 4 mode adds a separate packing mode on top of a JESD204B
transmitter/receiver to fix the serial lane rate at four times the
sample rate (fS).
The JESD204B link settings are
In fS × 4 mode, five 12-bit ADC samples (along with an extra
4 bits) are packed into four 16-bit JESD204B samples to create a
64-bit frame.
L=8
M=2
F=2
S=5
N’ = 12
N = 12
CS = 0
CF = 2
HD = 1
The following SPI writes are necessary to place the device in fS × 4
mode:
However, CF = 2 is not supported by the design; therefore, the
following link parameters are used along with separate packing:
The transmit architecture of fS × 4 mode is shown in Figure 114
and the receive portion is shown in Figure 115. fS × 4 mode only
works in full bandwidth mode (Register 0x0200 = 0x00).
L=8
M=2
F=2
S=4
fS × 4 MODE (TRANSMIT)
12-BITS
AT fS
64-BITS
AT fS/5
64-BITS
AT fS/5
ADC0
ADC1
ADC0 SAMPLE N (12 BITS)
ADC1 SAMPLE N (12 BITS)
1/5 RATE EXCHANGE
ADC0
SAMPLE N (12 BITS)
ADC0
SAMPLE N + 1 (12 BITS)
S[N][11:0], S[N + 1][11:8]
(16 BITS)
CONVERTER 0
SAMPLE N (16 BITS)
ADC0
SAMPLE N + 2 (12 BITS)
S[N + 1][7:0], S[N + 2][11:4]
(16 BITS)
CONVERTER 0
SAMPLE N + 1 (16 BITS)
S[N][15:0]
ADC0
SAMPLE N + 4 (12 BITS)
S[N + 2][3:0], S[N + 3][11:0]
(16 BITS)
CONVERTER 0
SAMPLE N + 2 (16 BITS)
S[N + 1][15:0]
1/5 RATE EXCHANGE
0000
ADC0
SAMPLE N + 3 (12 BITS)
(4 BITS)
S[N + 4][11:0], 0000
(16 BITS)
CONVERTER 0
SAMPLE N + 3 (16 BITS)
S[N + 2][15:0]
ADC1
SAMPLE N (12 BITS)
ADC1
SAMPLE N + 1 (12 BITS)
S[N][11:0], S[N + 1][11:8]
(16 BITS)
CONVERTER 1
SAMPLE N (16 BITS)
S[N + 3][15:0]
ADC1
SAMPLE N + 2 (12 BITS)
S[N + 1][7:0], S[N + 2][11:4]
(16 BITS)
CONVERTER 1
SAMPLE N+1 (16 BITS)
S[N][15:0]
0000
ADC1
SAMPLE N + 3 (12 BITS)
ADC1
SAMPLE N + 4 (12 BITS)
S[N + 2][3:0], S[N + 3][11:0]
(16 BITS)
CONVERTER 1
SAMPLE N+2 (16 BITS)
S[N + 1][15:0]
APPLICATION
LAYER
(4 BITS)
S[N + 4][11:0], 0000
(16 BITS)
CONVERTER 1
SAMPLE N+3 (16 BITS)
S[N + 2][15:0]
S[N + 3][15:0]
TRANSPORT,
DATA LINK,
AND PHY
LAYERS
JESD204B FRAMER + PHY
(M = 2; L = 8; S = 4; F = 2; N = 16; N’ = 16; CF = 0; HD = 0)
15547-109
Register 0x0570 = 0xFE. This setting places the device in M =
2, L = 8, fS × 4 mode.
Register 0x058B = 0x0F. This setting places the device CS =
0, N’ = 16 mode.
Register 0x058F = 0x2F. This setting places the device in
Subclass 1 mode, N = 16.
LANE 0 LANE 1 LANE 2 LANE 3 LANE 4 LANE 5 LANE 6 LANE 7
Figure 114. fS × 4 Mode (Transmit)
fS × 4 MODE (RECEIVE)
LANE 0 LANE 1 LANE 2 LANE 3 LANE 4 LANE 5 LANE 6 LANE 7
DATA LINK,
TRANSPORT,
AND PHY
LAYERS
JESD204B FRAMER + PHY
(M = 2; L = 8; S = 4; F = 2; N = 16; N’ = 16; CF = 0; HD = 0)
S[N][15:0]
64-BITS
AT fS/5
64-BITS
AT fS/5
CONVERTER 0
SAMPLE N (16 BITS)
S[N + 1][15:0]
CONVERTER 0
SAMPLE N + 1 (16 BITS)
S[N][11:0], S[N + 1][11:8]
(16 BITS)
ADC0
SAMPLE N (12 BITS)
ADC0
SAMPLE N + 1 (12 BITS)
S[N + 2][15:0]
CONVERTER 0
SAMPLE N + 2 (16 BITS)
S[N + 1][7:0], S[N + 2][11:4]
(16 BITS)
ADC0
SAMPLE N + 2 (12 BITS)
S[N + 3][15:0]
CONVERTER 0
SAMPLE N + 3 (16 BITS)
S[N + 2][3:0], S[N + 3][11:0]
(16 BITS)
ADC0
SAMPLE N + 3 (12 BITS)
S[N][15:0]
CONVERTER 1
SAMPLE N (16 BITS)
(4 BITS)
CONVERTER 1
SAMPLE N + 1 (16 BITS)
S[N][11:0], S[N + 1][11:8]
(16 BITS)
S[N + 4][11:0], 0000
(16 BITS)
ADC0
SAMPLE N + 4 (12 BITS)
S[N + 1][15:0]
ADC1
SAMPLE N (12 BITS)
ADC1
SAMPLE N + 1 (12 BITS)
0000
USER APPLICATION
Figure 115. fS × 4 Mode (Receive)
Rev. 0 | Page 71 of 136
S[N + 2][15:0]
CONVERTER 1
SAMPLE N + 2 (16 BITS)
S[N + 1][7:0], S[N + 2][11:4]
(16 BITS)
ADC1
SAMPLE N + 2 (12 BITS)
S[N + 3][15:0]
CONVERTER 1
SAMPLE N + 3 (16 BITS)
S[N + 2][3:0], S[N + 3][11:0]
(16 BITS)
ADC1
SAMPLE N + 3 (12 BITS)
S[N + 4][11:0], 0000
(16 BITS)
ADC1
SAMPLE N + 4 (12 BITS)
APPLICATION
LAYER
(4 BITS)
0000
15547-110
N’ = 16
N = 16
CS = 0
CF = 0
HD = 0
AD9208
Data Sheet
SETTING UP THE AD9208 DIGITAL INTERFACE
To ensure proper operation of the AD9208 at startup, some SPI
writes are required to initialize the link. Additionally, these
registers must be written every time the ADC is reset. Any one
of the following resets warrants the initialization routine for the
digital interface:
Hard reset, as with power-up.
Power-up using the PDWN pin.
Power-up using the SPI via Register 0x0002, Bits[1:0].
SPI soft reset by setting Register 0x0000 = 0x81.
Datapath soft reset by setting Register 0x0001 = 0x02.
JESD204B link power cycle by setting Register 0x0571 =
0x15, then 0x14.
If the internal DDCs are used for on-chip digital processing, M
represents the number of virtual converters. The virtual converter
mapping setup is shown in Figure 77.
The maximum lane rate allowed by the AD9208 is 16 Gbps. The
lane rate is related to the JESD204B parameters using the
following equation:
10
M N ' f OUT
8
Lane Rate =
L
where fOUT =
f ADC _ CLOCK
Decimation Ratio
The decimation ratio (DCM) is the parameter programmed in
Register 0x201.
The initialization SPI writes are as shown in Table 32.
Use the following procedure to configure the output:
Table 32. AD9208 JESD204B Initialization
1.
2.
3.
4.
5.
6.
7.
Register
0x1228
0x1228
0x1222
0x1222
0x1222
0x1262
0x1262
Value
0x4F
0x0F
0x00
0x04
0x00
0x08
0x00
Comment
Reset JESD204B start-up circuit
JESD204B start-up circuit in normal operation
JESD204B PLL force normal operation
Reset JESD204B PLL calibration
JESD204B PLL normal operation
Clear loss of lock bit
Loss of lock bit normal operation
The AD9208 has one JESD204B link. The serial outputs
(SERDOUT0± to SERDOUT7±) are considered to be part of
one JESD204B link. The basic parameters that determine the
link setup are
Number of lanes per link (L)
Number of converters per link (M)
Number of octets per frame (F)
Power down the link.
Select the JESD204B link configuration options.
Configure the detailed options.
Set output lane mapping (optional).
Set additional driver configuration options (optional).
Power up the link.
Initialize the JESD204B link by issuing the commands
described in Table 32.
If the lane rate calculated is less than 6.25 Gbps, select the low
lane rate option by programming a value of 0x10 to
Register 0x056E.
Table 33 and Table 34 show the JESD204B output configurations
supported for both N΄ = 16 and N΄ = 8 for a given number of
virtual converters. Take care to ensure that the serial lane rate
for a given configuration is within the supported range of
3.4 Gbps to 16 Gbps.
Table 33. JESD204B Output Configurations for N΄ = 161
Number of
Virtual
Converters
Supported
(Same as M)
1
Supported Decimation Rates
JESD204B
Serial
Lane
Rate2
20 × fOUT
5 × fOUT
Lane Rate =
1.7 Gbps to
3.4 Gbps
2, 4, 5, 6, 8, 10, 12,
20, 24
2, 4, 5, 6, 8, 10, 12,
20, 24
1, 2, 3, 4, 5, 6, 8,
10, 12
1, 2, 3, 4, 5, 6, 8,
10, 12
1, 2, 3, 4, 5, 6, 8
5 × fOUT
JESD204B Transport Layer Settings3
Lane Rate =
3.4 Gbps to
6.8 Gbps
1, 2, 3, 4, 5, 6, 8,
10, 12
1, 2, 3, 4, 5, 6, 8,
10, 12
1, 2, 3, 4, 5, 6, 8
Lane Rate =
6.8 Gbps to
13.6 Gbps
1, 2, 3, 4, 5, 6, 8
Lane Rate =
13.6 Gbps to
15.5 Gbps
1, 2, 3, 4
L
1
M
1
F
2
S
1
HD N
N'
0
8 to 16 16
1, 2, 3, 4, 5, 6, 8
1, 2, 3, 4
1
1
4
2
0
8 to 16 16
1, 2, 3, 4
1, 2
2
1
1
1
1
8 to 16 16
1, 2, 3, 4, 5, 6, 8
1, 2, 3, 4
1, 2
2
1
2
2
0
8 to 16 16
1, 2, 3, 4
1, 2
1
4
1
1
2
1
8 to 16 16
1, 2, 3, 4, 5, 6, 8
1, 2, 3, 4
1, 2
1
4
1
2
4
0
8 to 16 16
2.5 × fOUT
1, 2, 3, 4
1, 2
1
8
1
1
4
1
8 to 16 16
2.5 × fOUT
1, 2, 3, 4
1, 2
1
8
1
2
8
0
8 to 16 16
20 × fOUT
10 × fOUT
10 × fOUT
Rev. 0 | Page 72 of 136
CS
0 to
3
0 to
3
0 to
3
0 to
3
0 to
3
0 to
3
0 to
3
0 to
3
K
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
Data Sheet
Number of
Virtual
Converters
Supported
(Same as M)
2
Supported Decimation Rates
JESD204B
Serial
Lane
Rate2
40 × fOUT
JESD204B Transport Layer Settings3
Lane Rate =
3.4 Gbps to
6.8 Gbps
2, 4, 5, 6, 8, 10,
12, 15, 16, 20,
24, 30
2, 4, 5, 6, 8, 10,
12, 15, 16, 20,
24, 30
1, 2, 3, 4, 5, 6, 8,
10, 12, 15, 16
1, 2, 3, 4, 5, 6, 8,
10, 12, 15, 16
1, 2, 3, 4, 5, 6, 8
Lane Rate =
6.8 Gbps to
13.6 Gbps
1, 2, 3, 4, 5, 6, 8,
10, 12, 15, 16
Lane Rate =
13.6 Gbps to
15.5 Gbps
1, 2, 3, 4, 5, 6, 8
L
1
M
2
F
4
S
1
HD N
N'
0
8 to 16 16
CS K
0 to See
3
Note 4
1, 2, 3, 4, 5, 6, 8,
10, 12, 15, 16
1, 2, 3, 4, 5, 6, 8
1
2
8
2
0
8 to 16 16
0 to See
3
Note 4
1, 2, 3, 4, 5, 6, 8
1, 2, 3, 4
2
2
2
1
0
8 to 16 16
1, 2, 3, 4, 5, 6, 8
1, 2, 3, 4
2
2
4
2
0
8 to 16 16
1, 2, 3, 4
1, 2
4
2
1
1
1
8 to 16 16
1, 2, 3, 4, 5, 6, 8
1, 2, 3, 4
1, 2
4
2
2
2
0
8 to 16 16
1, 2, 3, 4
1, 2
1
8
2
1
2
1
8 to 16 16
0 to
3
0 to
3
0 to
3
0 to
3
0 to
3
0 to
3
0 to
3
4, 8, 10, 12, 15, 16,
20, 24, 30, 40, 48
20 × fOUT
5 × fOUT
2, 4, 5, 6, 8, 10, 12,
15, 16, 20, 24, 30
2, 4, 5, 6, 8, 10, 12,
15, 16, 20, 24, 30
1, 2, 3, 4, 5, 6, 8,
10, 12, 15, 16
1, 2, 3, 4, 5, 6, 8,
10, 12, 15, 16
1, 2, 3, 4, 5, 6, 8
5 × fOUT
1, 2, 3, 4, 5, 6, 8
1, 2, 3, 4
1, 2
1
8
2
2
4
0
8 to 16 16
80 × fOUT
8, 16, 20, 24, 30,
40, 48
2, 4, 6, 8, 10, 12,
16, 20, 24, 30
2, 4, 6, 8, 10, 12, 1
16
4
8
1
0
8 to 16 16
40 × fOUT
4, 8, 10, 12, 15, 16,
20, 24, 30, 40, 48
1, 2, 3, 4, 5, 6, 8,
10, 12, 15, 16
1, 2, 3, 4, 5, 6, 8
2
4
4
1
0
8 to 16 16
0 to See
3
Note 4
40 × fOUT
4, 8, 10, 12, 15, 16,
20, 24, 30, 40, 48
1, 2, 3, 4, 5, 6, 8,
10, 12, 15, 16
1, 2, 3, 4, 5, 6, 8
2
4
8
2
0
8 to 16 16
0 to See
3
Note 4
20 × fOUT
1, 2, 3, 4, 5, 6, 8
1, 2, 3, 4
4
4
2
1
0
8 to 16 16
1, 2, 3, 4, 5, 6, 8
1, 2, 3, 4
4
4
4
2
0
8 to 16 16
1, 2, 3, 4
1, 2
8
4
1
1
1
8 to 16 16
1, 2, 3, 4, 5, 6, 8
1, 2, 3, 4
1, 2
8
4
2
2
0
8 to 16 16
160 × fOUT
2, 4, 5, 6, 8, 10, 12,
15, 16, 20, 24, 30
2, 4, 5, 6, 8, 10, 12,
15, 16, 20, 24, 30
1, 2, 3, 4, 5, 6, 8,
10, 12, 15, 16
1, 2, 3, 4, 5, 6, 8,
10, 12, 15, 16
16, 40, 48
4, 8, 10, 12, 16,
20, 24, 30, 40,
48
2, 4, 5, 6, 8, 10,
12, 15, 16, 20,
24, 30
2, 4, 5, 6, 8, 10,
12, 15, 16, 20,
24, 30
1, 2, 3, 4, 5, 6, 8,
10, 12, 15, 16
1, 2, 3, 4, 5, 6, 8,
10, 12, 15, 16
1, 2, 3, 4, 5, 6, 8
1
0
8 to 16 16
8
8
1
0
8 to 16 16
40 × fOUT
4, 8, 10, 12, 16, 20,
24, 40, 48
4, 8, 10, 12, 16, 20,
24, 40, 48
2, 4, 6, 8, 10, 12,
16, 20, 24
2, 4, 6, 8, 10, 12,
16, 20, 24
4, 8, 12, 16, 20, 1
24
2, 4, 6, 8, 10, 12, 2
16
2, 4, 6, 8
4
16
8, 16, 20, 24, 40, 48
4, 8, 12, 16, 20,
24, 40, 48
2, 4, 6, 8, 10, 12,
16, 20, 24
2, 4, 6, 8, 10, 12,
16
2, 4, 6, 8, 10, 12,
16
2, 4, 6, 8
8
80 × fOUT
8, 16, 20, 24, 40,
48
4, 8, 10, 12, 16,
20, 24, 40, 48
2, 4, 6, 8, 10, 12,
16, 20, 24
2, 4, 6, 8, 10, 12,
16, 20, 24
2, 4, 6, 8, 10, 12,
16
2, 4, 6, 8, 10, 12,
16
8
4
1
0
8 to 16 16
2, 4, 6, 8
4
8
8
2
0
8 to 16 16
2, 4
8
8
2
1
0
8 to 16 16
2, 4, 6, 8
2, 4
8
8
4
2
0
8 to 16 16
0 to
3
0 to
3
0 to
3
0 to
3
0 to
3
0 to
3
0 to
3
0 to
3
0 to
3
0 to
3
10 × fOUT
10 × fOUT
20 × fOUT
10 × fOUT
10 × fOUT
8
Lane Rate =
1.7 Gbps to
3.4 Gbps
4, 8, 10, 12, 15, 16,
20, 24, 30, 40, 48
40 × fOUT
20 × fOUT
4
AD9208
40 × fOUT
20 × fOUT
20 × fOUT
1
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
Due to the internal clock requirements, only certain decimation rates are supported for certain link parameters.
JESD204B transport layer descriptions are as follows: L is the number of lanes per converter device (lanes per link); M is the number of virtual converters per converter
device (virtual converters per link); F is the octets per frame; S is the samples transmitted per virtual converter per frame cycle; HD is the high density mode; N is the virtual
converter resolution (in bits); N' is the total number of bits per sample (JESD204B word size); CS is the number of control bits per conversion sample; K is the number of frames per
multiframe.
3
fADC_CLK is the ADC sample rate; DCM = chip decimation ratio; fOUT is the output sample rate = fADC_CLK/DCM; SLR is the JESD204B serial lane rate. The following equations must be
met due to internal clock divider requirements: SLR ≥ 1.6875 Gbps and SLR ≤ 15.5 Gbps; SLR/40 ≤ fADC_CLK; least common multiple (20 × DCM × fOUT/SLR, DCM) ≤ 64. When the SLR
is ≤ 15500 Mbps and > 13500 Mbps, Register 0x056E must be set to 0x30. When the SLR is ≤ 13500 Mbps and ≥ 6750 Mbps, Register 0x056E must be set to 0x00. When the SLR is
< 6750 Mbps and ≥ 3375 Mbps, Register 0x056E must be set to 0x10. When the SLR is < 3375 Mbps and ≥ 1687.5 Mbps, Register 0x056E must be set to 0x50.
4
Only valid K × F values that are divisible by 4 are supported: for F = 1, K = 20, 24, 28, 32; for F = 2, K = 12, 16, 20, 24, 28, 32; for F = 4, K = 8, 12, 16, 20, 24, 28, 32; for F = 8, K = 4,
8, 12, 16, 20, 24, 28, 32; and for F = 16, K = 4, 8, 12, 16, 20, 24, 28, 32.
2
Rev. 0 | Page 73 of 136
AD9208
Data Sheet
Table 34. JESD204B Output Configurations (N' = 12)1
No. of
Virtual
Converters
Supported
(Same Value
as M)
1
2
4
8
Serial
Lane
Rate2
15 × fOUT
Supported
Decimation
Rates for
Lane Rate =
1.7 Gbps to
3.4 Gbps
3, 6, 12
Supported
Decimation
Rates for
Lane Rate =
3.4 Gbps to
6.8 Gbps
3, 6, 12
Supported
Decimation
Rates for
Lane Rate =
6.8 Gbps to
13.5 Gbps
3, 6
7.5 × fOUT
3, 6
3, 6
7.5 × fOUT
3, 6
5 × fOUT
Supported
Decimation
Rates for
Lane Rate =
13.5 Gbps
to 15.5 Gbps
JESD204B Transport Layer Settings3
L
1
M
1
F
3
S
2
HD
0
N
8 to 12
N'
12
L
0 to 3
3
2
1
3
4
1
8 to 12
12
0 to 3
3, 6
3
2
1
6
8
0
8 to 12
12
0 to 3
1, 2, 3, 4
1, 2
3
1
1
2
1
8 to 12
12
0 to 3
30 × fOUT
1, 2, 3, 4, 5, 6,
8
3, 6, 12, 24
3, 6, 12, 24
3, 6, 12
1
2
3
1
0
8 to 12
12
0 to 3
15 × fOUT
3, 6, 12
3, 6, 12
3, 6
2
2
3
2
0
8 to 12
12
0 to 3
10 × fOUT
1, 2, 3, 4, 5, 6,
8
3, 6
1, 2, 3, 4
3
2
1
1
1
8 to 12
12
0 to 3
7.5 × fOUT
1, 2, 3, 4, 5, 6,
8, 10, 12, 16
3, 6
3
4
2
3
4
0
8 to 12
12
0 to 3
60 × fOUT
6, 12, 24, 48
3, 6, 12, 24, 48
3, 6, 12, 24
1
4
6
1
0
8 to 12
12
0 to 3
30 × fOUT
3, 6, 12, 24
3, 6, 12, 24
3, 6, 12
2
4
3
1
0
8 to 12
12
0 to 3
20 × fOUT
1, 2, 3, 4, 5, 6,
8, 10, 12, 16
3, 6, 12
1, 2, 3, 4, 5,
6, 8
3, 6
3
4
2
1
1
8 to 12
12
0 to 3
15 × fOUT
2, 4, 5, 6, 8, 10,
12, 16, 20, 24
3, 6, 12
4
4
3
2
0
8 to 12
12
0 to 3
60 × fOUT
6, 12, 24, 48
6, 12, 24, 48
6, 12, 24
2
8
6
1
0
8 to 12
12
0 to 3
30 × fOUT
6, 12, 24
6, 12, 24
6, 12
4
8
3
1
0
8 to 12
12
0 to 3
1
1, 2
1, 2, 3, 4
1
K
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
Due to the internal clock requirements, only certain decimation rates are supported for certain link parameters.
fADC_CLK is the ADC sample rate; DCM is the chip decimation ratio; fOUT is the output sample rate = fADC_CLK/DCM; SLR is the JESD204B serial lane rate. The following equations
must be met due to internal clock divider requirements: SLR ≥ 1.6875 Gbps and SLR ≤ 15.5 Gbps; SLR/40 ≤ fADC_CLK; least common multiple (20 × DCM × fOUT/SLR, DCM) ≤ 64.
When the SLR is ≤ 15500 Mbps and > 13500 Mbps, Register 0x056E must be set to 0x30. When the SLR is ≤ 13500 Mbps and ≥ 6750 Mbps, Register 0x056E must be set
to 0x00. When the SLR is < 6750 Mbps and ≥ 3375 Mbps, Register 0x056E must be set to 0x10. When the SLR is < 3375 Mbps and ≥ 1687.5 Mbps, Register 0x056E must
be set to 0x50.
3
JESD204B transport layer descriptions are as follows: L is the number of lanes per converter device (lanes per link); M is the number of virtual converters per converter device
(virtual converters per link); F is the octets per frame; S is the samples transmitted per virtual converter per frame cycle; HD is the high density mode; N is the virtual converter
resolution (in bits); N' is the total number of bits per sample (JESD204B word size); CS is the number of control bits per conversion sample; K is the number of frames per
multiframe.
4
Only valid K × F values that are divisible by 4 are supported: for F = 1, K = 20, 24, 28, 32; for F = 2, K = 12, 16, 20, 24, 28, 32; for F = 4, K = 8, 12, 16, 20, 24, 28, 32; for F = 8, K = 4,
8, 12, 16, 20, 24, 28, 32; and for F = 16, K = 4, 8, 12, 16, 20, 24, 28, 32.
2
Rev. 0 | Page 74 of 136
Data Sheet
AD9208
Table 32. JESD204B Output Configurations for N΄ = 81
Supported
Decimation
Rates for
Lane Rate =
3.4 Gbps to
6.8 Gbps
1, 2, 3, 4, 5,
6, 8
1, 2, 3, 4, 5,
6, 8
1, 2, 3, 4
Supported
Decimation
Rates for
Lane Rate =
6.8 Gbps to
13.5 Gbps
1, 2, 3, 4
Supported
Decimation
Rates for
Lane Rate =
13.5 Gbps to
15.5 Gbps
1, 2
L
1
M
1
JESD204B Transport Layer Settings3
F
S
HD
N
N'
CS
1
1
0
7 to 8 8
0 to 1
1, 2, 3, 4
1, 2
1
1
2
2
0
7 to 8
8
0 to 1
1, 2
1
2
1
1
2
0
7 to 8
8
0 to 1
1, 2, 3, 4
1, 2
1
2
1
2
4
0
7 to 8
8
0 to 1
1, 2, 3, 4
1, 2
1
2
1
4
8
0
7 to 8
8
0 to 1
2.5 × fOUT
Supported
Decimation
Rates for
Lane Rate =
1.7 Gbps to
3.4 Gbps
1, 2, 3, 4, 5, 6,
8, 10, 12
1, 2, 3, 4, 5, 6,
8, 10, 12
1, 2, 3, 4, 5, 6,
8
1, 2, 3, 4, 5, 6,
8
1, 2, 3, 4, 5, 6,
8
1, 2, 3, 4
1, 2
1
4
1
1
4
0
7 to 8
8
0 to 1
1
2.5 × fOUT
1, 2, 3, 4
1, 2
1
4
1
2
8
0
7 to 8
8
0 to 1
2
20 × fOUT
1, 2, 3, 4
1
2
2
1
0
7 to 8
8
0 to 1
10 × fOUT
1, 2, 3, 4, 5,
6, 8, 10, 12,
15, 16
1, 2, 3, 4, 5,
6, 8
1, 2, 3, 4, 5,
6, 8
2
1, 2, 3, 4
1, 2
2
2
1
1
0
7 to 8
8
0 to 1
See
Note 4
2
10 × fOUT
1, 2, 3, 4, 5,
6, 8
1, 2, 3, 4
1, 2
2
2
2
2
0
7 to 8
8
0 to 1
See
Note 4
2
5 × fOUT
1, 2, 3, 4
1, 2
1
4
2
1
2
0
7 to 8
8
0 to 1
2
5 × fOUT
1, 2, 3, 4
1, 2
1
4
2
2
4
0
7 to 8
8
0 to 1
2
5 × fOUT
2, 4, 5, 6, 8, 10,
12, 15, 16, 20,
24, 30
1, 2, 3, 4, 5, 6,
8, 10, 12, 15,
16
1, 2, 3, 4, 5, 6,
8, 10, 12, 15,
16
1, 2, 3, 4, 5, 6,
8
1, 2, 3, 4, 5, 6,
8
1, 2, 3, 4, 5, 6,
8
1, 2, 3, 4
1, 2
1
4
2
4
8
0
7 to 8
8
0 to 1
See
Note 4
See
Note 4
See
Note 4
No. of
Virtual
Converters
Supported
(Same Value
as M)
1
Serial
Lane
Rate2
10 × fOUT
1
10 × fOUT
1
5 × fOUT
1
5 × fOUT
1
5 × fOUT
1
1
K
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
See
Note 4
Due to the internal clock requirements, only certain decimation rates are supported for certain link parameters.
fADC_CLK is the ADC sample rate; DCM is the chip decimation ratio; fOUT is the output sample rate = fADC_CLK/DCM; SLR is the JESD204B serial lane rate. The following equations
must be met due to internal clock divider requirements: SLR ≥ 1.6875 Gbps and SLR ≤ 15.5 Gbps; SLR/40 ≤ fADC_CLK; least common multiple (20 × DCM × fOUT/SLR, DCM) ≤ 64.
When the SLR is ≤ 15500 Mbps and > 13500 Mbps, Register 0x056E must be set to 0x30. When the SLR is ≤ 13500 Mbps and ≥ 6750 Mbps, Register 0x056E must be set
to 0x00. When the SLR is < 6750 Mbps and ≥ 3375 Mbps, Register 0x056E must be set to 0x10. When the SLR is < 3375 Mbps and ≥ 1687.5 Mbps, Register 0x056E must
be set to 0x50.
3
JESD204B transport layer descriptions are as follows: L is the number of lanes per converter device (lanes per link); M is the number of virtual converters per converter device
(virtual converters per link); F is the octets per frame; S is the samples transmitted per virtual converter per frame cycle; HD is the high density mode; N is the virtual converter
resolution (in bits); N' is the total number of bits per sample (JESD204B word size); CS is the number of control bits per conversion sample; K is the number of frames per
multiframe.
4
Only valid K × F values that are divisible by 4 are supported: for F = 1, K = 20, 24, 28, 32; for F = 2, K = 12, 16, 20, 24, 28, 32; for F = 4, K = 8, 12, 16, 20, 24, 28, 32; for F = 8, K = 4,
8, 12, 16, 20, 24, 28, 32; and for F = 16, K = 4, 8, 12, 16, 20, 24, 28, 32.
2
Rev. 0 | Page 75 of 136
AD9208
Data Sheet
Example 1—Full Bandwidth Mode
14745.6MSPS
2949.12MSPS
SYNC~
F=1
14-BIT
ADC
CORE
L0
M0
L1
L2
JESD204B
LINK
(L = 8,
M = 2,
F = 1,
S = 2,
N´ = 16,
N = 16,
CS = 0,
HD = 1)
VIN_B
REAL
L3
L4
L5
L6
M1
14-BIT
ADC
CORE
L7
I = REAL COMPONENT
Q = QUADRATURE COMPONENT
DCM = DECIMATION
C2R = COMPLEX TO REAL
MX = VIRTUAL CONVERTER X
LY = LANE Y
SZ = SAMPLE Z INSIDE A JESD204B FRAME
C = CONTROL BIT (OVERRANGE, AMONG OTHERS)
T = TAIL BIT
M0S0[15:8]
M0S0[7:0]
M0S1[15:8]
M0S1[7:0]
M1S0[15:8]
M1S0[7:0]
M1S1[15:8]
M1S1[7:0]
15547-111
VIN_A
REAL
Figure 116. Full Bandwidth Mode
The AD9208 is set up as shown in Figure 116, with the following
configurations:
The JESD204B supported output configurations are as follows
(see Table 33):
Two 14-bit converters at 2.94912 GSPS.
Full bandwidth application layer mode.
Decimation filters bypassed.
The JESD204B output configuration is as follows:
Two virtual converters required (see Table 33).
Output sample rate (fOUT) = 2949.12/1 = 2949.12 MSPS.
Rev. 0 | Page 76 of 136
N΄ = 16 bits.
N = 14 bits.
L = 8, M = 2, and F = 1, or L = 8, M = 2, and F = 2.
CS = 0.
K = 32.
Output serial lane rate = 14.7456 Gbps per lane.
The PLL control register, Register 0x056E, is set to 0x30.
Data Sheet
AD9208
Example 2—ADC with DDC Option (Two ADCs Plus Two DDCs)
2949.12MSPS
368.64MSPS
7.3728Gbps
SYNC~
L2
L3
M0(I)S0[7:0]
15547-112
I = REAL COMPONENT
Q = QUADRATURE COMPONENT
DCM = DECIMATION
C2R = COMPLEX TO REAL
MX = VIRTUAL CONVERTER X
LY = LANE Y
SZ = SAMPLE Z INSIDE A JESD204B FRAME
C = CONTROL BIT (OVER RANGE, AMONG OTHERS)
T = TAIL BIT
M1(Q)S0[7:0]
JESD204B LINK
(L = 4 M = 4 F = 2,
S = 1, N’ = 16, N = 16,
CS = 0, HD = 0)
M1(Q)S0[15:8]
L1
M3(Q)
M2(I)S0[7:0]
M2(I)
VIN_B
REAL
M2(I)S0[15:8]
14-BIT
ADC CORE
DDC 1
(REAL INPUT,
DCM = 8
C2R = BYPASS)
L0
M1(Q)
M3(Q)S0[7:0]
14-BIT
ADC CORE
DDC 0
(REAL INPUT,
DCM = 8
C2R = BYPASS)
M3(Q)S0[15:8]
M0(I)
VIN_A
REAL
M0(I)S0[15:8]
F=2
Figure 117. Two ADCs Plus Two DDCs Mode (L = 4, M = 4, F = 2, S = 1)
This example shows the flexibility in the digital and lane
configurations for the AD9208. The sample rate is 2.94912 GSPS;
however, the outputs are all combined in either two or four
lanes, depending on the input/output speed capability of the
receiving device.
The AD9208 is set up as shown in Figure 117, with the following
configuration:
Two 14-bit converters at 2.94912 GSPS.
Two DDC application layer mode with complex outputs
(I/Q).
Chip decimation ratio = 8.
DDC decimation ratio = 8 (see Table 46).
The JESD204B output configuration is as follows:
Four virtual converters required (see Table 33).
Output sample rate (fOUT) = 2949.12/8 = 368.64 MSPS.
The JESD204B supported output configurations are as follows
(see Table 33):
N΄ = 16 bits.
N = 14 bits .
L = 2, M = 4, and F = 4, or L = 4, M = 4, and F = 2.
CS = 0.
K = 32.
Output serial lane rate = 14.7456 Gbps per lane (L = 2) or
7.3728 Gbps per lane (L = 4).
For L = 2, set the PLL control register, Register 0x056E, to 0x30.
For L = 4, set the PLL control register, Register 0x056E, to 0x00.
Rev. 0 | Page 77 of 136
AD9208
Data Sheet
DETERMINISTIC LATENCY
Both ends of the JESD204B link contain various clock domains
distributed throughout each system. Data traversing from one
clock domain to a different clock domain can lead to ambiguous
delays in the JESD204B link. These ambiguities lead to nonrepeatable latencies across the link from one power cycle or link
reset to the next. Section 6 of the JESD204B specification
addresses the issue of deterministic latency with mechanisms
defined as Subclass 1 and Subclass 2.
SUBCLASS 1 OPERATION
The JESD204B protocol organizes data samples into octets, frames,
and multiframes as described in the Transport Layer section.
The LMFC is synchronous with the beginnings of these
multiframes. In Subclass 1 operation, the SYSREF is used to
synchronize the LMFCs for each device in a link or across
multiple links (within the AD9208, SYSREF also synchronizes
the internal sample dividers), as shown in Figure 118. The
JESD204B receiver uses the multiframe boundaries and
buffering to achieve consistent latency across lanes (or even
multiple devices), and also to achieve a fixed latency between
power cycles and link reset conditions.
The AD9208 supports JESD204B Subclass 0 and Subclass 1
operation. Register 0x0590, Bits[7:5] set the subclass mode for the
AD9208 and its default is set for Subclass 1 operating mode
(Register 0x0590, Bit 5 = 1). If deterministic latency is not a
system requirement, Subclass 0 operation is recommended and
the SYSREF signal may not be required. Even in Subclass 0
mode, the SYSREF signal may be required in an application
where multiple AD9208 devices must be synchronized with
each other. This topic is addressed in the Timestamp Mode
section.
Deterministic Latency Requirements
Several key factors are required for achieving deterministic
latency in a JESD204B Subclass 1 system.
SUBCLASS 0 OPERATION
If there is no requirement for multichip synchronization while
operating in Subclass 0 mode (Register 0x0590, Bits[7:5]= 0),
the SYSREF input can be left disconnected. In this mode, the
relationship of the JESD204B clocks between the JESD204B
transmitter and receiver are arbitrary, but does not affect the ability
of the receiver to capture and align the lanes within the link.
SYSREF± signal distribution skew within the system must
be less than the desired uncertainty for the system.
SYSREF± setup and hold time requirements must be met
for each device in the system.
The total latency variation across all lanes, links, and
devices must be ≤1 LMFC periods (see Figure 118). This
includes both variable delays and the variation in fixed
delays from lane to lane, link to link, and device to device
in the system.
SYSREF
DEVICE CLOCK
SYSREF-ALIGNED
GLOBAL LMFC
SYSREF TO LMFC DELAY
ALL LMFCs
DATA
ILAS
Figure 118. SYSREF and LMFC
Rev. 0 | Page 78 of 136
DATA
15547-113
POWER CYCLE VARIATION
(MUST BE < tLMFC)
Data Sheet
AD9208
Setting Deterministic Latency Registers
this adjustment. If the total latency in the system is not near an
integer multiple of the LMFC period or if the appropriate
adjustments have been made to the LMFC phase at the clock
source, it is still possible to have variable latency from one
power cycle to the next. By design, the AD9208 has circuitry in
place to minimize this variation from power-up to power-up. In
this case, the user must check for the possibility that the setup
and hold time requirements for the SYSREF signal are not being
met, by reading the SYSREF setup/hold monitor register
(Register 0x0128). This function is fully described in the
SYSREF± Setup/Hold Window Monitor section.
The JESD204B receiver in the logic device buffers data starting
on the LMFC boundary. If the total link latency in the system is
near an integer multiple of the LMFC period, it is possible that
from one power cycle to the next, the data arrival time at the
receive buffer may straddle an LMFC boundary. To ensure
deterministic latency in this case, a phase adjustment of the
LMFC at either the transmitter or receiver must be performed.
Typically, adjustments to accommodate the receive buffer are
made to the LMFC of the receiver. Alternatively, this adjustment
can be made in the AD9208 using the LMFC offset register
(Register 0x0578, Bits[4:0]). This delays the LMFC in frame
clock increments, depending on the F parameter (number of
octets per lane per frame). For F = 1, every fourth setting (0, 4,
8, and so on) is valid and results in a four frame clock shift. For
F = 2, every other setting (0, 2, 4, and so on) is valid and results
in a two frame clock shift. For all other values of F, each setting
results in a one frame clock shift. Figure 119 shows that, when
the link latency is near an LMFC boundary, the local LMFC of
the AD9208 can be adjusted to delay the data arrival time at the
receiver. Figure 120 shows how the LMFC of the receiver is
delayed to accommodate the receive buffer timing. Consult the
applicable JESD204B receiver user guide for details on making
If reading Register 0x0128 indicates there may be a timing
problem, there are a few adjustments that can made in the
AD9208. Changing the SYSREF level that is used for alignment is
possible using the SYSREF transition select bit (Register 0x0120,
Bit 4). Also, changing which edge of CLK is used to capture
SYSREF can be done using the CLK edge select bit
(Register 0x0120, Bit 3). Both of these options are described in
the SYSREF Control Features section. If neither of these measures
helps to achieve an acceptable setup and hold time, adjusting
the phase of SYSREF and/or the device clock (CLK±) may be
required.
POWER CYCLE VARIATION
LMFCTX DELAY TIME
SYSREF-ALIGNED
GLOBAL LMFC
Tx LOCAL LMFC
ILAS
DATA
(AT Rx INPUT)
DATA
ILAS
DATA
Tx LMFC MOVED (DELAYING THE ARRIVAL OF DATA RELATIVE
TO THE GLOBAL LMFC) SO THE RECIEVE BUFFER RELEASE TIME
IS ALWAYS REFERENCED TO THE SAME LMFC EDGE
15547-114
DATA
(AT Tx INPUT)
Figure 119. Adjusting the JESD204B Tx LMFC in the AD9208
LMFCRX DELAY TIME
POWER CYCLE VARIATION
SYSREF-ALIGNED
GLOBAL LMFC
DATA
(AT Tx INPUT)
DATA
(AT Rx INPUT)
DATA
ILAS
ILAS
ILAS
DATA
Rx LMFC MOVED SO THE RECEIVE BUFFER RELEASE TIME
IS ALWAYS REFERENCED TO THE SAME LMFC EDGE
Figure 120. Adjusting the JESD204B Rx LMFC in the Logic Device
Rev. 0 | Page 79 of 136
15547-115
Rx LOCAL LMFC
AD9208
Data Sheet
MULTICHIP SYNCHRONIZATION
The flowchart in Figure 122 shows the internal mechanism for
multichip synchronization in the AD9208. There are two methods
by which multichip synchronization can take place, as determined
by the chip synchronization mode bit (Register 0x01FF, Bit 0).
Each method involves different applications of the SYSREF signal.
NORMAL MODE
The default sate of the chip synchronization mode bit is 0, which
configures the AD9208 for normal chip synchronization. The
JESD204B standard specifies the use of SYSREF to provide for
deterministic latency within a single link. This same concept,
when applied to a system with multiple converters and logic
devices can also provide multichip synchronization. In Figure 122,
this is referred to as normal mode. Following the process in the
flowchart ensures that the AD9208 is configured appropriately. The
user must also consult the logic devices user IP guide to ensure
that the JESD204B receivers are configured appropriately.
TIMESTAMP MODE
For all AD9208 full bandwidth operating modes, the SYSREF
input can also be used to timestamp samples. This is another
method by which multiple channels and multiple devices can
achieve synchronization. This method is especially effective when
synchronizing multiple devices to one or more logic devices. The
logic devices buffer the data streams, identify the timestamped
samples, and align them. When the chip synchronization mode
bit (Register 0x01FF, Bit 0) is set to 1, the timestamp method is
used for synchronization of multiple channels and/or devices.
In this mode, SYSREF resets the sample dividers and the
JESD204B clocking. When the chip sync mode is set to 1, the
clocks are not reset; instead, the coinciding sample is timestamped
using the JESD204B control bits of that sample. To operate in
timestamp mode, these additional settings are necessary:
Continuous or N-shot SYSREF must be enabled
(Register 0x0120, Bits[2:1] = 1 or 2).
At least one control bit must be enabled (Register 0x058F,
Bits[7:6] = 1, 2, or 3).
Set the function for one of the control bits to SYSREF:
Register 0x0559, Bits[3:0] = 5 if using Control Bit 0.
Register 0x0559, Bits[7:4] = 5 if using Control Bit 1.
Register 0x055A, Bits[3:0] = 5 if using Control Bit 2.
Figure 121 shows how the input sample coincident with
SYSREF is timestamped and ultimately output of the ADC. In
this example, there are two control bits, and Control Bit 0 is the
bit indicating which sample was coincident with the SYSREF
rising edge. Note that the pipeline latencies for each channel are
identical. If so desired, the SYSREF timestamp delay register
(Register 0x0123) can be used to adjust the timing of which
sample is time stamped.
Note that time stamping is not supported by any AD9208
operating modes that use decimation.
14-BIT SAMPLES OUT
N–1
N+1
N+2
N+3
N – 1 00
N
CONTROL BIT 0 USED TO
TIME STAMP SAMPLE N
ENCODE CLK
SYSREF
AINB
01 N + 1 00 N + 2 00 N + 3 00
CHANNEL A
N–1
N
CHANNEL B
N+1
N+2
N – 1 00
N
01 N + 1 00 N + 2 00 N + 3 00
N+3
2 CONTROL BITS
15547-116
AINA
N
Figure 121. AD9208 Timestamping Example—CS = 2 (Register 0x058F, Bits[7:6] = 2), Control Bit 0 is SYSREF (Register 0x0559, Bits[3:0] = 5)
Rev. 0 | Page 80 of 136
Data Sheet
AD9208
INCREMENT
SYSREF IGNORE
COUNTER
START
NO
NO
RESET
SYSREF IGNORE
COUNTER
NO
SYSREF
ENABLED?
(0x0120)
YES
SYSREF
ASSERTED?
SYSREF
MODE
(0x0120)
YES
SYSREF
IGNORE
COUNTER
EXPIRED?
(0x0121)
N-SHOT
MODE
YES
CONTINUOUS
MODE
CLEAR SYSREF IGNORE COUNTER
AND DISABLE SYSREF
(CLEAR BIT 2 IN 0x0120)
UPDATE SETUP/HOLD
DETECTOR STATUS
(0x0128)
ALIGN CLOCK
DIVIDER PHASE
TO SYSREF
YES
INPUT
CLOCK DIVIDER
ALIGNMENT
REQUIRED?
NO
SYNCHRONIZATION
MODE?
(0x01FF)
TIMESTAMP
MODE
SYSREF
TIMESTAMP
DELAY
(0x0123)
YES
CLOCK
DIVIDER
AUTO ADJUST
ENABLED?
CLOCK
DIVIDER
>1?
(0x010B)
YES
NO
INCREMENT
SYSREF COUNTER
(0x012A)
NO
SYSREF
ENABLED
IN CONTROL BITS?
(0x0559, 0x055A,
0x058F)
SYSREF INSERTED
IN JESD204B
CONTROL BITS
YES
NO
RAMP
TEST MODE
ENABLED?
(0x0550)
NORMAL
MODE
SYSREF RESETS
RAMP TEST MODE
GENERATOR
YES
BACK TO START
NO
JESD204B
LMFC
ALIGNMENT
REQUIRED?
YES
ALIGN PHASE OF ALL
INTERNAL CLOCKS
(INCLUDING LMFC)
TO SYSREF
SEND INVALID 8-BIT/
10-BIT CHARACTERS
(ALL 0s)
SYNC~
ASSERTED
NO
NO
SEND K28.5
CHARACTERS
NORMAL
JESD204B
INITIALIZATION
NO
YES
ALIGN SIGNAL
MONITOR
COUNTERS
DDC NCO
ALIGNMENT
ENABLED?
(0x0300)
YES
ALIGN DDC NCO
PHASE
ACCUMULATOR
BACK TO START
NO
15547-117
SIGNAL
MONITOR
ALIGNMENT
ENABLED?
(0x026F)
YES
Figure 122. SYSREF Capture Scenarios and Multichip Synchronization
Rev. 0 | Page 81 of 136
AD9208
Data Sheet
The SYSREF input signal is used as a high accuracy system
reference for deterministic latency and multichip synchronization. The AD9208 accepts a single-shot or periodic input
signal. The SYSREF mode select bits (Register 0x0120, Bits[2:1])
select the input signal type and also arm the SYSREF state
machine when set. If in single (or N) shot mode (Register 0x0120,
Bits[2:1] = 2), the SYSREF mode select bit self clears after the
appropriate SYSREF transition is detected. The pulse width
must have a minimum width of two CLK± periods. If the clock
divider (Register 0x010B, Bits[3:0]) is set to a value other than
divide by 1, multiply this minimum pulse width requirement by
the divide ratio (that is, if set to divide by 8, the minimum pulse
width is 16 CLK± cycles). When using a continuous SYSREF
signal (Register 0x0120, Bits[2:1] = 1), the period of the SYSREF
signal must be an integer multiple of the LMFC. LMFC can be
derived using the following formula:
The third SYSREF related feature available is the ability to
ignore a programmable number (up to 16) of SYSREF events.
The AD9208 is able to ignore N SYSREF events (note that the
SYSREF ignore feature is enabled by setting the SYSREF mode
register (Register 0x0120, Bits[2:1]) to 2'b10, which is labeled as
N-shot mode. This feature is useful for handling periodic SYSREF
signals, which need time to settle after startup. Ignoring SYSREF
until the clocks in the system have settled can avoid an inaccurate
SYSREF trigger. Figure 127 shows an example of the SYSREF
ignore feature when ignoring three SYSREF events.
SETUP
REQUIREMENT
–65ps
HOLD
REQUIREMENT
95ps
SYSREF
SAMPLE POINT
CLK
SYSREF
KEEP OUT WINDOW
where:
S is the JESD204B parameter for number of samples per converter.
K is the number of frames per multiframe.
The input clock divider, DDCs, signal monitor block, and
JESD204B link are all synchronized using the SYSREF± input when
in normal synchronization mode (Register 0x01FF, Bit 0 = 0).
The SYSREF± input can also be used to timestamp an ADC
sample to provide a mechanism for synchronizing multiple
AD9208 devices in a system. For the highest level of timing
accuracy, SYSREF± must meet setup and hold requirements
relative to the CLK± input. There are several features in the
AD9208 that can be used to ensure these requirements are met;
these features are described in the SYSREF Control Features
section.
SYSREF Control Features
Figure 123. SYSREF Setup and Hold Time Requirements—SYSREF Low to
High Transition Using Rising Edge Clock (Default)
SETUP
REQUIREMENT
–65ps
HOLD
REQUIREMENT
95ps
SYSREF
SAMPLE POINT
CLK
15547-119
LMFC = ADC clock/(S × K)
15547-118
SYSREF INPUT
SYSREF
Figure 124. SYSREF Low to High Transition Using Falling Edge Clock Capture
(Register 0x0120, Bit 4 = 1’b0; Register 0x0120, Bit 3 = 1’b1)
SETUP
REQUIREMENT
–65ps
HOLD
REQUIREMENT
95ps
SYSREF
SAMPLE POINT
15547-120
CLK
SYSREF
Figure 125. SYSREF High to Low Transition Using Rising Edge Clock Capture
(Register 0x0120, Bit 4 = 1’b1; Register 0x0120, Bit 3 = 1’b0)
SETUP
REQUIREMENT
–65ps
HOLD
REQUIREMENT
95ps
SYSREF
SAMPLE POINT
CLK
SYSREF
15547-121
SYSREF is used, along with the input clock (CLK), as part of a
source-synchronous timing interface and requires setup and
hold timing requirements of −65 ps and 95 ps relative to the
input clock (see Figure 123). The AD9208 has several features
that aid users in meeting these requirements. First, the SYSREF
sample event can be defined as either a synchronous low to high
transition or synchronous high to low transition. Second, the
AD9208 allows the SYSREF signal to be sampled using either
the rising edge or falling edge of the input clock. Figure 123,
Figure 124, Figure 125, and Figure 126 show all four possible
combinations.
Figure 126. SYSREF High to Low Transition Using Falling Edge Clock Capture
(Register 0x0120, Bit 4 = 1’b1; Register 0x0120, Bit 3 = 1’b1)
Rev. 0 | Page 82 of 136
Data Sheet
AD9208
SYSREF SAMPLE PART 1
SYSREF SAMPLE PART 2
SYSREF SAMPLE PART 3
SYSREF SAMPLE PART 4
SYSREF SAMPLE PART 5
CLK
15547-122
SYSREF
SAMPLE THE FOURTH SYSREF
IGNORE FIRST THREE SYSREFs
Figure 127. SYSREF Ignore Example (SYSREF Ignore Count, Register 0x0121, Bits[3:0] = 3)
SYSREF SKEW WINDOW = ±3
SYSREF SKEW WINDOW = ±2
SYSREF SKEW WINDOW = ±1
SYSREF SKEW WINDOW = 0
15547-123
SAMPLE CLOCK
SYSREF
Figure 128. SYSREF Skew Window
When in continuous SYSREF mode (Register 0x0120, Bits[2:1] =
1), the AD9208 monitors the placement of the SYSREF leading
edge compared to the internal LMFC. If the SYSREF is captured
with a clock edge other than the one that is aligned with LMFC,
the AD9208 initiates a resynchronization of the link. Because
input clock rates for AD9208 can be up to 4 GHz, the AD9208
provides another SYSREF related feature that makes it possible
to accommodate periodic SYSREF signals where cycle accurate
capture is not feasible or not required. For these scenarios, the
AD9208 has a programmable SYSREF skew window that allows
the internal dividers to remain undisturbed unless SYSREF
occurs outside the skew window. The resolution of the SYSREF
skew window is set in sample clock cycles. If the SYSREF negative
skew window is 1 and the positive skew window is 1, the total
skew window is ±1 sample clock cycles, meaning that, as long as
SYSREF is captured within ±1 sample clock cycle of the clock that
is aligned with LMFC, the link continues to operate normally. If
the SYSREF has jitter, which can cause a misalignment between
SYSREF and LMFC, this feature allows the system to continue
running without a resynchronization, while still allowing the
device to monitor for larger errors not caused by jitter. For the
AD9208, the positive and negative skew window is controlled by
the SYSREF window negative register (Register 0x0122, Bits[3:2])
and SYSREF window positive register (Register 0x0122, Bits[1:0]).
Figure 128 shows information on the location of the skew window
settings relative to Phase 0 of the internal dividers. Negative skew
is defined as occurring before the internal dividers reach Phase 0,
and positive skew is defined after the internal dividers reach
Phase 0.
Rev. 0 | Page 83 of 136
AD9208
Data Sheet
SYSREF± SETUP/HOLD WINDOW MONITOR
To ensure a valid SYSREF signal capture, the AD9208 has a
SYSREF± setup/hold window monitor. This feature allows the
system designer to determine the location of the SYSREF± signals
relative to the CLK± signals by reading back the amount of
setup/hold margin on the interface through the memory map.
Figure 129 and Figure 130 show the setup and hold status values
for different phases of SYSREF±. The setup detector returns the
status of the SYSREF± signal before the CLK± edge, and the
hold detector returns the status of the SYSREF signal after the
CLK± edge. Register 0x0128 stores the status of SYSREF± and
notifies the user if the SYSREF± signal is captured by the ADC.
Table 36 shows the description of the contents of Register 0x0128
and how to interpret them.
0xF
0xE
0xD
0xC
0xB
0xA
0x9
REG 0x0128[3:0] 0x8
0x7
0x6
0x5
0x4
0x3
0x2
0x1
0x0
CLK±
INPUT
VALID
SYSREF±
INPUT
FLIP-FLOP
HOLD (MIN)
FLIP-FLOP
HOLD (MIN)
Figure 129. SYSREF± Setup Detector
Rev. 0 | Page 84 of 136
15547-124
FLIP-FLOP
SETUP (MIN)
Data Sheet
AD9208
0xF
0xE
0xD
0xC
0xB
0xA
0x9
0x8
0x7
0x6
0x5
0x4
0x3
0x2
0x1
REG 0x0128[7:4] 0x0
CLK±
INPUT
SYSREF±
INPUT
FLIP-FLOP
SETUP (MIN)
FLIP-FLOP
HOLD (MIN)
FLIP-FLOP
HOLD (MIN)
15547-125
VALID
Figure 130. SYSREF± Hold Detector
Table 36. SYSREF± Setup/Hold Monitor, Register 0x0128
Register 0x0128, Bits[7:4]
Hold Status
0x0
0x0 to 0x8
0x8
0x8
0x9 to 0xF
0x0
Register 0x0128, Bits[3:0]
Setup Status
0x0 to 0x7
0x8
0x9 to 0xF
0x0
0x0
0x0
Description
Possible setup error. The smaller this number, the smaller the setup margin.
No setup or hold error (best hold margin).
No setup or hold error (best setup and hold margin).
No setup or hold error (best setup margin).
Possible hold error. The larger this number, the smaller the hold margin.
Possible setup or hold error.
Rev. 0 | Page 85 of 136
AD9208
Data Sheet
LATENCY
END TO END TOTAL LATENCY
EXAMPLE LATENCY CALCULATIONS
Total latency in the AD9208 is dependent on the chip
application mode and the JESD204B configuration. For any
given combination of these parameters, the latency is
deterministic, however, the value of this deterministic latency
must be calculated as described in the Example Latency
Calculations section.
Example Configuration 1 is as follows:
Table 34 shows the combined latency through the ADC and
DSP for the different chip application modes supported by the
AD9208. Table 35 shows the latency through the JESD204B
block for each application mode based on the M/L ratio. For
both tables, latency is typical and is in units of the encode clock.
The latency through the JESD204B block does not depend on
the output data type (real or complex). Therefore, data type is
not included in Table 35.
To determine the total latency, select the appropriate ADC + DSP
latency from Table 34 and add it to the appropriate JESD204B
latency from Table 35. Example calculations are provided in the
following section.
ADC application mode = full bandwidth
Real outputs
L = 8, M = 2, F = 1, S = 2 (JESD204B mode)
20 × (M/L) = 5
Latency = 31 + 44 = 75 encode clocks
Example Configuration 2 is as follows:
ADC application mode = DCM4
Complex outputs
L = 4, M = 2, F = 1, S = 1 (JESD204B mode)
20 × (M/L) = 10
Latency = 162 + 88 = 250 encode clocks
LMFC REFERENCED LATENCY
Some FPGA vendors may require the end user to know LMFCreferenced latency to make appropriate deterministic latency
adjustments. If they are required, the latency values in Table 34
and Table 35 can be used for the analog in to LMFC and LMFC
to data out latency values.
Rev. 0 | Page 86 of 136
Data Sheet
AD9208
Table 37. Latency Through the ADC + DSP Blocks (Number of Sample Clocks)1
Chip Application Mode
Full Bandwidth
DCM1 (Real)
DCM2 (Complex)
DCM3 (Complex)
DCM2 (Real)
DCM4 (Complex)
DCM3 (Real)
DCM6 (Complex)
DCM4 (Real)
DCM8 (Complex)
DCM5 (Real)
DCM10 (Complex)
DCM6 (Real)
DCM12 (Complex)
DCM15 (Real)
DCM8 (Real)
DCM16 (Complex)
DCM10 (Real)
DCM20 (Complex)
DCM12 (Real)
DCM24 (Complex)
DCM30 (Complex)
DCM20 (Real)
DCM40 (Complex)
DCM24 (Real)
DCM48 (Complex)
1
Enabled Filters
Not applicable
HB1
HB1
TB1
HB2 + HB1
HB2 + HB1
TB2 + HB1
TB2 + HB1
HB3 +HB2 + HB1
HB3 +HB2 + HB1
FB2 + HB1
FB2 + HB1
TB2 + HB2 + HB1
TB2 + HB2 + HB1
FB2 + TB1
HB4 + HB3 + HB2 + HB1
HB4 + HB3 + HB2 + HB1
FB2 + HB2 + HB1
FB2 + HB2 + HB1
TB2 + HB3 + HB2 + HB1
TB2 + HB3 + HB2 + HB1
HB2 + FB2 + TB1
FB2 + HB3 + HB2 + HB1
FB2 + HB3 + HB2 + HB1
TB2 + HB4 + HB3 + HB2 + HB1
TB2 + HB4 + HB3 + HB2 + HB1
ADC + DSP Latency
31
90
90
102
162
162
212
212
292
292
380
380
424
424
500
552
552
694
694
814
814
836
1420
1420
1594
1594
DCMx indicates the decimation ratio.
Table 38. Latency Through JESD204B Block (Number of Sample Clocks)1
Chip Application Mode
Full Bandwidth
DCM1
DCM2
DCM3
DCM4
DCM5
DCM6
DCM8
DCM10
DCM12
DCM15
DCM16
DCM20
DCM24
DCM30
DCM40
DCM48
0.125
82
82
160
237
315
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0.25
44
44
84
124
164
2033
243
323
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
0.5
25
25
46
67
88
1093
130
172
213
255
3184
3394
N/A
N/A
N/A
N/A
N/A
1
M/L Ratio2
1
14
14
27
39
50
623
73
96
119
142
1764
1884
233
279
3484
N/A
N/A
N/A means not applicable and indicates that the application mode is not supported at the M/L ratio listed.
M/L ratio is the number of converters divided by the number of lanes for the configuration.
3
The application mode at the M/L ratio listed is only supported in real output mode.
4
The application mode at the M/L ratio listed is only supported in complex output mode.
2
Rev. 0 | Page 87 of 136
2
7
7
14
21
27
433
39
50
62
73
904
964
119
142
1764
2334
2794
4
9
N/A
7
11
14
N/A
21
27
33
39
474
504
62
73
904
1194
1424
8
3
N/A
N/A
N/A
9
N/A
14
18
22
27
334
354
43
51
624
824
974
AD9208
Data Sheet
TEST MODES
ADC TEST MODES
The AD9208 has various test options that aid in the system level
implementation. The AD9208 has ADC test modes that are
available in Register 0x550. These test modes are described in
Table 39. When an output test mode is enabled, the analog section
of the ADC is disconnected from the digital back-end blocks,
and the test pattern is run through the output formatting block.
Some of the test patterns are subject to output formatting, and
some are not. The PN generators from the PN sequence tests
can be reset by setting Bit 4 or Bit 5 of Register 0x0550. These
tests can be performed with or without an analog signal (if
present, the analog signal is ignored); however, they do require
an encode clock.
If the application mode is set to select a DDC mode of
operation, the test modes must be enabled for each DDC
enabled. The test patterns can be enabled via Bit 2 and Bit 0 of
Register 0x0327, Register 0x0347, and Register 0x0367,
depending on which DDC(s) are selected. The (I) data uses the
test patterns selected for Channel A, and the (Q) data uses the
test patterns selected for Channel B. For DDC3 only, the (I) data
uses the test patterns from Channel A, and the (Q) data does
not output test patterns. Bit 0 of Register 0x0387 selects the
Channel A test patterns to be used for the (I) data. For more
information, see the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI.
Table 39. ADC Test Modes
Output Test Mode
Bit Sequence
0000
0001
0010
0011
0100
0101
0110
0111
1000
Pattern Name
Off (default)
Midscale short
+Full-scale short
−Full-scale short
Checkerboard
PN sequence long
PN sequence short
One-/zero-word toggle
User input
Expression
Not applicable
0000 0000 0000
01 1111 1111 1111
10 0000 0000 0000
10 1010 1010 1010
x23 + x18 + 1
x9 + x5 + 1
11 1111 1111 1111
Register 0x0551 to
Register 0x0558
1111
Ramp output
(x) % 214
Default/
Seed Value
Not applicable
Not applicable
Not applicable
Not applicable
Not applicable
0x3AFF
0x0092
Not applicable
Not applicable
Not applicable
Rev. 0 | Page 88 of 136
Sample (N, N + 1, N + 2, …)
Not applicable
Not applicable
Not applicable
Not applicable
0x1555, 0x2AAA, 0x1555, 0x2AAA, 0x1555
0x3FD7, 0x0002, 0x26E0, 0x0A3D, 0x1CA6
0x125B, 0x3C9A, 0x2660, 0x0c65, 0x0697
0x0000, 0x3FFF, 0x0000, 0x3FFF, 0x0000
User Pattern 1[15:2], User Pattern 2[15:2],
User Pattern 3[15:2], User Pattern 4[15:2],
User Pattern 1[15:2] … for repeat mode
User Pattern 1[15:2], User Pattern 2[15:2],
User Pattern 3[15:2], User Pattern 4[15:2],
0x0000 … for single mode
(x) % 214, (x +1) % 214, (x +2) % 214, (x +3) % 214
Data Sheet
AD9208
JESD204B BLOCK TEST MODES
In addition to the ADC pipeline test modes, the AD9208 also has
flexible test modes in the JESD204B block. These test modes are
listed in Register 0x0573 and Register 0x0574. These test patterns
can be injected at various points along the output datapath. These
test injection points are shown in Figure 107. Table 40 describes
the various test modes available in the JESD204B block. For the
AD9208, a transition from test modes (Register 0x0573 ≠ 0x00)
to normal mode (Register 0x0573 = 0x00) requires an SPI soft
reset. This is done by writing 0x81 to Register 0x0000 (self cleared).
Transport Layer Sample Test Mode
The transport layer samples are implemented in the AD9208 as
defined by Section 5.1.6.3 in the JEDEC JESD204B specification.
These tests are shown in Register 0x0571, Bit 5. The test pattern
is equivalent to the raw samples from the ADC.
Interface Test Modes
The interface test modes are described in Register 0x0573, Bits[3:0].
These test modes are also explained in Table 40. The interface tests
can be injected at various points along the data. See Figure 107
for more information on the test injection points. Register 0x0573,
Bits[5:4] show where these tests are injected.
Table 41, Table 42, and Table 43 show examples of some of the
test modes when injected at the JESD204B sample input, PHY
10-bit input, and scrambler 8-bit input. UPx in the tables
represent the user pattern control bits from the user register
map.
Table 40. JESD204B Interface Test Modes
Output Test Mode
Bit Sequence
0000
0001
0010
0011
0100
0101
0110
0111
1000
1110
1111
Pattern Name
Off (default)
Alternating checker board
1/0 word toggle
31-bit PN sequence
23-bit PN sequence
15-bit PN sequence
9-bit PN sequence
7-bit PN sequence
Ramp output
Continuous/repeat user test
Single user test
Expression
Not applicable
0x5555, 0xAAAA, 0x5555, …
0x0000, 0xFFFF, 0x0000, …
x31 + x28 + 1
x23 + x18 + 1
x15 + x14 + 1
x9 + x5 + 1
x7 + x6 + 1
(x) % 216
Register 0x0551 to Register 0x0558
Register 0x0551 to Register 0x0558
Default
Not applicable
Not applicable
Not applicable
0x0003AFFF
0x003AFF
0x03AF
0x092
0x07
Ramp size depends on test injection point
User Pattern 1 to User Pattern 4, then repeat
User Pattern 1 to User Pattern 4, then zeros
Table 41. JESD204B Sample Input for M = 2, S = 2, N' = 16 (Register 0x0573, Bits[5:4] = 'b00)
Frame
Number
0
0
0
0
1
1
1
1
2
2
2
2
3
3
3
3
4
4
4
4
Converter
Number
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Sample
Number
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Alternating
Checkerboard
0x5555
0x5555
0x5555
0x5555
0xAAAA
0xAAAA
0xAAAA
0xAAAA
0x5555
0x5555
0x5555
0x5555
0xAAAA
0xAAAA
0xAAAA
0xAAAA
0x5555
0x5555
0x5555
0x5555
1/0 Word
Toggle
0x0000
0x0000
0x0000
0x0000
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0x0000
0x0000
0x0000
0x0000
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0x0000
0x0000
0x0000
0x0000
Ramp
(x) % 216
(x) % 216
(x) % 216
(x) % 216
(x +1) % 216
(x +1) % 216
(x +1) % 216
(x +1) % 216
(x +2) % 216
(x +2) % 216
(x +2) % 216
(x +2) % 216
(x +3) % 216
(x +3) % 216
(x +3) % 216
(x +3) % 216
(x +4) % 216
(x +4) % 216
(x +4) % 216
(x +4) % 216
Rev. 0 | Page 89 of 136
PN9
0x496F
0x496F
0x496F
0x496F
0xC9A9
0xC9A9
0xC9A9
0xC9A9
0x980C
0x980C
0x980C
0x980C
0x651A
0x651A
0x651A
0x651A
0x5FD1
0x5FD1
0x5FD1
0x5FD1
PN23
0xFF5C
0xFF5C
0xFF5C
0xFF5C
0x0029
0x0029
0x0029
0x0029
0xB80A
0xB80A
0xB80A
0xB80A
0x3D72
0x3D72
0x3D72
0x3D72
0x9B26
0x9B26
0x9B26
0x9B26
User Repeat
UP1[15:0]
UP1[15:0]
UP1[15:0]
UP1[15:0]
UP2[15:0]
UP2[15:0]
UP2[15:0]
UP2[15:0]
UP3[15:0]
UP3[15:0]
UP3[15:0]
UP3[15:0]
UP4[15:0]
UP4[15:0]
UP4[15:0]
UP4[15:0]
UP1[15:0]
UP1[15:0]
UP1[15:0]
UP1[15:0]
User Single
UP1[15:0]
UP1[15:0]
UP1[15:0]
UP1[15:0]
UP2[15:0]
UP2[15:0]
UP2[15:0]
UP2[15:0]
UP3[15:0]
UP3[15:0]
UP3[15:0]
UP3[15:0]
UP4[15:0]
UP4[15:0]
UP4[15:0]
UP4[15:0]
0x0000
0x0000
0x0000
0x0000
AD9208
Data Sheet
Table 42. Physical Layer 10-Bit Input (Register 0x0573, Bits[5:4] = 'b01)
10-Bit Symbol
Number
0
1
2
3
4
5
6
7
8
9
10
11
Alternating
Checkerboard
0x155
0x2AA
0x155
0x2AA
0x155
0x2AA
0x155
0x2AA
0x155
0x2AA
0x155
0x2AA
1/0 Word
Toggle
0x000
0x3FF
0x000
0x3FF
0x000
0x3FF
0x000
0x3FF
0x000
0x3FF
0x000
0x3FF
Ramp
(x) % 210
(x + 1) % 210
(x + 2) % 210
(x + 3) % 210
(x + 4) % 210
(x + 5) % 210
(x + 6) % 210
(x + 7) % 210
(x + 8) % 210
(x + 9) % 210
(x + 10) % 210
(x + 11) % 210
PN9
0x125
0x2FC
0x26A
0x198
0x031
0x251
0x297
0x3D1
0x18E
0x2CB
0x0F1
0x3DD
PN23
0x3FD
0x1C0
0x00A
0x1B8
0x028
0x3D7
0x0A6
0x326
0x10F
0x3FD
0x31E
0x008
User Repeat
UP1[15:6]
UP2[15:6]
UP3[15:6]
UP4[15:6]
UP1[15:6]
UP2[15:6]
UP3[15:6]
UP4[15:6]
UP1[15:6]
UP2[15:6]
UP3[15:6]
UP4[15:6]
User Single
UP1[15:6]
UP2[15:6]
UP3[15:6]
UP4[15:6]
0x000
0x000
0x000
0x000
0x000
0x000
0x000
0x000
Table 43. Scrambler 8-bit Input (Register 0x0573, Bits[5:4] = 'b10)
8-Bit Octet
Number
0
1
2
3
4
5
6
7
8
9
10
11
Alternating
Checkerboard
0x55
0xAA
0x55
0xAA
0x55
0xAA
0x55
0xAA
0x55
0xAA
0x55
0xAA
1/0 Word
Toggle
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
0x00
0xFF
Ramp
(x) % 28
(x + 1) % 28
(x + 2) % 28
(x + 3) % 28
(x + 4) % 28
(x + 5) % 28
(x + 6) % 28
(x + 7) % 28
(x + 8) % 28
(x + 9) % 28
(x + 10) % 28
(x + 11) % 28
Data Link Layer Test Modes
The data link layer test modes are implemented in the AD9208
as defined by Section 5.3.3.8.2 in the JEDEC JESD204B
Specification. These tests are shown in Register 0x0574,
PN9
0x49
0x6F
0xC9
0xA9
0x98
0x0C
0x65
0x1A
0x5F
0xD1
0x63
0xAC
PN23
0xFF
0x5C
0x00
0x29
0xB8
0x0A
0x3D
0x72
0x9B
0x26
0x43
0xFF
User Repeat
UP1[15:9]
UP2[15:9]
UP3[15:9]
UP4[15:9]
UP1[15:9]
UP2[15:9]
UP3[15:9]
UP4[15:9]
UP1[15:9]
UP2[15:9]
UP3[15:9]
UP4[15:9]
User Single
UP1[15:9]
UP2[15:9]
UP3[15:9]
UP4[15:9]
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Bits[2:0]. Test patterns inserted at this point are useful for
verifying the functionality of the data link layer. When the data
link layer test modes are enabled, disable SYNCINB± by writing
0xC0 to Register 0x0572.
Rev. 0 | Page 90 of 136
Data Sheet
AD9208
SERIAL PORT INTERFACE
The AD9208 SPI allows the user to configure the converter for
specific functions or operations through a structured register
space provided inside the ADC. The SPI gives the user added
flexibility and customization, depending on the application.
Addresses are accessed via the serial port and can be written to
or read from via the port. Memory is organized into bytes that
can be further divided into fields. These fields are documented
in the Memory Map section. For detailed operational information,
see the Serial Control Interface Standard (Rev. 1.0).
command is issued, which allows the SDIO pin to change
direction from an input to an output.
CONFIGURATION USING THE SPI
Data can be sent in MSB first mode or in LSB first mode. MSB
first is the default on power-up and can be changed via the SPI
port configuration register. For more information about this
and other features, see the Serial Control Interface Standard
(Rev. 1.0).
Three pins define the SPI of the AD9208 ADC: the SCLK pin,
the SDIO pin, and the CSB pin (see Table 44). The SCLK (serial
clock) pin synchronizes the read and write data presented
from/to the ADC. The SDIO (serial data input/output) pin is a
dual-purpose pin that allows data to be sent and read from the
internal ADC memory map registers. The CSB (chip select bar)
pin is an active low control that enables or disables the read and
write cycles.
Table 44. SPI Pins
Pin
SCLK
SDIO
CSB
Function
Serial clock. The serial shift clock input that is used to
synchronize serial interface, reads, and writes.
Serial data input/output. A dual-purpose pin that
typically serves as an input or an output, depending on
the instruction being sent and the relative position in the
timing frame.
Chip select bar. An active low control that gates the read
and write cycles.
The falling edge of CSB, in conjunction with the rising edge of
SCLK, determines the start of the framing. An example of the
serial timing and its definitions can be found in Figure 4 and
Table 5.
Other modes involving the CSB pin are available. The CSB pin
can be held low indefinitely, which permanently enables the
device; this is called streaming. The CSB can stall high between
bytes to allow additional external timing. When CSB is tied
high, SPI functions are placed in a high impedance mode. This
mode turns on any SPI pin secondary functions.
All data is composed of 8-bit words. The first bit of each
individual byte of serial data indicates whether a read or write
In addition to word length, the instruction phase determines
whether the serial frame is a read or write operation, allowing
the serial port to be used both to program the chip and to read
the contents of the on-chip memory. If the instruction is a
readback operation, performing a readback causes the SDIO pin
to change direction from an input to an output at the appropriate
point in the serial frame.
HARDWARE INTERFACE
The pins described in Table 44 comprise the physical interface
between the user programming device and the serial port of the
AD9208. The SCLK pin and the CSB pin function as inputs
when using the SPI interface. The SDIO pin is bidirectional,
functioning as an input during write phases and as an output
during readback.
The SPI interface is flexible enough to be controlled by either
FPGAs or microcontrollers. One method for SPI configuration
is described in detail in the AN-812 Application Note,
Microcontroller-Based Serial Port Interface (SPI) Boot Circuit.
Do not activate the SPI port during periods when the full
dynamic performance of the converter is required. Because the
SCLK signal, the CSB signal, and the SDIO signal are typically
asynchronous to the ADC clock, noise from these signals can
degrade converter performance. If the on-board SPI bus is
used for other devices, it may be necessary to provide buffers
between this bus and the AD9208 to prevent these signals from
transitioning at the converter inputs during critical sampling
periods.
SPI ACCESSIBLE FEATURES
Table 45 provides a brief description of the general features that
are accessible via the SPI. These features are described in detail
in the Serial Control Interface Standard (Rev. 1.0). The AD9208
device specific features are described in the Memory Map section.
Table 45. Features Accessible Using the SPI
Feature
Mode
Clock
DDC
Test Input/Output
Output Mode
SERDES Output Setup
Description
Allows the user to set either power-down mode or standby mode.
Allows the user to access the clock divider via the SPI.
Allows the user to set up decimation filters for different applications.
Allows the user to set test modes to have known data on output bits.
Allows the user to set up outputs.
Allows the user to vary SERDES settings such as swing and emphasis.
Rev. 0 | Page 91 of 136
AD9208
Data Sheet
MEMORY MAP
READING THE MEMORY MAP REGISTER TABLE
Default Values
Each row in the memory map register table has eight bit
locations. The memory map is divided into the following
sections:
After the AD9208 is reset, critical registers are loaded with
default values. The default values for the registers are given in
the memory map register table, Table 43.
Logic Levels
Analog Devices SPI registers (Register 0x0000 to
Register 0x000F)
Clock/SYSREF/chip power-down pin control registers
(Register 0x003F to Register 0x0201)
Fast detect and signal monitor control registers
(Register 0x0245 to Register 0x027A)
DDC function registers (Register 0x0300 to
Register 0x03CD)
Digital outputs and test modes registers (Register 0x0550 to
Register 0x05CB)
Programmable filter control and coefficients registers
(Register 0x0DF8 to Register 0x0F7F)
VREF/analog input control registers (Register 0x18A6 to
Register 0x1A4D)
Table 43 (see the Memory Map Register Details section)
documents the default hexadecimal value for each hexadecimal
address shown. The column with the heading Bit 7 (MSB) is the
start of the default hexadecimal value given. For example,
Address 0x0561, the output sample mode register, has a
hexadecimal default value of 0x01, which means that Bit 0 = 1,
and the remaining bits are 0s. This setting is the default output
format value, which is twos complement. For more information
on this function and others, see Table 43.
Open and Reserved Locations
An explanation of logic level terminology follows:
“Bit is set” is synonymous with “bit is set to Logic 1” or
“writing Logic 1 for the bit.”
“Clear a bit” is synonymous with “bit is set to Logic 0” or
“writing Logic 0 for the bit.”
X denotes a don’t care bit.
Channel Specific Registers
Some channel setup functions, such as the buffer control
register (Register 0x1A4C), can be programmed to a different
value for each channel. In these cases, channel address locations
are internally duplicated for each channel. These registers and
bits are designated in Table 43 as local. These local registers and
bits can be accessed by setting the appropriate Channel A or
Channel B bits in Register 0x0008. If both bits are set, the
subsequent write affects the registers of both channels. In a read
cycle, set only Channel A or Channel B to read one of the two
registers. If both bits are set during an SPI read cycle, the device
returns the value for Channel A. Registers and bits designated as
global in Table 43 affect the entire device and the channel
features for which independent settings are not allowed
between channels. The settings in Register 0x0005 do not affect
the global registers and bits.
SPI Soft Reset
All address and bit locations that are not included in Table 43
are not currently supported for this device. Write unused bits
of a valid address location with 0s unless the default value is
set otherwise. Writing to these locations is required only when
part of an address location is unassigned (for example,
Address 0x0561). If the entire address location is open (for
example, Address 0x0013), do not write to this address location.
After issuing a soft reset by programming 0x81 to Register 0x0000,
the AD9208 requires 5 ms to recover. When programming the
AD9208 for application setup, ensure that an adequate delay is
programmed into the firmware after asserting the soft reset and
before starting the device setup.
Rev. 0 | Page 92 of 136
Data Sheet
AD9208
MEMORY MAP REGISTER DETAILS
All address locations that are not included in Table 46 are not currently supported for this device and must not be written.
Table 46. Memory Map Register Details
Addr.
Name
Bits
Analog Devices SPI Registers
0x0000 SPI Configuration A 7
6
5
Bit Name
Settings
Description
Reset Access
0x0
R/WC
0
1
Whenever a soft reset is issued, the user must wait 5 ms before
writing to any other register. This provides sufficient time for
the boot loader to complete.
Do nothing.
Reset the SPI and registers (self clearing).
0x0
R/W
1
0
Least significant bit (LSB) shifted first for all SPI operations.
Most significant bit (MSB) shifted first for all SPI operations.
0x0
R/W
0
1
Multibyte SPI operations cause addresses to autodecrement.
Multibyte SPI operations cause addresses to autoincrement.
Reserved.
0x0
0x0
R
R/W
0x0
R/W
0x0
R/WC
0x0
0x0
R
R/WC
0x0
0x0
R
R
0x0
R/W
0x03
R
0xE2
R
0x0
0x0
0x0
0x0
0x1
R
R
R
R
R/W
0x1
R/W
0x0
R/W
0x1
R
Soft reset mirror
(self clearing)
LSB first mirror
Address ascension mirror
[4:3] Reserved
2
Address ascension
1
0
0
1
Multibyte SPI operations cause addresses to auto-decrement.
Multibyte SPI operations cause addresses to auto-increment.
1
0
LSB shifted first for all SPI operations.
MSB shifted first for all SPI operations.
Whenever a soft reset is issued, the user must wait 5 ms before
writing to any other register. This provides sufficient time for
the boot loader to complete.
Do nothing.
Reset the SPI and registers (self clearing).
Reserved.
LSB first
Soft reset (self clearing)
0
1
0x0001
SPI Configuration B [7:2] Reserved
1
Datapath soft reset
(self clearing)
0
1
0x0002
Chip configuration
(local)
Normal operation.
Datapath soft reset (self clearing).
Reserved.
Reserved.
0
Reserved
[7:2] Reserved
[1:0] Channel power mode
00
10
11
0x0003
Chip type
[7:0] Chip type
0x3
0x0004
Chip ID LSB
[7:0] Chip ID LSB [7:0]
0xDF
0x0005
0x0006
Chip ID MSB
Chip grade
0x0008
Device index
[7:0]
[7:4]
[3:0]
[7:2]
1
Chip ID MSB [15:8]
Chip speed grade
Reserved
Reserved
Channel B
0x0
0
1
0
Channel power modes.
Normal mode (power-up).
Standby mode; digital datapath clocks disabled; JESD204B
interface enabled.
Power-down mode; digital datapath clocks disabled; digital
datapath held in reset; JESD204B interface disabled.
Chip type.
High speed ADC.
Chip ID.
AD9208.
Chip ID.
Chip speed grade.
Reserved.
Reserved.
ADC Core B does not receive the next SPI command.
ADC Core B receives the next SPI command.
Channel A
0
1
0x000A Scratch pad
[7:0] Scratch pad
0x000B
[7:0] SPI revision
SPI revision
ADC Core A does not receive the next SPI command.
ADC Core A receives the next SPI command.
Chip scratch pad register. This register provides a consistent
memory location for software debugging.
SPI revision register. 0x01: Revision 1.0.
00000001 Revision 1.0.
Rev. 0 | Page 93 of 136
AD9208
Addr.
0x000C
0x000D
0x000F
Name
Vendor ID LSB
Vendor ID MSB
Transfer
Data Sheet
Bits
[7:0]
[7:0]
[7:1]
0
Bit Name
Vendor ID LSB
Vendor ID MSB
Reserved
Chip transfer
Settings
0
1
Clock/SYSREF/Chip PDWN Pin Control Registers
0x003F Chip PDWN pin
7
Local chip PDWN pin
(local)
disable
0
1
0x0040
Chip Pin Control 1
[6:0] Reserved
[7:6] Global chip PDWN pin
functionality
01
10
[5:3] Chip FD_B/GPIO_B0 pin
functionality
000
001
110
111
[2:0] Chip FD_A/GPIO_A0 pin
functionality
000
001
110
111
Chip Pin Control 2
Reset
0x56
0x04
0x0
0x0
Access
R
R
R
R/W
Function is determined by Register 0x0040, Bits[7:6].
0x0
R/W
Power-down pin (PDWN/STBY) enabled (default).
Power-down pin (PDWN/STBY) disabled/ignored.
Reserved.
0x0
0x0
External power-down pin functionality. Assertion of the
external power-down pin (PDWN/STBY) has higher priority
than the channel power mode control bits (Register 0x0002,
Bits[1:0]). The PDWN/STBY pin is only used when Register 0x0040,
Bits[7:6] = 00 or 01.
Power-down pin (default). Assertion of external power-down pin
(PDWN/STBY) causes the chip to enter full power-down mode.
Standby pin. Assertion of external power-down pin (PDWN/STBY)
causes the chip to enter standby mode.
Pin disabled. Power-down pin (PDWN/STBY) is ignored.
Fast Detect B/GPIO B0 pin functionality.
0x7
00
0x0041
Description
Vendor ID [7:0].
Vendor ID [15:8].
Reserved.
Self clearing chip transfer bit. This bit is used to update the
DDC phase increment and phase offset registers when DDC
phase update mode (Register 0x0300, Bit 7 ) = 1. This makes it
possible to synchronously update the DDC mixer frequencies.
This bit is also used to update the coefficients for the
programmable filter (PFILT).
Do nothing. Bit is only cleared after transfer is complete.
Self clearing bit used to synchronize the transfer of data from
master to slave registers.
[7:4] Chip FD_B/GPIO_B0 pin
secondary functionality
0000
0001
1000
1001
[3:0] Chip FD_A/GPIO_A0 pin
secondary functionality
0000
0001
1000
1001
Fast Detect B output.
JESD204B LMFC output.
Pin functionality determined by 0x0041[7:4]
Disabled. Configured as input with weak pull-down (default).
Fast Detect A/GPIO A0 pin functionality.
Fast Detect A output.
JESD204B LMFC output.
Pin functionality determined by Register 0x0041, Bits[3:0]
Disabled. Configured as an input with weak pull-down (default).
Fast Detect B/GPIO B0 pin secondary functionality (only used
when Register 0x0040, Bits[5:3] = 110).
Chip GPIO B0 input (NCO channel selection).
Chip transfer input.
Master next trigger output (MNTO).
Slave next trigger input (SNTI).
Fast Detect A/GPIO B0 pin secondary functionality (only used
when Register 0x0040, Bits[2:0] = 110).
Chip GPIO A0 input (NCO channel selection).
Chip transfer input.
Master next trigger output (MNTO).
Slave next trigger input (SNTI).
Rev. 0 | Page 94 of 136
R
R/W
R/W
0x7
R/W
0x0
R/W
0x0
R/W
Data Sheet
Addr.
0x0042
Name
Chip Pin Control 3
AD9208
Bits Bit Name
[7:4] Chip GPIO_B1 pin
functionality
Settings
Description
GPIO B1 pin functionality.
Reset Access
0xF
R/W
0000
1000
1001
1111
Chip GPIO B1 input (NCO channel selection).
Master next trigger output (MNTO).
Slave next trigger input (SNTI).
Disabled (configured as input with weak pull-down).
GPIO A1 pin functionality.
0xF
R/W
0x0
0x0
R
R/W
0x0
R
0x0
R/W
0x0
R/W
0x0
0x0
R
R/W
0x0
R/W
[3:0] Chip GPIO_B1 pin
functionality
0000
1000
1001
1111
0x0108
Clock divider control [7:3] Reserved
[2:0] Input clock divider
(CLK± pins)
00
01
11
0x0109
Clock divider
phase (local)
Chip GPIO A1 input (NCO channel selection).
Master next trigger output (MNTO).
Slave next trigger input (SNTI).
Disabled (configured as input with weak pull-down).
Reserved.
Divide by 1.
Divide by 2.
Divide by 4.
Reserved.
[7:4] Reserved
[3:0] Clock divider phase offset
0000
0001
0010
…
1110
1111
0x010A Clock divider and
SYSREF control
7
Clock divider auto phase
adjust enable
0
1
[6:4] Reserved
[3:2] Clock divider negative
skew window
0
1
10
11
[1:0] Clock divider positive
skew window
0
1
10
11
0 input clock cycles delayed.
½ input clock cycles delayed (invert clock).
1 input clock cycles delayed.
…
7 input clock cycles delayed.
7½ input clock cycles delayed.
Clock divider autophase adjust enable. When enabled,
Register 0x0129, Bits[3:0] contain the phase of the divider when
SYSREF occurred. The actual divider phase offset =
Register 0x0129, Bits[3:0] + Register 0x0109, Bits[3:0].
Clock divider phase is not changed by SYSREF (disabled).
Clock divider phase is automatically adjusted by SYSREF (enabled).
Reserved.
Clock divider negative skew window (measured in ½ input
device clocks). Number of ½ clock cycles before the input
device clock by which captured SYSREF transitions are ignored.
Only used when Register 0x010A, Bit 7 = 1. Register 0x010A,
Bits[3:2] + Register 0x010A, Bits[1:0] < Register 0x0108, Bits[2:0].
This allows some uncertainty in the sampling of SYSREF
without disturbing the input clock divider. Also, SYSREF must
be disabled (Register 0x0120, Bits[2:1] = 0x0) when changing
this control field.
No negative skew; SYSREF must be captured accurately.
½ device clock of negative skew.
1 device clocks of negative skew.
1½ device clocks of negative skew.
Clock divider positive skew window (measured in ½ input
device clocks). Number of clock cycles after the input device
clock by which captured SYSREF transitions are ignored. Only
used when Register 0x010A, Bit 7 = 1. Register 0x010A, Bits[3:2] +
Register 0x010A, Bits[1:0] < Register 0x0108, Bits[2:0]. This
allows some uncertainty in the sampling of SYSREF without
disturbing the input clock divider. Also, SYSREF must be
disabled (Register 0x0120, Bits[2:1] = 0x0) when changing this
control field.
No positive skew; SYSREF must be captured accurately.
½ device clock of positive skew.
1 device clocks of positive skew.
1½ device clocks of positive skew.
Rev. 0 | Page 95 of 136
AD9208
Addr.
0x010B
Name
Clock divider
SYSREF status
Data Sheet
Bits Bit Name
[7:4] Reserved
Settings
[3:0] Clock divider SYSREF
offset
0x0110
Clock delay control [7:3] Reserved
[2:0] Clock delay mode select
000
010
011
100
110
0x0111
Clock superfine
delay (local)
[7:0] Clock superfine delay
adjust
0x00
…
0x08
…
0x80
0x0112
Clock fine delay
(local)
[7:0] Set clock fine delay
0x00
…
0x08
…
0xC0
0x011B
Clock status
[7:1] Reserved
0
Input clock detect
0
1
0x011C
Clock Duty Cycle
Stabilizer 1 control
(local)
[7:2] Reserved
1
DCS1 enable
0
1
0
DCS1 power up
0
1
0x011E
Clock Duty Cycle
Stabilizer 2 control
[7:2]
Reserved
1
DCS2 enable
0
1
0
DCS2 power up
0
1
Description
Reserved.
Reset Access
0x0
R
Clock divider phase status (measured in ½ clock cycles).
Internal clock divider phase of the captured SYSREF signal
applied to the phase offset. Only used when 0x010A[7] = 1.
When Register 0x010A, Bit 7 = 1, Register 0x010A, Bits[3:2] = 0,
and Register 0x010A, Bits[1:0] = 0, the clock divider SYSREF
offset = Register 0x0129, Bits[3:0].
Reserved.
Clock delay mode select. Used in conjunction with
Register 0x0111 and Register 0x0112.
No clock delay.
Fine delay: only 0 to 16 delay steps are valid.
Fine delay (lowest jitter): only 0 to 16 delay steps are valid.
Fine delay: all 192 delay steps are valid.
Fine delay enabled (all 192 delay steps are valid); superfine
delay enabled (all 128 delay steps are valid).
Clock superfine delay adjust. This is an unsigned control to
adjust the superfine sample clock delay in 0.25 ps steps. These
bits are only used when Register 0x0110, Bits[2:0] = 010 or 110.
0 delay steps.
…
8 delay steps.
…
128 delay steps.
Clock fine delay adjust. This is an unsigned control to adjust the
fine sample clock skew in 1.725 ps steps. These bits are only
used when Register 0x0110, Bits[2:0] = 0x2, 0x3, 0x4, or 0x6.
Minimum = 0. Maximum = 192. Increment = 1. Unit = delay
steps.
0 delay steps.
…
8 delay steps.
…
192 delay steps.
Reserved.
Clock detection status.
Input clock not detected.
Input clock detected/locked.
Reserved
0x0
R
0x0
0x0
R
R/W
0x0
R/W
0xC0
R/W
0x0
0x0
R
R
0x0
R/W
Clock DCS1 enable.
DCS1 bypassed.
DCS1 enabled.
Clock DCS1 power-up.
DCS1 powered down.
DCS1 powered up.
Reserved.
0x1
R/W
0x1
R/W
0x0
R/W
Clock DCS2 enable.
DCS2 bypassed.
DCS2 enabled.
Clock DCS2 power-up.
DCS2 powered down.
DCS2 powered up.
0x1
R/W
0x1
R/W
Rev. 0 | Page 96 of 136
Data Sheet
Addr.
0x0120
Name
SYSREF Control 1
AD9208
Bits
7
6
5
4
Bit Name
Reserved
SYSREF± flag reset
Settings
Description
Reserved.
0
1
Normal flag operation.
SYSREF flags held in reset (setup and hold error flags cleared).
Reserved.
Reserved
SYSREF± transition select
0
CLK± edge select
0
1
Captured on the rising edge of CLK± input.
Captured on the falling edge of CLK± input.
0
1
10
Disabled.
Continuous.
N-shot.
Reserved.
Reserved.
[2:1] SYSREF± mode select
0x0121
SYSREF Control 2
0
Reserved
[7:4] Reserved
[3:0] SYSREF N-shot ignore
counter select
0000
0001
0010
0011
…
1110
1111
0x0122
SYSREF Control 3
[7:4] Reserved
[3:2] SYSREF window negative
00
01
10
11
[1:0] SYSREF window positive
00
01
10
11
0x0123
SYSREF Control 4
7
Reserved
[6:0] SYSREF± timestamp
delay, Bits[6:0]
0
1
…
111 1111
0x0128
SYSREF Status 1
[7:4] SYSREF± hold status
[3:0] SYSREF± setup status
0x0
0x0
R
R/W
0x0
R/W
0x0
R/W
0x0
0x0
0x0
R
R
R/W
0x0
0x0
R
R/W
0x0
R/W
0x0
0x00
R
R/W
0x0
0x0
R
R
SYSREF is valid on low to high transitions using the selected
CLK± edge. When changing this setting, SYSREF± mode select
must be set to disabled.
SYSREF is valid on high to low transitions using the selected
CLK± edge. When changing this setting, SYSREF± mode select
must be set to disabled.
1
3
Reset Access
0x0
R
0x0
R/W
Next SYSREF only (do not ignore).
Ignore the first SYSREF± transition.
Ignore the first two SYSREF± transitions.
Ignore the first three SYSREF± transitions.
…
Ignore the first 14 SYSREF± transitions.
Ignore the first 15 SYSREF± transitions.
Reserved.
Negative skew window (measured in sample clocks). Number
of clock cycles before the sample clock by which captured
SYSREF transitions are ignored.
No negative skew; SYSREF must be captured accurately.
One sample clock of negative skew.
Two sample clocks of negative skew.
Three sample clocks of negative skew.
Positive skew window (measured in sample clocks). Number of
clock cycles before the sample clock by which captured SYSREF
transitions are ignored.
No positive skew; SYSREF must be captured accurately.
One sample clock of positive skew.
Two sample clocks of positive skew.
Three sample clocks of positive skew.
Reserved.
SYSREF timestamp delay (in converter sample clock cycles).
0 sample clock cycle delay.
1 sample clock cycle delay.
…
127 sample clock cycle delay.
SYSREF hold status.
SYSREF setup status.
Rev. 0 | Page 97 of 136
AD9208
Addr.
0x0129
Name
SYSREF Status 2
0x012A SYSREF Status 3
0x01FF
Chip sync mode
Data Sheet
Bits Bit Name
Settings
[7:4] Reserved
[3:0] Clock divider phase when
SYSREF± was captured
0000
0001
0010
0011
0100
…
1111
[7:0] SYSREF counter, Bits[7:0]
increments when a
SYSREF± is captured
[7:1] Reserved
0
Synchronization mode
0
Chip Operating Mode Control Registers
0x0200 Chip mode
[7:6] Reserved
5
Chip Q ignore
Reserved.
Chip real (I) only selection.
Both real (I) and complex (Q) selected.
Only real (I) selected; complex (Q) is ignored.
Reserved.
0
1
4
Reserved
[3:0] Chip application mode
0000
0001
0010
0011
Chip decimation
ratio
Reset Access
0x0
R
0x0
R
0x0
R
0x0
0x0
R
R/W
0x0
0x0
R/W
R/W
0x0
0x0
R
R/W
0x0
R
0x0
R/W
JESD204B synchronization mode. The SYSREF signal resets all
internal clock dividers. Use this mode when synchronizing
multiple chips as specified in the JESD204B standard. If the
phase of any of the dividers must change, the JESD204B link
goes down.
Timestamp mode. The SYSREF signal does not reset internal
clock dividers. In this mode, the JESD204B link and the signal
monitor are not affected by the SYSREF signal. The SYSREF
signal timestamps a sample as it passes through the ADC and is
used as a control bit in the JESD204B output word.
1
0x0201
Description
Reserved.
SYSREF divider phase. Represents the phase of the divider
when SYSREF was captured.
In phase.
SYSREF± is ½ cycle delayed from clock.
SYSREF± is 1 cycle delayed from clock.
SYSREF± is 1½ input clock cycles delayed.
SYSREF± is 2 input clock cycles delayed.
…
SYSREF± is 7½ input clock cycles delayed.
SYSREF count. Running counter that increments whenever a
SYSREF event is captured. Reset by Register 0x120, Bit 6. Wraps
around at 255. Read these bits only when Register 0x120, Bits[2:1]
are set to disabled.
Reserved.
[7:4] Reserved
[3:0] Chip decimation ratio
0000
0001
1000
0010
0101
1001
0011
0110
1010
0111
0100
1101
1011
1110
1111
1100
Full bandwidth mode (default).
One DDC mode (DDC0 only)
Two DDC mode (DDC0 and DDC1 only)
Four DDC mode (DDC0, DDC1, DDC2, and DDC3)
Reserved.
Chip decimation ratio.
Full sample rate (decimate by 1, DDCs are bypassed).
Decimate by 2.
Decimate by 3.
Decimate by 4.
Decimate by 5.
Decimate by 6.
Decimate by 8.
Decimate by 10.
Decimate by 12.
Decimate by 15.
Decimate by 16.
Decimate by 20.
Decimate by 24.
Decimate by 30.
Decimate by 40.
Decimate by 48.
Rev. 0 | Page 98 of 136
Data Sheet
AD9208
Addr.
Name
Bits Bit Name
Fast Detect and Signal Monitor Control Registers
0x0245 Fast detect control [7:4] Reserved
(local)
3
Force FD_A/FD_B pins
Settings
0
1
2
1
0
Force value of
FD_A/FD_B pins
Reserved
Enable fast detect output
0
1
0x0247
Fast detect up LSB
(local)
0x0248
Fast detect up MSB [7:5] Reserved
(local)
[4:0] Fast detect upper
threshold
0x0249
[7:0] Fast detect upper
threshold
Fast detect low LSB [7:0] Fast detect lower
(local)
threshold
0x024A Fast detect low
MSB (local)
[7:5] Reserved
[4:0] Fast detect lower
threshold
Description
Reset Access
Reserved.
0x0
R
0x0
R/W
0x0
R/W
0x0
0x0
R
R/W
0x0
R/W
0x0
R
MSBs of the fast detect upper threshold. This register contains
the 8 LSBS of the programmable 13-bit upper threshold that is
compared to the fine ADC magnitude.
LSBs of the fast detect lower threshold. This register contains
the 8 LSBS of the programmable 13-bit lower threshold that is
compared to the fine ADC magnitude.
Reserved.
0x0
R/W
0x0
R/W
0x0
R
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R
0x0
R/W
Continuous mode.
Next synchronization mode. Only the next valid edge of the
SYSREF± pin is used to synchronize the signal monitor block.
Subsequent edges of the SYSREF± pin are ignored. When the
next SYSREF is found, Register 0x026F, Bit 0 clears. The SYSREF± pin
must be an integer multiple of the signal monitor period for
this function to operate correctly in continuous mode.
Signal monitor synchronization enable
0x0
R/W
Synchronization disabled.
If Register 0x026F, Bit 1 = 1, only the next valid edge of the
SYSREF± pin is used to synchronize the signal monitor block.
Subsequent edges of the SYSREF± pin are ignored. When the
next SYSREF signal is received, this bit is cleared. The SYSREF± input
pin must be enabled to synchronize the signal monitor blocks.
Reserved.
0x0
R
Normal operation of the fast detect pin.
Force a value on the fast detect pin (see Bit 2).
The fast detect output pin for this channel is set to this value
when the output is forced.
Reserved.
Fast detect disabled.
Fast detect enabled.
LSBs of the fast detect upper threshold. This register contains
the 8 LSBs of the programmable 13-bit upper threshold that is
compared to the fine ADC magnitude.
Reserved.
0x024B
Fast detect dwell
LSB (local)
[7:0] Fast detect dwell time
0x024C
Fast detect dwell
MSB (local)
[7:0] Fast detect dwell time
0x026F
Signal monitor
sync control
[7:2] Reserved
MSBs of the fast detect lower threshold. This register contains
the 8 LSBs of the programmable 13-bit lower threshold that is
compared to the fine ADC magnitude
LSBs of the fast detect dwell time counter target. This is a load
value for a 16-bit counter that determines how long the ADC
data must remain below the lower threshold before the FD_x
pins are reset to 0.
MSBs of the fast detect dwell time counter target. This is a load
value for a 16-bit counter that determines how long the ADC
data must remain below the lower threshold before the
FD_x pins are reset to 0.
Reserved.
1
Signal monitor next synchronization mode.
Signal monitor next
synchronization mode
0
1
0
Signal monitor
synchronization mode
0
1
0x0270
Signal monitor
control (local)
[7:2] Reserved
1
Peak detector
0
1
0x0271
Signal Monitor
Period 0 (local)
0
Reserved
[7:0] Signal monitor period
[7:0]
Peak detector disabled.
Peak detector enabled.
Reserved.
Bits[7:0] of the 24-bit value that sets the number of output
clock cycles over which the signal monitor performs its
operation. Only even values are supported.
Rev. 0 | Page 99 of 136
0x0
R/W
0x0
0x80
R
R/W
AD9208
Data Sheet
Addr.
0x0272
Name
Signal Monitor
Period 1 (local)
Bits Bit Name
[7:0] Signal monitor period
[15:8]
0x0273
Signal Monitor
Period 2 (local)
[7:0] Signal monitor period
[23:16]
0x0274
Signal monitor
status control
(local)
[7:5] Reserved
4
Settings
Result update
1
Update signal monitor status registers, Register 0x0275 to
Register 0x0278. Self clearing.
Reserved.
3
Reserved
[2:0] Result selection
001
0x0275
0x0276
0x0277
0x0278
0x0279
Signal Monitor
Status 0 (local)
Signal Monitor
Status 1 (local)
Signal Monitor
Status 2 (local)
Signal monitor
status frame
counter (local)
Signal monitor
serial framer
control (local)
Description
Bits[15:8] of the 24-bit value that sets the number of output
clock cycles over which the signal monitor performs its
operation. Only even values are supported.
Bits[23:16] of the 24-bit value that sets the number of output
clock cycles over which the signal monitor performs its
operation. Only even values are supported.
Reserved.
0x0
R/W
0x0
R
0x0
R/WC
0x0
0x1
R
R/W
Peak detector placed on status readback signals.
Signal monitor status result. This 20-bit value contains the
status result calculated by the signal monitor block.
Signal monitor status result.
0x0
R
0x0
R
Reserved.
0x0
R
[3:0] Signal monitor result
[19:16]
[7:0] Period count result,
Bits[7:0]
Signal monitor status result.
0x0
R
Signal monitor frame counter status bits. Frame counter
increments whenever the period counter expires.
0x0
R
[7:2] Reserved
Reserved.
0x0
R
0x0
R/W
0x0
R
Signal monitor serial framer input selection. When each
individual bit is a 1, the corresponding signal statistics
information is sent within the frame.
Disabled.
Peak detector data inserted in the serial frame.
Reserved.
0x1
R/W
0x0
R
Select DDC FTW/POW/MAW/MBW update mode.
0x0
R/W
Instantaneous/continuous update. FTW/POW/MAW/MBW
values are updated immediately.
FTW/POW/MAW/MBW values are updated synchronously when
the chip transfer bit (Register 0x000F, Bit 0) is set.
Reserved.
0x0
This bit can be used to synchronize all the NCOs inside the DDC 0x0
blocks.
Normal operation.
DDC held in reset.
Reserved.
0x0
R
R/W
[7:0] Signal monitor result [7:0]
[7:0] Signal monitor result
[15:8]
[7:4] Reserved
[1:0] Signal monitor SPORT
over JESD204B enable
00
11
0x027A SPORT over
JESD204B input
selection (local)
Reset Access
0x0
R/W
[7:6] Reserved
1
SPORT over JESD204B
input selection
0
1
0
Reserved
DDC Function Registers (See the Digital Downconverter (DDC) Section)
0x0300 DDC SYNC control 7
DDC FTW/POW/MAW/
MBW update mode
0
1
[6:5] Reserved
4
DDC NCO soft reset
0
1
[3:2] Reserved
Disabled.
Enabled.
Reserved.
Rev. 0 | Page 100 of 136
R
Data Sheet
Addr.
Name
AD9208
Bits
1
Bit Name
DDC next
synchronization
Settings
Description
0
Continuous mode. The SYSREF frequency must be an integer
multiple of the NCO frequency for this function to operate
correctly in continuous mode.
Only the next valid edge of the SYSREF± pin is used to
synchronize the NCO in the DDC block. Subsequent edges of
the SYSREF± pin are ignored. When the next SYSREF signal is
found, the DDC synchronization enable bit (Register 0x0300,
Bit 0) is cleared.
The SYSREF input pin must be enabled to synchronize the DDCs.
1
0
DDC synchronization
mode
0
1
0x0310
DDC0 control
7
DDC0 mixer select
DDC0 gain select
0
1
[5:4] DDC0 intermediate
frequency (IF) mode
00
01
10
11
3
0x0
R/W
0x0
Real mixer (I and Q inputs must be from the same real channel).
Complex mixer (I and Q must be from separate, real and imaginary
quadrature ADC receive channels; analog demodulator).
Gain can be used to compensate for the 6 dB loss associated
0x0
with mixing an input signal down to baseband and filtering out
its negative component.
0 dB gain.
6 dB gain (multiply by 2).
0x0
R/W
Synchronization disabled.
If DDC next synchronization (Register 0x0300, Bit 1 = 1), only
the next valid edge of the SYSREF± pin is used to synchronize
the NCO in the DDC block. Subsequent edges of the SYSREF±
pin are ignored. When the next SYSREF signal is received, this
bit is cleared.
0
1
6
Reset Access
0x0
R/W
Complex (I and Q) outputs contain valid data.
Real (I) output only. complex to real enabled. Uses extra fS
mixing to convert to real.
Decimation filter selection.
[2:0] DDC0 decimation rate
select
000
001
010
011
100
101
110
111
R/W
Variable IF mode.
0 Hz IF mode.
fS Hz IF mode.
Test mode.
DDC0 complex to real
enable
0
1
R/W
HB1 + HB2 filter selection: decimate by 2 (complex to real
enabled), or decimate by 4 (complex to real disabled).
HB1 + HB2 + HB3 filter selection: decimate by 4 (complex to
real enabled), or decimate by 8 (complex to real disabled).
HB1 + HB2 + HB3 + HB4 filter selection: decimate by 8
(complex to real enabled), or decimate by 16 (complex to real
disabled).
HB1 filter selection: decimate by 1 (complex to real enabled), or
decimate by 2 (complex to real disabled).
HB1 + TB2 filter selection: decimate by 3 (complex to real
enabled), or decimate by 6 (complex to real disabled).
HB1 + HB2 + TB2 filter selection: decimate by 6 (complex to real
enabled), or decimate by 12 (complex to real disabled).
HB1 + HB2 + HB3 + TB2 filter selection: decimate by 12 (complex to
real enabled), or decimate by 24 (complex to real disabled).
Decimation determined by Register 0x0311, Bits[7:4].
Rev. 0 | Page 101 of 136
0x0
R/W
0x0
R/W
AD9208
Addr.
0x0311
Name
DDC0 input select
Data Sheet
Bits Bit Name
[7:4] DDC0 decimation rate
select
Settings
Description
Only valid when Register 0x0310, Bits[2:0] = 3'b111.
0
TB2 + HB4 + HB3 + HB2 + HB1 filter selection: decimate by 48
(complex to real disabled), or decimate by 24 (complex to real
enabled).
FB2 + HB1 filter selection: decimate by 10 (complex to real
disabled), or decimate by 5 (complex to real enabled).
FB2 + HB2 + HB1 filter selection: decimate by 20 (complex to
real disabled), or decimate by 10 (complex to real enabled).
FB2 + HB3 + HB2 + HB1 filter selection: decimate by 40 (complex to
real disabled), or decimate by 20 (complex to real enabled).
TB1 filter selection: decimate by 3 (decimate by 1.5 not supported).
FB2 + TB1 filter selection: decimate by 15 (decimate by 7.5 not
supported).
HB2 + FB2 + TB1 filter selection: decimate by 30 (decimate by
15 not supported).
Reserved.
0x0
0x0
Channel A.
Channel B.
Reserved.
0x0
0x0
Channel A.
Channel B.
For edge control, the internal counter wraps after the
0x0
Register 0x0314, Bits[3:0] value is reached.
Use Register 0x0314, Bits[3:0].
2'b0, GPIO_B0, GPIO_A0.
2'b0, GPIO_B1, GPIO_A1.
2'b00, GPIO_A1, GPIO_A0.
2'b00, GPIO_B1, GPIO_B0.
GPIO_B1, GPIO_A1, GPIO_B0, GPIO_A0.
GPIO_B1, GPIO_B0, GPIO_A1, GPIO_A0.
Increment internal counter on rising edge of the GPIO_A0 pin.
Increment internal counter on rising edge of the GPIO_A1 pin.
Increment internal counter on rising edge of the GPIO_B0 pin.
Increment internal counter on rising edge of the GPIO_B1 pin.
NCO channel select register map control.
0x0
10
11
100
111
1000
1001
3
2
Reserved
DDC0 Q input select
0
1
1
0
Reserved
DDC0 I input select
0
1
0x0314
DDC0 NCO control
[7:4] DDC0 NCO channel select
mode
0
1
10
11
100
101
110
1000
1001
1010
1011
[3:0] DDC0 NCO register map
channel select
0
1
10
11
100
101
110
111
1000
1001
1010
1011
1100
1101
1110
1111
Select NCO Channel 0.
Select NCO Channel 1.
Select NCO Channel 2.
Select NCO Channel 3.
Select NCO Channel 4.
Select NCO Channel 5.
Select NCO Channel 6.
Select NCO Channel 7.
Select NCO Channel 8.
Select NCO Channel 9.
Select NCO Channel 10.
Select NCO Channel 11.
Select NCO Channel 12.
Select NCO Channel 13.
Select NCO Channel 14.
Select NCO Channel 15.
Rev. 0 | Page 102 of 136
Reset Access
0x0
R/W
R
R/W
R
R/W
R/W
R/W
Data Sheet
Addr.
0x0315
Name
DDC0 phase
control
AD9208
Bits Bit Name
[7:4] Reserved
Settings
[3:0] DDC0 phase update
index
0000
0001
0010
0011
0x0316
DDC0 Phase
Increment 0
0x0317 DDC0 Phase
Increment 1
0x0318 DDC0 Phase
Increment 2
0x0319 DDC0 Phase
Increment 3
0x031A DDC0 Phase
Increment 4
0x031B DDC0 Phase
Increment 5
0x031D DDC0 Phase Offset 0
0x031E DDC0 Phase Offset 1
0x031F DDC0 Phase Offset 2
0x0320 DDC0 Phase Offset 3
0x0321 DDC0 Phase Offset 4
0x0322 DDC0 Phase Offset 5
0x0327 DDC0 test enable
[7:0] DDC0 phase increment
[7:0]
[7:0] DDC0 phase increment
[15:8]
[7:0] DDC0 phase increment
[23:16]
[7:0] DDC0 phase increment
[31:24]
[7:0] DDC0 phase increment
[39:32]
[7:0] DDC0 phase increment
[47:40]
[7:0] DDC0 phase offset [7:0]
[7:0] DDC0 phase offset [15:8]
[7:0] DDC0 phase offset [23:16]
[7:0] DDC0 phase offset [31:24]
[7:0] DDC0 phase offset [39:32]
[7:0] DDC0 phase offset [47:40]
[7:3] Reserved
2
DDC0 Q output test
mode enable
0
1
1
0
Reserved
DDC0 I output test mode
enable
0
1
0x0330
DDC1 control
7
DDC1 mixer select
0
1
6
DDC1 gain select
0
1
[5:4] DDC1 intermediate
frequency (IF) mode
00
01
10
11
3
Description
Reserved.
Reset Access
0x0
R
Indexes the NCO channel whose phase and offset is updated.
The update method is based on the DDC phase update mode,
which can be continuous or require chip transfer.
Update NCO Channel 0.
Update NCO Channel 1.
Update NCO Channel 2.
Update NCO Channel 3.
FTW. Twos complement phase increment value for the NCO.
Complex mixing frequency = (DDC phase increment × fS)/248.
FTW. Twos complement phase increment value for the NCO.
Complex mixing frequency = (DDC phase increment × fS)/248.
FTW. Twos complement phase increment value for the NCO.
Complex mixing frequency = (DDC phase increment × fS)/248.
FTW. Twos complement phase increment value for the NCO.
Complex mixing frequency = (DDC phase increment × fS)/248.
FTW. Twos complement phase increment value for the NCO.
Complex mixing frequency = (DDC phase increment × fS)/248.
FTW. Twos complement phase increment value for the NCO.
Complex mixing frequency = (DDC phase increment × fS)/248.
Twos complement phase offset value for the NCO.
Twos complement phase offset value for the NCO.
Twos complement phase offset value for the NCO.
Twos complement phase offset value for the NCO.
Twos complement phase offset value for the NCO.
Twos complement phase offset value for the NCO.
Reserved.
Q samples always use the Test Mode B block. The test mode is
selected using the channel dependent Register 0x0550, Bits[3:0].
Test mode disabled.
Test mode enabled.
Reserved.
I samples always use the Test Mode A block. The test mode is
selected using the channel dependent Register 0x0550, Bits[3:0].
Test mode disabled.
Test mode enabled.
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
R/W
R/W
R/W
R/W
R/W
R/W
R
R/W
0x0
0x0
R
R/W
0x0
Real mixer (I and Q inputs must be from the same real channel).
Complex mixer (I and Q must be from separate, real and imaginary
quadrature ADC receive channels; analog demodulator).
Gain can be used to compensates for the 6 dB loss associated
0x0
with mixing an input signal down to baseband and filtering out
its negative component.
0 dB gain.
6 dB gain (multiply by 2).
0x0
R/W
R/W
Variable IF mode.
0 Hz IF mode.
fS Hz IF mode.
Test mode.
DDC1 complex to real
enable
0x0
0
1
R/W
Complex (I and Q) outputs contain valid data.
Real (I) output only. Complex to real enabled. Uses extra fS
mixing to convert to real.
Rev. 0 | Page 103 of 136
R/W
AD9208
Addr.
Name
Data Sheet
Bits Bit Name
[2:0] DDC1 decimation rate
select
Settings
Description
Decimation filter selection.
000
HB1 + HB2 filter selection: decimate by 2 (complex to real
enabled), or decimate by 4 (complex to real disabled).
HB1 + HB2 + HB3 filter selection: decimate by 4 (complex to
real enabled), or decimate by 8 (complex to real disabled).
HB1 + HB2 + HB3 + HB4 filter selection: decimate by 8
(complex to real enabled), or decimate by 16 (complex to real
disabled).
HB1 filter selection: decimate by 1 (complex to real enabled), or
decimate by 2 (complex to real disabled).
HB1 + TB2 filter selection: decimate by 3 (complex to real
enabled), or decimate by 6 (complex to real disabled).
HB1 + HB2 + TB2 filter selection: decimate by 6 (complex to real
enabled), or decimate by 12 (complex to real disabled).
HB1 + HB2 + HB3 + TB2 filter selection: decimate by 12 (complex
to real enabled), or decimate by 24 (complex to real disabled).
Decimation determined by Register 0x0331, Bits[7:4].
Only valid when Register 0x0310, Bits[2:0] = 3'b111.
0x0
001
010
011
100
101
110
111
0x0331
DDC1 input select
[7:4] DDC1 decimation rate
select
0
10
11
100
111
1000
1001
3
2
Reserved
DDC1 Q input select
0
1
1
0
Channel A.
Channel B.
Reserved.
Reserved
DDC1 I input select
0
1
0x0334
DDC1 NCO control
TB2 + HB4 + HB3 + HB2 + HB1 filter selection: decimate by 48
(complex to real disabled), or decimate by 24 (complex to real
enabled).
FB2 + HB1 filter selection: decimate by 10 (complex to real
disabled), or decimate by 5 (complex to real enabled).
FB2 + HB2 + HB1 filter selection: decimate by 20 (complex to
real disabled), or decimate by 10 (complex to real enabled).
FB2 + HB3 + HB2 + HB1 filter selection: decimate by 40 (complex
to real disabled), or decimate by 20 (complex to real enabled).
TB1 filter selection: decimate by 3 (decimate by 1.5 not supported).
FB2 + TB1 filter selection: decimate by 15 (decimate by 7.5 not
supported).
HB2 + FB2 + TB1 filter selection: decimate by 30 (decimate by
15 not supported).
Reserved.
[7:4] DDC1 NCO channel select
mode
0
1
10
11
100
101
110
1000
1001
1010
1011
Channel A.
Channel B.
For edge control, the internal counter wraps when the
Register 0x0334, Bits[3:0] value is reached.
Use Register 0x0314, Bits[3:0]
2'b0, GPIO_B0, GPIO_A0.
2'b0, GPIO_B1, GPIO_A1.
2'b00, GPIO_A1, GPIO_A0.
2'b00, GPIO_B1, GPIO_B0.
GPIO_B1, GPIO_A1, GPIO_B0, GPIO_A0.
GPIO_B1, GPIO_B0, GPIO_A1, GPIO_A0.
Increment internal counter when rising edge of the GPIO_A0 pin.
Increment internal counter when rising edge of the GPIO_A1 pin.
Increment internal counter when rising edge of the GPIO_B0 pin.
Increment internal counter when rising edge of the GPIO_B1 pin.
Rev. 0 | Page 104 of 136
Reset Access
0x0
R/W
R/W
0x0
0x1
R
R/W
0x0
0x1
R
R/W
0x0
R/W
Data Sheet
Addr.
0x0335
Name
DDC1 phase
control
AD9208
Bits Bit Name
[3:0] DDC1 NCO register map
channel select
Settings
Description
NCO channel select register map control
Reset Access
0x0
R/W
0
1
10
11
100
101
110
111
1000
1001
1010
1011
1100
1101
1110
1111
Select NCO Channel 0.
Select NCO Channel 1.
Select NCO Channel 2.
Select NCO Channel 3.
Select NCO Channel 4.
Select NCO Channel 5.
Select NCO Channel 6.
Select NCO Channel 7.
Select NCO Channel 8.
Select NCO Channel 9.
Select NCO Channel 10.
Select NCO Channel 11.
Select NCO Channel 12.
Select NCO Channel 13.
Select NCO Channel 14.
Select NCO Channel 15.
Reserved.
0x0
R
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
[7:4] Reserved
[3:0] DDC1 phase update
index
[7:0] DDC1 phase increment
[7:0]
[7:0] DDC1 phase increment
[15:8]
[7:0] DDC1 phase increment
[23:16]
[7:0] DDC1 phase increment
[31:24]
[7:0] DDC1 phase increment
[39:32]
[7:0] DDC1 phase increment
[47:40]
[7:0] DDC1 phase offset [7:0]
Indexes the NCO channel for which the phase and offset is to
be updated. The update method is based on the DDC phase
update mode, which can be continuous or require chip transfer.
Update NCO Channel 0.
Update NCO Channel 1.
Update NCO Channel 2.
Update NCO Channel 3.
FTW. Twos complement phase increment value for the NCO.
Complex mixing frequency = (DDC phase increment × fS)/248.
FTW. Twos complement phase increment value for the NCO.
Complex mixing frequency = (DDC phase increment × fS)/248.
FTW. Twos complement phase increment value for the NCO.
Complex mixing frequency = (DDC phase increment × fS)/248.
FTW. Twos complement phase increment value for the NCO.
Complex mixing frequency = (DDC phase increment × fS)/248.
FTW. Twos complement phase increment value for the NCO.
Complex mixing frequency = (DDC phase increment × fS)/248.
FTW. Twos complement phase increment value for the NCO.
Complex mixing frequency = (DDC phase increment × fS)/248.
Twos complement phase offset value for the NCO.
[7:0] DDC1 phase offset [15:8]
Twos complement phase offset value for the NCO.
0x0
R/W
[7:0] DDC1 phase offset [23:16]
Twos complement phase offset value for the NCO.
0x0
R/W
[7:0] DDC1 phase offset [31:24]
Twos complement phase offset value for the NCO.
0x0
R/W
[7:0] DDC1 phase offset [39:32]
Twos complement phase offset value for the NCO.
0x0
R/W
[7:0] DDC1 phase offset [47:40]
Twos complement phase offset value for the NCO.
0x0
R/W
[7:3] Reserved
2
DDC1 Q output test
mode enable
Reserved.
Q samples always use the Test Mode B block. The test mode is
selected using the channel dependent Register 0x0550, Bits[3:0].
Test mode disabled.
Test mode enabled.
Reserved.
I samples always use the Test Mode A block. The test mode is
selected using the channel dependent Register 0x0550, Bits[3:0].
Test mode disabled.
Test mode enabled.
0x0
0x0
R
R/W
0x0
0x0
R
R/W
0000
0001
0010
0011
0x0336
DDC1 Phase
Increment 0
0x0337 DDC1 Phase
Increment 1
0x0338 DDC1 Phase
Increment 2
0x0339 DDC1 Phase
Increment 3
0x033A DDC1 Phase
Increment 4
0x033B DDC1 Phase
Increment 5
0x033D DDC1 Phase
Offset 0
0x033E DDC1 Phase
Offset 1
0x033F DDC1 Phase
Offset 2
0x0340 DDC1 Phase
Offset 3
0x0341 DDC1 Phase
Offset 4
0x0342 DDC1 Phase
Offset 5
0x0347 DDC1 test enable
0
1
1
0
Reserved
DDC1 I output test mode
enable
0
1
Rev. 0 | Page 105 of 136
AD9208
Addr.
0x0350
Name
DDC2 control
Data Sheet
Bits
7
6
Bit Name
DDC2 mixer select
Settings
Description
0
1
Real mixer (I and Q inputs must be from the same real channel)
Complex mixer (I and Q must be from separate, real and imaginary
quadrature ADC receive channels; analog demodulator)
Gain can be used to compensates for the 6 dB loss associated
0x0
with mixing an input signal down to baseband and filtering out
its negative component.
0 dB gain.
6 dB gain (multiply by 2).
0x0
DDC2 gain select
0
1
[5:4] DDC2 intermediate
frequency (IF) mode
00
01
10
11
3
000
001
010
011
100
101
110
111
0x0351
DDC2 input select
[7:4] DDC2 decimation rate
select
0
10
11
100
3
2
Reserved
DDC2 Q input select
0
1
1
0
Reserved
DDC2 I input select
0
1
R/W
0x0
R/W
0x0
R/W
HB1 + HB2 filter selection: decimate by 2 (complex to real
enabled), or decimate by 4 (complex to real disabled).
HB1 + HB2 + HB3 filter selection: decimate by 4 (complex to
real enabled), or decimate by 8 (complex to real disabled).
HB1 + HB2 + HB3 + HB4 filter selection: decimate by 8
(complex to real enabled), or decimate by 16 (complex to real
disabled).
HB1 filter selection: decimate by 1 (complex to real enabled), or
decimate by 2 (complex to real disabled).
HB1 + TB2 filter selection: decimate by 3 (complex to real
enabled), or decimate by 6 (complex to real disabled).
HB1 + HB2 + TB2 filter selection: decimate by 6 (complex to real
enabled), or decimate by 12 (complex to real disabled).
HB1 + HB2 + HB3 + TB2 filter selection: decimate by 12 (complex to
real enabled), or decimate by 24 (complex to real disabled).
Decimation determined by Register 0x0351, Bits[7:4].
Only valid when Register 0x0310, Bits[2:0] = 3'b111.
0x0
R/W
Complex (I and Q) outputs contain valid data.
Real (I) output only. Complex to real enabled. Uses extra fS
mixing to convert to real.
Decimation filter selection.
[2:0] DDC2 decimation rate
select
R/W
Variable IF mode.
0 Hz IF mode.
fS Hz IF mode.
Test mode.
DDC2 complex to real
enable
0
1
Reset Access
0x0
R/W
TB2 + HB4 + HB3 + HB2 + HB1 filter selection: decimate by 48
(complex to real disabled), or decimate by 24 (complex to real
enabled).
FB2 + HB1 filter selection: decimate by 10 (complex to real
disabled), or decimate by 5 (complex to real enabled).
FB2 + HB2 + HB1 filter selection: decimate by 20 (complex to
real disabled), or decimate by 10 (complex to real enabled).
FB2 + HB3 + HB2 + HB1 filter selection: decimate by 40 (complex to
real disabled), or decimate by 20 (complex to real enabled).
Reserved.
0x0
0x0
Channel A.
Channel B.
Reserved.
0x0
0x0
Channel A.
Channel B.
Rev. 0 | Page 106 of 136
R
R/W
R
R/W
Data Sheet
Addr.
0x0354
0x0355
Name
DDC2 NCO control
DDC2 phase
control
AD9208
Bits Bit Name
Settings
[7:4] DDC2 NCO channel select
mode
0
1
10
11
100
101
110
1000
1001
1010
1011
[3:0] DDC2 NCO register map
channel select
0
1
10
11
100
101
110
111
1000
1001
1010
1011
1100
1101
1110
1111
[7:4] Reserved
Description
For edge control, the internal counter wraps when the
Register 0x0354, Bits[3:0] value is reached.
Use 0x0314[3:0]
2'b0, GPIO B0, GPIO A0.
2'b0, GPIO B1, GPIO A1.
2'b00, GPIO A1, GPIO A0.
2'b00, GPIO B1, GPIO B0.
GPIO B1, GPIO A1, GPIO B0, GPIO A0.
GPIO B1, GPIO B0, GPIO A1, GPIO A0.
Increment internal counter when rising edge of the GPIO_A0 pin.
Increment internal counter when rising edge of the GPIO_A1 pin.
Increment internal counter when rising edge of the GPIO_B0 pin.
Increment internal counter when rising edge of the GPIO_B1 pin.
NCO channel select register map control.
[3:0] DDC2 phase update
index
[7:0] DDC2 phase increment
[7:0]
[7:0] DDC2 phase increment
[15:8]
[7:0] DDC2 phase increment
[23:16]
[7:0] DDC2 phase increment
[31:24]
[7:0] DDC2 phase increment
[39:32]
[7:0] DDC2 phase increment
[47:40]
[7:0] DDC2 phase offset [7:0]
Indexes the NCO channel whose phase and offset gets
updated. The update method is based on the DDC phase
update mode, which can be continuous or require chip
transfer.
Update NCO Channel 0.
Update NCO Channel 1.
Update NCO Channel 2.
Update NCO Channel 3.
FTW. Twos complement phase increment value for the NCO.
Complex mixing frequency = (DDC phase increment × fS)/248.
FTW. Twos complement phase increment value for the NCO.
Complex mixing frequency = (DDC phase increment × fS)/248.
FTW. Twos complement phase increment value for the NCO.
Complex mixing frequency = (DDC phase increment × fS)/248.
FTW. Twos complement phase increment value for the NCO.
Complex mixing frequency = (DDC phase increment × fS)/248.
FTW. Twos complement phase increment value for the NCO.
Complex mixing frequency = (DDC phase increment × fS)/248.
FTW. Twos complement phase increment value for the NCO.
Complex mixing frequency = (DDC phase increment × fS)/248.
Twos complement phase offset value for the NCO.
[7:0] DDC2 phase offset [15:8]
0x0
R/W
0x0
R
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
Twos complement phase offset value for the NCO.
0x0
R/W
[7:0] DDC2 phase offset [23:16]
Twos complement phase offset value for the NCO.
0x0
R/W
[7:0] DDC2 phase offset [31:24]
Twos complement phase offset value for the NCO.
0x0
R/W
0000
0001
0010
0011
0x0356
DDC2 Phase
Increment 0
0x0357 DDC2 Phase
Increment 1
0x0358 DDC2 Phase
Increment 2
0x0359 DDC2 Phase
Increment 3
0x035A DDC2 Phase
Increment 4
0x035B DDC2 Phase
Increment 5
0x035D DDC2 Phase
Offset 0
0x035E DDC2 Phase
Offset 1
0x035F DDC2 Phase
Offset 2
0x0360 DDC2 Phase
Offset 3
Reset Access
0x0
R/W
Select NCO Channel 0.
Select NCO Channel 1.
Select NCO Channel 2.
Select NCO Channel 3.
Select NCO Channel 4.
Select NCO Channel 5.
Select NCO Channel 6.
Select NCO Channel 7.
Select NCO Channel 8.
Select NCO Channel 9.
Select NCO Channel 10.
Select NCO Channel 11.
Select NCO Channel 12.
Select NCO Channel 13.
Select NCO Channel 14.
Select NCO Channel 15.
Reserved.
Rev. 0 | Page 107 of 136
AD9208
Addr.
0x0361
0x0362
0x0367
Name
DDC2 Phase
Offset 4
DDC2 Phase
Offset 5
DDC2 test enable
Data Sheet
Bits Bit Name
[7:0] DDC2 phase offset [39:32]
Settings
Description
Twos complement phase offset value for the NCO.
Reset Access
0x0
R/W
[7:0] DDC2 phase offset [47:40]
Twos complement phase offset value for the NCO.
0x0
R/W
[7:3] Reserved
2
DDC2 Q output test
mode enable
Reserved.
Q samples always use the Test Mode B block. The test mode is
selected using the channel dependent Register 0x0550, Bits[3:0].
Test mode disabled.
Test mode enabled.
Reserved.
I samples always use the Test Mode A block. The test mode is
selected using the channel dependent Register 0x0550, Bits[3:0].
Test mode disabled.
Test mode enabled.
0x0
0x0
R
R/W
0x0
0x0
R
R/W
0x0
Real mixer (I and Q inputs must be from the same real channel).
Complex mixer (I and Q must be from separate, real and imaginary
quadrature ADC receive channels; analog demodulator).
0x0
Gain can be used to compensate for the 6 dB loss associated
with mixing an input signal down to baseband and filtering out
its negative component.
0 dB gain.
6 dB gain (multiply by 2)
0x0
R/W
0
1
1
0
Reserved
DDC2 I output test mode
enable
0
1
0x0370
DDC3 control
7
DDC3 mixer select
0
1
6
DDC3 gain select
0
1
[5:4] DDC3 intermediate
frequency (IF) mode
00
01
10
11
3
Complex (I and Q) outputs contain valid data.
Real (I) output only. complex to real enabled. Uses extra fS
mixing to convert to real.
Decimation filter selection.
[2:0] DDC3 decimation rate
select
000
001
010
011
100
101
110
111
R/W
Variable IF mode.
0 Hz IF mode.
fS Hz IF mode.
Test mode.
DDC3 complex to real
enable
0
1
R/W
HB1 + HB2 filter selection: decimate by 2 (complex to real
enabled), or decimate by 4 (complex to real disabled).
HB1 + HB2 + HB3 filter selection: decimate by 4 (complex to
real enabled), or decimate by 8 (complex to real disabled).
HB1 + HB2 + HB3 + HB4 filter selection: decimate by 8
(complex to real enabled), or decimate by 16 (complex to real
disabled).
HB1 filter selection: decimate by 1 (complex to real enabled), or
decimate by 2 (complex to real disabled).
HB1 + TB2 filter selection: decimate by 3 (complex to real
enabled), or decimate by 6 (complex to real disabled).
HB1 + HB2 + TB2 filter selection: decimate by 6 (complex to real
enabled), or decimate by 12 (complex to real disabled).
HB1 + HB2 + HB3 + TB2 filter selection: decimate by 12 (complex to
real enabled), or decimate by 24 (complex to real disabled).
Decimation determined by Register 0x0371, Bits[7:4].
Rev. 0 | Page 108 of 136
0x0
R/W
0x0
R/W
Data Sheet
Addr.
0x0371
Name
DDC3 input select
AD9208
Bits Bit Name
[7:4] DDC3 decimation rate
select
Settings
Description
Only valid when Register 0x0310, Bits[2:0] = 3'b111.
0
TB2 + HB4 + HB3 + HB2 + HB1 filter selection: decimate by 48
(complex to real disabled), or decimate by 24 (complex to real
enabled).
FB2 + HB1 filter selection: decimate by 10 (complex to real
disabled), or decimate by 5 (complex to real enabled)
FB2 + HB2 + HB1 filter selection: decimate by 20 (complex to real
disabled), or decimate by 10 (complex to real enabled)
FB2 + HB3 + HB2 + HB1 filter selection: decimate by 40 (complex
to real disabled), or decimate by 20 (complex to real enabled)
Reserved.
10
11
100
3
2
Reserved
DDC3 Q input select
0
1
1
0
Channel A.
Channel B.
Reserved.
Reserved
DDC3 I input select
0
1
0x0374
DDC3 NCO control
[7:4] DDC3 NCO channel select
mode
0
1
10
11
100
101
110
1000
1001
1010
1011
[3:0] DDC3 NCO register map
channel select
0
1
10
11
100
101
110
111
1000
1001
1010
1011
1100
1101
1110
1111
0x0375
DDC3 phase
control
[7:4] Reserved
[3:0] DDC3 phase update
index
0000
0001
0010
0011
Channel A.
Channel B.
For edge control, the internal counter wraps when the
Register 0x0374, Bits[3:0] value is reached.
Use Register 0x0314, Bits[3:0].
2'b0, GPIO B0, GPIO A0.
2'b0, GPIO B1, GPIO A1.
2'b00, GPIO A1, GPIO A0.
2'b00, GPIO B1, GPIO B0.
GPIO B1, GPIO A1, GPIO B0, GPIO A0.
GPIO B1, GPIO B0, GPIO A1, GPIO A0.
Increment internal counter when rising edge of GPIO_A0 pin.
Increment internal counter when rising edge of GPIO_A1 pin.
Increment internal counter when rising edge of GPIO_B0 pin.
Increment internal counter when rising edge of GPIO_B1 pin.
NCO channel select register map control.
Select NCO Channel 0.
Select NCO Channel 1.
Select NCO Channel 2.
Select NCO Channel 3.
Select NCO Channel 4.
Select NCO Channel 5.
Select NCO Channel 6.
Select NCO Channel 7.
Select NCO Channel 8.
Select NCO Channel 9.
Select NCO Channel 10.
Select NCO Channel 11.
Select NCO Channel 12.
Select NCO Channel 13.
Select NCO Channel 14.
Select NCO Channel 15.
Reserved.
Indexes the NCO channel whose phase and offset gets
updated. The update method is based on the DDC phase
update mode, which can be continuous or require chip
transfer.
Update NCO Channel 0.
Update NCO Channel 1.
Update NCO Channel 2.
Update NCO Channel 3.
Rev. 0 | Page 109 of 136
Reset Access
0x0
R/W
0x0
0x1
R
R/W
0x0
0x1
R
R/W
0x0
R/W
0x0
R/W
0x0
R
0x0
R/W
AD9208
Addr.
0x0376
Name
DDC3 Phase
Increment 0
0x0377 DDC3 Phase
Increment 1
0x0378 DDC3 Phase
Increment 2
0x0379 DDC3 Phase
Increment 3
0x037A DDC3 Phase
Increment 4
0x037B DDC3 Phase
Increment 5
0x037D DDC3 Phase
Offset 0
0x037E DDC3 Phase
Offset 1
0x037F DDC3 Phase
Offset 2
0x0380 DDC3 Phase
Offset 3
0x0381 DDC3 Phase
Offset 4
0x0382 DDC3 Phase
Offset 5
0x0387 DDC3 test enable
Data Sheet
Bits Bit Name
[7:0] DDC3 phase increment
[7:0]
[7:0] DDC3 phase increment
[15:8]
[7:0] DDC3 phase increment
[23:16]
[7:0] DDC3 phase increment
[31:24]
[7:0] DDC3 phase increment
[39:32]
[7:0] DDC3 phase increment
[47:40]
[7:0] DDC3 phase offset [7:0]
Settings
Description
FTW. Twos complement phase increment value for the NCO.
Complex mixing frequency = (DDC phase increment × fS)/248.
FTW. Twos complement phase increment value for the NCO.
Complex mixing frequency = (DDC phase increment × fS)/248
FTW. Twos complement phase increment value for the NCO.
Complex mixing frequency = (DDC phase increment × fS)/248.
FTW. Twos complement phase increment value for the NCO.
Complex mixing frequency = (DDC phase increment × fS)/248.
FTW. Twos complement phase increment value for the NCO.
Complex mixing frequency = (DDC phase increment × fS)/248.
FTW. Twos complement phase increment value for the NCO.
Complex mixing frequency = (DDC phase increment × fS)/248.
Twos complement phase offset value for the NCO.
Reset Access
0x0
R/W
[7:0] DDC3 phase offset [15:8]
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
Twos complement phase offset value for the NCO.
0x0
R/W
[7:0] DDC3 phase offset [23:16]
Twos complement phase offset value for the NCO.
0x0
R/W
[7:0] DDC3 phase offset [31:24]
Twos complement phase offset value for the NCO.
0x0
R/W
[7:0] DDC3 phase offset [39:32]
Twos complement phase offset value for the NCO.
0x0
R/W
[7:0] DDC3 phase offset [47:40]
Twos complement phase offset value for the NCO.
0x0
R/W
[7:3] Reserved
2
DDC3 Q output test
mode enable
Reserved.
Q samples always use the Test Mode B block. The test mode is
selected using the channel dependent Register 0x0550, Bits[3:0].
Test mode disabled.
Test mode enabled.
Reserved.
I samples always use the Test Mode A block. The test mode is
selected using the channel dependent Register 0x0550, Bits[3:0].
Test mode disabled.
Test mode enabled.
Numerator correction term for Modulus Phase Accumulator A.
0x0
0x0
R
R/W
0x0
0x0
R
R/W
0x0
R/W
[7:0] DDC0 Phase Increment
Fractional A [15:8]
Numerator correction term for Modulus Phase Accumulator A.
0x0
R/W
[7:0] DDC0 Phase Increment
Fractional A [23:16]
Numerator correction term for Modulus Phase Accumulator A.
0x0
R/W
[7:0] DDC0 Phase Increment
Fractional A [31:24]
Numerator correction term for Modulus Phase Accumulator A.
0x0
R/W
[7:0] DDC0 Phase Increment
Fractional A [39:32]
Numerator correction term for Modulus Phase Accumulator A.
0x0
R/W
[7:0] DDC0 Phase Increment
Fractional A [47:40]
Numerator correction term for Modulus Phase Accumulator A.
0x0
R/W
[7:0] DDC0 Phase Increment
Fractional B [7:0]
Denominator correction term for Modulus Phase Accumulator B.
0x0
R/W
[7:0] DDC0 Phase Increment
Fractional B [15:8]
Denominator correction term for Modulus Phase Accumulator B.
0x0
R/W
[7:0] DDC0 Phase Increment
Fractional B [23:16]
Denominator correction term for Modulus Phase Accumulator B.
0x0
R/W
[7:0] DDC0 Phase Increment
Fractional B [31:24]
Denominator correction term for Modulus Phase Accumulator B.
0x0
R/W
0
1
1
0
Reserved
DDC3 I output test mode
enable
0
1
0x0390
DDC0 Phase
Increment
Fractional A0
0x0391 DDC0 Phase
Increment
Fractional A1
0x0392 DDC0 Phase
Increment
Fractional A2
0x0393 DDC0 Phase
Increment
Fractional A3
0x0394 DDC0 Phase
Increment
Fractional A4
0x0395 DDC0 Phase
Increment
Fractional A5
0x0398 DDC0 Phase
Increment
Fractional B0
0x0399 DDC0 Phase
Increment
Fractional B1
0x039A DDC0 Phase
Increment
Fractional B2
0x039B DDC0 Phase
Increment
Fractional B3
[7:0] DDC0 Phase Increment
Fractional A [7:0]
Rev. 0 | Page 110 of 136
Data Sheet
Addr.
0x039C
0x039D
0x03A0
0x03A1
0x03A2
0x03A3
0x03A4
0x03A5
0x03A8
0x03A9
0x03AA
0x03AB
0x03AC
0x03AD
0x03B0
0x03B1
0x03B2
0x03B3
0x03B4
0x03B5
0x03B8
0x03B9
Name
DDC0 Phase
Increment
Fractional B4
DDC0 Phase
Increment
Fractional B5
DDC1 Phase
Increment
Fractional A0
DDC1 Phase
Increment
Fractional A1
DDC1 Phase
Increment
Fractional A2
DDC1 Phase
Increment
Fractional A3
DDC1 Phase
Increment
Fractional A4
DDC1 Phase
Increment
Fractional A5
DDC1 Phase
Increment
Fractional B0
DDC1 Phase
Increment
Fractional B1
DDC1 Phase
Increment
Fractional B2
DDC1 Phase
Increment
Fractional B3
DDC1 Phase
Increment
Fractional B4
DDC1 Phase
Increment
Fractional B5
DDC2 Phase
Increment
Fractional A0
DDC2 Phase
Increment
Fractional A1
DDC2 Phase
Increment
Fractional A2
DDC2 Phase
Increment
Fractional A3
DDC2 Phase
Increment
Fractional A4
DDC2 Phase
Increment
Fractional A5
DDC2 Phase
Increment
Fractional B0
DDC2 Phase
Increment
Fractional B1
AD9208
Bits Bit Name
[7:0] DDC0 Phase Increment
Fractional B [39:32]
Settings
Description
Denominator correction term for Modulus Phase Accumulator B.
Reset Access
0x0
R/W
[7:0] DDC0 Phase Increment
Fractional B [47:40]
Denominator correction term for Modulus Phase Accumulator B.
0x0
R/W
[7:0] DDC1 Phase Increment
Fractional A [7:0]
Numerator correction term for Modulus Phase Accumulator A.
0x0
R/W
[7:0] DDC1 Phase Increment
Fractional A [15:8]
Numerator correction term for Modulus Phase Accumulator A.
0x0
R/W
[7:0] DDC1 Phase Increment
Fractional A [23:16]
Numerator correction term for Modulus Phase Accumulator A.
0x0
R/W
[7:0] DDC1 Phase Increment
Fractional A [31:24]
Numerator correction term for Modulus Phase Accumulator A.
0x0
R/W
[7:0] DDC1 Phase Increment
Fractional A [39:32]
Numerator correction term for Modulus Phase Accumulator A.
0x0
R/W
[7:0] DDC1 Phase Increment
Fractional A [47:40]
Numerator correction term for Modulus Phase Accumulator A.
0x0
R/W
[7:0] DDC1 Phase Increment
Fractional B [7:0]
Denominator correction term for Modulus Phase Accumulator B.
0x0
R/W
[7:0] DDC1 Phase Increment
Fractional B [15:8]
Denominator correction term for Modulus Phase Accumulator B.
0x0
R/W
[7:0] DDC1 Phase Increment
Fractional B [23:16]
Denominator correction term for Modulus Phase Accumulator B.
0x0
R/W
[7:0] DDC1 Phase Increment
Fractional B [31:24]
Denominator correction term for Modulus Phase Accumulator B.
0x0
R/W
[7:0] DDC1 Phase Increment
Fractional B [39:32]
Denominator correction term for Modulus Phase Accumulator B.
0x0
R/W
[7:0] DDC1 Phase Increment
Fractional B [47:40]
Denominator correction term for Modulus Phase Accumulator B.
0x0
R/W
[7:0] DDC2 Phase Increment
Fractional A [7:0]
Numerator correction term for Modulus Phase Accumulator A.
0x0
R/W
[7:0] DDC2 Phase Increment
Fractional A [15:8]
Numerator correction term for Modulus Phase Accumulator A.
0x0
R/W
[7:0] DDC2 Phase Increment
Fractional A [23:16]
Numerator correction term for Modulus Phase Accumulator A.
0x0
R/W
[7:0] DDC2 Phase Increment
Fractional A [31:24]
Numerator correction term for Modulus Phase Accumulator A.
0x0
R/W
[7:0] DDC2 Phase Increment
Fractional A [39:32]
Numerator correction term for Modulus Phase Accumulator A.
0x0
R/W
[7:0] DDC2 Phase Increment
Fractional A [47:40]
Numerator correction term for Modulus Phase Accumulator A.
0x0
R/W
[7:0] DDC2 Phase Increment
Fractional B [7:0]
Denominator correction term for Modulus Phase Accumulator B.
0x0
R/W
[7:0] DDC2 Phase Increment
Fractional B [15:8]
Denominator correction term for Modulus Phase Accumulator B.
0x0
R/W
Rev. 0 | Page 111 of 136
AD9208
Data Sheet
Addr.
Name
Bits Bit Name
[7:0] DDC2 Phase Increment
0x03BA DDC2 Phase
Fractional B [23:16]
Increment
Fractional B2
[7:0] DDC2 Phase Increment
0x03BB DDC2 Phase
Fractional B [31:24]
Increment
Fractional B3
0x03BC DDC2 Phase
[7:0] DDC2 Phase Increment
Fractional B [39:32]
Increment
Fractional B4
0x03BD DDC2 Phase
[7:0] DDC2 Phase Increment
Fractional B [47:40]
Increment
Fractional B5
0x03C0 DDC3 Phase
[7:0] DDC3 Phase Increment
Increment
Fractional A [7:0]
Fractional A0
0x03C1 DDC3 Phase
[7:0] DDC3 Phase Increment
Increment
Fractional A [15:8]
Fractional A1
0x03C2 DDC3 Phase
[7:0] DDC3 Phase Increment
Increment
Fractional A [23:16]
Fractional A2
0x03C3 DDC3 Phase
[7:0] DDC3 Phase Increment
Increment
Fractional A [31:24]
Fractional A3
0x03C4 DDC3 Phase
[7:0] DDC3 Phase Increment
Increment
Fractional A [39:32]
Fractional A4
0x03C5 DDC3 Phase
[7:0] DDC3 Phase Increment
Increment
Fractional A [47:40]
Fractional A5
[7:0] DDC3 Phase Increment
0x03C8 DDC3 Phase
Fractional B [7:0]
Increment
Fractional B0
[7:0] DDC3 Phase Increment
0x03C9 DDC3 Phase
Fractional B [15:8]
Increment
Fractional B1
[7:0] DDC3 Phase Increment
0x03CA DDC3 Phase
Fractional B [23:16]
Increment
Fractional B2
0x03CB DDC3 Phase
[7:0] DDC3 Phase Increment
Increment
Fractional B [31:24]
Fractional B3
0x03CC DDC3 Phase
[7:0] DDC3 Phase Increment
Increment
Fractional B [39:32]
Fractional B4
0x03CD DDC3 Phase
[7:0] DDC3 Phase Increment
Increment
Fractional B [47:40]
Fractional B5
Digital Outputs and Test Modes Registers
0x0550 ADC test mode
7
User pattern selection
control (local)
Settings
0
1
6
5
Reserved
Reset PN long generator
0
1
Description
Denominator correction term for Modulus Phase Accumulator B.
Reset Access
0x0
R/W
Denominator correction term for Modulus Phase Accumulator B.
0x0
R/W
Denominator correction term for Modulus Phase Accumulator B.
0x0
R/W
Denominator correction term for Modulus Phase Accumulator B.
0x0
R/W
Numerator correction term for Modulus Phase Accumulator A.
0x0
R/W
Numerator correction term for Modulus Phase Accumulator A.
0x0
R/W
Numerator correction term for Modulus Phase Accumulator A.
0x0
R/W
Numerator correction term for Modulus Phase Accumulator A.
0x0
R/W
Numerator correction term for Modulus Phase Accumulator A.
0x0
R/W
Numerator correction term for Modulus Phase Accumulator A.
0x0
R/W
Denominator correction term for Modulus Phase Accumulator B.
0x0
R/W
Denominator correction term for Modulus Phase Accumulator B.
0x0
R/W
Denominator correction term for Modulus Phase Accumulator B.
0x0
R/W
Denominator correction term for Modulus Phase Accumulator B.
0x0
R/W
Denominator correction term for Modulus Phase Accumulator B.
0x0
R/W
Denominator correction term for Modulus Phase Accumulator B.
0x0
R/W
0x0
Test mode user pattern selection. This bit is only used when
Register 0x0550, Bits[3:0] = 4’b1000 (user input mode).
Otherwise, it is ignored. User Pattern 1 is found in the User
Pattern 1 MSB register (Register 0x0552) and the User Pattern 1
LSB (Register 0x0551) registers. User Pattern 2 is found in the
User Pattern 2 MSB register (Register 0x0554) and the User
Patter 2 LSB (Register 0x0553) register, and so on.
Continuous/repeat pattern. Place each user pattern (1, 2, 3, and
4) on the output for 1 clock cycle and then repeat. (Output User
Pattern 1, 2, 3, 4, 1, 2, 3, 4, 1, 2, 3, 4, and so on.)
Single pattern. Place each user pattern (1, 2, 3, and 4) on the
output for 1 clock cycle and then output all zeros. (Output User
Pattern 1, 2, 3, 4, and then output all zeros)
Reserved.
0x0
Test mode long pseudorandom number test generator reset.
0x0
Long PN enabled.
Long PN held in reset.
R/W
Rev. 0 | Page 112 of 136
R
R/W
Data Sheet
Addr.
Name
AD9208
Bits
4
Bit Name
Reset PN short generator
Settings
0
1
[3:0] Test mode selection
0000
0001
0010
0011
0100
0101
0110
0111
1000
1111
0x0551
0x0552
0x0553
0x0554
0x0555
0x0556
0x0557
0x0558
0x0559
User Pattern 1 LSB
User Pattern 1 MSB
User Pattern 2 LSB
User Pattern 2 MSB
User Pattern 3 LSB
User Pattern 3 MSB
User Pattern 4 LSB
User Pattern 4 MSB
Output Mode
Control 1
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:4]
User Pattern 1 [7:0]
User Pattern 1 [15:8]
User Pattern 2 [7:0]
User Pattern 2 [15:8]
User Pattern 3 [7:0]
User Pattern 3 [15:8]
User Pattern 4 [7:0]
User Pattern 4 [15:8]
Converter control Bit 1
selection
0000
0001
0010
0011
0101
Description
Test mode short pseudorandom number test generator reset.
Short PN enabled.
Short PN held in reset.
Test mode generation selection.
Off (normal operation).
Midscale short.
Positive full scale.
Negative full scale.
Alternating checker board.
PN sequence (long).
PN sequence (short).
1/0 word toggle.
User pattern test mode (used with Register 0x0550, Bit 7 and
the User Pattern 1, User Pattern 2, User Pattern 3, and User
Pattern 4 registers).
Ramp output.
User Test Pattern 1 least significant byte.
User Test Pattern 1 least significant byte.
User Test Pattern 2 least significant byte.
User Test Pattern 2 least significant byte.
User Test Pattern 3 least significant bits.
User Test Pattern 3 least significant bits.
User Test Pattern 4 least significant bits.
User Test Pattern 4 least significant bits.
0x0
R/W
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
0x0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
0x0
R/W
0x0
R
0x1
R/W
0x0
0x0
R/W
R/W
0x1
Offset binary.
Twos complement (default)
Overrange clear bits (one bit for each virtual converter). Writing 0x0
a 1 to the overrange clear bit clears the corresponding
overrange sticky bit.
Overrange bit enabled.
Overrange bit cleared.
R/W
Tie low (1'b0).
Overrange bit.
Signal monitor bit .
Fast detect (FD) bit.
SYSREF.
[3:0] Converter control Bit 0
selection
0000
0001
0010
0011
0101
0x055A Output Mode
Control 2
[7:4] Reserved
Tie low (1'b0).
Overrange bit.
Signal monitor bit.
Fast detect (FD) bit.
SYSREF.
Reserved.
[3:0] Converter control Bit 2
selection
0000
0001
0010
0011
0101
0x0561
Out sample mode
[7:3] Reserved
2
Sample invert
0
1
00
01
Out overrange
clear
[7:0] Data format overrange
clear
0
1
Tie low (1'b0).
Overrange bit.
Signal monitor bit.
Fast detect (FD) bit.
SYSREF.
Reserved.
ADC sample data is not inverted.
ADC sample data is inverted.
[1:0] Data format select
0x0562
Reset Access
0x0
R/W
Rev. 0 | Page 113 of 136
R/W
AD9208
Addr.
0x0563
Name
Out overrange
status
Data Sheet
Bits Bit Name
[7:0] Data format overrange
Settings
0
1
0x0564
0x056E
0x056F
Out channel select
PLL control
PLL status
[7:1] Reserved
0
Converter channel swap
control
0
1
Normal channel ordering.
Channel swap enabled.
0000
0001
0011
0101
Lane rate = 6.75 Gbps to 13.5 Gbps.
Lane rate = 3.375 Gbps to 6.75 Gbps.
Lane rate = 13.5 Gbps to 15.5 Gbps.
Lane rate = 1.6875 Gbps to 3.375 Gbps.
Reserved.
[7:4] JESD204B lane rate control
[3:0] Reserved
7
PLL lock status
0
1
[6:4] Reserved
3
PLL loss of lock
1
0x0570
[2:0] Reserved
fS × 4 configuration [7:0]
0xFE
0xFF
0x0571
JESD204B Link
Control 1
Description
Overrange sticky bit status (one bit for each virtual converter).
Writing a 1 to the overrange clear bit clears the corresponding
overrange sticky bit.
No overrange occurred.
Overrange occurred.
Reserved.
7
6
5
4
Standby mode
Standby mode forces zeros for all converter samples.
Standby mode forces code group synchronization (K28.5
characters).
0
1
Disable.
Enable.
0
1
JESD204B test samples disabled.
JESD204B test samples enabled; long transport layer test
sample sequence (as specified in JESD204B Section 5.1.6.3)
sent on all link lanes.
0
1
Disable FACI uses /K28.7/.
Enable FACI uses /K28.3/ and /K28.7/.
00
Initial lane alignment sequence disabled (JESD204B
Section 5.3.3.5).
Initial lane alignment sequence enabled (JESD204B Section 5.3.3.5).
Initial lane alignment sequence always on test mode. JESD204B
data link layer test mode where repeated lane alignment sequence
(as specified in JESD204B Section 5.3.3.8.2) sent on all lanes.
Tail bit(t) PN
Long transport layer test
Lane synchronization
[3:2] ILAS sequence mode
1
FACI
0
1
0x0
0x0
R
R/W
0x3
R/W
0x0
0x0
R
R
Not locked.
Locked.
Reserved.
0x0
Loss of lock sticky bit.
Indicate a loss of lock has occurred at some time. Cleared by
setting Register 0x0571, Bit 0.
Reserved
See the fS × 4 Mode section.
0xFF
L = 8, M = 2, F = 2, S = 4, N’ = 16, N = 16, CS = 0, CF = 0, HD = 0;
fS × 4 mode enabled.
fS × 4 mode disabled. L, M, and F set by Register 0x058B, Bits[4:0],
Register 0x58E, Bits[7:0], and Register 0x058C, Bits[7:0], respectively.
0x0
0
1
01
11
Reset Access
0x0
R
Frame alignment character insertion enabled (JESD204B
Section 5.3.3.4).
Frame alignment character insertion disabled. For debug only
(JESD204B Section 5.3.3.4).
Rev. 0 | Page 114 of 136
R
R/W
R/W
0x0
R/W
0x0
R/W
0x1
R/W
0x1
R/W
0x0
R/W
Data Sheet
Addr.
Name
AD9208
Bits
0
Bit Name
Link control
Settings
Description
0
JESD204B serial transmit link enabled. Transmission of the
/K28.5/ characters for code group synchronization is controlled
by the SYNC~ signal.
JESD204B serial transmit link powered down (held in reset and
clock gated).
1
0x0572
JESD204B Link
Control 2
[7:6] SYNCINB± pin control
5
4
3
2
1
0x0573
JESD204B Link
Control 3
00
10
11
Normal mode.
Ignore SYNCINB± (force CGS).
Ignore SYNCINB± (force ILAS/user data).
0
1
SYNCINB± pin not inverted.
SYNCINB± pin inverted.
0
1
LVDS differential pair SYNC~ input.
CMOS single-ended SYNC~ input. SYNCINB+ used.
Reserved.
SYNCINB± pin invert
SYNCINB± pin type
Reserved
8-bit/10-bit bypass
0
1
8-bit/10-bit enabled.
8-bit/10-bit bypassed (most significant 2 bits are 0).
0
1
Normal.
Invert a, b, c, d, e, f, g, h, I, and j symbols.
Reserved.
8-bit/10-bit bit invert
0
Reserved
[7:6] Checksum mode
00
10
11
Checksum is the sum of all 8-bit registers in the link
configuration table.
Checksum is the sum of all individual link configuration fields
(LSB aligned).
Checksum is disabled (set to zero). For test purposes only.
Unused.
0
1
10
N' sample input.
10-bit data at 8-bit/10-bit output (for PHY testing).
8-bit data at scrambler input.
01
[5:4] Test injection point
[3:0] JESD204B test mode
patterns
0
1
10
11
100
101
110
111
1000
1110
1111
Normal operation (test mode disabled).
Alternating checkerboard.
1/0 word toggle.
31-bit pseudorandom number (PN) sequence: x31 + x28 + 1.
23-bit PN sequence: x23 + x18 + 1.
15-bit PN sequence: x15 + x14 + 1.
9-bit PN sequence: x9 + x5 + 1.
7-bit PN sequence: x7 + x6 + 1.
Ramp output.
Continuous/repeat user test.
Single user test.
Rev. 0 | Page 115 of 136
Reset Access
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
0x0
R
R/W
0x0
R/W
0x0
0x0
R/W
R/W
0x0
R/W
0x0
R/W
AD9208
Addr.
0x0574
Name
JESD204B Link
Control 4
Data Sheet
Bits Bit Name
[7:4] ILAS delay
Settings
Description
0
1
10
11
100
101
110
111
1000
1001
1010
1011
1100
1101
1110
1111
Transmit ILAS on first LMFC after SYNCINB± deasserted.
Transmit ILAS on second LMFC after SYNCINB± deasserted.
Transmit ILAS on third LMFC after SYNCINB± deasserted.
Transmit ILAS on fourth LMFC after SYNCINB± deasserted.
Transmit ILAS on fifth LMFC after SYNCINB± deasserted.
Transmit ILAS on sixth LMFC after SYNCINB± deasserted.
Transmit ILAS on seventh LMFC after SYNCINB± deasserted.
Transmit ILAS on eighth LMFC after SYNCINB± deasserted.
Transmit ILAS on ninth LMFC after SYNCINB± deasserted.
Transmit ILAS on tenth LMFC after SYNCINB± deasserted.
Transmit ILAS on eleventh LMFC after SYNCINB± deasserted.
Transmit ILAS on twelfth LMFC after SYNCINB± deasserted.
Transmit ILAS on thirteenth LMFC after SYNCINB± deasserted.
Transmit ILAS on fourteenth LMFC after SYNCINB± deasserted.
Transmit ILAS on fifteenth LMFC after SYNCINB± deasserted.
Transmit ILAS on sixteenth LMFC after SYNCINB± deasserted.
Reserved.
3
Reserved
[2:0] Link layer test mode
0x0
0x0
R
R/W
0x0
R
0x0
R/W
[7:0] JESD204B Tx DID value
Local multiframe clock (LMFC) phase offset value (in frame
clocks). Refer to the Deterministic Latency section.
JESD204B serial device identification (DID) number.
0x0
R/W
[7:4] Reserved
Reserved.
0x0
R
[3:0] JESD204B Tx BID value
0x0
R/W
[7:5] Reserved
JESD204B serial bank identification (BID) number (extension to
DID).
Reserved.
0x0
R
[4:0] Lane 0 LID value
[7:5] Reserved
JESD204B serial lane identification (LID) number for Lane 0.
Reserved.
0x0
0x0
R/W
R
[4:0] Lane 1 LID value
[7:5] Reserved
JESD204B serial lane identification (LID) number for Lane 1.
Reserved.
0x1
0x0
R/W
R
[4:0] Lane 2 LID value
[7:5] Reserved
JESD204B serial lane identification (LID) number for Lane 2.
Reserved.
0x2
0x0
R/W
R
[4:0] Lane 3 LID value
[7:5] Reserved
JESD204B serial lane identification (LID) number for Lane 3.
Reserved.
0x3
0x0
R/W
R
[4:0] Lane 4 LID value
[7:5] Reserved
JESD204B serial lane identification (LID) number for Lane 4.
Reserved.
0x4
0x0
R/W
R
[4:0] Lane 5 LID value
[7:5] Reserved
JESD204B serial lane identification (LID) number for Lane 5.
Reserved.
0x5
0x0
R/W
R
[4:0] Lane 6 LID value
[7:5] Reserved
JESD204B serial lane identification (LID) number for Lane 6.
Reserved.
0x6
0x0
R/W
R
[4:0] Lane 7 LID value
JESD204B serial lane identification (LID) number for Lane 7.
0x7
R/W
000
001
010
011
100
101
110
111
0x0578
JESD204B LMFC
offset
[7:5] Reserved
[4:0] LMFC phase offset value
0x0580
0x0581
JESD204B DID
configuration
JESD204B BID
configuration
0x0583
JESD204B LID0
configuration
0x0584
JESD204B LID1
configuration
0x0585
JESD204B LID2
configuration
0x0586
JESD204B LID3
configuration
0x0587
JESD204B LID4
configuration
0x0588
JESD204B LID5
configuration
0x0589
JESD204B LID6
configuration
0x058A JESD204B LID7
configuration
Reset Access
0x0
R/W
Normal operation (link layer test mode disabled).
Continuous sequence of /D21.5/ characters.
Reserved.
Reserved.
Modified RPAT test sequence.
JSPAT test sequence.
JTSPAT test sequence.
Reserved.
Reserved.
Rev. 0 | Page 116 of 136
Data Sheet
Addr.
0x058B
Name
JESD204B
scrambling and
number lanes (L)
configuration
AD9208
Bits
7
Bit Name
JESD204B scrambling
(SCR)
Settings
Description
0
1
JESD204B scrambler disabled (SCR = 0).
JESD204B scrambler enabled (SCR = 1).
Reserved.
[6:5] Reserved
[4:0] JESD204B lanes (L)
0x0
0x1
0x3
0x7
0x058C
JESD204B link
number of octets
per frames (F)
[7:0] JESD204B F configuration
0
1
10
11
101
111
1111
0x058D JESD204B link
number of frames
per multiframe (K)
[7:5] Reserved
JESD204B link
number of
converters (M)
[7:0] JESD204B M
configuration
0
1
11
111
0x058F
F = 1.
F = 2.
F = 3.
F = 4.
F = 6.
F = 8.
F = 16.
Reserved.
0x0
0x7
R
R/W
0x0
R/W
0x0
R
0x1F
JESD204B number of frames per multiframe (K = JESD204B K
configuration + 1). Only values where F × K is divisible by 4 can
be used.
JESD204B number of converters per link/device (M = JESD204B 0x1
M configuration).
[4:0] JESD204B K configuration
0x058E
One lane per link (L = 1).
Two lanes per link (L = 2).
Four lanes per link (L = 4).
Eight lanes per Link (L = 8).
JESD204B number of octets per frame (F = JESD204B
F configuration + 1)
Reset Access
0x1
R/W
5
Reserved
[4:0] ADC converter resolution
(N)
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
R/W
Link connected to one virtual converter (M = 1).
Link connected to two virtual converters (M = 2).
Link connected to four virtual converters (M = 4).
Link connected to eight virtual converters (M = 8).
JESD204B number [7:6] Number of control bits
(CS) per sample
of control bits (CS)
and ADC resolution
(N)
0
1
10
11
R/W
No control bits (CS = 0).
1 control bit (CS = 1), Control Bit 2 only.
2 control bits (CS = 2), Control Bit 2 and Control Bit 1 only.
3 control bits (CS = 3), all control bits (Control Bit 2, Control Bit 1,
and Control Bit 0).
Reserved.
N = 7-bit resolution.
N = 8-bit resolution.
N = 9-bit resolution.
N = 10-bit resolution.
N = 11-bit resolution.
N = 12-bit resolution.
N = 13-bit resolution.
N = 14-bit resolution.
N = 15-bit resolution.
N = 16-bit resolution.
Rev. 0 | Page 117 of 136
0x0
R/W
0x0
0xF
R
R/W
AD9208
Addr.
0x0590
Name
JESD204B SCV NP
configuration
Data Sheet
Bits Bit Name
[7:5] Subclass support
Settings
Description
000
001
Subclass 0.
Subclass 1.
[4:0] ADC number of bits per
sample(N')
0 0111
0 1011
0 1111
0x0591
0x0592
JESD204B JV S
configuration
JESD204B HD CF
configuration
[7:5] Reserved
[4:0] Samples per converter
frame cycle (S)
7
HD value
Samples per converter frame cycle (S = Register 0x0591,
Bits[4:0] + 1).
0
1
0x05A0 JESD204B
Checksum 0
configuration
0x05A1 JESD204B
Checksum 1
configuration
0x05A2 JESD204B
Checksum 2
configuration
0x05A3 JESD204B
Checksum 3
configuration
0x05B0 JESD204B lane
power-down
[6:5] Reserved
[4:0] Control words per frame
clock cycle per link (CF)
[7:0] Checksum 0 checksum
value for SERDOUT0±
[7:0] Checksum 1 checksum
value for SERDOUT1±
[7:0] Checksum 2 checksum
value for SERDOUT2±
[7:0] Checksum 3 checksum
value for SERDOUT3±
7
JESD204B Lane 7 powerdown
0
1
6
JESD204B Lane 6 powerdown
0
1
5
JESD204B Lane 5 powerdown
0
1
4
JESD204B Lane 4 powerdown
0
1
3
JESD204B Lane 3 powerdown
0
1
2
JESD204B Lane 2 powerdown
0
1
1
JESD204B Lane 1 powerdown
0
1
0
N' = 8.
N' = 12.
N' = 16.
Reserved.
JESD204B Lane 0 powerdown
0
1
Reset Access
0x1
R/W
0xF
R/W
0x1
R
0x0
R
0x0
R
0x0
0x0
R
R
0xC3
R
0xC4
R
0xC5
R
High density format disabled.
High density format enabled.
Reserved.
Number of control words per frame clock cycle per link
(CF = Register 0x0592, Bits[4:0]).
Serial checksum value for Lane 0. Automatically calculated for
each lane. Sum (all link configuration parameters for Lane 0)
mod 256.
Serial checksum value for Lane 1. Automatically calculated for
each lane. Sum (all link configuration parameters for Lane 1)
mod 256.
Serial checksum value for Lane 2. Automatically calculated for
each lane. Sum (all link configuration parameters for each lane)
mod 256.
Serial checksum value for Lane 3. Automatically calculated for
each lane. Sum (all link configuration parameters for Lane 3)
mod 256.
Physical Lane 7 force power-down.
0xC6
R
0x0
R/W
SERDOUT7± normal operation.
SERDOUT7± power-down.
Physical Lane 6 force power-down.
0x0
R/W
SERDOUT6± normal operation.
SERDOUT6± power-down.
Physical Lane 5 force power-down.
0x0
R/W
SERDOUT5± normal operation.
SERDOUT5± power-down.
Physical Lane 4 force power-down.
0x0
R/W
SERDOUT4± normal operation.
SERDOUT4± power-down.
Physical Lane 3 force power-down.
0x0
R/W
SERDOUT3± normal operation.
SERDOUT3± power-down.
Physical Lane 2 force power-down.
0x0
R/W
SERDOUT2± normal operation.
SERDOUT2± power-down.
Physical Lane 1 force power-down.
0x0
R/W
SERDOUT1± normal operation.
SERDOUT1± power-down.
Physical Lane 0 force power-down.
0x0
R/W
SERDOUT0± normal operation.
SERDOUT0± power-down.
Rev. 0 | Page 118 of 136
Data Sheet
Addr.
0x05B2
Name
JESD204B Lane
Assign 1
AD9208
Bits
7
Bit Name
Reserved
Settings
[6:4] SERDOUT1± lane
assignment
0
1
10
11
100
101
110
111
3
Reserved
[2:0] SERDOUT0± lane
assignment
0
1
10
11
100
101
110
111
0x05B3
JESD204B Lane
Assign 2
7
Reserved
[6:4] SERDOUT3± lane
assignment
0
1
10
11
100
101
110
111
3
Reserved
[2:0] SERDOUT2± lane
assignment
0
1
10
11
100
101
110
111
0x05B5
JESD204B Lane
Assign 3
7
Reserved
[6:4] SERDOUT5± lane
assignment
0
1
10
11
100
101
110
111
3
Reserved
Description
Reserved.
Reset Access
0x0
R
Physical Lane 1 assignment.
0x1
R/W
Logical Lane 0.
Logical Lane 1 (default).
Logical Lane 2.
Logical Lane 3.
Logical Lane 4.
Logical Lane 5.
Logical Lane 6.
Logical Lane 7.
Reserved.
Physical Lane 0 assignment.
0x0
0x0
R
R/W
Logical Lane 0 (default).
Logical Lane 1.
Logical Lane 2.
Logical Lane 3.
Logical Lane 4.
Logical Lane 5.
Logical Lane 6.
Logical Lane 7.
Reserved.
0x0
R
Physical Lane 3 assignment.
0x3
R/W
Logical Lane 0.
Logical Lane 1.
Logical Lane 2.
Logical Lane 3 (default).
Logical Lane 4.
Logical Lane 5.
Logical Lane 6.
Logical Lane 7.
Reserved.
Physical Lane 2 assignment.
0x0
0x2
R
R/W
Logical Lane 0.
Logical Lane 1
Logical Lane 2 (default).
Logical Lane 3.
Logical Lane 4.
Logical Lane 5.
Logical Lane 6.
Logical Lane 7.
Reserved.
0x0
R
Physical Lane 5 assignment.
0x5
R/W
Logical Lane 0.
Logical Lane 1.
Logical Lane 2.
Logical Lane 3.
Logical Lane 4.
Logical Lane 5 (default).
Logical Lane 6.
Logical Lane 7.
Reserved.
0x0
R
Rev. 0 | Page 119 of 136
AD9208
Addr.
0x05B6
Name
JESD204B Lane
Assign 4
Data Sheet
Bits Bit Name
[2:0] SERDOUT4± lane
assignment
7
Settings
Description
Physical Lane 4 assignment.
Reset Access
0x4
R/W
0
1
10
11
100
101
110
111
Logical Lane 0.
Logical Lane 1.
Logical Lane 2.
Logical Lane 3.
Logical Lane 4 (default).
Logical Lane 5.
Logical Lane 6.
Logical Lane 7.
Reserved.
0x0
R
Physical Lane 7 assignment.
0x7
R/W
Logical Lane 0.
Logical Lane 1.
Logical Lane 2.
Logical Lane 3.
Logical Lane 4.
Logical Lane 5.
Logical Lane 6.
Logical Lane 7 (default).
Reserved.
Physical Lane 6 assignment.
0x0
0x6
R
R/W
Logical Lane 0.
Logical Lane 1.
Logical Lane 2.
Logical Lane 3.
Logical Lane 4.
Logical Lane 5.
Logical Lane 6 (default).
Logical Lane 7.
Invert SERDOUT7± data.
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
Reserved
[6:4] SERDOUT7± lane
assignment
0
1
10
11
100
101
110
111
3
Reserved
[2:0] SERDOUT6± lane
assignment
0
1
10
11
100
101
110
111
0x05BF
SERDOUTx± data
invert
7
Invert SERDOUT7± data
0
1
6
Invert SERDOUT6± data
0
1
5
Invert SERDOUT5± data
0
1
4
Invert SERDOUT4± data
0
1
3
Invert SERDOUT3± data
0
1
2
Invert SERDOUT2± data
0
1
1
Invert SERDOUT1± data
0
1
0
Invert SERDOUT0± data
0
1
Normal.
Invert.
Invert SERDOUT6± data.
Normal.
Invert.
Invert SERDOUT5± data.
Normal.
Invert.
Invert SERDOUT4± data.
Normal.
Invert.
Invert SERDOUT3± data.
Normal.
Invert.
Invert SERDOUT2± data.
Normal.
Invert.
Invert SERDOUT1± data.
Normal.
Invert.
Invert SERDOUT0± data.
Normal.
Invert.
Rev. 0 | Page 120 of 136
Data Sheet
Addr.
0x05C0
Name
JESD204B Swing
Adjust 1
AD9208
Bits
7
Bit Name
Reserved
Settings
[6:4] SERDOUT1± voltage
swing adjust
000
001
010
3
Reserved
[2:0] SERDOUT0± voltage
swing adjust
000
001
010
0x05C1
JESD204B Swing
Adjust 2
7
Reserved
[6:4] SERDOUT3± voltage
swing adjust
000
001
010
3
Reserved
[2:0] SERDOUT2± voltage
swing adjust
000
001
010
0x05C2
JESD204B Swing
Adjust 3
7
Reserved
[6:4] SERDOUT5± voltage
swing adjust
000
001
010
3
Reserved
[2:0] SERDOUT4± voltage
swing adjust
000
001
010
0x05C3
JESD204B Swing
Adjust 4
7
Reserved
[6:4] SERDOUT7± voltage
swing adjust
000
001
010
3
Reserved
[2:0] SERDOUT6± voltage
swing adjust
000
001
010
Description
Reserved.
Reset Access
0x0
R
Output swing level for SERDOUT1±.
0x1
R/W
1.0 × DRVDD1.
0.850 × DRVDD1.
0.750 × DRVDD1.
Reserved.
Output swing level for SERDOUT0±.
0x0
0x1
R
R/W
1.0 × DRVDD1.
0.850 × DRVDD1.
0.750 × DRVDD1.
Reserved.
0x0
R
Output swing level for SERDOUT3±.
0x1
R/W
1.0 × DRVDD1.
0.850 × DRVDD1.
0.750 × DRVDD1.
Reserved.
Output swing level for SERDOUT2±.
0x0
0x1
R
R/W
1.0 × DRVDD1.
0.850 × DRVDD1.
0.750 × DRVDD1.
Reserved.
0x0
R
Output swing level for SERDOUT5±.
0x1
R/W
1.0 × DRVDD1.
0.850 × DRVDD1.
0.750 × DRVDD1.
Reserved.
Output swing level for SERDOUT4±.
0x0
0x1
R
R/W
1.0 × DRVDD1.
0.850 × DRVDD1.
0.750 × DRVDD1.
Reserved.
0x0
R
Output swing level for SERDOUT7±.
0x1
R/W
1.0 × DRVDD1.
0.850 × DRVDD1.
0.750 × DRVDD1.
Reserved.
Output swing level for SERDOUT6±.
0x0
0x1
R
R/W
1.0 × DRVDD1.
0.850 × DRVDD1.
0.750 × DRVDD1.
Rev. 0 | Page 121 of 136
AD9208
Addr.
0x05C4
Name
SERDOUT0 preemphasis select
Data Sheet
Bits
7
Bit Name
Post tap enable
Settings
Description
Post tap enable.
Reset Access
0x0
R/W
0
1
Disable.
Enable.
Set post tap level.
0x0
R/W
0 dB.
3 dB.
6 dB.
9 dB.
12 dB.
Reserved.
Post tap enable.
0x0
0x0
R/W
R/W
Disable.
Enable.
Set post tap level.
0x0
R/W
0 dB.
3 dB.
6 dB.
9 dB.
12 dB.
Reserved.
Post tap enable.
0x0
0x0
R/W
R/W
Disable.
Enable.
Set post tap level.
0x0
R/W
0 dB.
3 dB.
6 dB.
9 dB.
12 dB.
Reserved.
Post tap enable.
0x0
0x0
R/W
R/W
Disable.
Enable.
Set post tap level.
0x0
R/W
0 dB.
3 dB.
6 dB.
9 dB.
12 dB.
Reserved.
Post tap enable.
0x0
0x0
R/W
R/W
Disable.
Enable.
Set post tap level.
0x0
R/W
0 dB.
3 dB.
6 dB.
9 dB.
12 dB.
Reserved.
0x0
R/W
[6:4] Set post tap level for
SERDOUT0±
000
001
010
011
100
0x05C5
SERDOUT1 preemphasis select
[3:0] Reserved
7
Post tap enable
0
1
[6:4] Set post tap level for
SERDOUT1±
000
001
010
011
100
0x05C6
SERDOUT2 preemphasis select
[3:0] Reserved
7
Post tap enable
0
1
[6:4] Set post tap level for
SERDOUT2±
000
001
010
011
100
0x05C7
SERDOUT3 preemphasis select
[3:0] Reserved
7
Post tap enable
0
1
[6:4] Set post tap level for
SERDOUT3±
000
001
010
011
100
0x05C8
SERDOUT4 preemphasis select
[3:0] Reserved
7
Post tap enable
0
1
[6:4] Set post tap level for
SERDOUT4±
000
001
010
011
100
[3:0] Reserved
Rev. 0 | Page 122 of 136
Data Sheet
Addr.
0x05C9
Name
SERDOUT5 preemphasis select
AD9208
Bits
7
Bit Name
Post tap enable
Settings
Description
Post tap enable.
Reset Access
0x0
R/W
0
1
Disable.
Enable.
Set post tap level.
0x0
R/W
0 dB.
3 dB.
6 dB.
9 dB.
12 dB.
Reserved.
Post tap enable.
0x0
0x0
R/W
R/W
Disable.
Enable.
Set post tap level.
0x0
R/W
0 dB.
3 dB.
6 dB.
9 dB.
12 dB.
Reserved.
Post tap enable.
0x0
0x0
R/W
R/W
Disable
Enable
Set post tap level.
0x0
R/W
0 dB.
3 dB.
6 dB.
9 dB.
12 dB.
Reserved.
See Table 32.
0x0
0x00
R/W
R/W
JESD204B PLL Normal Operation
Reset JESD204B PLL calibration
See Table 32.
0x0F
R/W
JESD204B start-up circuit in normal operation.
Reset JESD204B start-up circuit.
See Table 32.
0x00
R/W
[6:4] Set post tap level for
SERDOUT5±
000
001
010
011
100
0x05CA SERDOUT6 preemphasis select
[3:0] Reserved
7
Post tap enable
0
1
[6:4] Set post tap level for
SERDOUT6±
000
001
010
011
100
0x05CB SERDOUT7 preemphasis select
[3:0] Reserved
7
Post tap enable
0
1
[6:4] Set post tap level for
SERDOUT7±
000
001
010
011
100
0x1222
JESD204B PLL
calibration
[3:0] Reserved
[7:0]
0x00
0x04
0x1228
JESD204B PLL
start-up control
[7:0]
0x0F
0x4F
0x1262
JESD204B PLL LOL
bit control
[7:0]
0x00
0x80
Loss of lock bit normal operation.
Clear loss of lock bit.
Rev. 0 | Page 123 of 136
AD9208
Data Sheet
Addr.
Name
Bits Bit Name
Programmable Filter Control and Coefficients Registers
0x0DF8 PFILT control
[7:3] Reserved
[2:0] PFILT mode
0x0DF9 PFILT gain
Settings
7
Reserved
[6:4] PFILT Y gain
110
111
000
001
010
3
Reserved
[2:0] PFILT X gain
110
111
000
001
010
0x0E00
0x0E01
0x0E02
0x0E03
0x0E04
0x0E05
0x0E06
0x0E07
0x0E08
0x0E09
0x0E0A
0x0E0B
PFILT X
Coefficient 0
PFILT X
Coefficient 1
PFILT X
Coefficient 2
PFILT X
Coefficient 3
PFILT X
Coefficient 4
PFILT X
Coefficient 5
PFILT X
Coefficient 6
PFILT X
Coefficient 7
PFILT X
Coefficient 8
PFILT X
Coefficient 9
PFILT X
Coefficient 10
PFILT X
Coefficient 11
[7:0] PFILT X Coefficient 0
[7:0] PFILT X Coefficient 1
[7:0] PFILT X Coefficient 2
[7:0] PFILT X Coefficient 3
[7:0] PFILT X Coefficient 4
[7:0] PFILT X Coefficient 5
[7:0] PFILT X Coefficient 6
[7:0] PFILT X Coefficient 7
[7:0] PFILT X Coefficient 8
[7:0] PFILT X Coefficient 9
[7:0] PFILT X Coefficient 10
[7:0] PFILT X Coefficient 11
Description
Reset Access
Reserved.
Programmable filter (PFILT) mode.
000 = disabled (filters bypassed).
001 = single filter (X only).
DOUT_I[n] = DIN_I[n] * X_I[n].
DOUT_Q[n] = DIN_Q[n] * X_Q[n].
010 = single filter (X and Y together).
DOUT_I[n] = DIN_I[n] * XY_I[n].
DOUT_Q[n] = DIN_Q[n] * XY_Q[n].
100 = cascaded filters (X to Y).
DOUT_I[n] = DIN_I[n] * X_I[n] * Y_I[n].
DOUT_Q[n] = DIN_Q[n] * X_Q[n] * Y_Q[n].
DOUT_Q[n] = DIN_Q[n] * X_Q[n] * Y_Q[n].
101 = complex filters.
DOUT_I[n] = DIN_I[n] * X_I[n] + DIN_Q[n] * Y_Q[n].
DOUT_Q[n] = DIN_Q[n] * X_Q[n] + DIN_I[n] * Y_I[n].
110 = half complex filter.
DOUT_I[n] = DIN_I[n].
DOUT_Q[n] = DIN_Q[n] * XY_Q[n] + DIN_I[n] * XY_I[n].
111 = real 96-tap filter.
DOUT_I[n] = DIN_I[n] * XY_I[n].
DOUT_Q[n] = DIN_Q[n] * XY_Q[n].
Reserved.
PFILT Y gain.
−12 dB loss.
−6 dB loss.
0 dB gain.
+6 dB gain.
+12 dB gain.
Reserved.
PFILT X gain.
−12 dB loss.
−6 dB loss.
0 dB gain.
+6 dB gain.
+12 dB gain.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
0x0
0x0
R
R/W
0x0
0x0
R
R/W
0x0
0x0
R
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
Rev. 0 | Page 124 of 136
Data Sheet
Addr.
0x0E0C
Name
PFILT X
Coefficient 12
0x0E0D PFILT X
Coefficient 13
0x0E0E PFILT X
Coefficient 14
0x0E0F PFILT X
Coefficient 15
0x0E10 PFILT X
Coefficient 16
0x0E11 PFILT X
Coefficient 17
0x0E12 PFILT X
Coefficient 18
0x0E13 PFILT X
Coefficient 19
0x0E14 PFILT X
Coefficient 20
0x0E15 PFILT X
Coefficient 21
0x0E16 PFILT X
Coefficient 22
0x0E17 PFILT X
Coefficient 23
0x0E18 PFILT X
Coefficient 24
0x0E19 PFILT X
Coefficient 25
0x0E1A PFILT X
Coefficient 26
0x0E1B PFILT X
Coefficient 27
0x0E1C PFILT X
Coefficient 28
0x0E1D PFILT X
Coefficient 29
0x0E1E PFILT X
Coefficient 30
0x0E1F PFILT X
Coefficient 31
0x0E20 PFILT X
Coefficient 32
0x0E21 PFILT X
Coefficient 33
0x0E22 PFILT X
Coefficient 34
0x0E23 PFILT X
Coefficient 35
0x0E24 PFILT X
Coefficient 36
0x0E25 PFILT X
Coefficient 37
0x0E26 PFILT X
Coefficient 38
0x0E27 PFILT X
Coefficient 39
0x0E28 PFILT X
Coefficient 40
0x0E29 PFILT X
Coefficient 41
0x0E2A PFILT X
Coefficient 42
0x0E2B PFILT X
Coefficient 43
AD9208
Bits Bit Name
[7:0] PFILT X Coefficient 12
[7:0] PFILT X Coefficient 13
[7:0] PFILT X Coefficient 14
[7:0] PFILT X Coefficient 15
[7:0] PFILT X Coefficient 16
[7:0] PFILT X Coefficient 17
[7:0] PFILT X Coefficient 18
[7:0] PFILT X Coefficient 19
[7:0] PFILT X Coefficient 20
[7:0] PFILT X Coefficient 21
[7:0] PFILT X Coefficient 22
[7:0] PFILT X Coefficient 23
[7:0] PFILT X Coefficient 24
[7:0] PFILT X Coefficient 25
[7:0] PFILT X Coefficient 26
[7:0] PFILT X Coefficient 27
[7:0] PFILT X Coefficient 28
[7:0] PFILT X Coefficient 29
[7:0] PFILT X Coefficient 30
[7:0] PFILT X Coefficient 31
[7:0] PFILT X Coefficient 32
[7:0] PFILT X Coefficient 33
[7:0] PFILT X Coefficient 34
[7:0] PFILT X Coefficient 35
[7:0] PFILT X Coefficient 36
[7:0] PFILT X Coefficient 37
[7:0] PFILT X Coefficient 38
[7:0] PFILT X Coefficient 39
[7:0] PFILT X Coefficient 40
[7:0] PFILT X Coefficient 41
[7:0] PFILT X Coefficient 42
[7:0] PFILT X Coefficient 43
Settings
Description
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Rev. 0 | Page 125 of 136
Reset Access
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
AD9208
Addr.
0x0E2C
Name
PFILT X
Coefficient 44
0x0E2D PFILT X
Coefficient 45
0x0E2E PFILT X
Coefficient 46
0x0E2F PFILT X
Coefficient 47
0x0E30 PFILT X
Coefficient 48
0x0E31 PFILT X
Coefficient 49
0x0E32 PFILT X
Coefficient 50
0x0E33 PFILT X
Coefficient 51
0x0E34 PFILT X
Coefficient 52
0x0E35 PFILT X
Coefficient 53
0x0E36 PFILT X
Coefficient 54
0x0E37 PFILT X
Coefficient 55
0x0E38 PFILT X
Coefficient 56
0x0E39 PFILT X
Coefficient 57
0x0E3A PFILT X
Coefficient 58
0x0E3B PFILT X
Coefficient 59
0x0E3C PFILT X
Coefficient 60
0x0E3D PFILT X
Coefficient 61
0x0E3E PFILT X
Coefficient 62
0x0E3F PFILT X
Coefficient 63
0x0E40 PFILT X
Coefficient 64
0x0E41 PFILT X
Coefficient 65
0x0E42 PFILT X
Coefficient 66
0x0E43 PFILT X
Coefficient 67
0x0E44 PFILT X
Coefficient 68
0x0E45 PFILT X
Coefficient 69
0x0E46 PFILT X
Coefficient 70
0x0E47 PFILT X
Coefficient 71
0x0E48 PFILT X
Coefficient 72
0x0E49 PFILT X
Coefficient 73
0x0E4A PFILT X
Coefficient 74
0x0E4B PFILT X
Coefficient 75
Data Sheet
Bits Bit Name
[7:0] PFILT X Coefficient 44
[7:0] PFILT X Coefficient 45
[7:0] PFILT X Coefficient 46
[7:0] PFILT X Coefficient 47
[7:0] PFILT X Coefficient 48
[7:0] PFILT X Coefficient 49
[7:0] PFILT X Coefficient 50
[7:0] PFILT X Coefficient 51
[7:0] PFILT X Coefficient 52
[7:0] PFILT X Coefficient 53
[7:0] PFILT X Coefficient 54
[7:0] PFILT X Coefficient 55
[7:0] PFILT X Coefficient 56
[7:0] PFILT X Coefficient 57
[7:0] PFILT X Coefficient 58
[7:0] PFILT X Coefficient 59
[7:0] PFILT X Coefficient 60
[7:0] PFILT X Coefficient 61
[7:0] PFILT X Coefficient 62
[7:0] PFILT X Coefficient 63
[7:0] PFILT X Coefficient 64
[7:0] PFILT X Coefficient 65
[7:0] PFILT X Coefficient 66
[7:0] PFILT X Coefficient 67
[7:0] PFILT X Coefficient 68
[7:0] PFILT X Coefficient 69
[7:0] PFILT X Coefficient 70
[7:0] PFILT X Coefficient 71
[7:0] PFILT X Coefficient 72
[7:0] PFILT X Coefficient 73
[7:0] PFILT X Coefficient 74
[7:0] PFILT X Coefficient 75
Settings
Description
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Rev. 0 | Page 126 of 136
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Data Sheet
Addr.
0x0E4C
Name
PFILT X
Coefficient 76
0x0E4D PFILT X
Coefficient 77
0x0E4E PFILT X
Coefficient 78
0x0E4F PFILT X
Coefficient 79
0x0E50 PFILT X
Coefficient 80
0x0E51 PFILT X
Coefficient 81
0x0E52 PFILT X
Coefficient 82
0x0E53 PFILT X
Coefficient 83
0x0E54 PFILT X
Coefficient 84
0x0E55 PFILT X
Coefficient 85
0x0E56 PFILT X
Coefficient 86
0x0E57 PFILT X
Coefficient 87
0x0E58 PFILT X
Coefficient 88
0x0E59 PFILT X
Coefficient 89
0x0E5A PFILT X
Coefficient 90
0x0E5B PFILT X
Coefficient 91
0x0E5C PFILT X
Coefficient 92
0x0E5D PFILT X
Coefficient 93
0x0E5E PFILT X
Coefficient 94
0x0E5F PFILT X
Coefficient 95
0x0E60 PFILT X
Coefficient 96
0x0E61 PFILT X
Coefficient 97
0x0E62 PFILT X
Coefficient 98
0x0E63 PFILT X
Coefficient 99
0x0E64 PFILT X
Coefficient 100
0x0E65 PFILT X
Coefficient 101
0x0E66 PFILT X
Coefficient 102
0x0E67 PFILT X
Coefficient 103
0x0E68 PFILT X
Coefficient 104
0x0E69 PFILT X
Coefficient 105
0x0E6A PFILT X
Coefficient 106
0x0E6B PFILT X
Coefficient 107
AD9208
Bits Bit Name
[7:0] PFILT X Coefficient 76
[7:0] PFILT X Coefficient 77
[7:0] PFILT X Coefficient 78
[7:0] PFILT X Coefficient 79
[7:0] PFILT X Coefficient 80
[7:0] PFILT X Coefficient 81
[7:0] PFILT X Coefficient 82
[7:0] PFILT X Coefficient 83
[7:0] PFILT X Coefficient 84
[7:0] PFILT X Coefficient 85
[7:0] PFILT X Coefficient 86
[7:0] PFILT X Coefficient 87
[7:0] PFILT X Coefficient 88
[7:0] PFILT X Coefficient 89
[7:0] PFILT X Coefficient 90
[7:0] PFILT X Coefficient 91
[7:0] PFILT X Coefficient 92
[7:0] PFILT X Coefficient 93
[7:0] PFILT X Coefficient 94
[7:0] PFILT X Coefficient 95
[7:0] PFILT X Coefficient 96
[7:0] PFILT X Coefficient 97
[7:0] PFILT X Coefficient 98
[7:0] PFILT X Coefficient 99
[7:0] PFILT X Coefficient 100
[7:0] PFILT X Coefficient 101
[7:0] PFILT X Coefficient 102
[7:0] PFILT X Coefficient 103
[7:0] PFILT X Coefficient 104
[7:0] PFILT X Coefficient 105
[7:0] PFILT X Coefficient 106
[7:0] PFILT X Coefficient 107
Settings
Description
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Rev. 0 | Page 127 of 136
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AD9208
Addr.
0x0E6C
Name
PFILT X
Coefficient 108
0x0E6D PFILT X
Coefficient 109
0x0E6E PFILT X
Coefficient 110
0x0E6F PFILT X
Coefficient 111
0x0E70 PFILT X
Coefficient 112
0x0E71 PFILT X
Coefficient 113
0x0E72 PFILT X
Coefficient 114
0x0E73 PFILT X
Coefficient 115
0x0E74 PFILT X
Coefficient 116
0x0E75 PFILT X
Coefficient 117
0x0E76 PFILT X
Coefficient 118
0x0E77 PFILT X
Coefficient 119
0x0E78 PFILT X
Coefficient 120
0x0E79 PFILT X
Coefficient 121
0x0E7A PFILT X
Coefficient 122
0x0E7B PFILT X
Coefficient 123
0x0E7C PFILT X
Coefficient 124
0x0E7D PFILT X
Coefficient 125
0x0E7E PFILT X
Coefficient 126
0x0E7F PFILT X
Coefficient 127
0x0F00 PFILT Y
Coefficient 0
0x0F01 PFILT Y
Coefficient 1
0x0F02 PFILT Y
Coefficient 2
0x0F03 PFILT Y
Coefficient 3
0x0F04 PFILT Y
Coefficient 4
0x0F05 PFILT Y
Coefficient 5
0x0F06 PFILT Y
Coefficient 6
0x0F07 PFILT Y
Coefficient 7
0x0F08 PFILT Y
Coefficient 8
0x0F09 PFILT Y
Coefficient 9
0x0F0A PFILT Y
Coefficient 10
0x0F0B PFILT Y
Coefficient 11
Data Sheet
Bits Bit Name
[7:0] PFILT X Coefficient 108
[7:0] PFILT X Coefficient 109
[7:0] PFILT X Coefficient 110
[7:0] PFILT X Coefficient 111
[7:0] PFILT X Coefficient 112
[7:0] PFILT X Coefficient 113
[7:0] PFILT X Coefficient 114
[7:0] PFILT X Coefficient 115
[7:0] PFILT X Coefficient 116
[7:0] PFILT X Coefficient 117
[7:0] PFILT X Coefficient 118
[7:0] PFILT X Coefficient 119
[7:0] PFILT X Coefficient 120
[7:0] PFILT X Coefficient 121
[7:0] PFILT X Coefficient 122
[7:0] PFILT X Coefficient 123
[7:0] PFILT X Coefficient 124
[7:0] PFILT X Coefficient 125
[7:0] PFILT X Coefficient 126
[7:0] PFILT X Coefficient 127
[7:0] PFILT Y Coefficient 0
[7:0] PFILT Y Coefficient 1
[7:0] PFILT Y Coefficient 2
[7:0] PFILT Y Coefficient 3
[7:0] PFILT Y Coefficient 4
[7:0] PFILT Y Coefficient 5
[7:0] PFILT Y Coefficient 6
[7:0] PFILT Y Coefficient 7
[7:0] PFILT Y Coefficient 8
[7:0] PFILT Y Coefficient 9
[7:0] PFILT Y Coefficient 10
[7:0] PFILT Y Coefficient 11
Settings
Description
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter X coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Rev. 0 | Page 128 of 136
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Data Sheet
Addr.
0x0F0C
Name
PFILT Y
Coefficient 12
0x0F0D PFILT Y
Coefficient 13
0x0F0E PFILT Y
Coefficient 14
0x0F0F PFILT Y
Coefficient 15
0x0F10 PFILT Y
Coefficient 16
0x0F11 PFILT Y
Coefficient 17
0x0F12 PFILT Y
Coefficient 18
0x0F13 PFILT Y
Coefficient 19
0x0F14 PFILT Y
Coefficient 20
0x0F15 PFILT Y
Coefficient 21
0x0F16 PFILT Y
Coefficient 22
0x0F17 PFILT Y
Coefficient 23
0x0F18 PFILT Y
Coefficient 24
0x0F19 PFILT Y
Coefficient 25
0x0F1A PFILT Y
Coefficient 26
0x0F1B PFILT Y
Coefficient 27
0x0F1C PFILT Y
Coefficient 28
0x0F1D PFILT Y
Coefficient 29
0x0F1E PFILT Y
Coefficient 30
0x0F1F PFILT Y
Coefficient 31
0x0F20 PFILT Y
Coefficient 32
0x0F21 PFILT Y
Coefficient 33
0x0F22 PFILT Y
Coefficient 34
0x0F23 PFILT Y
Coefficient 35
0x0F24 PFILT Y
Coefficient 36
0x0F25 PFILT Y
Coefficient 37
0x0F26 PFILT Y
Coefficient 38
0x0F27 PFILT Y
Coefficient 39
0x0F28 PFILT Y
Coefficient 40
0x0F29 PFILT Y
Coefficient 41
0x0F2A PFILT Y
Coefficient 42
0x0F2B PFILT Y
Coefficient 43
AD9208
Bits Bit Name
[7:0] PFILT Y Coefficient 12
[7:0] PFILT Y Coefficient 13
[7:0] PFILT Y Coefficient 14
[7:0] PFILT Y Coefficient 15
[7:0] PFILT Y Coefficient 16
[7:0] PFILT Y Coefficient 17
[7:0] PFILT Y Coefficient 18
[7:0] PFILT Y Coefficient 19
[7:0] PFILT Y Coefficient 20
[7:0] PFILT Y Coefficient 21
[7:0] PFILT Y Coefficient 22
[7:0] PFILT Y Coefficient 23
[7:0] PFILT Y Coefficient 24
[7:0] PFILT Y Coefficient 25
[7:0] PFILT Y Coefficient 26
[7:0] PFILT Y Coefficient 27
[7:0] PFILT Y Coefficient 28
[7:0] PFILT Y Coefficient 29
[7:0] PFILT Y Coefficient 30
[7:0] PFILT Y Coefficient 31
[7:0] PFILT Y Coefficient 32
[7:0] PFILT Y Coefficient 33
[7:0] PFILT Y Coefficient 34
[7:0] PFILT Y Coefficient 35
[7:0] PFILT Y Coefficient 36
[7:0] PFILT Y Coefficient 37
[7:0] PFILT Y Coefficient 38
[7:0] PFILT Y Coefficient 39
[7:0] PFILT Y Coefficient 40
[7:0] PFILT Y Coefficient 41
[7:0] PFILT Y Coefficient 42
[7:0] PFILT Y Coefficient 43
Settings
Description
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Rev. 0 | Page 129 of 136
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0x0
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0x0
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0x0
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0x0
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0x0
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0x0
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0x0
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0x0
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0x0
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0x0
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AD9208
Addr.
0x0F2C
Name
PFILT Y
Coefficient 44
0x0F2D PFILT Y
Coefficient 45
0x0F2E PFILT Y
Coefficient 46
0x0F2F PFILT Y
Coefficient 47
0x0F30 PFILT Y
Coefficient 48
0x0F31 PFILT Y
Coefficient 49
0x0F32 PFILT Y
Coefficient 50
0x0F33 PFILT Y
Coefficient 51
0x0F34 PFILT Y
Coefficient 52
0x0F35 PFILT Y
Coefficient 53
0x0F36 PFILT Y
Coefficient 54
0x0F37 PFILT Y
Coefficient 55
0x0F38 PFILT Y
Coefficient 56
0x0F39 PFILT Y
Coefficient 57
0x0F3A PFILT Y
Coefficient 58
0x0F3B PFILT Y
Coefficient 59
0x0F3C PFILT Y
Coefficient 60
0x0F3D PFILT Y
Coefficient 61
0x0F3E PFILT Y
Coefficient 62
0x0F3F PFILT Y
Coefficient 63
0x0F40 PFILT Y
Coefficient 64
0x0F41 PFILT Y
Coefficient 65
0x0F42 PFILT Y
Coefficient 66
0x0F43 PFILT Y
Coefficient 67
0x0F44 PFILT Y
Coefficient 68
0x0F45 PFILT Y
Coefficient 69
0x0F46 PFILT Y
Coefficient 70
0x0F47 PFILT Y
Coefficient 71
0x0F48 PFILT Y
Coefficient 72
0x0F49 PFILT Y
Coefficient 73
0x0F4A PFILT Y
Coefficient 74
0x0F4B PFILT Y
Coefficient 75
Data Sheet
Bits Bit Name
[7:0] PFILT Y Coefficient 44
[7:0] PFILT Y Coefficient 45
[7:0] PFILT Y Coefficient 46
[7:0] PFILT Y Coefficient 47
[7:0] PFILT Y Coefficient 48
[7:0] PFILT Y Coefficient 49
[7:0] PFILT Y Coefficient 50
[7:0] PFILT Y Coefficient 51
[7:0] PFILT Y Coefficient 52
[7:0] PFILT Y Coefficient 53
[7:0] PFILT Y Coefficient 54
[7:0] PFILT Y Coefficient 55
[7:0] PFILT Y Coefficient 56
[7:0] PFILT Y Coefficient 57
[7:0] PFILT Y Coefficient 58
[7:0] PFILT Y Coefficient 59
[7:0] PFILT Y Coefficient 60
[7:0] PFILT Y Coefficient 61
[7:0] PFILT Y Coefficient 62
[7:0] PFILT Y Coefficient 63
[7:0] PFILT Y Coefficient 64
[7:0] PFILT Y Coefficient 65
[7:0] PFILT Y Coefficient 66
[7:0] PFILT Y Coefficient 67
[7:0] PFILT Y Coefficient 68
[7:0] PFILT Y Coefficient 69
[7:0] PFILT Y Coefficient 70
[7:0] PFILT Y Coefficient 71
[7:0] PFILT Y Coefficient 72
[7:0] PFILT Y Coefficient 73
[7:0] PFILT Y Coefficient 74
[7:0] PFILT Y Coefficient 75
Settings
Description
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Rev. 0 | Page 130 of 136
Reset Access
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
Data Sheet
Addr.
0x0F4C
Name
PFILT Y
Coefficient 76
0x0F4D PFILT Y
Coefficient 77
0x0F4E PFILT Y
Coefficient 78
0x0F4F PFILT Y
Coefficient 79
0x0F50 PFILT Y
Coefficient 80
0x0F51 PFILT Y
Coefficient 81
0x0F52 PFILT Y
Coefficient 82
0x0F53 PFILT Y
Coefficient 83
0x0F54 PFILT Y
Coefficient 84
0x0F55 PFILT Y
Coefficient 85
0x0F56 PFILT Y
Coefficient 86
0x0F57 PFILT Y
Coefficient 87
0x0F58 PFILT Y
Coefficient 88
0x0F59 PFILT Y
Coefficient 89
0x0F5A PFILT Y
Coefficient 90
0x0F5B PFILT Y
Coefficient 91
0x0F5C PFILT Y
Coefficient 92
0x0F5D PFILT Y
Coefficient 93
0x0F5E PFILT Y
Coefficient 94
0x0F5F PFILT Y
Coefficient 95
0x0F60 PFILT Y
Coefficient 96
0x0F61 PFILT Y
Coefficient 97
0x0F62 PFILT Y
Coefficient 98
0x0F63 PFILT Y
Coefficient 99
0x0F64 PFILT Y
Coefficient 100
0x0F65 PFILT Y
Coefficient 101
0x0F66 PFILT Y
Coefficient 102
0x0F67 PFILT Y
Coefficient 103
0x0F68 PFILT Y
Coefficient 104
0x0F69 PFILT Y
Coefficient 105
0x0F6A PFILT Y
Coefficient 106
0x0F6B PFILT Y
Coefficient 107
AD9208
Bits Bit Name
[7:0] PFILT Y Coefficient 76
[7:0] PFILT Y Coefficient 77
[7:0] PFILT Y Coefficient 78
[7:0] PFILT Y Coefficient 79
[7:0] PFILT Y Coefficient 80
[7:0] PFILT Y Coefficient 81
[7:0] PFILT Y Coefficient 82
[7:0] PFILT Y Coefficient 83
[7:0] PFILT Y Coefficient 84
[7:0] PFILT Y Coefficient 85
[7:0] PFILT Y Coefficient 86
[7:0] PFILT Y Coefficient 87
[7:0] PFILT Y Coefficient 88
[7:0] PFILT Y Coefficient 89
[7:0] PFILT Y Coefficient 90
[7:0] PFILT Y Coefficient 91
[7:0] PFILT Y Coefficient 92
[7:0] PFILT Y Coefficient 93
[7:0] PFILT Y Coefficient 94
[7:0] PFILT Y Coefficient 95
[7:0] PFILT Y Coefficient 96
[7:0] PFILT Y Coefficient 97
[7:0] PFILT Y Coefficient 98
[7:0] PFILT Y Coefficient 99
[7:0] PFILT Y Coefficient 100
[7:0] PFILT Y Coefficient 101
[7:0] PFILT Y Coefficient 102
[7:0] PFILT Y Coefficient 103
[7:0] PFILT Y Coefficient 104
[7:0] PFILT Y Coefficient 105
[7:0] PFILT Y Coefficient 106
[7:0] PFILT Y Coefficient 107
Settings
Description
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Rev. 0 | Page 131 of 136
Reset Access
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
AD9208
Data Sheet
Addr.
0x0F6C
Name
Bits
PFILT Y
[7:0]
Coefficient 108
0x0F6D PFILT Y
[7:0]
Coefficient 109
0x0F6E PFILT Y
[7:0]
Coefficient 110
0x0F6F PFILT Y
[7:0]
Coefficient 111
0x0F70 PFILT Y
[7:0]
Coefficient 112
0x0F71 PFILT Y
[7:0]
Coefficient 113
0x0F72 PFILT Y
[7:0]
Coefficient 114
0x0F73 PFILT Y
[7:0]
Coefficient 115
0x0F74 PFILT Y
[7:0]
Coefficient 116
0x0F75 PFILT Y
[7:0]
Coefficient 117
0x0F76 PFILT Y
[7:0]
Coefficient 118
0x0F77 PFILT Y
[7:0]
Coefficient 119
0x0F78 PFILT Y
[7:0]
Coefficient 120
0x0F79 PFILT Y
[7:0]
Coefficient 121
0x0F7A PFILT Y
[7:0]
Coefficient 122
0x0F7B PFILT Y
[7:0]
Coefficient 123
0x0F7C PFILT Y
[7:0]
Coefficient 124
0x0F7D PFILT Y
[7:0]
Coefficient 125
0x0F7E PFILT Y
[7:0]
Coefficient 126
0x0F7F PFILT Y
[7:0]
Coefficient 127
VREF/Analog Input Control Registers
0x0701 DC offset calibration [7:0]
control (local)
0x18A6 VREF control
Bit Name
PFILT Y Coefficient 108
Settings
PFILT Y Coefficient 109
PFILT Y Coefficient 110
PFILT Y Coefficient 111
PFILT Y Coefficient 112
PFILT Y Coefficient 113
PFILT Y Coefficient 114
PFILT Y Coefficient 115
PFILT Y Coefficient 116
PFILT Y Coefficient 117
PFILT Y Coefficient 118
PFILT Y Coefficient 119
PFILT Y Coefficient 120
PFILT Y Coefficient 121
PFILT Y Coefficient 122
PFILT Y Coefficient 123
PFILT Y Coefficient 124
PFILT Y Coefficient 125
PFILT Y Coefficient 126
PFILT Y Coefficient 127
DC offset calibration
control
0x06
0x86
[7:1] Reserved
0
VREF control
0
1
0x18E3
External VCM
buffer control
7
Reserved
6
External VCM buffer
0
1
[5:0] External VCM buffer [5:0]
Description
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Programmable Filter Y coefficients. Coefficients are only
applied after the chip transfer bit is written.
Disable.
Enable.
Reserved.
Internal reference.
External reference.
Reserved.
Disable.
Enable.
See the Input Common Mode section.
Rev. 0 | Page 132 of 136
Reset Access
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x0
R/W
0x06
R/W
0x0
0x0
R
R/W
0x0
R
0x0
R/W
0x0
R/W
Data Sheet
Addr.
0x18E6
0x1908
AD9208
Name
Bits Bit Name
Temperature diode [7:0] Temperature diode
export
location select
Analog input
control (local)
Settings
Description
See the Temperature Diode section.
Reset Access
0x0
R/W
0x00
0x01
0x02
0x03
0x40
0x41
0x42
0x43
0x50
0x51
0x52
0x53
Central diode. VREF pin = high-Z.
Central diode. VREF pin = 1× diode voltage output.
Central diode. VREF pin = 20× diode voltage output.
Central diode. VREF pin = GND.
Channel A diode. VREF pin = high-Z.
Channel A diode. VREF pin = 1× diode voltage output.
Channel A diode. VREF pin = 20× diode voltage output.
Channel A diode. VREF pin = GND.
Channel B diode. VREF pin = high-Z.
Channel B diode. VREF pin = 1× diode voltage output.
Channel B diode. VREF pin = 20× diode voltage output.
Channel B diode. VREF pin = GND.
Reserved.
0x0
R
0x0
R/W
0x0
0x0
R
R
Full-scale voltage setting.
1.13 V p-p differential.
1.25 V p-p differential.
1.7 V p-p differential.
1.81 V p-p differential.
1.93 V p-p differential.
2.04 V p-p differential.
Reserved.
0xD
R/W
0x0
R
Input Buffer Main Current 1. See the Analog Input Buffer
Controls and SFDR Optimization section.
Buffer current set to 400 μA.
Buffer current set to 500 μA.
Buffer current set to 600 μA.
Buffer current set to 700 μA.
Buffer current set to 800 μA.
Buffer current set to 1000 μA.
Reserved.
0x19
R/W
0x0
R
Input Buffer Main Current 2. See the Analog Input Buffer
Controls and SFDR Optimization section.
Buffer current set to 400 μA.
Buffer current set to 500 μA.
Buffer current set to 600 μA.
Buffer current set to 700 μA.
Buffer current set to 800 μA.
Buffer current set to 1000 μA.
0x19
R/W
[7:3] Reserved
2
Enable dc coupling
0
1
0x1910
Input full-scale
control (local)
Analog input is optimized for ac coupling.
Analog input is optimized for dc coupling.
Reserved.
Reserved.
[1:0] Reserved
[7:4] Reserved
[3:0] Input full-scale voltage
1000
1001
1101
1110
1111
0000
0x1A4C Buffer Control 1
(local)
[7:6] Reserved
[5:0] Buffer Control 1
00 0100
00 1001
01 1110
10 0011
10 1000
11 0010
0x1A4D Buffer Control 2
(local)
[7:6] Reserved
[5:0] Buffer Control 2
00 0100
00 1001
01 1110
10 0011
10 1000
11 0010
Rev. 0 | Page 133 of 136
AD9208
Data Sheet
APPLICATIONS INFORMATION
POWER SUPPLY RECOMMENDATIONS
The power supplies needed to power the AD9208 are shown in
Table 47. A power-on sequence is not required to operate the
AD9208. The power supply domains can be powered up in any
order.
Table 47. Typical Power Supplies for the AD9208
Voltage (V)
0.975
0.975
0.975
0.975
1.9
1.9
1.9
2.5
Tolerance (%)
±2.5
±2.5
±2.5
±2.5
±2.5
±2.5
±2.5
±2.5
For applications requiring an optimal high power efficiency and
low noise performance, it is recommended that the ADP5054
quad switching regulator be used to convert an input voltage in
the 6.0 V to 15 V range to intermediate rails (1.3 V, 2.4 V, and
3.0 V). These intermediate rails are then postregulated by very
low noise, low dropout (LDO) regulators (ADP1763, ADP7159,
and ADP151). Figure 131 shows the recommended power
supply scheme for the AD9208.
6.0V
TO
15.0V
1.3V
ANALOG
ADP5054 1.3V
DIGITAL
ADP1763
ADP1763
Alternatively, the LDOs can be bypassed altogether and the
AD9208 can be driven directly from the dc-to-dc converter.
Note that this approach has risks in that there may be more
power supply noise injected into the power supply domains of
the ADC. To minimize noise, follow the layout guidelines of the
dc-to-dc converter.
12V FROM FMC OR
6.0V FROM WALL
SUPPLY
SW1
SW2
ADP5054
1.3V
ANALOG
ADP1763
1.3V
DIGITAL
DVDD
0.975V
SW3
AVDD1
0.975V
DRVDD1
0.975V
SW4
AVDD1_SR
0.975V
OPTIONAL
DVDD
0.975V
2.4V
ADP7159
ADP7159
ADP151
SPIVDD
1.9V
AVDD2
1.9V
FERRITE BEAD
LDO
SWITCHER
OPTIONAL PATH
OPTIONAL
DRVDD2
1.9V
ADP7159
3.0V
ADP7159
AVDD3
2.5V
NOTES
1. ALL VOLTAGES REFERENCED TO AGND.
Figure 132. Simplified Power Solution for the AD9208
SPIVDD
1.9V
3.0V
AVDD2
1.9V
DRVDD2
1.9V
DRVDD1
0.975V
2.4V
AVDD1
0.975V
AVDD1_SR
0.975V
AVDD3
2.5V
15547-126
LDO
SWITCHER
OPTIONAL PATH
REFERENCED TO AGND
The user can employ several different decoupling capacitors to
cover both high and low frequencies. These capacitors must be
located close to the point of entry at the PCB level and close to
the devices, with minimal trace lengths.
Figure 131. High Efficiency, Low Noise Power Solution for the AD9208
Rev. 0 | Page 134 of 136
15547-127
Domain
AVDD1
AVDD1_SR
DVDD
DRVDD1
AVDD2
DRVDD2
SPIVDD
AVDD3
It is not necessary to split all of these power domains in all cases.
The recommended solution shown in Figure 131 provides the
lowest noise, highest efficiency power delivery system for the
AD9208. If only one 0.975 V supply is available, route to AVDD1
first and then tap it off and isolate it with a ferrite bead or a
filter choke, preceded by decoupling capacitors for AVDD1_SR,
DVDD, and DRVDD1, in that order. Figure 132 shows the
simplified schematic. The dc resistance (DCR) of the ferrite
bead must be taken into consideration when choosing the
appropriate ferrite bead. Otherwise, excessive loss across the
ferrite bead can lead to a malfunctioning ADC. Adjustable LDOs
can be employed to output a higher voltage to account for the
drop across the ferrite bead.
Data Sheet
AD9208
LAYOUT GUIDELINES
AVDD1_SR (PIN E7) AND AGND (PIN E6 AND PIN E8)
The ADC evaluation board can be used as a guide to follow
good layout practices. The evaluation board layout is set up in
such a way as to
AVDD1_SR (Pin E7) and AGND (Pin E6 and Pin E8) can be
used to provide a separate power supply node to the SYSREF±
circuits of the AD9208. If running in Subclass 1, the AD9208
can support periodic one-shot or gapped signals. To minimize
the coupling of this supply into the AVDD1 supply node,
adequate supply bypassing is needed.
Minimize coupling between the analog inputs (Channel A
to Channel B and Channel B to Channel A).
Minimize clock coupling to the analog inputs.
Provide enough power and ground planes for the various
supply domains while reducing cross coupling.
Provide adequate thermal relief to the ADC.
Figure 133 shows the overall layout scheme used for the
AD9208 evaluation board.
CH.A
EF
SR
SY
ADC
CH.B
JESD204B LANES
POWER
Figure 133. Recommended PCB Layout for the AD9208
Rev. 0 | Page 135 of 136
15547-128
CLK
AD9208
Data Sheet
OUTLINE DIMENSIONS
7.50 SQ
11.20 SQ
TOP VIEW
1.53
1.42
1.31
A
B
C
D
E
F
G
H
J
K
L
M
N
P
10.40 REF
SQ
0.80
BOTTOM VIEW
0.80 REF
DETAIL A
SIDE VIEW
0.71
REF
DETAIL A
1.19
1.09
0.99
0.38
0.33
0.28
0.34 REF
SEATING
PLANE
PKG-004807
A1 BALL
PAD CORNER
14 13 12 11 10 9 8 7 6 5 4 3 2 1
0.50
0.45
0.40
BALL DIAMETER
COPLANARITY
0.12
COMPLIANT TO JEDEC STANDARDS MO-275-GGAB-1.
12-07-2015-B
A1 BALL
PAD CORNER
12.10
12.00 SQ
11.90
Figure 134. 196-Ball Ball Grid Array, Thermally Enhanced [BGA_ED]
12 mm × 12 mm (BP-196-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
AD9208BBPZ-3000
AD9208BBPZRL-3000
AD9208-3000EBZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
196-Ball Ball Grid Array, Thermally Enhanced [BGA_ED]
196-Ball Ball Grid Array, Thermally Enhanced [BGA_ED]
Evaluation Board
Z = RoHS Compliant Part.
©2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D15547-0-4/17(0)
Rev. 0 | Page 136 of 136
Package Option
BP-196-4
BP-196-4
工商网监
湘ICP备2023018690号
