AD9228ABCPZRL7-40

Quad, 12-Bit, 40 MSPS/65 MSPS Serial LVDS 1.8 V A/D Converter AD9228 Data Sheet FUNCTIONAL BLOCK DIAGRAM 4 ADCs integrated into 1 package 119 mW ADC power per channel at 65 MSPS SNR = 70 dB (to Nyquist) ENOB = 11.3 bits SFDR = 82 dBc (to Nyquist) Excellent linearity DNL = ±0.3 LSB (typical) INL = ±0.4 LSB (typical) Serial LVDS (ANSI-644, default) Low power, reduced signal option (similar to IEEE 1596.3) Data and frame clock outputs 315 MHz full power analog bandwidth 2 V p-p input voltage range 1.8 V supply operation Serial port control Full chip and individual channel power-down modes Flexible bit orientation Built in and custom digital test pattern generation Programmable clock and data alignment Programmable output resolution Standby mode AVDD GENERAL DESCRIPTION The AD9228 is a quad, 12-bit, 40/65 MSPS analog-to-digital converter (ADC) with an on-chip sample-and-hold circuit designed for low cost, low power, small size, and ease of use. The product operates at a conversion rate of up to 65 MSPS and is optimized for outstanding dynamic performance and low power in applications where a small package size is critical. The ADC requires a single 1.8 V power supply and LVPECL-/ CMOS-/LVDS-compatible sample rate clock for full performance operation. No external reference or driver components are required for many applications. The ADC automatically multiplies the sample rate clock for the appropriate LVDS serial data rate. A data clock output (DCO) for Rev. G DRVDD AD9228 PIPELINE ADC VIN + B VIN – B PIPELINE ADC VIN + C VIN – C PIPELINE ADC VIN + D VIN – D PIPELINE ADC REFT REFB DRGND 12 VIN + A VIN – A SERIAL LVDS D+A D–A SERIAL LVDS D+B D–B SERIAL LVDS D+C D–C SERIAL LVDS D+D D–D 12 12 12 VREF SENSE + – REF SELECT FCO+ 0.5V SERIAL PORT INTERFACE DATA RATE MULTIPLIER RBIAS AGND CSB SDIO/ODM SCLK/DTP CLK+ CLK– FCO– DCO+ DCO– Figure 1. PRODUCT HIGHLIGHTS 1. APPLICATIONS Medical imaging and nondestructive ultrasound Portable ultrasound and digital beam-forming systems Quadrature radio receivers Diversity radio receivers Tape drives Optical networking Test equipment PDWN 05727-001 FEATURES 2. 3. 4. 5. Small Footprint. Four ADCs are contained in a small, spacesaving package. Low power of 119 mW/channel at 65 MSPS. Ease of Use. A data clock output (DCO) is provided that operates at frequencies of up to 390 MHz and supports double data rate (DDR) operation. User Flexibility. The SPI control offers a wide range of flexible features to meet specific system requirements. Pin-Compatible Family. This includes the AD9287 (8-bit), AD9219 (10-bit), and AD9259 (14-bit). capturing data on the output and a frame clock output (FCO) for signaling a new output byte are provided. Individual channel power-down is supported and typically consumes