Octal, 14-Bit, 50 MSPS,
Serial LVDS, 1.8 V ADC
AD9252
Data Sheet
8 analog-to-digital converters (ADCs) integrated into 1 package
93.5 mW ADC power per channel at 50 MSPS
SNR = 73 dB (to Nyquist)
ENOB = 12 bits
SFDR = 84 dBc (to Nyquist)
Excellent linearity
DNL = ±0.4 LSB (typical); INL = ±1.5 LSB (typical)
Serial LVDS (ANSI-644, default)
Low power, reduced signal option (similar to IEEE 1596.3)
Data and frame clock outputs
325 MHz, full-power analog bandwidth
2 V p-p input voltage range
1.8 V supply operation
Serial port control
Full-chip and individual-channel power-down modes
Flexible bit orientation
Built-in and custom digital test pattern generation
Programmable clock and data alignment
Programmable output resolution
Standby mode
APPLICATIONS
Medical imaging and nondestructive ultrasound
Portable ultrasound and digital beam-forming systems
Quadrature radio receivers
Diversity radio receivers
Tape drives
Optical networking
Test equipment
GENERAL DESCRIPTION
The AD9252 is an octal, 14-bit, 50 MSPS ADC with an on-chip
sample-and-hold circuit designed for low cost, low power, small size,
and ease of use. Operating at a conversion rate of up to 50 MSPS,
it is optimized for outstanding dynamic performance and low
power in applications where a small package size is critical.
The ADC requires a single 1.8 V power supply and LVPECL-/
CMOS-/LVDS-compatible sample rate clock for full performance
operation. No external reference or driver components are
required for many applications.
The ADC automatically multiplies the sample rate clock for
the appropriate LVDS serial data rate. A data clock (DCO)
for capturing data on the output and a frame clock (FCO) for
signaling a new output byte are provided. Individual channel
power-down is supported and typically consumes less than
2 mW when all channels are disabled.
FUNCTIONAL BLOCK DIAGRAM
PDWN
AVDD
DRVDD
AD9252
DRGND
14
VIN + A
VIN – A
ADC
VIN + B
VIN – B
ADC
VIN + C
VIN – C
ADC
VIN + D
VIN – D
ADC
VIN + E
VIN – E
ADC
VIN + F
VIN – F
ADC
VIN + G
VIN – G
ADC
VIN + H
VIN – H
ADC
SERIAL
LVDS
D+A
D–A
SERIAL
LVDS
D+B
D–B
SERIAL
LVDS
D+C
D–C
SERIAL
LVDS
D+D
D–D
SERIAL
LVDS
D+E
D–E
SERIAL
LVDS
D+F
D–F
SERIAL
LVDS
D+G
D–G
SERIAL
LVDS
D+H
D–H
14
14
14
14
14
14
14
VREF
SENSE
FCO+
0.5V
REFT
REFB
REF
SELECT
RBIAS
SERIAL PORT
INTERFACE
AGND CSB
SDIO/
ODM
SCLK/
DTP
DATA RATE
MULTIPLIER
CLK+
CLK–
FCO–
DCO+
DCO–
06296-001
FEATURES
Figure 1.
The ADC contains several features designed to maximize
flexibility and minimize system cost, such as programmable
clock and data alignment and programmable digital test pattern
generation. The available digital test patterns include built-in
deterministic and pseudorandom patterns, along with custom userdefined test patterns entered via the serial port interface (SPI).
The AD9252 is available in an RoHS compliant, 64-lead LFCSP. It is
specified over the industrial temperature range of −40°C to +85°C.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
Small Footprint. Eight ADCs are contained in a small package.
Low Power of 93.5 mW per Channel at 50 MSPS.
Ease of Use. A data clock output (DCO) operates up to
350 MHz and supports double data rate (DDR) operation.
User Flexibility. SPI control offers a wide range of flexible
features to meet specific system requirements.
Pin-Compatible Family. This includes the AD9212 (10-bit)
and AD9222 (12-bit).
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2006–2011 Analog Devices, Inc. All rights reserved.
AD9252
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Clock Input Considerations ...................................................... 19
Applications ....................................................................................... 1
Serial Port Interface (SPI) .............................................................. 27
General Description ......................................................................... 1
Hardware Interface ..................................................................... 27
Functional Block Diagram .............................................................. 1
Memory Map .................................................................................. 29
Product Highlights ........................................................................... 1
Reading the Memory Map Table .............................................. 29
Revision History ............................................................................... 2
Reserved Locations .................................................................... 29
Specifications..................................................................................... 3
Default Values ............................................................................. 29
AC Specifications.......................................................................... 4
Logic Levels ................................................................................. 29
Digital Specifications ................................................................... 5
Applications Information .............................................................. 32
Switching Specifications .............................................................. 6
Design Guidelines ...................................................................... 32
Timing Diagrams.......................................................................... 7
Evaluation Board ............................................................................ 33
Absolute Maximum Ratings ............................................................ 9
Power Supplies ............................................................................ 33
Thermal Impedance ..................................................................... 9
Input Signals................................................................................ 33
ESD Caution .................................................................................. 9
Output Signals ............................................................................ 33
Pin Configuration and Function Descriptions ........................... 10
Default Operation and Jumper Selection Settings ................. 34
Equivalent Circuits ......................................................................... 12
Alternative Analog Input Drive Configuration...................... 35
Typical Performance Characteristics ........................................... 14
Outline Dimensions ....................................................................... 52
Theory of Operation ...................................................................... 17
Ordering Guide .......................................................................... 52
Analog Input Considerations.................................................... 17
REVISION HISTORY
12/11—Rev. D to Rev. E
Changes to Output Signals Section and Figure 58 ..................... 33
Change to Default Operation and Jumper Selection Settings
Section .............................................................................................. 34
Added Endnote 2 in Ordering Guide .......................................... 52
4/10—Rev. C to Rev. D
Changes to Address 16 in Table 16............................................... 31
Updated Outline Dimensions ....................................................... 52
Changes to Ordering Guide .......................................................... 52
12/09—Rev. B to Rev. C
Updated Outline Dimensions ....................................................... 52
Changes to Ordering Guide .......................................................... 52
7/09—Rev. A to Rev. B
Changes to Figure 5 ........................................................................ 10
Changes to Figure 38 and Figure 39............................................. 18
Changes to Figure 51 and Figure 52............................................. 25
Updated Outline Dimensions ....................................................... 52
12/07—Rev. 0 to Rev. A
Changes to Features.......................................................................... 1
Changes to Crosstalk Parameter..................................................... 3
Changes to Figure 2 to Figure 4 ...................................................... 7
Changes to Table 9 Endnote .......................................................... 23
Changes to Digital Outputs and Timing Section ....................... 24
Added Table 10 ............................................................................... 24
Changes to Table 11 and Table 12 ................................................ 24
Changes to RBIAS Pin Section ..................................................... 25
Deleted Figure 51 to Figure 52...................................................... 25
Moved Figure 53 ............................................................................. 25
Changes to Serial Port Interface (SPI) Section ........................... 27
Changes to Table 15 ....................................................................... 28
Changes to Reading the Memory Map Table Section ............... 29
Added Applications Information and
Design Guidelines Sections ...................................................... 32
Changes to Input Signals Section ................................................. 33
Changes to Output Signals Section .............................................. 33
Changes to Figure 60...................................................................... 33
Changes to Default Operation and Jumper Selection
Settings Section .......................................................................... 34
Changes to Alternative Analog Input Drive
Configuration Section............................................................... 35
Added Figure 62 and Figure 63 .................................................... 35
Changes to Figure 68...................................................................... 42
Changes to Table 17 ....................................................................... 48
Updated Outline Dimensions ....................................................... 52
Changes to Ordering Guide .......................................................... 52
10/06—Revision 0: Initial Version
Rev. E | Page 2 of 52
Data Sheet
AD9252
SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 1.
Parameter 1
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Offset Matching
Gain Error
Gain Matching
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
TEMPERATURE DRIFT
Offset Error
Gain Error
Reference Voltage (1 V Mode)
REFERENCE
Output Voltage Error (VREF = 1 V)
Load Regulation @ 1.0 mA (VREF = 1 V)
Input Resistance
ANALOG INPUTS
Differential Input Voltage Range (VREF = 1 V)
Common-Mode Voltage
Differential Input Capacitance
Analog Bandwidth, Full Power
POWER SUPPLY
AVDD
DRVDD
IAVDD
IDRVDD
Total Power Dissipation (Including Output Drivers)
Power-Down Dissipation
Standby Dissipation 2
CROSSTALK
AIN = −0.5 dBFS
Overrange 3
Temperature
Min
14
AD9252-50
Typ
Max
Full
Full
Full
Full
Full
Full
Full
Guaranteed
±1
±3
±1.5
±0.3
±0.4
±1.5
Full
Full
Full
±2
±17
±21
Full
Full
Full
±2
3
6
Full
Full
Full
Full
2
AVDD/2
7
325
Full
Full
Full
Full
Full
Full
Full
Full
Full
1.7
1.7
1.8
1.8
360
55.5
748
2
89
−90
−90
±8
±8
±2.5
±0.7
±1
±4
Unit
Bits
mV
mV
% FS
% FS
LSB
LSB
ppm/°C
ppm/°C
ppm/°C
±30
mV
mV
kΩ
V p-p
V
pF
MHz
1.9
1.9
373.4
58
773
11
V
V
mA
mA
mW
mW
mW
dB
dB
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
Can be controlled via the SPI.
3
Overrange condition is specific with 6 dB of the full-scale input range.
1
2
Rev. E | Page 3 of 52
AD9252
Data Sheet
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 2.
Parameter 1
SIGNAL-TO-NOISE RATIO (SNR)
fIN = 2.4 MHz
fIN = 19.7 MHz
fIN = 35 MHz
fIN = 70 MHz
SIGNAL-TO-NOISE AND DISTORTION RATIO (SINAD)
fIN = 2.4 MHz
fIN = 19.7 MHz
fIN = 35 MHz
fIN = 70 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 2.4 MHz
fIN = 19.7 MHz
fIN = 35 MHz
fIN = 70 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 2.4 MHz
fIN = 19.7 MHz
fIN = 35 MHz
fIN = 70 MHz
WORST HARMONIC (SECOND OR THIRD)
fIN = 2.4 MHz
fIN = 19.7 MHz
fIN = 35 MHz
fIN = 70 MHz
WORST OTHER (EXCLUDING SECOND OR THIRD)
fIN = 2.4 MHz
fIN = 19.7 MHz
fIN = 35 MHz
fIN = 70 MHz
TWO-TONE INTERMODULATION DISTORTION (IMD)—AIN1 AND AIN2 = −7.0 dBFS
fIN1 = 15 MHz, fIN2 = 16 MHz
fIN1 = 70 MHz, fIN2 = 71 MHz
1
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Min
71
70.2
11.5
73
AD9252-50
Typ
Max
Unit
73.2
73
72.7
71
dB
dB
dB
dB
72.5
72.2
72
70.5
dB
dB
dB
dB
11.87
11.84
11.79
11.5
Bits
Bits
Bits
Bits
85
84
83
79
dBc
dBc
dBc
dBc
Full
Full
Full
Full
−85
−84
−83
−79
Full
Full
Full
Full
−90
−90
−90
−89
25°C
25°C
80.0
80.0
−73
−80
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
Rev. E | Page 4 of 52
Data Sheet
AD9252
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 3.
Parameter 1
CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Differential Input Voltage 2
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
LOGIC INPUTS (PDWN, SCLK/DTP)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (CSB)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC INPUT (SDIO/ODM)
Logic 1 Voltage
Logic 0 Voltage
Input Resistance
Input Capacitance
LOGIC OUTPUT (SDIO/ODM)3
Logic 1 Voltage (IOH = 800 μA)
Logic 0 Voltage (IOL = 50 μA)
DIGITAL OUTPUTS (D + x, D − x), (ANSI-644)
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
DIGITAL OUTPUTS (D + x, D − x),
(LOW POWER, REDUCED SIGNAL OPTION)
Logic Compliance
Differential Output Voltage (VOD)
Output Offset Voltage (VOS)
Output Coding (Default)
1
2
3
Temperature
Min
Full
Full
25°C
25°C
250
Full
Full
25°C
25°C
1.2
Full
Full
25°C
25°C
1.2
Full
Full
25°C
25°C
1.2
0
AD9252-50
Typ
Max
Unit
CMOS/LVDS/LVPECL
mV p-p
V
kΩ
pF
1.2
20
1.5
3.6
0.3
V
V
kΩ
pF
3.6
0.3
V
V
kΩ
pF
DRVDD + 0.3
0.3
V
V
kΩ
pF
30
0.5
70
0.5
30
2
Full
Full
1.79
0.05
V
V
454
1.375
mV
V
250
1.30
mV
V
LVDS
Full
Full
247
1.125
Offset binary
LVDS
Full
Full
150
1.10
Offset binary
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
This is specified for LVDS and LVPECL only.
This is specified for 13 SDIO pins sharing the same connection.
Rev. E | Page 5 of 52
AD9252
Data Sheet
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, 2 V p-p differential input, 1.0 V internal reference, AIN = −0.5 dBFS, unless otherwise noted.
Table 4.
Parameter 1
CLOCK 2
Maximum Clock Rate
Minimum Clock Rate
Clock Pulse Width High (tEH)
Clock Pulse Width Low (tEL)
OUTPUT PARAMETERS2, 3
Propagation Delay (tPD)
Rise Time (tR) (20% to 80%)
Fall Time (tF) (20% to 80%)
FCO Propagation Delay (tFCO)
DCO Propagation Delay (tCPD) 4
DCO to Data Delay (tDATA)4
DCO to FCO Delay (tFRAME)4
Data-to-Data Skew (tDATA-MAX − tDATA-MIN)
Wake-Up Time (Standby)
Wake-Up Time (Power-Down)
Pipeline Latency
APERTURE
Aperture Delay (tA)
Aperture Uncertainty (Jitter)
Out-of-Range Recovery Time
Temp
Min
Full
Full
Full
Full
50
Full
Full
Full
Full
Full
Full
Full
Full
25°C
25°C
Full
1.5
AD9252-50
Typ
Max
10
10.0
10.0
1.5
(tSAMPLE/28) − 300
(tSAMPLE/28) − 300
25°C
25°C
25°C
2.3
300
300
2.3
tFCO + (tSAMPLE/28)
(tSAMPLE/28)
(tSAMPLE/28)
±50
600
375
8
750