14-Bit, 150 MSPS, 1.8 V
Analog-to-Digital Converter
AD9254
FEATURES
FUNCTIONAL BLOCK DIAGRAM
AVDD
AD9254
VIN+
VIN–
Macro, micro, and pico cell infrastructure
GENERAL DESCRIPTION
The AD9254 is a monolithic, single 1.8 V supply, 14-bit, 150 MSPS
analog-to-digital converter (ADC), featuring a high performance
sample-and-hold amplifier (SHA) and on-chip voltage reference.
The product uses a multistage differential pipeline architecture
with output error correction logic to provide 14-bit accuracy at
150 MSPS data rates and guarantees no missing codes over the
full operating temperature range.
The wide bandwidth, truly differential SHA allows a variety of
user-selectable input ranges and offsets, including single-ended
applications. It is suitable for multiplexed systems that switch
full-scale voltage levels in successive channels and for sampling
single-channel inputs at frequencies well beyond the Nyquist rate.
Combined with power and cost savings over previously available
ADCs, the AD9254 is suitable for applications in
communications, imaging, and medical ultrasound.
A differential clock input controls all internal conversion cycles.
A duty cycle stabilizer (DCS) compensates for wide variations in
the clock duty cycle while maintaining excellent overall ADC
performance.
8-STAGE
1 1/2-BIT PIPELINE
MDAC1
SHA
4
8
A/D
3
A/D
REFT
REFB
CORRECTION LOGIC
OR
15
OUTPUT BUFFERS
DCO
D13 (MSB)
VREF
D0 (LSB)
SENSE
0.5V
REF
SELECT
AGND
APPLICATIONS
Ultrasound equipment
IF sampling in communications receivers
CDMA2000, WCDMA, TD-SCDMA, and WiMax
Battery-powered instruments
Hand-held scopemeters
Low cost digital oscilloscopes
DRVDD
CLOCK
DUTY CYCLE
STABILIZER
CLK+
CLK–
SCLK/DFS
MODE
SELECT
PDWN
SDIO/DCS
CSB
DRGND
06216-001
1.8 V analog supply operation
1.8 V to 3.3 V output supply
SNR = 71.8 dBc (72.8 dBFS) to 70 MHz input
SFDR = 84 dBc to 70 MHz input
Low power: 430 mW @ 150 MSPS
Differential input with 650 MHz bandwidth
On-chip voltage reference and sample-and-hold amplifier
DNL = ±0.4 LSB
Flexible analog input: 1 V p-p to 2 V p-p range
Offset binary, Gray code, or twos complement data format
Clock duty cycle stabilizer
Data output clock
Serial port control
Built-in selectable digital test pattern generation
Programmable clock and data alignment
Figure 1.
The digital output data is presented in offset binary, Gray code, or
twos complement formats. A data output clock (DCO) is
provided to ensure proper latch timing with receiving logic.
The AD9254 is available in a 48-lead LFCSP and is specified over
the industrial temperature range (−40°C to +85°C).
PRODUCT HIGHLIGHTS
1.
The AD9254 operates from a single 1.8 V power supply
and features a separate digital output driver supply to
accommodate 1.8 V to 3.3 V logic families.
2.
The patented SHA input maintains excellent performance
for input frequencies up to 225 MHz.
3.
The clock DCS maintains overall ADC performance over a
wide range of clock pulse widths.
4.
A standard serial port interface supports various product
features and functions, such as data formatting (offset
binary, twos complement, or Gray coding), enabling the
clock DCS, power-down, and voltage reference mode.
5.
The AD9254 is pin-compatible with the AD9233, allowing
a simple migration from 12 bits to 14 bits.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice.
No license is granted by implication or otherwise under any patent or patent rights of Analog
Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2006–2020 Analog Devices, Inc. All rights reserved.
AD9254
TABLE OF CONTENTS
Features .............................................................................................. 1
Timing ......................................................................................... 20
Applications ...................................................................................... 1
Serial Port Interface (SPI) ............................................................. 21
General Description ......................................................................... 1
Configuration Using the SPI .................................................... 21
Functional Block Diagram .............................................................. 1
Hardware Interface .................................................................... 21
Product Highlights ........................................................................... 1
Configuration Without the SPI ................................................ 21
Revision History ............................................................................... 2
Memory Map .................................................................................. 22
Specifications .................................................................................... 3
Reading the Memory Map Register Table .............................. 22
DC Specifications ......................................................................... 3
Memory Map Register Table .................................................... 23
AC Specifications ......................................................................... 4
Layout Considerations................................................................... 25
Digital Specifications ................................................................... 5
Power and Ground Recommendations .................................. 25
Switching Specifications .............................................................. 6
CML ............................................................................................. 25
Timing Diagram ........................................................................... 6
RBIAS........................................................................................... 25
Absolute Maximum Ratings ........................................................... 7
Reference Decoupling................................................................ 25
Thermal Resistance ...................................................................... 7
Evaluation Board ............................................................................ 26
ESD Caution.................................................................................. 7
Power Supplies ........................................................................... 26
Pin Configuration and Function Descriptions ............................ 8
Input Signals ............................................................................... 26
Equivalent Circuits ........................................................................... 9
Output Signals ............................................................................ 26
Typical Performance Characteristics ........................................... 10
Default Operation and Jumper Selection Settings ................ 27
Theory of Operation ...................................................................... 14
Alternative Clock Configurations ............................................ 27
Analog Input Considerations ................................................... 14
Alternative Analog Input Drive Configuration ..................... 27
Differential Input Configurations ............................................ 15
Schematics ................................................................................... 29
Voltage Reference....................................................................... 16
Evaluation Board Layout........................................................... 34
Clock Input Considerations...................................................... 17
Bill of Materials .......................................................................... 37
Jitter Considerations .................................................................. 19
Outline Dimensions ....................................................................... 40
Power Dissipation and Standby Mode .................................... 19
Ordering Guide .......................................................................... 40
Digital Outputs ........................................................................... 20
REVISION HISTORY
11/2020—Rev. 0 to Rev. A
Changed CP-48-3 to CP-48-5 ...................................... Throughout
Changes to Figure 3.......................................................................... 8
Updated Outline Dimensions ....................................................... 40
Changes to Ordering Guide .......................................................... 40
10/2006—Revision 0: Initial Version
Rev. A | Page 2 of 40
AD9254
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS enabled,
unless otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)1
Integral Nonlinearity (INL)1
TEMPERATURE DRIFT
Offset Error
Gain Error
INTERNAL VOLTAGE REFERENCE
Output Voltage Error (1 V Mode)
Load Regulation @ 1.0 mA
INPUT REFERRED NOISE
VREF = 1.0 V
ANALOG INPUT
Input Span, VREF = 1.0 V
Input Capacitance2
REFERENCE INPUT RESISTANCE
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
Supply Current
IAVDD1
IDRVDD1(DRVDD = 1.8 V)
IDRVDD1 (DRVDD = 3.3 V)
POWER CONSUMPTION
DC Input
Sine Wave Input1 (DRVDD = 1.8 V)
Sine Wave Input1 (DRVDD = 3.3 V)
Standby Power3
Power-Down Power
Temperature
Full
Min
14
AD9254BCPZ-150
Typ
Max
Unit
Bits
Full
Full
Full
25°C
Full
25°C
Full
Guaranteed
±0.3
±0.8
±0.6
±4.5
±0.4
±1.0
±1.5
±5.0
% FSR
% FSR
LSB
LSB
LSB
LSB
Full
Full
±15
±95
ppm/°C
ppm/°C
Full
Full
±5
7
25°C
1.3
LSB rms
Full
Full
Full
2
8
6
V p-p
pF
kΩ
Full
Full
mV
mV
1.8
2.5
1.9
3.6
V
V
Full
Full
Full
240
11
23
260
mA
mA
mA
Full
Full
Full
Full
Full
430
450
506
40
1.8
470
mW
mW
mW
mW
mW
1
1.7
1.7
±35
Measured with a low input frequency, full-scale sine wave, with approximately 5 pF loading on each output bit.
Input capacitance refers to the effective capacitance between one differential input pin and AGND. Refer to Figure 4 for the equivalent analog input structure.
3
Standby power is measured with a dc input, the CLK pin inactive (set to AVDD or AGND).
2
Rev. A | Page 3 of 40
AD9254
AC SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS enabled,
unless otherwise noted.
Table 2.
Parameter1
SIGNAL-TO-NOISE-RATIO (SNR)
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
SIGNAL-TO-NOISE AND DISTORTION (SINAD)
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
WORST SECOND OR THIRD HARMONIC
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
WORST OTHER (HARMONIC OR SPUR)
fIN = 2.4 MHz
fIN = 70 MHz
fIN = 100 MHz
fIN = 170 MHz
TWO-TONE SFDR
fIN = 29 MHz (−7 dBFS ), 32 MHz (−7 dBFS )
fIN = 169 MHz (−7 dBFS ), 172 MHz (−7 dBFS )
ANALOG INPUT BANDWIDTH
1
Temperature
25°C
25°C
Full
25°C
25°C
25°C
25°C
Full
25°C
25°C
Min
AD9254BCPZ-150
Typ
Max
72.0
71.8
Unit
dBc
dBc
dBc
dBc
dBc
70.0
71.6
70.8
71.7
71.0
70.6
69.8
dBc
dBc
dBc
dBc
dBc
25°C
25°C
25°C
25°C
11.7
11.7
11.6
11.5
Bits
Bits
Bits
Bits
25°C
25°C
Full
25°C
25°C
−90
−84
dBc
dBc
dBc
dBc
dBc
25°C
25°C
Full
25°C
25°C
90
84
69.0
−74
−83
−80
dBc
dBc
dBc
dBc
dBc
74
83
80
25°C
25°C
Full
25°C
25°C
−93
−93
−90
−90
dBc
dBc
dBc
dBc
dBc
25°C
25°C
25°C
90
90
650
dBFS
dBFS
MHz
See Application Note AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
Rev. A | Page 4 of 40
−85
AD9254
DIGITAL SPECIFICATIONS
AVDD = 1.8 V; DRVDD = 2.5 V, maximum sample rate, 2 V p-p differential input, 1.0 V internal reference; AIN = −1.0 dBFS, DCS enabled,
unless otherwise noted.
Table 3.
Parameter
DIFFERENTIAL CLOCK INPUTS (CLK+, CLK−)
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
Input Voltage Range
Input Common-Mode Range
High Level Input Voltage (VIH)
Low Level Input Voltage (VIL)
High Level Input Current (IIH)
Low Level Input Current (IIL)
Input Resistance
Input Capacitance
LOGIC INPUTS (SCLK/DFS, OEB, PWDN)
High Level Input Voltage (VIH)
Low Level Input Voltage (VIL)
High Level Input Current (IIH)
Low Level Input Current (IIL)
Input Resistance
Input Capacitance
LOGIC INPUTS (CSB)
High Level Input Voltage (VIH)
Low Level Input Voltage (VIL)
High Level Input Current (IIH)
Low Level Input Current (IIL)
Input Resistance
Input Capacitance
LOGIC INPUTS (SDIO/DCS)
High Level Input Voltage (VIH)
Low Level Input Voltage (VIL)
High Level Input Current (IIH)
Low Level Input Current (IIL)
Input Resistance
Input Capacitance
DIGITAL OUTPUTS
DRVDD = 3.3 V
High Level Output Voltage (VOH, IOH = 50 μA)
High Level Output Voltage (VOH, IOH = 0.5 mA)
Low Level Output Voltage (VOL, IOL = 1.6 mA)
Low Level Output Voltage (VOL, IOL = 50 μA)
DRVDD = 1.8 V
High Level Output Voltage (VOH, IOH = 50 μA)
High Level Output Voltage (VOH, IOH = 0.5 mA)
Low Level Output Voltage (VOL, IOL = 1.6 mA)
Low Level Output Voltage (VOL, IOL = 50 μA)
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Min
AD9254BCPZ-150
Typ
Max
Unit
6
AVDD + 1.6
AVDD
3.6
0.8
+10
+10
12
V
V p-p
V
V
V
V
μA
μA
kΩ
pF
CMOS/LVDS/LVPECL
1.2
0.2
AVDD − 0.3
1.1
1.2
0
−10
−10
8
Full
Full
Full
Full
Full
Full
1.2
0
−50
−10
Full
Full
Full
Full
Full
Full
1.2
0
−10
+40
Full
Full
Full
Full
Full
Full
1.2
0
−10
+40
Full
Full
Full
Full
3.29
3.25
Full
Full
Full
Full
1.79
1.75
10
4
3.6
0.8
−75
+10
V
V
μA
μA
kΩ
pF
3.6
0.8
+10
+135
V
V
μA
μA
kΩ
pF
DRVDD + 0.3
0.8
+10
+130
V
V
μA
μA
kΩ
pF
30
2
26
2
26
5
Rev. A | Page 5 of 40
0.2
0.05
V
V
V
V
0.2
0.05
V
V
V
V
AD9254
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 2.5 V, unless otherwise noted.
Table 4.
Parameter1
CLOCK INPUT PARAMETERS
Conversion Rate, DCS Enabled
Conversion Rate, DCS Disabled
CLK Period
CLK Pulse Width High, DCS Enabled
CLK Pulse Width High, DCS Disabled
DATA OUTPUT PARAMETERS
Data Propagation Delay (tPD)2
DCO Propagation Delay (tDCO)
Setup Time (tS)
Hold Time (tH)
Pipeline Delay (Latency)
Aperture Delay (tA)
Aperture Uncertainty (Jitter, tJ)
Wake-Up Time3
OUT-OF-RANGE RECOVERY TIME
SERIAL PORT INTERFACE4
SCLK Period (tCLK)
SCLK Pulse Width High Time (tHI)
SCLK Pulse Width Low Time (tLO)
SDIO to SCLK Setup Time (tDS)
SDIO to SCLK Hold Time (tDH)
CSB to SCLK Setup Time (tS)
CSB to SCLK Hold Time (tH)
Temperature
Min
Full
Full
Full
Full
Full
20
10
6.7
2.0
3.0
Full
Full
Full
Full
Full
Full
Full
Full
Full
3.1
Full
Full
Full
Full
Full
Full
Full
40
16
16
5
2
5
2
AD9254BCPZ-150
Typ
Max
150
150
1.9
3.0
3.3
3.3
4.7
3.7
3.9
4.4
2.9
3.8
12
0.8
0.1
350
3
4.8
See Application Note AN-835, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions.
Output propagation delay is measured from CLK 50% transition to DATA 50% transition, with 5 pF load.
Wake-up time is dependent on the value of the decoupling capacitors, values shown with 0.1 μF capacitor across REFT and REFB.
4
See Figure 50 and the Serial Port Interface (SPI) section.
2
3
TIMING DIAGRAM
N+2
N+3
N
N+4
tA
N+8
N+5
N+6
N+7
N–7
N–6
tCLK
CLK+
CLK–
tPD
N – 13
tS
N – 12
N – 11
tH
N – 10
N–9
N–8
tDCO
DCO
Figure 2. Timing Diagram
Rev. A | Page 6 of 40
tCLK
N–5
N–4
06216-002
DATA
MSPS
MSPS
ns
ns
ns
ns
ns
ns
ns
Cycles
ns
ps rms
μs
Cycles
ns
ns
ns
ns
ns
ns
ns
1
N+1
Unit
AD9254
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
ELECTRICAL
AVDD to AGND
DRVDD to DGND
AGND to DGND
AVDD to DRVDD
D0 through D13 to DGND
DCO to DGND
OR to DGND
CLK+ to AGND
CLK− to AGND
VIN+ to AGND
VIN− to AGND
VREF to AGND
SENSE to AGND
REFT to AGND
REFB to AGND
SDIO/DCS to DGND
PDWN to AGND
CSB to AGND
SCLK/DFS to AGND
OEB to AGND
ENVIRONMENTAL
Storage Temperature Range
Operating Temperature Range
Lead Temperature
(Soldering 10 Sec)
Junction Temperature
Rating
−0.3 V to +2.0 V
−0.3 V to +3.9 V
−0.3 V to +0.3 V
−3.9 V to +2.0 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to +3.9 V
−0.3 V to +3.9 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to DRVDD + 0.3 V
−0.3 V to +3.9 V
−0.3 V to +3.9 V
−0.3 V to +3.9 V
−0.3 V to +3.9 V
–65°C to +125°C
–40°C to +85°C
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL RESISTANCE
The exposed paddle must be soldered to the ground plane for
the LFCSP package. Soldering the exposed paddle to the
customer board increases the reliability of the solder joints,
maximizing the thermal capability of the package.
Table 6. Thermal Resistance
Package Type
48-lead LFCSP (CP-48-5)
θJA
26.4
θJC
2.4
Unit
°C/W
Typical θJA and θJC are specified for a 4-layer board in still air.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, metal in direct contact with the package leads from
metal traces and through holes, ground, and power planes,
reduces the θJA.
ESD CAUTION
150°C
Rev. A | Page 7 of 40
AD9254
48
47
46
45
44
43
42
41
40
39
38
37
DRVDD
DRGND
D1
D0 (LSB)
DCO
OEB
AVDD
AGND
AVDD
CLK–
CLK+
AGND
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
D2 1
D3 2
D4 3
D5 4
D6 5
D7 6
DRGND 7
DRVDD 8
D8 9
D9 10
D10 11
D11 12
AD9254
PDWN
RBIAS
CML
AVDD
AGND
VIN–
VIN+
AGND
REFT
REFB
VREF
SENSE
06216-003
D12
D13 (MSB)
OR
DRGND
DRVDD
SDIO/DCS
SCLK/DFS
CSB
AGND
AVDD
AGND
AVDD
13
14
15
16
17
18
19
20
21
22
23
24
TOP VIEW
(Not to Scale)
36
35
34
33
32
31
30
29
28
27
26
25
Figure 3. Pin Configuration
Table 7. Pin Function Description
Pin No.
0, 21, 23, 29, 32,
37, 41
45, 46, 1 to 6,
9 to 14
7, 16, 47
8, 17, 48
15
18
Mnemonic
AGND
Description
Analog Ground. (Pin 0 is the exposed thermal pad on the bottom of the package.)
D0 (LSB) to D13 (MSB)
Data Output Bits.
DRGND
DRVDD
OR
SDIO/DCS
19
20
22, 24, 33, 40, 42
25
26
27
28
30
31
34
35
SCLK/DFS
CSB
AVDD
SENSE
VREF
REFB
REFT
VIN+
VIN–
CML
RBIAS
36
38
39
43
44
PDWN
CLK+
CLK–
OEB
DCO
Digital Output Ground.
Digital Output Driver Supply (1.8 V to 3.3 V).
Out-of-Range Indicator.
Serial Port Interface (SPI) Data Input/Output (Serial Port Mode); Duty Cycle Stabilizer Select
(External Pin Mode). See Table 10.
Serial Port Interface Clock (Serial Port Mode); Data Format Select Pin (External Pin Mode).
Serial Port Interface Chip Select (Active Low). See Table 10.
Analog Power Supply.
Reference Mode Selection. See Table 9.
Voltage Reference Input/Output.
Differential Reference (−).
Differential Reference (+).
Analog Input Pin (+).
Analog Input Pin (−).
Common-Mode Level Bias Output.
External Bias Resistor Connection. A 10 kΩ resistor must be connected between this pin and
analog ground (AGND).
Power-Down Function Select.
Clock Input (+).
Clock Input (−).
Output Enable (Active Low).
Data Clock Output.
Rev. A | Page 8 of 40
AD9254
EQUIVALENT CIRCUITS
1kΩ
SCLK/DFS
OEB
PDWN
30kΩ
06216-008
06216-004
VIN
Figure 8. Equivalent SCLK/DFS, OEB, PDWN Input Circuit
Figure 4. Equivalent Analog Input Circuit
AVDD
AVDD
26kΩ
1.2V
1kΩ
CLK–
06216-005
CLK+
CSB
10kΩ
06216-009
10kΩ
Figure 9. Equivalent CSB Input Circuit
Figure 5. Equivalent Clock Input Circuit
DRVDD
SENSE
1kΩ
1kΩ
06216-006
06216-010
SDIO/DCS
Figure 10. Equivalent Sense Circuit
Figure 6. Equivalent SDIO/DCS Input Circuit
DRVDD
AVDD
6kΩ
06216-007
DRGND
06216-011
VREF
Figure 11. Equivalent VREF Circuit
Figure 7. Equivalent Digital Output Circuit
Rev. A | Page 9 of 40
AD9254
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 1.8 V; DRVDD = 2.5 V; maximum sample rate, DCS enabled, 1 V internal reference; 2 V p-p differential input; AIN = −1.0 dBFS;
64k sample; TA = 25°C, unless otherwise noted.
0
–40
–60
–80
–40
–60
–80
–100
18.75
37.50
56.25
75.00
FREQUENCY (MHz)
–120
06216-012
0
–60
–80
–40
–60
–80
–100
18.75
37.50
56.25
75.00
–120
06216-013
0
FREQUENCY (MHz)
0
18.75
37.50
56.25
75.00
Figure 16. AD9254 Single-Tone FFT with fIN = 140.3 MHz
0
150MSPS
70.3MHz @ –1dBFS
SNR = 71.8dBc (72.8dBFS)
ENOB = 11.7 BITS
SFDR = 84dBc
150MSPS
170.3MHz @ –1dBFS
SNR = 70.8dBc (71.8dBFS)
ENOB = 11.5 BITS
SFDR = 80dBc
–20
AMPLITUDE (dBFS)
–20
0
FREQUENCY (MHz)
Figure 13. AD9254 Single-Tone FFT with fIN = 30.3 MHz
–40
–60
–80
–40
–60
–80
–100
0
18.75
37.50
56.25
FREQUENCY (MHz)
75.00
Figure 14. AD9254 Single-Tone FFT with fIN = 70.3 MHz
–120
0
18.75
37.50
56.25
75.00
FREQUENCY (MHz)
Figure 17. AD9254 Single-Tone FFT with fIN = 170.3 MHz
Rev. A | Page 10 of 40
06216-017
–100
06216-014
AMPLITUDE (dBFS)
75.00
06216-016
–100
–120
56.25
150MSPS
140.3MHz @ –1dBFS
SNR = 71.5dBc (72.5dBFS)
ENOB = 11.5 BITS
SFDR = 81dBc
–20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
0
–40
–120
37.50
Figure 15. AD9254 Single-Tone FFT with fIN = 100.3 MHz
150MSPS
30.3MHz @ –1dBFS
SNR = 71.9dBc (72.9dBFS)
ENOB = 11.7 BITS
SFDR = 88dBc
–20
18.75
FREQUENCY (MHz)
Figure 12. AD9254 Single-Tone FFT with fIN = 2.3 MHz
0
0
06216-015
–100
–120
150MSPS
100.3MHz @ –1dBFS
SNR = 71.6dBc (72.6dBFS)
ENOB = 11.6 BITS
SFDR = 83dBc
–20
AMPLITUDE (dBFS)
–20
AMPLITUDE (dBFS)
0
150MSPS
2.3MHz @ –1dBFS
SNR = 72.0dBc (73.0dBFS)
ENOB = 11.7 BITS
SFDR = 90.0dBc
AD9254
0
SFDR (dBFS)
100
SNR/SFDR (dBc and dBFS)
–20
AMPLITUDE (dBFS)
120
150MSPS
250.3MHz @ –1dBFS
SNR = 69.3dBc (70.3dBFS)
ENOB = 11.3 BITS
SFDR = 79dBc
–40
–60
–80
–100
80
SNR (dBFS)
60
40
SFDR (dBc)
85dBc
REFERENCE LINE
20
37.50
56.25
75.00
FREQUENCY (MHz)
SFDR/WORST IMD3 (dBc and dBFS)
AMPLITUDE (dBFS)
–60
–80
18.75
37.50
56.25
75.00
FREQUENCY (MHz)
–40
–30
–20
–10
0
–20
SFDR (–dBc)
–40
WORST IMD3 (dBc)
–60
–80
SFDR (–dBFS)
–100
–120
–90
06216-019
–100
0
–50
0
–40
–120
–60
Figure 21. AD9254 Single-Tone SNR/SFDR vs. Input Amplitude (AIN)
with fIN = 2.4 MHz
150MSPS
fIN1 = 29.1MHz @ –7dBFS
fIN2 = 32.1MHz @ –7dBFS
SFDR = 83.2dBc (90.2dBFS)
WoIMD3 = –83.9dBc (–90.9dBFS)
–20
–70
INPUT AMPLITUDE (dBFS)
Figure 18. AD9254 Single-Tone FFT with fIN = 250.3 MHz
0
–80
WORST IMD3 (dBFS)
–78
–66
–54
–42
–30
–18
–6
INPUT AMPLITUDE (dBFS)
06216-022
18.75
06216-018
0
0
–90
06216-021
SNR (dBc)
–120
Figure 22. AD9254 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN)
with fIN1 = 29.1 MHz, fIN2 = 32.1 MHz
Figure 19. AD9254 Two-Tone FFT with fIN1 = 29.1 MHz, fIN2 = 32.1 MHz
90
90
SFDR +25°C
SFDR –40°C
SFDR –40°C
85
85
SNR/SFDR (dBc)
75
SNR –40°C
SFDR +85°C
65
60
SNR +25°C
0
50
100
150
200
250
300
INPUT FREQUENCY (MHz)
80
SFDR +85°C
75
70
SNR +25°C
SNR –40°C
65
SNR +85°C
350
400
60
Figure 20. AD9254 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and
Temperature with 2 V p-p Full Scale
SNR +85°C
0
50
100
150
200
250
300
INPUT FREQUENCY (MHz)
350
400
06216-023
70
06216-020
SNR/SFDR (dBc)
SFDR +25°C
80
Figure 23. AD9254 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and
Temperature with 1 V p-p Full Scale
Rev. A | Page 11 of 40
AD9254
2.0
0
150MSPS
fIN1 = 169.1MHz @ –7dBFS
fIN2 = 172.1MHz @ –7dBFS
SFDR = 83dBc (90dBFS)
WoIMD3 = –83dBc (90dBFS)
AMPLITUDE (dBFS)
–20
1.5
1.0
INL ERROR (LSB)
–40
–60
–80
0.5
0
–0.5
–1.0
–100
18.75
37.50
56.25
75.00
–2.0
FREQUENCY (MHz)
0
2048
4096
6144
8192
10240
12288
14336
16384
OUTPUT CODE
06216-031
0
06216-024
–120
–1.5
Figure 27. AD9254 INL with fIN = 10.3 MHz
Figure 24. AD9254 Two-Tone FFT with fIN1 = 169.1 MHz, fIN2 = 172.1 MHz
12000
95
32768 SAMPLES
1.25 LSB rms
10000
90
85
NUMBER OF HITS
SNR/SFDR (dBc)
SFDR
80
75
8000
6000
4000
SNR
20
30
40
50
60
70
80
0
06216-025
65
10
90 100 110 120 130 140 150
CLOCK FREQUENCY (MSPS)
N–5N–4N–3N–2N–1
N+1N+2N+3N+4N+5
Figure 28. AD9254 Grounded Input Histogram
Figure 25. AD9254 Single-Tone SNR/SFDR vs. Clock Frequency (fCLK)
with fIN = 2.4 MHz
0
0
OFFSET ERROR
–20
–0.5
SFDR (–dBc)
–40
ERROR (%FS)
SFDR/WORST IMD3 (dBc and dBFS)
N
CODE
06216-032
2000
70
WORST IMD3 (dBc)
–60
–1.0
–1.5
–80
GAIN ERROR
SFDR (–dBFS)
–2.0
–100
–66
–54
–42
–30
INPUT AMPLITUDE (dBFS)
–18
–6
–2.5
–40
–20
0
20
40
60
TEMPERATURE (°C)
Figure 29. AD9254 Gain and Offset vs. Temperature
Figure 26. AD9254 Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN)
with fIN1 = 169.1 MHz, fIN2 = 172.11 MHz
Rev. A | Page 12 of 40
80
06216-033
–78
06216-027
WORST IMD3 (dBFS)
–120
–90
AD9254
0.5
0.4
0.2
0.1
0
–0.1
–0.2
–0.3
–0.4
–0.5
0
2048
4096
6144
8192
10240
12288
14336
OTUPUT CODE
16384
06216-034
DNL ERROR (LSB)
0.3
Figure 30. AD9254 DNL with fIN = 10.3 MHz
Rev. A | Page 13 of 40
AD9254
THEORY OF OPERATION
S
The AD9254 architecture consists of a front-end sample-andhold amplifier (SHA) followed by a pipelined switched
capacitor ADC. The quantized outputs from each stage are
combined into a final 14-bit result in the digital correction
logic. The pipeline architecture permits the first stage to
operate on a new input sample, while the remaining stages
operate on preceding samples. Sampling occurs on the rising
edge of the clock.
The input stage contains a differential SHA that can be ac- or
dc-coupled in differential or single-ended modes. The output
staging block aligns the data, carries out the error correction,
and passes the data to the output buffers. The output buffers
are powered from a separate supply, allowing adjustment of the
output voltage swing. During power-down, the output buffers
go into a high impedance state.
ANALOG INPUT CONSIDERATIONS
CS
VIN+
CPIN, PAR
S
H
CS
VIN–
CH
CPIN, PAR
S
06216-035
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue
amplifier magnifies the difference between the reconstructed
DAC output and the flash input for the next stage in the
pipeline. One bit of redundancy is used in each stage to
facilitate digital correction of flash errors. The last stage
consists only of a flash ADC.
CH
S
Figure 31. Switched-Capacitor SHA Input
For best dynamic performance, the source impedances driving
VIN+ and VIN− should match such that common-mode settling
errors are symmetrical. These errors are reduced by the commonmode rejection of the ADC.
An internal differential reference buffer creates two reference
voltages used to define the input span of the ADC core. The
span of the ADC core is set by the buffer to be 2 × VREF. The
reference voltages are not available to the user. Two bypass points,
REFT and REFB, are brought out for decoupling to reduce the
noise contributed by the internal reference buffer. It is recommended that REFT be decoupled to REFB by a 0.1 μF capacitor,
as described in the Layout Considerations section.
Input Common Mode
The analog input to the AD9254 is a differential switched
capacitor SHA that has been designed for optimum
performance while processing a differential input signal.
The clock signal alternately switches the SHA between sample
mode and hold mode (see Figure 31). When the SHA is switched
into sample mode, the signal source must be capable of charging
the sample capacitors and settling within one-half of a clock cycle.
A small resistor in series with each input can help reduce the
peak transient current required from the output stage of the
driving source.
A shunt capacitor can be placed across the inputs to provide
dynamic charging currents. This passive network creates a lowpass filter at the ADC input; therefore, the precise values are
dependent upon the application.
The analog inputs of the AD9254 are not internally dc-biased.
In ac-coupled applications, the user must provide this bias
externally. Setting the device such that VCM = 0.55 × AVDD is
recommended for optimum performance; however, the device
functions over a wider range with reasonable performance (see
Figure 30). An on-board common-mode voltage reference is
included in the design and is available from the CML pin.
Optimum performance is achieved when the common-mode
voltage of the analog input is set by the CML pin voltage
(typically 0.55 × AVDD). The CML pin must be decoupled to
ground by a 0.1 μF capacitor, as described in the Layout
Considerations section.
In IF undersampling applications, any shunt capacitors should
be reduced. In combination with the driving source impedance,
these capacitors would limit the input bandwidth. For more
information, see Application Note AN-742, Frequency Domain
Response of Switched-Capacitor ADCs; Application Note AN-827,
A Resonant Approach to Interfacing Amplifiers to SwitchedCapacitor ADCs; and the Analog Dialogue article, “TransformerCoupled Front-End for Wideband A/D Converters.”
Rev. A | Page 14 of 40
AD9254
DIFFERENTIAL INPUT CONFIGURATIONS
Optimum performance is achieved by driving the AD9254 in a
differential input configuration. For baseband applications, the
AD8138 differential driver provides excellent performance and a
flexible interface to the ADC. The output common-mode voltage
of the AD8138 is easily set with the CML pin of the AD9254 (see
Figure 32), and the driver can be configured in a Sallen-Key filter
topology to provide band limiting of the input signal.
Table 8. RC Network Recommended Values
499Ω
R
VIN+
499Ω
523Ω
R
AVDD
AD9254
C
AD8138
0.1µF
CML
VIN–
499Ω
VIN+
R
10µF
AD9254
VIN–
R
CML
0.1µF
AVDD
1kΩ
1V p-p
06216-037
C
C Differential (pF)
15
5
5
Open
In this configuration, SFDR and distortion performance
degrade due to the large input common-mode swing. If the
source impedances on each input are matched, there should be
little effect on SNR performance. Figure 34 details a typical
single-ended input configuration.
The signal characteristics must be considered when selecting
a transformer. Most RF transformers saturate at frequencies
below a few megahertz, and excessive signal power can cause
core saturation, which leads to distortion.
49.9Ω
R Series (Ω)
33
33
15
15
Although not recommended, it is possible to operate the
AD9254 in a single-ended input configuration, as long as the
input voltage swing is within the AVDD supply. Single-ended
operation can provide adequate performance in cost-sensitive
applications.
For baseband applications where SNR is a key parameter,
differential transformer coupling is the recommended input
configuration (see Figure 33). The CML voltage can be
connected to the center tap of the secondary winding of the
transformer to bias the analog input.
R
Frequency Range (MHz)
0 to 70
70 to 200
200 to 300
>300
Single-Ended Input Configuration
Figure 32. Differential Input Configuration Using the AD8138
2V p-p
In any configuration, the value of the shunt capacitor, C,
is dependent on the input frequency and source impedance and
may need to be reduced or removed. Table 8 displays recommended values to set the RC network. However, these values
are dependent on the input signal and should only be used as a
starting guide.
49.9Ω
0.1µF
AVDD
1kΩ
10µF
0.1µF
VIN+
1kΩ
C
R
AD9254
VIN–
1kΩ
Figure 33. Differential Transformer-Coupled Configuration
At input frequencies in the second Nyquist zone and above, the
noise performance of most amplifiers is not adequate to achieve
the true SNR performance of the AD9254. For applications
where SNR is a key parameter, transformer coupling is the
recommended input. For applications where SFDR is a key
parameter, differential double balun coupling is the recommended input configuration (see Figure 35).
Rev. A | Page 15 of 40
Figure 34. Single-Ended Input Configuration
06216-038
49.9Ω
06216-036
1V p-p
As an alternative to using a transformer-coupled input at
frequencies in the second Nyquist zone, the AD8352
differential driver can be used (see Figure 36).
AD9254
0.1µF
0.1µF
R
VIN+
2V p-p
25Ω
S
S
P
0.1µF
25Ω
AD9254
C
0.1µF
R
06216-039
PA
CML
VIN–
Figure 35. Differential Double Balun Input Configuration
VCC
0.1µF
0Ω
16
8, 13
1
0.1µF
11
R
2
VIN+
200Ω
CD
RD
AD8352
RG
3
0.1µF
10
200Ω
4
5
0.1µF
0Ω
AD9254
C
R
VIN–
CML
14
0.1µF
0.1µF
06216-040
0.1µF
Figure 36. Differential Input Configuration Using the AD8352
Table 9. Reference Configuration Summary
Selected Mode
External Reference
Internal Fixed Reference
Programmable Reference
SENSE Voltage
AVDD
VREF
0.2 V to VREF
Resulting VREF (V)
N/A
0.5
Internal Fixed Reference
AGND to 0.2 V
1.0
R2
0.5 1
(see Figure 38)
R1
VOLTAGE REFERENCE
A stable and accurate voltage reference is built into the
AD9254. The input range is adjustable by varying the reference
voltage applied to the AD9254, using either the internal
reference or an externally applied reference voltage. The input
span of the ADC tracks reference voltage changes linearly. The
various reference modes are summarized in the following
sections. The Reference Decoupling section describes the best
practices and requirements for PCB layout of the reference.
Internal Reference Connection
A comparator within the AD9254 detects the potential at the
SENSE pin and configures the reference into four possible
states, as summarized in Table 9. If SENSE is grounded, the
reference amplifier switch is connected to the internal resistor
divider (see Figure 37), setting VREF to 1 V.
Resulting Differential
Span (V p-p)
2 × external reference
1.0
2 × VREF
2.0
Connecting the SENSE pin to VREF switches the reference
amplifier input to the SENSE pin, completing the loop and
providing a 0.5 V reference output. If a resistor divider is
connected external to the chip, as shown in Figure 38, the
switch sets to the SENSE pin. This puts the reference amplifier
in a noninverting mode with the VREF output defined as
R2
VREF 0.5 1
R1
If the SENSE pin is connected to AVDD, the reference
amplifier is disabled, and an external reference voltage can be
applied to the VREF pin (see the External Reference Operation
section).
The input range of the ADC always equals twice the voltage at
the reference pin for either an internal or an external reference.
Rev. A | Page 16 of 40
AD9254
External Reference Operation
–
The use of an external reference may be necessary to enhance
the gain accuracy of the ADC or improve thermal drift
characteristics. Figure 40 shows the typical drift characteristics
of the internal reference in both 1 V and 0.5 V modes.
REFT
0.1µF
REFB
0.1µF
0.1µF
10
REFERENCE VOLTAGE ERROR (mV)
VREF
SELECT
LOGIC
SENSE
06216-041
0.5V
AD9254
ADC
CORE
VIN–
4
2
0
–40
–
VIN+
VREF = 0.5V
6
–
Figure 37. Internal Reference Configuration
VREF = 1V
8
REFT
–20
0
20
40
TEMPERATURE (°C)
0.1µF
When the SENSE pin is tied to AVDD, the internal reference is
disabled, allowing the use of an external reference. An internal
resistor divider loads the external reference with an equivalent
6 kΩ load (see Figure 11). In addition, an internal buffer
generates the positive and negative full-scale references for the
ADC core. Therefore, the external reference must be limited to
a maximum of 1 V.
REFB
R2
SENSE
SELECT
LOGIC
0.5V
R1
06216-042
0.1µF
AD9254
CLOCK INPUT CONSIDERATIONS
Figure 38. Programmable Reference Configuration
If the internal reference of the AD9254 is used to drive multiple
converters to improve gain matching, the loading of the reference
by the other converters must be considered. Figure 39 depicts
how the internal reference voltage is affected by loading.
The AD9254 has a very flexible clock input structure. The clock
input can be a CMOS, LVDS, LVPECL, or sine wave signal.
Regardless of the type of signal used, the jitter of the clock
source is of the most concern, as described in the Jitter
Considerations section.
VREF = 0.5V
–0.25
VREF = 1V
–0.50
–0.75
–1.00
0
0.5
1.0
1.5
LOAD CURRENT (mA)
Figure 39. VREF Accuracy vs. Load
2.0
06216-043
REFERENCE VOLTAGE ERROR (%)
For optimum performance, the AD9254 sample clock inputs
(CLK+ and CLK−) should be clocked with a differential signal.
The signal is typically ac-coupled into the CLK+ pin and the
CLK− pin via a transformer or capacitors. These pins are biased
internally (see Figure 5) and require no external bias.
Clock Input Options
0
–1.25
80
Figure 40. Typical VREF Drift
0.1µF
VREF
60
06216-044
ADC
CORE
VIN–
–
VIN+
Figure 41 shows one preferred method for clocking the
AD9254. A low jitter clock source is converted from singleended to a differential signal using an RF transformer. The
back-to-back Schottky diodes across the transformer secondary
limit clock excursions into the AD9254 to approximately 0.8 V p-p
differential. This helps prevent the large voltage swings of the
clock from feeding through to other portions of the AD9254,
while preserving the fast rise and fall times of the signal, which
are critical to a low jitter performance.
Rev. A | Page 17 of 40
AD9254
CLOCK
INPUT
CLK+
ADC
AD9254
100Ω
0.1µF
1kΩ
OPTIONAL
0.1µF
100Ω
AD951x
CMOS DRIVER
ADC
AD9254
CLK–
CLK–
06216-045
SCHOTTKY
DIODES:
HMS2812
0.1µF
CLK+
1kΩ
50Ω1
0.1µF
150Ω
Figure 41. Transformer Coupled Differential Clock
39kΩ
06216-048
50Ω
0.1µF
RESISTOR IS OPTIONAL.
Figure 44. Single-Ended 1.8 V CMOS Sample Clock
If a low jitter clock source is not available, another option is to
ac-couple a differential PECL signal to the sample clock input
pins as shown in Figure 42. The AD9510/AD9511/AD9512/
AD9513/AD9514/AD9515 family of clock drivers offers
excellent jitter performance.
VCC
CLOCK
INPUT
0.1µF
50Ω1
1kΩ
AD951x
CMOS DRIVER
OPTIONAL 0.1µF
100Ω
1kΩ
0.1µF
CLK+
ADC
AD9254
CLK–
0.1µF
CLOCK
INPUT
CLK+
100Ω
AD951x
0.1µF PECL DRIVER
0.1µF
CLK
50Ω1
240Ω
50Ω1
Figure 45. Single-Ended 3.3 V CMOS Sample Clock
ADC
AD9254
Clock Duty Cycle
CLK–
240Ω
06216-046
CLOCK
INPUT
150Ω RESISTOR IS OPTIONAL.
0.1µF
CLK
150Ω RESISTORS ARE OPTIONAL.
Figure 42. Differential PECL Sample Clock
A third option is to ac-couple a differential LVDS signal to the
sample clock input pins, as shown in Figure 43. The AD9510/
AD9511/AD9512/AD9513/AD9514/AD9515 family of clock
drivers offers excellent jitter performance.
0.1µF
CLOCK
INPUT
AD951x
0.1µF LVDS DRIVER
0.1µF
CLK
50Ω1
150Ω
ADC
AD9254
CLK–
50Ω1
RESISTORS ARE OPTIONAL.
06216-047
CLOCK
INPUT
CLK+
100Ω
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to clock duty cycle. Commonly, a ±5% tolerance is
required on the clock duty cycle to maintain dynamic
performance characteristics.
The AD9254 contains a duty cycle stabilizer (DCS) that retimes
the nonsampling, or falling edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows a wide range
of clock input duty cycles without affecting the performance of
the AD9254. Noise and distortion performance are nearly flat
for a wide range of duty cycles when the DCS is on, as shown in
Figure 28.
0.1µF
CLK
06216-049
0.1µF
CLOCK
INPUT
VCC
MINI-CIRCUITS
ADT1–1WT, 1:1Z
0.1µF
XFMR
Figure 43. Differential LVDS Sample Clock
In some applications, it is acceptable to drive the sample clock
inputs with a single-ended CMOS signal. In such applications,
directly drive CLK+ from a CMOS gate, while bypassing the
CLK− pin to ground using a 0.1 μF capacitor in parallel with a
39 kΩ resistor (see Figure 44). CLK+ can be directly driven
from a CMOS gate. This input is designed to withstand input
voltages up to 3.6 V, making the selection of the drive logic
voltage very flexible. When driving CLK+ with a 1.8 V CMOS
signal, biasing the CLK− pin with a 0.1 μF capacitor in parallel
with a 39 kΩ resistor (see Figure 44) is required. The 39 kΩ
resistor is not required when driving CLK+ with a 3.3 V CMOS
signal (see Figure 45).
Jitter in the rising edge of the input is still of paramount concern
and is not reduced by the internal stabilization circuit. The duty
cycle control loop does not function for clock rates less than
20 MHz nominally. The loop has a time constant associated
with it that needs to be considered in applications where the
clock rate can change dynamically. This requires a wait time
of 1.5 μs to 5 μs after a dynamic clock frequency increase (or
decrease) before the DCS loop is relocked to the input signal.
During the time period the loop is not locked, the DCS loop is
bypassed, and the internal device timing is dependent on the
duty cycle of the input clock signal. In such an application, it
may be appropriate to disable the duty cycle stabilizer. In all
other applications, enabling the DCS circuit is recommended
to maximize ac performance.
Rev. A | Page 18 of 40
AD9254
The DCS can be enabled or disabled by setting the SDIO/DCS
pin when operating in the external pin mode (see Table 10), or
via the SPI, as described in Table 13.
Table 10. Mode Selection (External Pin Mode)
SCLK/DFS
Binary (default)
Twos complement
SDIO/DCS
DCS disabled
DCS enabled
(default)
JITTER CONSIDERATIONS
The power dissipated by the AD9254 is proportional to its sample
rate (see Figure 47). The digital power dissipation is determined
primarily by the strength of the digital drivers and the load on each
output bit. Maximum DRVDD current (IDRVDD) can be calculated
as
I DRVDD VDRVDD CLOAD
where N is the number of output bits, 14 in the AD9254.
High speed, high resolution ADCs are sensitive to the quality of
the clock input. The degradation in SNR at a given input
frequency (fIN) due to jitter (tJ) is calculated as follows:
SNR = −20 log (2π × fIN × tJ)
In the equation, the rms aperture jitter represents the root
mean square of all jitter sources, which include the clock input,
analog input signal, and ADC aperture jitter specification. IF
under-sampling applications are particularly sensitive to jitter,
as shown in Figure 46.
This maximum current occurs when every output bit switches
on every clock cycle, that is, a full-scale square wave at the
Nyquist frequency, fCLK/2. In practice, the DRVDD current is
established by the average number of output bits switching,
which is determined by the sample rate and the characteristics
of the analog input signal. Reducing the capacitive load
presented to the output drivers can minimize digital power
consumption. The data in Figure 47 was taken under the same
operating conditions as the data for the Typical Performance
Characteristics section, with a 5 pF load on each output driver.
75
500
0.05ps
I (AVDD)
0.20ps
POWER (mW)
440
60
0.5ps
55
1.0ps
50
45
10
400
340
2.50ps
3.00ps
320
100
POWER
1000
Figure 46. SNR vs. Input Frequency and Jitter
150
380
2.00ps
INPUT FREQUENCY (MHz)
200
420
100
360
1.50ps
1
250
460
06216-050
SNR (dBc)
480
MEASURED
PERFORMANCE
65
300
300
CURRENT (mA)
70
40
fCLK
N
2
50
I (DRVDD)
0
0
10 20 30 40 50 60 70 80 90 100 110 120 130 140 150
CLOCK FREQUENCY (MHz)
06216-051
Voltage at Pin
AGND
AVDD
POWER DISSIPATION AND STANDBY MODE
Figure 47. AD9254 Power and Current vs. Clock Frequency fIN = 30 MHz
Treat the clock input as an analog signal in cases where
aperture jitter can affect the dynamic range of the AD9254. Power
supplies for clock drivers should be separated from the ADC
output driver supplies to avoid modulating the clock signal
with digital noise. The power supplies should also not be shared
with analog input circuits, such as buffers, to avoid the clock
modulating onto the input signal or vice versa. Low jitter, crystalcontrolled oscillators make the best clock sources. If the clock is
generated from another type of source (by gating, dividing, or
other methods), it should be retimed by the original clock at the
last step.
Refer to Application Notes AN-501, Aperture Uncertainty and
ADC System Performance; and AN-756, Sampled Systems and
the Effects of Clock Phase Noise and Jitter, for more in-depth
information about jitter performance as it relates to ADCs.
Power-Down Mode
By asserting the PDWN pin high, the AD9254 is placed in powerdown mode. In this state, the ADC typically dissipates 1.8 mW.
During power-down, the output drivers are placed in a high
impedance state. Reasserting the PDWN pin low returns the
AD9254 to its normal operational mode. This pin is both 1.8 V
and 3.3 V tolerant.
Low power dissipation in power-down mode is achieved by
shutting down the reference, reference buffer, biasing networks,
and clock. The decoupling capacitors on REFT and REFB are
discharged when entering power-down mode and then must be
recharged when returning to normal operation. As a result, the
wake-up time is related to the time spent in power-down mode;
and shorter power-down cycles result in proportionally shorter
wake-up times. With the recommended 0.1 μF decoupling capacitors on REFT and REFB, it takes approximately 0.25 ms to fully
Rev. A | Page 19 of 40
AD9254
discharge the reference buffer decoupling capacitors and 0.35 ms
to restore full operation.
analog input returns to within the input range and another
conversion is completed.
Standby Mode
By logically AND’ing the OR bit with the MSB and its
complement, overrange high or underrange low conditions can be
detected. Table 11 is a truth table for the overrange/underrange
circuit in Figure 49, which uses NAND gates.
When using the SPI port interface, the user can place the ADC
in power-down or standby modes. Standby mode allows the
user to keep the internal reference circuitry powered when
faster wake-up times are required (see the Memory Map section).
MSB
The AD9254 output drivers can be configured to interface with
1.8 V to 3.3 V logic families by matching DRVDD to the digital
supply of the interfaced logic. The output drivers are sized to
provide sufficient output current to drive a wide variety of logic
families. However, large drive currents tend to cause current
glitches on the supplies that may affect converter performance.
Applications requiring the ADC to drive large capacitive loads
or large fan-outs may require external buffers or latches.
The output data format can be selected for either offset binary
or twos complement by setting the SCLK/DFS pin when
operating in the external pin mode (see Table 10). As detailed
in the Interfacing to High Speed ADCs via SPI user manual, the
data format can be selected for either offset binary, twos
complement, or Gray code when using the SPI control.
Out-of-Range (OR) Condition
An out-of-range condition exists when the analog input voltage
is beyond the input range of the ADC. OR is a digital output
that is updated along with the data output corresponding to the
particular sampled input voltage. Thus, OR has the same
pipeline latency as the digital data.
+FS – 1 LSB
OR
+FS
+FS – 1/2 LSB
06216-052
00 0000 0000 0001
00 0000 0000 0000
00 0000 0000 0000
–FS
–FS – 1/2 LSB
Figure 49. Overrange/Underrange Logic
Table 11. Overrange/Underrange Truth Table
OR
0
0
1
1
MSB
0
1
0
1
Analog Input Is:
Within range
Within range
Underrange
Overrange
Digital Output Enable Function (OEB)
The AD9254 has three-state ability. If the OEB pin is low, the
output data drivers are enabled. If the OEB pin is high, the
output data drivers are placed in a high impedance state. This is
not intended for rapid access to the data bus. Note that OEB is
referenced to the digital supplies (DRVDD) and should not
exceed that supply voltage.
TIMING
The lowest typical conversion rate of the AD9254 is 10 MSPS.
At clock rates below 10 MSPS, dynamic performance can degrade.
The AD9254 provides latched data outputs with a pipeline
delay of twelve clock cycles. Data outputs are available one
propagation delay (tPD) after the rising edge of the clock signal.
The length of the output data lines and the loads placed on
them should be minimized to reduce transients within the
AD9254. These transients can degrade the dynamic performance
of the converter.
–FS + 1/2 LSB
0
0
1
UNDER = 1
MSB
06216-053
DIGITAL OUTPUTS
OR DATA OUTPUTS
1 11 1111 1111 1111
0 11 1111 1111 1111
0 11 1111 1111 1110
OVER = 1
OR
Data Clock Output (DCO)
Figure 48. OR Relation to Input Voltage and Output Data
OR is low when the analog input voltage is within the analog
input range and high when the analog input voltage exceeds the
input range, as shown in Figure 48. OR remains high until the
The AD9254 also provides data clock output (DCO) intended for
capturing the data in an external register. The data outputs are
valid on the rising edge of DCO, unless the DCO clock polarity has
been changed via the SPI. See Figure 2 for a graphical timing
description.
Table 12. Output Data Format
Input (V)
VIN+ – VIN–
VIN+ – VIN–
VIN+ – VIN–
VIN+ – VIN–
VIN+ – VIN–
Condition (V)
< –VREF – 0.5 LSB
= –VREF
=0
= +VREF – 1.0 LSB
> +VREF – 0.5 LSB
Binary Output Mode
00 0000 0000 0000
00 0000 0000 0000
10 0000 0000 0000
11 1111 1111 1111
11 1111 1111 1111
Twos Complement Mode
10 0000 0000 0000
10 0000 0000 0000
00 0000 0000 0000
01 1111 1111 1111
01 1111 1111 1111
Rev. A | Page 20 of 40
Gray Code Mode
(SPI Accessible)
11 0000 0000 0000
11 0000 0000 0000
00 0000 0000 0000
10 0000 0000 0000
10 0000 0000 0000
OR
1
0
0
0
1
AD9254
SERIAL PORT INTERFACE (SPI)
The AD9254 serial port interface (SPI) allows the user to
configure the converter for specific functions or operations
through a structured register space provided inside the ADC.
This provides the user added flexibility and customization
depending on the application. Addresses are accessed via the
serial port and may be written to or read from via the port.
Memory is organized into bytes that are further divided into
fields, as documented in the Memory Map section. For detailed
operational information, see the Interfacing to High Speed
ADCs via SPI user manual.
CONFIGURATION USING THE SPI
As summarized in Table 13, three pins define the SPI of this
ADC. The SCLK/DFS pin synchronizes the read and write data
presented to the ADC. The SDIO/DCS dual-purpose pin allows
data to be sent to and read from the internal ADC memory
map registers. The CSB pin is an active low control that enables
or disables the read and write cycles.
Table 13. Serial Port Interface Pins
Pin Name
SCLK/DFS
SDIO/DCS
CSB
Function
SCLK (serial clock) is the serial shift clock in. SCLK
synchronizes serial interface reads and writes.
SDIO (serial data input/output) is a dual-purpose
pin. The typical role for this pin is an input and
output, depending on the instruction being sent
and the relative position in the timing frame.
CSB (chip select bar) is an active-low control that
gates the read and write cycles.
The falling edge of the CSB in conjunction with the rising edge
of the SCLK determines the start of the framing. Figure 50 and
Table 14 provide examples of the serial timing and its definitions.
Other modes involving the CSB are available. The CSB can be
held low indefinitely to permanently enable the device (this is
called streaming). The CSB can stall high between bytes to
allow for additional external timing. When CSB is tied high,
SPI functions are placed in a high impedance mode. This mode
turns on any SPI pin secondary functions.
During an instruction phase, a 16-bit instruction is transmitted.
Data follows the instruction phase and the length is determined
by the W0 bit and the W1 bit. All data is composed of 8-bit
words. The first bit of each individual byte of serial data
indicates whether a read or write command is issued. This
allows the serial data input/output (SDIO) pin to change
direction from an input to an output.
In addition to word length, the instruction phase determines if
the serial frame is a read or write operation, allowing the serial
port to be used to both program the chip as well as read the
contents of the on-chip memory. If the instruction is a
readback operation, performing a readback causes the serial
data input/output (SDIO) pin to change direction from an
input to an output at the appropriate point in the serial frame.
Data can be sent in MSB- or in LSB-first mode. MSB first is the
default on power-up and can be changed via the configuration
register. For more information, see the Interfacing to High
Speed ADCs via SPI user manual.
Table 14. SPI Timing Diagram Specifications
Name
tDS
tDH
tCLK
tS
tH
tHI
tLO
Description
Setup time between data and rising edge of SCLK
Hold time between data and rising edge of SCLK
Period of the clock
Setup time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK should be in a logic
high state
Minimum period that SCLK should be in a logic
low state
HARDWARE INTERFACE
The pins described in Table 13 comprise the physical interface
between the user’s programming device and the serial port of
the AD9254. The SCLK and CSB pins function as inputs when
using the SPI interface. The SDIO pin is bidirectional, functioning
as an input during write phases and as an output during readback.
The SPI interface is flexible enough to be controlled by either
PROM or PIC microcontrollers. This provides the user with the
ability to use an alternate method to program the ADC. One
method is described in detail in Application Note AN-812,
Microcontroller-Based Serial Port Interface Boot Circuit.
When the SPI interface is not used, some pins serve a dual
function. When strapped to AVDD or ground during device
power on, the pins are associated with a specific function.
CONFIGURATION WITHOUT THE SPI
In applications that do not interface to the SPI control registers,
the SDIO/DCS and SCLK/DFS pins serve as stand-alone
CMOS-compatible control pins. When the device is powered
up, it is assumed that the user intends to use the pins as static
control lines for the output data format and duty cycle
stabilizer (see Table 10). In this mode, the CSB chip select
should be connected to AVDD, which disables the serial port
interface. For more information, see the Interfacing to High
Speed ADCs via SPI user manual.
Rev. A | Page 21 of 40
AD9254
Default Values
MEMORY MAP
Coming out of reset, critical registers are loaded with default
values. The default values for the registers are shown in
Table 15.
READING THE MEMORY MAP REGISTER TABLE
Each row in the memory map register table has eight address
locations. The memory map is roughly divided into three
sections: the chip configuration registers map (Address 0x00 to
Address 0x02), the device index and transfer registers map
(Address 0xFF), and the ADC functions map (Address 0x08 to
Address 0x18).
Logic Levels
An explanation of two registers follows:
“Bit is set” is synonymous with “Bit is set to Logic 1” or
“Writing Logic 1 for the bit.”
Table 15 displays the register address number in hexadecimal
in the first column. The last column displays the default value
for each hexadecimal address. The Bit 7 (MSB) column is the
start of the default hexadecimal value given. For example,
Hexadecimal Address 0x14, output_phase, has a hexadecimal
default value of 0x00. This means Bit 3 = 0, Bit 2 = 0, Bit 1 = 1,
and Bit 0 = 1 or 0011 in binary. This setting is the default
output clock or DCO phase adjust option. The default value
adjusts the DCO phase 90° relative to the nominal DCO edge
and 180° relative to the data edge. For more information on this
function, consult the Interfacing to High Speed ADCs via SPI user
manual.
“Clear a bit” is synonymous with “Bit is set to Logic 0” or
“Writing Logic 0 for the bit.”
SPI-Accessible Features
A list of features accessible via the SPI and a brief description of
what the user can do with these features follows. These features
are described in detail in the Interfacing to High Speed ADCs via
SPI user manual.
Modes: Set either power-down or standby mode.
Clock: Access the DCS via the SPI.
Open Locations
Offset: Digitally adjust the converter offset.
Locations marked as open are currently not supported for this
device. When required, these locations should be written with
0s. Writing to these locations is required only when part of an
address location is open (for example, Address 0x14). If the
entire address location is open (Address 0x13), then the address
location does not need to be written.
Test I/O: Set test modes to have known data on output
bits.
Output Mode: Setup outputs, vary the strength of the
output drivers.
Output Phase: Set the output clock polarity.
VREF: Set the reference voltage.
tDS
tS
tHI
tCLK
tDH
tH
tLO
CSB
SCLK DON’T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
D4
D3
D2
D1
D0
DON’T CARE
06216-054
SDIO DON’T CARE
DON’T CARE
Figure 50. Serial Port Interface Timing Diagram
Rev. A | Page 22 of 40
AD9254
MEMORY MAP REGISTER TABLE
Table 15. Memory Map Register
Addr.
Bit 7
(Hex) Parameter Name (MSB)
Chip Configuration Registers
00
chip_port_config 0
01
chip_id
02
chip_grade
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
LSB first
0 = Off
(Default)
1 = On
Soft
reset
0 = Off
(Default)
1 = On
1
1
Soft
reset
0 = Off
(Default)
1 = On
LSB first
0 = Off
(Default)
1 = On
Bit 0
(LSB)
Default
Value
(Hex)
0
0x18
8-bit Chip ID Bits 7:0
(AD9254 = 0x00), (default)
Open
Open
Open
Open
Read
only
The nibbles
should be
mirrored. See
the Interfacing to
High Speed ADCs
via SPI user
manual.
Default is unique
chip ID, different
for each device.
Child ID used to
differentiate
speed grades.
Child ID
0 = 150
MSPS
Open
Open
Open
Read
only
Open
SW
transfer
0x00
Synchronously
transfers data
from the master
shift register to
the slave.
Determines
various generic
modes of chip
operation. See
the Power
Device Index and Transfer Registers
FF
device_update
Open
Open
Open
Open
Open
Open
Global ADC Functions
08
modes
Open
PDWN
0—Full
1—
Standby
Open
Open
Internal power-down mode
000—normal (power-up)
001—full power-down
010—standby
011—normal (power-up)
Note: External PDWN pin
overrides this setting.
0x00
Open
0x01
Open
Default Notes/
Comments
Dissipation and
Standby Mode
and the SPIAccessible
Features
sections.
09
clock
Open
Open
Open
Open
Open
Rev. 0 | Page 23 of 40
Open
Duty
cycle
stabilizer
0—
disabled
1—
enabled
See the Clock
Duty Cycle
section and the
SPI-Accessible
Features section.
AD9254
Addr.
Bit 7
(Hex)
Parameter Name (MSB)
Flexible ADC Functions
10
offset
Bit 6
Bit 5
test_io
14
output_mode
Output Driver
Configuration
00 for DRVDD = 2.5 V to
3.3 V
10 for DRVDD = 1.8 V
Open
16
output_phase
Open
Output Clock
Polarity
1 = inverted
0 = normal
(Default)
Internal Reference
Resistor Divider
00—VREF = 1.25 V
01—VREF = 1.5 V
10—VREF = 1.75 V
11—VREF = 2.00 V
(Default)
Open
1
VREF
Bit 3
Output
Disable
1—
disabled
0—
enabled1
Open
Bit 2
Bit 1
Offset in LSBs
+31
+30
+29
Digital Offset Adjust
011111
011110
011101
…
000010
000001
000000
111111
111110
111101
...
100001
100000
PN9
PN23
0 = normal 0 = normal
(Default)
(Default)
1 = reset
1 = reset
0D
18
Bit 4
Bit 0
(LSB)
Default
Value
(Hex)
Default
Notes/
Comments
0x00
Adjustable for
offset inherent
in the
converter. See
SPIAccessible
Features
+2
+1
0 (Default)
1
−2
−3
Open
Open
section.
−31
−32
Global Output Test Options
000—off
001—midscale short
010—+FS short
011—−FS short
100—checker board output
101—PN 23 sequence
110—PN 9
111—one/zero word toggle
Output
Data Format Select
Data
00—offset binary
Invert
(default)
1=
01—twos
invert
complement
10—Gray Code
Open
Open
Open
0x00
See the
Interfacing to
High Speed
ADCs via SPI
user manual.
0x00
Configures the
outputs and
the format of
the data.
0x00
See the SPIAccessible
Features
section.
Open
Open
Open
Open
Open
Open
0xC0
See the SPIAccessible
Features
section.
External output enable (OEB) pin must be high.
Rev. A | Page 24 of 40
AD9254
LAYOUT CONSIDERATIONS
SILKSCREEN PARTITION
PIN 1 INDICATOR
When connecting power to the AD9254, it is recommended
that two separate supplies be used: one for analog (AVDD, 1.8
V nominal) and one for digital (DRVDD, 1.8 V to 3.3 V
nominal). If only a single 1.8 V supply is available, it is routed
to AVDD first, then tapped off and isolated with a ferrite bead
or filter choke with decoupling capacitors proceeding
connection to DRVDD. The user can employ several different
decoupling capacitors to cover both high and low frequencies.
These should be located close to the point of entry at the PC
board level and close to the parts with minimal trace length.
A single PC board ground plane is sufficient when using the
AD9254. With proper decoupling and smart partitioning of
analog, digital, and clock sections of the PC board, optimum
performance is easily achieved.
Exposed Paddle Thermal Heat Slug Recommendations
It is required that the exposed paddle on the underside of the
ADC be connected to analog ground (AGND) to achieve the
best electrical and thermal performance of the AD9254. An
exposed, continuous copper plane on the PCB should mate to
the AD9254 exposed paddle, Pin 0. The copper plane should
have several vias to achieve the lowest possible resistive thermal
path for heat dissipation to flow through the bottom of the
PCB. These vias should be solder-filled or plugged.
To maximize the coverage and adhesion between the ADC and
PCB, partition the continuous plane by overlaying a silkscreen
on the PCB into several uniform sections. This provides several
tie points between the two during the reflow process. Using one
continuous plane with no partitions guarantees only one tie point
between the ADC and PCB. See Figure 51 for a PCB layout
example. For detailed information on packaging and the PCB
layout of chip scale packages, see Application Note AN-772,
A Design and Manufacturing Guide for the Lead Frame Chip
Scale Package.
06216-055
POWER AND GROUND RECOMMENDATIONS
Figure 51. Typical PCB Layout
CML
The CML pin should be decoupled to ground with a 0.1 μF
capacitor, as shown in Figure 33.
RBIAS
The AD9254 requires the user to place a 10 kΩ resistor between
the RBIAS pin and ground. This resister sets the master current
reference of the ADC core and should have at least a 1% tolerance.
REFERENCE DECOUPLING
The VREF pin should be externally decoupled to ground with a
low ESR 1.0 μF capacitor in parallel with a 0.1 μF ceramic low
ESR capacitor. In all reference configurations, REFT and REFB
are bypass points provided for reducing the noise contributed
by the internal reference buffer. It is recommended that an
external 0.1 μF ceramic capacitor be placed across REFT/REFB.
While placement of this 0.1 μF capacitor is not required, the SNR
performance degrades by approximately 0.1 dB without it. All
reference decoupling capacitors should be placed as close to the
ADC as possible with minimal trace lengths.
Rev. 0 | Page 25 of 40
AD9254
EVALUATION BOARD
The AD9254 evaluation board provides all of the support circuitry
required to operate the ADC in its various modes and configurations. The converter can be driven differentially through a
double balun configuration (default) or through the AD8352
differential driver. The ADC can also be driven in a single-ended
fashion. Separate power pins are provided to isolate the DUT
from the AD8352 drive circuitry. Each input configuration can
be selected by proper connection of various components (see
Figure 53 to Figure 63). Figure 52 shows the typical bench
characterization setup used to evaluate the ac performance of
the AD9254.
When operating the evaluation board in a nondefault
condition, L501, L503, L504, L508, and L509 can be removed to
disconnect the switching power supply. This enables the user to
individually bias each section of the board. Use P501 to connect
a different supply for each section. At least one 1.8 V supply is
needed with a 1 A current capability for AVDD_DUT and
DRVDD_DUT; however, it is recommended that separate
supplies be used for analog and digital. To operate the
evaluation board using the AD8352 option, a separate 5.0 V
supply (AMP_VDD) with a
1 A current capability is needed. To operate the evaluation
board using the alternate SPI options, a separate 3.3 V analog
supply is needed, in addition to the other supplies. The 3.3 V
supply (AVDD_3.3V) should have a 1 A current capability as
well. Solder Jumpers J501, J502, and J505 allow the user to
combine these supplies (see Figure 57 for more details).
It is critical that the signal sources used for the analog input and
clock have very low phase noise (
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