12-Bit, 370 MSPS/500 MSPS,
1.8 V Analog-to-Digital Converter
AD9434
Data Sheet
FEATURES
FUNCTIONAL BLOCK DIAGRAM
VREF
PWDN
AGND
AVDD
AD9434
REFERENCE
CML
VIN+
VIN–
DRVDD
DRGND
TRACK-AND-HOLD
ADC
CORE
CLK+
CLK–
12
OUTPUT 12
STAGING
LVDS
CLOCK
MANAGEMENT
D11± TO D0±
OR+
OR–
SERIAL PORT
DCO+
DCO–
SCLK/DFS
SDIO
CSB
09383-001
SNR = 65 dBFS at fIN up to 250 MHz at 500 MSPS
ENOB of 10.5 bits at fIN up to 250 MHz at 500 MSPS (−1.0 dBFS)
SFDR = 78 dBc at fIN up to 250 MHz at 500 MSPS (−1.0 dBFS)
Integrated input buffer
Excellent linearity
DNL = ±0.5 LSB typical
INL = ±0.6 LSB typical
LVDS at 500 MSPS (ANSI-644 levels)
1 GHz full power analog bandwidth
On-chip reference, no external decoupling required
Low power dissipation
690 mW at 500 MSPS—LVDS SDR mode
660 mW at 500 MSPS—LVDS DDR mode
Programmable (nominal) input voltage range
1.18 V p-p to 1.6 V p-p, 1.5 V p-p nominal
1.8 V analog and digital supply operation
Selectable output data format (offset binary, twos
complement, Gray code)
Clock duty cycle stabilizer
Integrated data clock output with programmable clock and
data alignment
Figure 1.
APPLICATIONS
Wireless and wired broadband communications
Cable reverse path
Communications test equipment
Radar and satellite subsystems
Power amplifier linearization
Fabricated on an advanced BiCMOS process, the AD9434 is
available in a 56-lead LFCSP, specified over the industrial
temperature range (−40°C to +85°C). This part is protected
under a U.S. patent.
GENERAL DESCRIPTION
1.
The AD9434is a 12-bit monolithic sampling analog-to-digital
converter (ADC) optimized for high performance, low power,
and ease of use. The part operates at up to a 500 MSPS
conversion rate and is optimized for outstanding dynamic
performance in wideband carrier and broadband systems. All
necessary functions, including a sample-and-hold and voltage
reference, are included on the chip to provide a complete signal
conversion solution. The VREF pin can be used to monitor the
internal reference or provide an external voltage reference
(external reference mode must be enabled through the SPI
port).
The ADC requires a 1.8 V analog voltage supply and a differential clock for full performance operation. The digital outputs are
LVDS (ANSI-644) compatible and support twos complement,
offset binary format, or Gray code. A data clock output is
available for proper output data timing.
Rev. B
PRODUCT HIGHLIGHTS
2.
3.
4.
5.
High Performance.
Maintains 65 dBFS SNR at 500 MSPS with a 250 MHz input.
Low Power.
Consumes only 660 mW at 500 MSPS.
Ease of Use.
LVDS output data and output clock signal allow interface
to FPGA technology. The on-chip reference and sampleand-hold provide flexibility in system design. Use of a
single 1.8 V supply simplifies system power supply design.
Serial Port Control.
Standard serial port interface supports various product
functions, such as data formatting, power-down, gain
adjust, and output test pattern generation.
The AD9434 is pin compatible with the AD9230, and can
be substituted in many applications with minimal design
changes.
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2011–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
AD9434
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 19
Applications ....................................................................................... 1
Analog Input and Voltage Reference ....................................... 19
General Description ......................................................................... 1
Clock Input Considerations ...................................................... 20
Functional Block Diagram .............................................................. 1
Power Dissipation and Power-Down Mode ........................... 21
Product Highlights ........................................................................... 1
Digital Outputs ........................................................................... 21
Revision History ............................................................................... 2
Timing.......................................................................................... 22
Specifications..................................................................................... 3
VREF ............................................................................................ 22
DC Specifications ......................................................................... 3
AD9434 Configuration Using the SPI ..................................... 22
AC Specifications.......................................................................... 4
Using the AD9434 to Replace the AD9230 ............................ 23
Digital Specifications ................................................................... 5
Hardware Interface ..................................................................... 23
Switching Specifications .............................................................. 6
Configuration Without the SPI ................................................ 23
Timing Diagrams.......................................................................... 7
Memory Map .................................................................................. 25
Absolute Maximum Ratings ............................................................ 8
Reading the Memory Map Table .............................................. 25
Thermal Resistance ...................................................................... 8
Reserved Locations .................................................................... 25
ESD Caution .................................................................................. 8
Default Values ............................................................................. 25
Pin Configurations and Function Descriptions ........................... 9
Logic Levels ................................................................................. 25
Typical Performance Characteristics ........................................... 13
Outline Dimensions ....................................................................... 28
Equivalent Circuits ......................................................................... 18
Ordering Guide .......................................................................... 28
REVISION HISTORY
2/13—Rev. A to Rev. B
Changes to Table 4 ............................................................................. 6
Changes to Table 5 ............................................................................. 8
Changes to Reading the Memory Map Table Section.................25
5/11—Rev. 0 to Rev. A
Changes to General Description ..................................................... 1
Changes to Table 4, Aperture Time Values .................................... 6
Changes to Figure 32 .......................................................................17
Changes to Figure 42 .......................................................................19
Changes to Table 13, Register 10, Bits[7:0] Value, Register 14
Default Value, Register 15 Default Value, Register 17, Bit 7 Value
and Register 18, Bit[4:0] Values .....................................................26
3/11—Revision 0: Initial Version
Rev. B | Page 2 of 28
Data Sheet
AD9434
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted.
Table 1.
Parameter 1
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)
Integral Nonlinearity (INL)
INTERNAL REFERENCE
VREF
TEMPERATURE DRIFT
Offset Error
Gain Error
ANALOG INPUTS (VIN+, VIN−)
Differential Input Voltage Range 2
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance (Differential)
POWER SUPPLY
AVDD
DRVDD
Supply Currents
IAVDD 3
IDRVDD3/SDR Mode 4
IDRVDD3/DDR Mode 5
Power Dissipation
SDR Mode4
DDR Mode5
Standby Mode
Power-Down Mode
Temp
Full
25°C
Full
25°C
Full
25°C
Full
25°C
Full
Full
Min
AD9434-370
Typ
Max
12
Min
Guaranteed
±0.25
−3.0
Guaranteed
±0.25
+1.0
−3.0
+7.0
−5.0
1.0
−5.0
+0.9
−0.92
0.71
Full
Full
0.75
+1.3
0.78
V
+7.0
±0.5
−0.95
±0.4
+1.0
±0.6
+0.92
−1.3
0.78
0.71
18
0.07
0.75
Unit
Bits
mV
mV
% FS
% FS
LSB
LSB
LSB
LSB
+1.0
1.0
±0.4
−0.9
AD9434-500
Typ
Max
12
18
0.07
µV/°C
%/°C
Full
Full
Full
25°C
1.18
1.5
1.7
1
1.3
1.6
1.18
1.5
1.7
1
1.3
1.6
V p-p
V
kΩ
pF
Full
Full
1.75
1.75
1.8
1.8
1.9
1.9
1.75
1.75
1.8
1.8
1.9
1.9
V
V
Full
Full
Full
260
88
70
280
100
80
283
100
82
301
114
96
mA
mA
mA
Full
Full
Full
Full
625
595
40
2.5
685
648
50
7
690
657
40
2.5
747
715
50
7
mW
mW
mW
mW
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
The input range is programmable through the SPI, and the range specified reflects the nominal values of each setting. See the Memory Map section.
IAVDD and IDRVDD are measured with a −1 dBFS, 30.3 MHz sine input at rated sample rate.
4
Single data rate mode; this is the default mode of the AD9434.
5
Double data rate mode; user-programmable feature. See the Memory Map section.
1
2
3
Rev. B | Page 3 of 28
AD9434
Data Sheet
AC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted.
Table 2.
Parameter 1, 2
SNR
fIN = 30.3 MHz
fIN = 70.3 MHz
fIN = 100.3 MHz
fIN = 250.3 MHz
fIN = 450.3 MHz
SINAD
fIN = 30.3 MHz
fIN = 70.3 MHz
fIN = 100.3 MHz
fIN = 250.3 MHz
fIN = 450.3 MHz
EFFECTIVE NUMBER OF BITS (ENOB)
fIN = 30.3 MHz
fIN = 70.3 MHz
fIN = 100.3 MHz
fIN = 250.3 MHz
fIN = 450.3 MHz
WORST HARMONIC (SECOND or THIRD)
fIN = 30.3 MHz
fIN = 70.3 MHz
fIN = 100.3 MHz
fIN = 250.3 MHz
fIN = 450.3 MHz
SFDR
fIN = 30.3 MHz
fIN = 70.3 MHz
fIN = 100.3 MHz
fIN = 250.3 MHz
fIN = 450.3 MHz
WORST OTHER HARMONIC (SFDR EXCLUDING SECOND and THIRD)
fIN = 30.3 MHz
fIN = 70.3 MHz
fIN = 100.3 MHz
fIN = 250.3 MHz
fIN = 450.3 MHz
TWO-TONE IMD
fIN1 = 119.5 MHz, fIN2 = 122.5 MHz
ANALOG INPUT BANDWIDTH
Full Power
1
2
Temp
25°C
25°C
25°C
Full
25°C
25°C
25°C
25°C
25°C
Full
25°C
25°C
Min
AD9434-370
Typ
Max
Min
66.3
66.2
66.1
AD9434-500
Typ
Max
65.9
65.9
65.8
65.3
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
64.5
65.5
64.0
65.2
63.5
66.1
66.1
66.0
65.9
65.8
65.8
Unit
65.3
63.7
64.8
62.9
dBFS
dBFS
dBFS
dBFS
dBFS
dBFS
25°C
25°C
25°C
25°C
25°C
10.7
10.7
10.7
10.6
10.3
10.7
10.6
10.6
10.5
10.2
Bits
Bits
Bits
Bits
Bits
25°C
25°C
25°C
Full
25°C
25°C
−93
−89
−83
−93
−91
−87
−80
−78
−78
−69
dBc
dBc
dBc
dBc
dBc
dBc
25°C
25°C
25°C
Full
25°C
25°C
89
88
83
84
82
83
65.2
64.4
−75
75
−74
dBc
dBc
dBc
dBc
dBc
dBc
74
79
78
78
68
25°C
25°C
25°C
Full
25°C
25°C
−90
−90
−91
−85
−82
−84
−83
−82
−85
−78
dBc
dBc
dBc
dBc
dBc
dBc
25°C
−85
−85
dBc
25°C
1
1
GHz
−75
−74
All ac specifications tested by driving CLK+ and CLK− differentially.
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
Rev. B | Page 4 of 28
Data Sheet
AD9434
DIGITAL SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted.
Table 3.
Parameter 1
CLOCK INPUTS
Logic Compliance
Internal Common-Mode Bias
Differential Input Voltage
High Level Input (VIH)
Low Level Input (VIL)
High Level Input Current (IIH)
Low Level Input Current (IIL)
Input Resistance (Differential)
Input Capacitance
LOGIC INPUTS
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Input Current (SDIO, CSB)
Logic 0 Input Current (SDIO, CSB)
Logic 1 Input Current (SCLK, PDWN)
Logic 0 Input Current (SCLK, PDWN)
Input Capacitance
LOGIC OUTPUTS 2
VOD Differential Output Voltage
VOS Output Offset Voltage
Output Coding
1
2
Temp
Min
Full
Full
AD9434-370
Typ Max
CMOS/LVDS/LVPECL
0.9
Full
Full
Full
Full
Full
Full
0.2
−1.8
−10
−10
8
Full
Full
Full
Full
Full
Full
25°C
0.8 × DRVDD
Full
Full
247
1.125
10
4
1.8
−0.2
+10
+10
12
AD9434-500
Typ Max
Min
CMOS/LVDS/LVPECL
0.9
0.2
−1.8
−10
−10
8
10
4
1.8
−0.2
+10
+10
12
0.8 × DRVDD
0.2 × DRVDD
0
−60
50
0
4
0.2 × DRVDD
0
−60
50
0
4
454
247
454
1.375
1.125
1.375
Twos complement, Gray code, or offset binary (default)
See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and how these tests were completed.
LVDS RTERMINATION = 100 Ω.
Rev. B | Page 5 of 28
Unit
V
V p-p
V p-p
µA
µA
kΩ
pF
V
V
µA
µA
µA
µA
pF
mV
V
AD9434
Data Sheet
SWITCHING SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, TMIN = −40°C, TMAX = +85°C, fIN = −1.0 dBFS, full scale = 1.5 V, unless otherwise noted.
Table 4.
Parameter
Maximum Conversion Rate
Minimum Conversion Rate
CLK+ Pulse Width High (tCH) 1, 2
CLK+ Pulse Width Low (tCL)
Output (LVDS—SDR Mode)1
Data Propagation Delay (tPD)
Rise Time (tR) (20% to 80%)
Fall Time (tF) (20% to 80%)
DCO Propagation Delay (tCPD)
Data to DCO Skew (tSKEW)
Latency
Output (LVDS—DDR Mode)2
Data Propagation Delay (tPD)
Rise Time (tR) (20% to 80%)
Fall Time (tF) (20% to 80%)
DCO Propagation Delay (tCPD)
Data to DCO Skew (tSKEW)
Latency
Aperture Time (tA)
Aperture Uncertainty (Jitter, tJ)
1
2
Temp
Full
Full
Full
Full
Full
25°C
25°C
Full
Full
Full
Full
25°C
25°C
Full
Full
Full
25°C
25°C
Min
370
AD9434-370
Typ
Max
50
11
11
1.1
1.1
Min
500
50
11
11
0.9
0.9
3.55
0.15
0.15
3.3
0.15
AD9434-500
Typ
Max
3.55
0.15
0.15
3.3
0.38
0.15
0.38
15
15
3.3
0.15
0.15
3.3
3.3
0.15
0.15
3.3
−0.07
+0.07
15
0.85
80
See Figure 2.
See Figure 3.
Rev. B | Page 6 of 28
−0.07
+0.07
15
0.85
80
Unit
MSPS
MSPS
ns
ns
ns
ns
ns
ns
ns
Cycles
ns
ns
ns
ns
ns
Cycles
ns
fs rms
Data Sheet
AD9434
Timing Diagrams
N–1
tA
N+4
N+5
N
N+3
VIN+, VIN–
N+1
tCH
tCL
N+2
1/fS
CLK+
CLK–
tCPD
DCO+
DCO–
tSKEW
tPD
Dx+
N – 14
N – 13
N – 12
N – 11
09383-002
N – 15
Dx–
Figure 2. Single Data Rate Mode
N–1
tA
N+4
N+5
N
N+3
VIN+, VIN–
N+1
tCH
tCL
N+2
1/fS
CLK+
CLK–
tCPD
DCO+
DCO–
tSKEW
tPD
D0/D6+
D6
N – 15
D0
N – 14
D6
N – 14
D0
N – 13
D6
N – 13
D0
N – 12
D6
N – 12
D0
N – 11
D6
N – 11
D0
N – 10
D11
N – 15
D5
N – 14
D11
N – 14
D5
N – 13
D11
N – 13
D5
N – 12
D11
N – 12
D5
N – 11
D11
N – 11
D5
N – 10
D5/D11+
D5/D11–
6 MSBs
6 LSBs
Figure 3. Double Data Rate Mode
Rev. B | Page 7 of 28
09383-003
D0/D6–
AD9434
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 5.
Parameter
Electrical
AVDD to AGND
DRVDD to DRGND
AGND to DRGND
AVDD to DRVDD
D0+/D0− Through D11+/D11−
to DRGND
DCO+, DCO− to DRGND
OR+, OR− to DRGND
CLK+ to AGND
CLK− to AGND
VIN+ to AGND
VIN− to AGND
CML to AGND
VREF to AGND
SDIO to DRGND
PDWN to AGND
CSB to AGND
SCLK/DFS to AGND
Environmental
Storage Temperature Range
Operating Temperature Range
Lead Temperature
(Soldering, 10 sec)
Junction Temperature
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rating
−0.3 V to +2.0 V
−0.3 V to +2.0 V
−0.3 V to +0.3 V
−2.0 V to +2.0 V
−0.3 V to DRVDD + 0.2 V
THERMAL RESISTANCE
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.4 V
−0.3 V to AVDD + 0.4 V
−0.3 V to AVDD + 0.2 V
−0.3 V to AVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−0.3 V to DRVDD + 0.2 V
−65°C to +125°C
−40°C to +85°C
300°C
The exposed paddle must be soldered to the ground plane for
the LFCSP package. Soldering the exposed paddle to the PCB
increases the reliability of the solder joints, maximizing the
thermal capability of the package.
Table 6.
Package Type
56-Lead LFCSP_VQ (CP-56-5)
θJA
23.7
θJC
1.7
Unit
°C/W
Typical θJA and θJC are specified for a 4-layer board in still air.
Airflow increases heat dissipation, effectively reducing θJA. In
addition, metal in direct contact with the package leads from
metal traces, through holes, ground, and power planes reduces
the θJA.
ESD CAUTION
150°C
Rev. B | Page 8 of 28
Data Sheet
AD9434
56
55
54
53
52
51
50
49
48
47
46
45
44
43
D2+
D2–
D1+
D1–
D0+
D0–
DCO+
DCO–
DRGND
DRVDD
AVDD
CLK–
CLK+
AVDD
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PIN 1
INDICATOR
AD9434
TOP VIEW
(Not to Scale)
PIN 0 (EXPOSED PADDLE) = AGND
42
41
40
39
38
37
36
35
34
33
32
31
30
29
AVDD
AVDD
CML
AVDD
AVDD
AVDD
VIN–
VIN+
AVDD
AVDD
AVDD
VREF
AVDD
PWDN
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
2. AGND AND DRGND SHOULD BE TIED TO A COMMON
QUIET GROUND PLANE.
3. THE EXPOSED PADDLE MUST BE SOLDERED TO
A GROUND PLANE.
09383-004
D9–
D9+
D10–
D10+
D11–
D11+
OR–
OR+
DRGND
DRVDD
SDIO
SCLK/DFS
CSB
DNC
15
16
17
18
19
20
21
22
23
24
25
26
27
28
D3–
D3+
D4–
D4+
D5–
D5+
DRVDD
DRGND
D6–
D6+
D7–
D7+
D8–
D8+
Figure 4. Pin Configuration—Single Data Rate Mode
Table 7. Pin Function Descriptions—Single Data Rate Mode
Pin No.
0
30, 32 to 34, 37 to 39,
41 to 43, 46
7, 24, 47
8, 23, 48
35
36
40
Mnemonic
AGND 1
AVDD
Description
Analog Ground. The exposed paddle must be soldered to a ground plane.
1.8 V Analog Supply.
DRVDD
DRGND1
VIN+
VIN−
CML
44
45
31
28
25
26
27
29
49
50
51
52
53
54
55
56
1
2
3
CLK+
CLK−
VREF
DNC
SDIO
SCLK/DFS
CSB
PWDN
DCO−
DCO+
D0−
D0+
D1−
D1+
D2−
D2+
D3−
D3+
D4−
1.8 V Digital Output Supply.
Digital Output Ground.
Analog Input—True.
Analog Input—Complement.
Common-Mode Output. Enabled through the SPI, this pin provides a reference for the
optimized internal bias voltage for VIN+/VIN−.
Clock Input—True.
Clock Input—Complement.
Voltage Reference Internal/Input/Output. Nominally 0.75 V.
Do Not Connect. Do not connect to this pin. This pin should be left floating.
Serial Port Interface (SPI) Data Input/Output (Serial Port Mode).
Serial Port Interface Clock (Serial Port Mode)/Data Format Select (External Pin Mode).
Serial Port Chip Select (Active Low).
Chip Power-Down.
Data Clock Output—Complement.
Data Clock Output—True.
D0 Complement Output (LSB).
D0 True Output (LSB).
D1 Complement Output.
D1 True Output.
D2 Complement Output.
D2 True Output.
D3 Complement Output.
D3 True Output.
D4 Complement Output.
Rev. B | Page 9 of 28
AD9434
Pin No.
4
5
6
9
10
11
12
13
14
15
16
17
18
19
20
21
22
1
Data Sheet
Mnemonic
D4+
D5−
D5+
D6−
D6+
D7−
D7+
D8−
D8+
D9−
D9+
D10−
D10+
D11−
D11+
OR−
OR+
Description
D4 True Output.
D5 Complement Output.
D5 True Output.
D6 Complement Output.
D6 True Output.
D7 Complement Output.
D7 True Output.
D8 Complement Output.
D8 True Output.
D9 Complement Output.
D9 True Output.
D10 Complement Output.
D10 True Output.
D11 Complement Output (MSB).
D11 True Output (MSB).
Overrange Complement Output.
Overrange True Output.
AGND and DRGND should be tied to a common quiet ground plane.
Rev. B | Page 10 of 28
AD9434
56
55
54
53
52
51
50
49
48
47
46
45
44
43
D2/D8+
D2/D8–
D1/D7+
D1/D7–
D0/D6+
D0/D6–
DCO+
DCO–
DRGND
DRVDD
AVDD
CLK–
CLK+
AVDD
Data Sheet
1
2
3
4
5
6
7
8
9
10
11
12
13
14
PIN 1
INDICATOR
AD9434
TOP VIEW
(Not to Scale)
PIN 0 (EXPOSED PADDLE) = AGND
42
41
40
39
38
37
36
35
34
33
32
31
30
29
AVDD
AVDD
CML
AVDD
AVDD
AVDD
VIN–
VIN+
AVDD
AVDD
AVDD
VREF
AVDD
PWDN
NOTES
1. DNC = DO NOT CONNECT. DO NOT CONNECT TO THIS PIN.
2. AGND AND DRGND SHOULD BE TIED TO A COMMON
QUIET GROUND PLANE.
3. THE EXPOSED PADDLE MUST BE SOLDERED TO
A GROUND PLANE.
09383-005
DNC
DNC
DNC
DNC
DNC
DNC
DNC/(OR–)
DNC/(OR+)
DRGND
DRVDD
SDIO
SCLK/DFS
CSB
DNC
15
16
17
18
19
20
21
22
23
24
25
26
27
28
D3/D9–
D3/D9+
D4/D10–
D4/D10+
D5/D11–
D5/D11+
DRVDD
DRGND
OR–
OR+
DNC
DNC
DNC
DNC
Figure 5. Pin Configuration—Double Data Rate Mode
Table 8. Pin Function Descriptions—Double Data Rate Mode
Pin No.
0
30, 32 to 34, 37 to 39, 41
to 43, 46
7, 24, 47
8, 23, 48
35
36
40
Mnemonic
AGND 1
AVDD
Description
Analog Ground. The exposed paddle must be soldered to a ground plane.
1.8 V Analog Supply.
DRVDD
DRGND1
VIN+
VIN−
CML
44
45
31
25
26
27
29
49
50
51
52
53
54
55
56
1
2
3
4
5
CLK+
CLK−
VREF
SDIO
SCLK/DFS
CSB
PWDN
DCO−
DCO+
D0/D6−
D0/D6+
D1/D7−
D1/D7+
D2/D8−
D2/D8+
D3/D9−
D3/D9+
D4/D10−
D4/D10+
D5/D11−
1.8 V Digital Output Supply.
Digital Output Ground.
Analog Input—True.
Analog Input—Complement.
Common-Mode Output. Enabled through the SPI, this pin provides a reference for the optimized
internal bias voltage for VIN+/VIN−.
Clock Input—True.
Clock Input—Complement.
Voltage Reference Internal/Input/Output. Nominally 0.75 V.
Serial Port Interface (SPI) Data Input/Output (Serial Port Mode).
Serial Port Interface Clock (Serial Port Mode)/Data Format Select (External Pin Mode).
Serial Port Chip Select (Active Low).
Chip Power-Down.
Data Clock Output—Complement.
Data Clock Output—True.
D0/D6 Complement Output (LSB).
D0/D6 True Output (LSB).
D1/D7 Complement Output.
D1/D7 True Output.
D2/D8 Complement Output.
D2/D8 True Output.
D3/D9 Complement Output.
D3/D9 True Output.
D4/D10 Complement Output.
D4/D10 True Output.
D5/D11 Complement Output (MSB).
Rev. B | Page 11 of 28
AD9434
Data Sheet
Pin No.
6
9
Mnemonic
D5/D11+
OR−
10
11 to 20, 28
21
OR+
DNC
DNC/(OR−)
22
DNC/(OR+)
1
Description
D5/D11 True Output (MSB).
Overrange Complement Output. (This pin is disabled if Pin 21 is reconfigured through the SPI to
be OR−.)
Overrange True Output. (This pin is disabled if Pin 22 is reconfigured through the SPI to be OR+.)
Do Not Connect. Do not connect to these pins. These pins should be left floating.
Do Not Connect. Do not connect to this pin. (This pin can be reconfigured as the overrange
complement output through the serial port register.)
Do Not Connect. Do not connect to this pin. (This pin can be reconfigured as the overrange true
output through the serial port register.)
Tie AGND and DRGND to a common quiet ground plane.
Rev. B | Page 12 of 28
Data Sheet
AD9434
TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 1.8 V, DRVDD = 1.8 V, rated sample rate, TA = 25°C, 1.5 V p-p differential input, AIN = −1 dBFS, unless otherwise noted.
0
0
370MSPS
30.3MHz AT –1.0dBFS
SNR: 65.4dB
ENOB: 10.7 BITS
SFDR: 90dBc
–40
–60
–80
–60
–80
20
40
60
80
100
120
FREQUENCY (MHz)
140
160
180
–120
Figure 6. AD9434-370 64k Point Single-Tone FFT; 370 MSPS, 30.3 MHz
0
20
40
60
80
100 120 140 160 180 200 220 240
FREQUENCY (MHz)
09383-109
0
09383-106
–120
Figure 9. AD9434-500 64k Point Single-Tone FFT; 500 MSPS, 30.3 MHz
0
0
370MSPS
100.3MHz AT –1.0dBFS
SNR: 65.3dB
ENOB: 10.7 BITS
SFDR: 83dBc
500MSPS
100.3MHz AT –1.0dBFS
SNR: 64.9dB
ENOB: 10.6 BITS
SFDR: 84dBc
–20
AMPLITUDE (dBFS)
–20
–40
–60
–80
–60
–80
–100
0
20
40
60
80
120
100
FREQUENCY (MHz)
140
160
180
–120
09383-107
–120
Figure 7. AD9434-370 64k Point Single-Tone FFT; 370 MSPS, 100.3 MHz
0
20
40
60
80
100 120 140 160 180 200 220 240
FREQUENCY (MHz)
09383-110
–100
–40
Figure 10. AD9434-500 64k Point Single-Tone FFT; 500 MSPS, 100.3 MHz
0
0
370MSPS
140.3MHz AT –1.0dBFS
SNR: 65.2dB
ENOB: 10.7 BITS
SFDR: 85dBc
500MSPS
140.3MHz AT –1.0dBFS
SNR: 64.8dB
ENOB: 10.6 BITS
SFDR: 79dBc
–20
AMPLITUDE (dBFS)
–20
–40
–60
–80
–100
–40
–60
–80
–100
0
20
40
60
80
120
100
FREQUENCY (MHz)
140
160
180
–120
09383-108
–120
Figure 8. AD9434-370 64k Point Single-Tone FFT; 370 MSPS, 140.3 MHz
0
20
40
60
80
100 120 140 160 180 200 220 240
FREQUENCY (MHz)
09383-111
AMPLITUDE (dBFS)
–40
–100
–100
AMPLITUDE (dBFS)
500MSPS
30.3MHz AT –1.0dBFS
SNR: 65.0dB
ENOB: 10.7 BITS
SFDR: 85dBc
–20
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
–20
Figure 11. AD9434-500 64k Point Single-Tone FFT; 500 MSPS, 140.3 MHz
Rev. B | Page 13 of 28
AD9434
Data Sheet
0
90
–20
85
SFDR (dBc), TA = +25°C
80
–40
SNR/SFDR (dB)
AMPLITUDE (dBFS)
SFDR (dBc), TA = –40°C
491.52MSPS
368.3MHz AT –1.0dBFS
SNR: 64.0dB
ENOB: 10.5 BITS
SFDR: 79dBc
–60
–80
75
SFDR (dBc), TA = +85°C
70
SNR (dBFS), TA = –40°C
65
SNR (dBFS), TA = +25°C
60
SNR (dBFS), TA = +85°C
–100
0
20
40
60
80
100 120 140 160 180 200 220 240
FREQUENCY (MHz)
50
09383-112
–120
Figure 12. AD9434-500 64k Point Single-Tone; 491.52 MSPS, 368.3 MHz
0
100
150
200
250
300
350
400
450
500
ANALOG INPUT FREQUECY (MHz)
Figure 15. AD9434-500 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and
Temperature; 500 MSPS
0
100
SFDR (dBc), 30.3MHz
491.52MSPS
450.3MHz AT –1.0dBFS
SNR: 63.5dB
ENOB: 10.3 BITS
SFDR: 72dBc
–20
90
–40
SNR/SFDR (dB)
AMPLITUDE (dBFS)
50
09383-115
55
–60
–80
80
SFDR (dBc), 100.3MHz
SNR (dBFS), 30.3MHz
70
60
SNR (dBFS), 100.3MHz
–100
0
20
40
60
80
100 120 140 160 180 200 220 240
FREQUENCY (MHz)
40
50
09383-113
–120
Figure 13. AD9434-500 64k Point Single-Tone; 491.52 MSPS, 450.3 MHz
100
150
200
250
300
350
400
450
500
550
SAMPLE RATE (MSPS)
09383-116
50
Figure 16. AD9434-370 SNR/SFDR vs. Sample Rate; 30.3 MHz, 100.3 MHz
100
100
95
SFDR (dBc), 30.3MHz
SFDR (dBc), TA = –40°C
90
90
SFDR (dBc), TA = +25°C
SNR/SFDR (dB)
SNR/SFDR (dB)
85
80
75
SFDR (dBc), TA = +85°C
SNR (dBFS), TA = –40°C
70
65
80
SFDR (dBc), 100.3MHz
SNR (dBFS), 30.3MHz
70
60
SNR (dBFS), 100.3MHz
SNR (dBFS), TA = +25°C
60
SNR (dBFS), TA = +85°C
50
0
50
100
150
200
250
300
350
400
ANALOG INPUT FREQUECY (MHz)
450
500
40
50
09383-114
50
Figure 14. AD9434-370 Single-Tone SNR/SFDR vs. Input Frequency (fIN) and
Temperature; 370 MSPS
100
150
200
250
300
350
400
SAMPLE RATE (MSPS)
450
500
550
09383-117
55
Figure 17. AD9434-500 SNR/SFDR vs. Sample Rate; 30.3 MHz, 100.3 MHz
Rev. B | Page 14 of 28
Data Sheet
AD9434
0.8
100
90
SFDR (dBFS)
0.6
80
0.4
SNR/SFDR (dB)
70
SNR (dBFS)
0.2
INL (LSB)
60
50
SFDR (dBc)
40
0
–0.2
30
SNR (dB)
–0.4
20
–80
–70
–60
–50
–40
–30
–20
–10
0
AMPLITUDE (dB)
–0.8
–1
09383-118
0
–90
1023
2047
3071
4095
OUTPUT CODE
Figure 18. AD9434-370 SNR/SFDR vs. Input Amplitude; 500 MSPS, 140.3 MHz
09383-121
–0.6
10
Figure 21. AD9434-500 INL; 500 MSPS
100
0.4
90
0.3
SFDR (dBFS)
80
0.2
SNR (dBFS)
60
DNL (LSB)
SNR/SFDR (dB)
70
50
SFDR (dBc)
40
0.1
0
–0.1
30
SNR (dB)
–0.2
20
–70
–60
–50
–40
–30
–20
–10
0
AMPLITUDE (dB)
–0.4
–1
0.4
0.2
0.3
0.1
0.2
DNL (LSB)
0.5
0.3
0
–0.1
0
–0.1
–0.3
–0.2
–0.4
–0.3
3071
OUTPUT CODE
4095
4095
0.1
–0.2
09383-120
INL (LSB)
0.6
0.4
2047
3071
Figure 22. AD9434-370 DNL; 370 MSPS
0.5
1023
2047
OUTPUT CODE
Figure 19. AD9434-500 SNR/SFDR vs. Input Amplitude; 500 MSPS, 140.3 MHz
–0.5
–1
1023
Figure 20. AD9434-370 INL; 370 MSPS
–0.4
–1
1023
2047
3071
OUTPUT CODE
Figure 23. AD9434-500 DNL, 500 MSPS
Rev. B | Page 15 of 28
4095
09383-123
–80
09383-119
0
–90
09383-122
–0.3
10
AD9434
Data Sheet
2.5
0
1.17LSB rms
AMPLITUDE (dB)
NUMBER OF HITS (M)
500MSPS
fIN1 = 119.5MHz AT –7.0dBFS
fIN2 = 122.5MHz AT –7.0dBFS
SFDR: 86dBc
–20
2.0
1.5
1.0
–40
–60
–80
0.5
N–3
N–2
N–1
N
N+1
BINS
N+2
N+3
MORE
–120
09383-124
0
Figure 24. AD9434-370 Grounded Input Histogram; 370 MSPS
0
100
200
150
250
FREQUENCY (MHz)
Figure 27. AD9434-500 64k Point, Two-Tone FFT; 500 MSPS, 119.2 MHz,
122.5 MHz
2.5
120
1.24LSB rms
IMD3 (dBFS)
100
2.0
SFDR (dBFS)
80
1.5
SFDR (dB)
1.0
60
SFDR (dBc)
40
0.5
20
N–3
N–2
N–1
N
N+1
BINS
N+2
N+3
MORE
0
–90
09383-125
0
–80
–70
–60
–50
–40
–30
–20
–10
0
AMPLITUDE (dBFS)
Figure 25. AD9434-500 Grounded Input Histogram; 500 MSPS
09383-128
NUMBER OF HITS (M)
50
09383-127
–100
Figure 28. AD9434-370 Two-Tone SFDR vs. Input Amplitude; 370 MSPS,
119.5 MHz, 122.5 MHz
120
0
IMD3 (dBFS)
370MSPS
fIN1 = 119.5MHz AT –7.0dBFS
fIN2 = 122.5MHz AT –7.0dBFS
SFDR: 82dBc
100
SFDR (dBFS)
80
–60
60
SFDR (dBc)
–80
40
–100
20
–120
0
50
100
150
FREQUENCY (MHz)
Figure 26. AD9434-370 64k Point, Two-Tone FFT; 370 MSPS,
119.5 MHz, 122.5 MHZ
0
–90
–80
–70
–60
–50
–40
–30
AMPLITUDE (dBFS)
–20
–10
0
09383-129
SFDR (dB)
–40
09383-126
AMPLITUDE (dB)
–20
Figure 29. AD9434-500 Two-Tone SFDR vs. Input Amplitude; 500 MSPS,
119.5 MHz, 122.5 MHz
Rev. B | Page 16 of 28
Data Sheet
AD9434
90
80
SFDR (dBc)
85
SFDR (dBc)
75
SNR/SFDR (dB)
SNR/SFDR (dB)
80
75
AD9434, 370MSPS
70
65
SNR (dBFS)
AD9434, 500MSPS
70
AD9434, 370MSPS
65
SNR (dBFS)
60
AD9434, 500MSPS
60
55
1.6
1.8
1.7
1.9
2.0
VCM (V)
50
500
09383-130
50
1.5
700
300
400
300
POWER (mW)
200
500
150
200
100
IDRVDD
100
50
SAMPLE RATE (MSPS)
09383-131
0
50
75
100
125
150
175
200
225
250
275
300
325
350
375
400
425
450
475
500
525
550
CURRENT (mA)
600
250
IAVDD
800
900
1000
Figure 32. SNR/SFDR for AD9434-370 and AD9434-500 at 370 MSPS and
500 MSPS; AIN Sweep at −1.0 dBFS
800
TOTAL POWER
700
ANALOG INPUT FREQUENCY (MHz)
Figure 30. SNR/SFDR vs. Common-Mode Voltage; 370 MSPS, 500 MSPS,
fIN = 140.3 MHz
350
600
09383-132
55
Figure 31. Current and Power vs. Sample Rate, fIN = 30.3 MHz
Rev. B | Page 17 of 28
AD9434
Data Sheet
EQUIVALENT CIRCUITS
AVDD
DRVDD
AVDD
AVDD
0.9V
15kΩ
CLK+
DRVDD
15kΩ
30kΩ
CLK–
DRVDD
350Ω
09383-006
09383-009
CSB
Figure 33. Clock Inputs
Figure 37. Equivalent CSB Input Circuit
VBOOST
AVDD
DRVDD
CML
V+
V–
D11– TO D0–
AVDD
D11+ TO D0+
V–
V+
09383-010
VIN+
AIN+
500Ω
AVDD
SPI
CONTROLLED
DC
Figure 38. LVDS Outputs (Dx+, Dx−, OR+, OR−, DCO+, DCO−)
500Ω
AVDD
VIN+
AIN–
20kΩ
(00)
09383-007
(01)
VREF
(10)
Figure 34. Analog Input DC Equivalent Circuit (VCML = ~1.7 V)
NOT USED
(11)
DRVDD
DRVDD
350Ω
09383-011
SPI CTRL VREF SELECT
00 = INTERNAL VREF
01 = IMPORT VREF
10 = EXPORT VREF
11 = NOT USED
Figure 39. Equivalent VREF Input/Output Circuit
SCLK/DFS
09383-008
30kΩ
DRVDD
DRVDD
Figure 35. Equivalent SCLK/DFS, PDWN Input Circuit
30kΩ
350Ω
VIN+
SDIO
CTRL
Figure 36. Analog Input AC Equivalent Circuit
Figure 40. Equivalent SDIO Input Circuit
Rev. B | Page 18 of 28
09383-012
VIN–
1000Ω
09383-025
1.3pF
Data Sheet
AD9434
THEORY OF OPERATION
The input stage contains a differential SHA that can be ac- or
dc-coupled in differential or single-ended mode. The output
staging block aligns the data, carries out the error correction,
and passes the data to the output buffers. The output buffers
are powered from a separate supply, allowing adjustment of the
output voltage swing. During power-down, the output buffers
enter a high impedance state.
ANALOG INPUT AND VOLTAGE REFERENCE
The analog input to the AD9434 is a differential buffer. For best
dynamic performance, match the source impedances driving
VIN+ and VIN− such that common-mode settling errors are
symmetrical. The analog input is optimized to provide superior
wideband performance and requires that the analog inputs be
driven differentially. SNR and SINAD performance degrades
significantly if the analog input is driven with a single-ended
signal.
Optimum performance is achieved while driving the AD9434
in a differential input configuration. For baseband applications,
the AD8138 differential driver provides excellent performance
and a flexible interface to the ADC. The output common-mode
voltage of the AD8138 is easily set to AVDD/2 + 0.5 V, and the
driver can be configured in a Sallen-Key filter topology to provide band limiting of the input signal.
1V p-p
499Ω
523Ω
AVDD
VIN+
33Ω
499Ω
AD8138
20pF
0.1µF
AD9434
VIN–
33Ω
499Ω
CML
Figure 41. Differential Input Configuration Using the AD8138
At input frequencies in the second Nyquist zone and above, the
performance of most amplifiers may not be adequate to achieve
the true performance of the AD9434. This is especially true in
IF undersampling applications where frequencies in the 70 MHz
to 100 MHz range are being sampled. For these applications,
differential transformer coupling is the recommended input
configuration. The signal characteristics must be considered
when selecting a transformer. Most RF transformers saturate at
frequencies below a few megahertz (MHz), and excessive signal
power can cause core saturation, which leads to distortion.
In any configuration, the value of the shunt capacitor, C (see
Figure 43), is dependent on the input frequency and may need
to be reduced or removed.
A wideband transformer, such as Mini-Circuits® ADT1-1WT,
can provide the differential analog inputs for applications that
require a single-ended-to-differential conversion. Both analog
inputs are self-biased by an on-chip reference to a nominal 1.7 V.
An internal differential voltage reference creates positive and
negative reference voltages that define the 1.5 V p-p fixed span
of the ADC core. This internal voltage reference can be adjusted
by means of an SPI control. See the AD9434 Configuration
Using the SPI section for more details.
49.9Ω
09383-013
Each stage of the pipeline, excluding the last, consists of a low
resolution flash ADC connected to a switched capacitor DAC
and interstage residue amplifier (MDAC). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each stage to facilitate digital correction
of flash errors. The last stage simply consists of a flash ADC.
Differential Input Configurations
15Ω
1.5V p-p
50Ω
2pF
15Ω
0.1µF
VIN+
AD9434
VIN–
09383-014
The AD9434 architecture consists of a front-end sample-andhold amplifier (SHA) followed by a pipelined switched capacitor
ADC. The quantized outputs from each stage are combined into
a final 12-bit result in the digital correction logic. The pipelined
architecture permits the first stage to operate on a new input
sample, whereas the remaining stages operate on preceding
samples. Sampling occurs on the rising edge of the clock.
Figure 42. Differential Transformer—Coupled Configuration
As an alternative to using a transformer-coupled input at frequencies in the second Nyquist zone, the AD8352 differential driver
can be used (see Figure 43).
Rev. B | Page 19 of 28
AD9434
Data Sheet
VCC
0.1µF
0.1µF
0Ω 16
8, 13
1
ANALOG INPUT
11
0.1µF
R
2
VIN+
200Ω
RD
CD
AD8352
RG
3
AD9434
C
0.1µF
200Ω
R
VIN– CML
4
5
14
0.1µF 0Ω
10
0.1µF
0.1µF
09383-015
ANALOG INPUT
Figure 43. Differential Input Configuration Using the AD8352
CLOCK INPUT CONSIDERATIONS
Figure 44 shows one preferred method for clocking the AD9434.
The low jitter clock source is converted from single-ended to
differential using an RF transformer. The back-to-back Schottky
diodes across the secondary transformer limit clock excursions
into the AD9434 to approximately 0.8 V p-p differential. This
helps prevent the large voltage swings of the clock from feeding
through to other portions of the AD9434 and preserves the fast
rise and fall times of the signal, which are critical to low jitter
performance.
CLOCK
INPUT
50Ω
100Ω
CLK+
AD9434
SCHOTTKY
DIODES:
HSM2812
ADC
AD9434
CLK–
CLK
240Ω
09383-017
240Ω
50Ω1
RESISTORS ARE OPTIONAL.
Figure 45. Differential PECL Sample Clock
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
0.1µF
CLOCK
INPUT
CLK+
100Ω
LVDS DRIVER
0.1µF
CLOCK
INPUT
50Ω1
150Ω
0.1µF
CLK
0.1µF
ADC
AD9434
CLK–
CLK
50Ω1
RESISTORS ARE OPTIONAL.
Figure 46. Differential LVDS Sample Clock
09383-016
CLK–
0.1µF
0.1µF
In some applications, it may be acceptable to drive the sample
clock inputs with a single-ended 1.8 V CMOS signal. In such
applications, drive the CLK+ pin directly from a CMOS gate,
and bypass the CLK− pin to ground with a 0.1 μF capacitor in
parallel with a 39 kΩ resistor (see Figure 47).
ADC
0.1µF
CLK+
100Ω
PECL DRIVER
0.1µF
CLOCK
INPUT
50Ω1
150Ω
0.1µF
CLK
VCC
Figure 44. Transformer-Coupled Differential Clock
0.1µF
If a low jitter clock is available, another option is to ac couple a
differential PECL signal to the sample clock input pins, as
shown in Figure 45. The AD9510/AD9511/AD9512/AD9513/
AD9514/AD9515 family of clock drivers offers excellent jitter
performance.
CLOCK
INPUT
50Ω1
1kΩ
AD951x
CMOS DRIVER
OPTIONAL
0.1µF
100Ω
1kΩ
CLK+
ADC
AD9434
CLK–
0.1µF
150Ω
39kΩ
RESISTOR IS OPTIONAL.
Figure 47. Single-Ended 1.8 V CMOS Input Clock (Up to 200 MHz)
Rev. B | Page 20 of 28
09383-024
0.1µF
MINI-CIRCUITS
ADT1–1WT, 1:1Z
0.1µF
XFMR
0.1µF
CLOCK
INPUT
09383-018
For optimum performance, drive the AD9434 sample clock
inputs (CLK+ and CLK−) with a differential signal. This signal
is typically ac-coupled into the CLK+ and CLK− pins via a
transformer or capacitors. These pins are biased at ~0.9 V
internally and require no additional bias. If the clock signal is
dc-coupled, then the common-mode voltage should remain
within a range of 0.9 V.
AD9510/AD9511/
AD9512/AD9513/
AD9514/AD9515
Data Sheet
AD9434
Clock Duty Cycle Considerations
POWER DISSIPATION AND POWER-DOWN MODE
Typical high speed ADCs use both clock edges to generate a
variety of internal timing signals. As a result, these ADCs may
be sensitive to clock duty cycle. A 5% tolerance is commonly
required on the clock duty cycle to maintain dynamic performance
characteristics. The AD9434 contains a duty cycle stabilizer (DCS)
that retimes the nonsampling edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows a wide range
of clock input duty cycles without affecting the performance of
the AD9434.
As shown in Figure 31, the power dissipated by the AD9434 is
proportional to its sample rate. The digital power dissipation
does not vary much because it is determined primarily by the
DRVDD supply and bias current of the LVDS output drivers.
The duty cycle stabilizer uses a delay-locked loop (DLL) to
create the nonsampling edge. As a result, any changes to the
sampling frequency require approximately 5 µs to allow the
DLL to acquire and lock to the new rate.
Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency
(fA) due only to aperture jitter (tJ) can be calculated by
SNR Degradation = 20 × log10(1/2 × π × fA × tJ)
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter specifications. IF undersampling
applications are particularly sensitive to jitter (see Figure 48).
Treat the clock input as an analog signal in cases where aperture
jitter may affect the dynamic range of the AD9434. Separate
power supplies for clock drivers from the ADC output driver
supplies to avoid modulating the clock signal with digital noise.
Low jitter, crystal-controlled oscillators make the best clock
sources. If the clock is generated from another type of source
(by gating, dividing, or other methods), it should be retimed by
the original clock at the last step.
Refer to the AN-501 Application Note and the AN-756
Application Note for more in-depth information about jitter
performance as it relates to ADCs (visit www.analog.com).
130
RMS CLOCK JITTER REQUIREMENT
120
100
16 BITS
90
14 BITS
80
12 BITS
10 BITS
60
8 BITS
40
0.125ps
0.25ps
0.5ps
1.0ps
2.0ps
30
1
10
100
ANALOG INPUT FREQUENCY (MHz)
1000
DIGITAL OUTPUTS
Digital Outputs and Timing
The AD9434 differential outputs conform to the ANSI-644
LVDS standard on default power-up. This can be changed to a
low power, reduced signal option similar to the IEEE 1596.3
standard using the SPI. This LVDS standard can further reduce
the overall power dissipation of the device, which reduces the
power by ~39 mW. See the Memory Map section for more information. The LVDS driver current is derived on chip and sets
the output current at each output equal to a nominal 3.5 mA.
A 100 Ω differential termination resistor placed at the LVDS
receiver inputs results in a nominal 350 mV swing at the receiver.
The AD9434 LVDS outputs facilitate interfacing with LVDS
receivers in custom ASICs and FPGAs that have LVDS capability
for superior switching performance in noisy environments.
Single point-to-point net topologies are recommended with a
100 Ω termination resistor placed as close to the receiver as
possible. No far end receiver termination or poor differential
trace routing may result in timing errors. It is recommended
that the trace length be no longer than 24 inches and that the
differential output traces be kept close together and at equal
lengths.
An example of the LVDS output using the ANSI standard (default)
data eye and a time interval error (TIE) jitter histogram with
trace lengths less than 24 inches on regular FR-4 material is
shown in Figure 49. Figure 50 shows an example of when the
trace lengths exceed 24 inches on regular FR-4 material. Notice
that the TIE jitter histogram reflects the decrease of the data eye
opening as the edge deviates from the ideal position. It is up to
the user to determine if the waveforms meet the timing budget
of the design when the trace lengths exceed 24 inches.
70
50
An additional standby mode is supported by means of varying
the clock input. When the clock rate falls below 50 MHz, the
AD9434 assumes a standby state. In this case, the biasing network
and internal reference remain on, but digital circuitry is powered
down. Upon reactivating the clock, the AD9434 resumes normal
operation after allowing for the pipeline latency.
09383-019
SNR (dB)
110
By asserting PDWN (Pin 29) high, the AD9434 is placed in
standby mode or full power-down mode, as determined by the
contents of Serial Port Register 08. Reasserting the PDWN pin
low returns the AD9434 to its normal operational mode.
Figure 48. Ideal SNR vs. Input Frequency and Jitter
Rev. B | Page 21 of 28
AD9434
Data Sheet
14
Out-of-Range (OR)
12
An out-of-range condition exists when the analog input voltage
is beyond the input range of the ADC. OR+ and OR− (OR±)
are digital outputs that are updated along with the data output
corresponding to the particular sampled input voltage. Thus,
OR± has the same pipeline latency as the digital data. OR± is
low when the analog input voltage is within the analog input
range and high when the analog input voltage exceeds the input
range, as shown in Figure 51. OR± remains high until the analog
input returns to within the input range and another conversion
is completed. By logically AND’ing OR± with the MSB and its
complement, overrange high or underrange low conditions can
be detected.
300
200
100
0
–100
–200
–300
–400
10
8
6
4
2
–3
–2
–1
0
1
2
0
–40
3
–20
0
20
09383-020
–500
40
TIME (ps)
TIME (ns)
OR± DATA OUTPUTS
1 1111 1111 1111
0 1111 1111 1111
0 1111 1111 1110
600
12
400
10
TIE JITTER HISTOGRAM (Hits)
200
0
–200
–600
–3
0
0
1
–2
–1
0
1
TIME (ns)
2
3
0000 0000 0001
0000 0000 0000
0000 0000 0000
8
–FS
–FS – 1/2 LSB
6
TIMING
4
0
–100
+FS
+FS – 1/2 LSB
Figure 51. OR± Relation to Input Voltage and Output Data
The AD9434 provides latched data outputs with a pipeline delay
of seven clock cycles. Data outputs are available one propagation delay (tPD) after the rising edge of the clock signal.
2
–400
+FS – 1 LSB
OR±
–FS + 1/2 LSB
0
09383-021
EYE DIAGRAM: VOLTAGE (mV)
Figure 49. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths Less
than 24 Inches on Standard FR-4, AD9434-500
09383-022
400
TIE JITTER HISTOGRAM (Hits)
EYE DIAGRAM: VOLTAGE (mV)
500
100
TIME (ps)
Figure 50. Data Eye for LVDS Outputs in ANSI Mode with Trace Lengths
Greater than 24 Inches on Standard FR-4, AD9434-500
The format of the output data is offset binary by default. An
example of the output coding format can be found in Table 12.
If it is desired to change the output data format to twos complement, see the AD9434 Configuration Using the SPI section.
An output clock signal is provided to assist in capturing data
from the AD9434. The DCO is used to clock the output data
and is equal to the sampling clock (CLK) rate. In single data
rate mode (SDR), data is clocked out of the AD9434 and must
be captured on the rising edge of the DCO. In double data rate
mode (DDR), data is clocked out of the AD9434 and must be
captured on the rising and falling edges of the DCO. See the
timing diagrams shown in Figure 2 and Figure 3 for more
information.
Minimize the length of the output data lines and loads placed
on them to reduce transients within the AD9434. These transients can degrade the dynamic performance of the converter.
The AD9434 also provides a data clock output (DCO) intended
for capturing the data in an external register. The data outputs are
valid on the rising edge of DCO.
The lowest conversion rate of the AD9434 is 50 MSPS. At clock
rates below 1 MSPS, the AD9434 assumes the standby mode.
VREF
The AD9434 VREF pin (Pin 31) allows the user to monitor the
on-board voltage reference, or provide an external reference
(requires configuration through the SPI). The three optional
settings are internal VREF (pin is connected to 20 kΩ to ground),
export VREF, and import VREF. Do not attach a bypass capacitor
to this pin. VREF is internally compensated and additional
loading may impact performance.
AD9434 CONFIGURATION USING THE SPI
Output Data Rate and Pinout Configuration
The output data of the AD9434 can be configured to drive 12
pairs of LVDS outputs at the same rate as the input clock signal
(SDR mode), or six pairs of LVDS outputs at 2× the rate of the
input clock signal (DDR mode). SDR is the default mode; the
device can be reconfigured for DDR by setting Bit 3 in Register 14
(see Table 13).
The AD9434 SPI allows the user to configure the converter for
specific functions or operations through a structured register
space inside the ADC. This gives the user added flexibility to
customize device operation depending on the application.
Addresses are accessed (programmed or readback) serially in
1-byte words. Each byte can be further divided into fields,
which are documented in the Memory Map section.
Rev. B | Page 22 of 28
Data Sheet
AD9434
data is composed of 8-bit words. The first bit of each individual
byte of serial data indicates whether this is a read or write command. This allows the serial data input/output (SDIO) pin to
change direction from an input to an output.
There are three pins that define the serial port interface (SPI) to
this particular ADC. They are the SCLK/DFS, SDIO, and CSB
pins. The SCLK/DFS (serial clock) is used to synchronize the
read and write data presented to the ADC. The SDIO (serial
data input/output) is a dual-purpose pin that allows data to be
sent to and read from the internal ADC memory map registers.
The CSB is an active low control that enables or disables the
read and write cycles (see Table 9).
Data can be sent in MSB or in LSB first mode. MSB first is
default on power-up and can be changed by changing the
configuration register. For more information about this feature
and others, see the AN-877 Application Note, Interfacing to
High Speed ADCs via SPI at www.analog.com.
USING THE AD9434 TO REPLACE THE AD9230
HARDWARE INTERFACE
The AD9434 can be used to replace the AD9230 in many
applications. In these designs, the user should consider these
important differences:
The pins described in Table 9 comprise the physical interface
between the programming device of the user and the serial port
of the AD9434. The SCLK pin and the CSB pin function as
inputs when using the SPI interface. The SDIO pin is bidirectional, functioning as an input during the write phase and as an
output during readback.
Pin 28 is a DNC (do not connect) on the AD9434, and
should be left floating. The reset functionality of the
AD9230 is not available through an external pin, but is
available through the SPI interface.
Pin 31 is the interface to the AD9434 reference circuit. It
can be used to monitor the internal reference or provide an
external reference voltage (nominally 0.5 V). If the internal
reference is used, then this pin can float. The RBIAS function of the AD9230 is not necessary with the AD9434.
The input voltage range of the AD9434 is nominally
1.5 V p-p, whereas the AD9230 input range is 1.25 V p-p.
This interface is flexible enough to be controlled by either
PROMs or PIC® mirocontrollers as well. This provides the user
with an alternate method to program the ADC other than a SPI
controller.
If the user chooses not to use the SPI interface, some pins serve
a dual function and are associated with a specific function when
strapped externally to AVDD or ground during device poweron. The Configuration Without the SPI section describes the
strappable functions supported on the AD9434.
Table 9. Serial Port Pins
Mnemonic
SCLK
SDIO
CSB
Function
SCLK (serial clock) is the serial shift clock in.
SCLK is used to synchronize serial interface
reads and writes.
SDIO (serial data input/output) is a dual-purpose
pin. The typical role for this pin is an input and
output depending on the instruction being sent
and the relative position in the timing frame.
CSB (chip select) is an active low control that
gates the read and write cycles.
CONFIGURATION WITHOUT THE SPI
In applications that do not interface to the SPI control registers,
the SCLK/DFS pin can alternately serve as a standalone CMOScompatible control pin. In this mode, connect the CSB pin to
AVDD, which disables the serial port interface.
Table 10. Mode Selection
Mnemonic
SCLK/DFS
The falling edge of the CSB, in conjunction with the rising edge
of the SCLK, determines the start of the framing. An example of
the serial timing and its definitions can be found in Figure 52
and Table 11.
External
Voltage
AVDD
AGND
Configuration
Twos complement enabled
Offset binary enabled
During an instruction phase, a 16-bit instruction is transmitted.
Data then follows the instruction phase and is determined by
the W0 and W1 bits, which is one or more bytes of data. All
tDS
tS
tHIGH
tCLK
tDH
tH
tLOW
CSB
SCLK DON’T CARE
R/W
W1
W0
A12
A11
A10
A9
A8
A7
D5
Figure 52. Serial Port Interface Timing Diagram
Rev. B | Page 23 of 28
D4
D3
D2
D1
D0
DON’T CARE
09383-023
SDIO DON’T CARE
DON’T CARE
AD9434
Data Sheet
Table 11. Serial Timing Definitions
Parameter
tDS
tDH
tCLK
tS
tH
tHIGH
tLOW
tEN_SDIO
Min (ns)
5
2
40
5
2
16
16
1
tDIS_SDIO
5
Description
Setup time between the data and the rising edge of SCLK
Hold time between the data and the rising edge of SCLK
Period of the clock
Setup time between CSB and SCLK
Hold time between CSB and SCLK
Minimum period that SCLK should be in a logic high state
Minimum period that SCLK should be in a logic low state
Minimum time for the SDIO pin to switch from an input to an output relative to the SCLK
falling edge (not shown in Figure 52)
Minimum time for the SDIO pin to switch from an output to an input relative to the SCLK rising
edge (not shown in Figure 52)
Table 12. Output Data Format
Input (V)
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
VIN+ − VIN−
Condition (V)
< −0.75 − 0.5 LSB
= −0.75
=0
= 0.75
> 0.75 + 0.5 LSB
Offset Binary Output Mode, D11 to D0
0000 0000 0000
0000 0000 0000
1000 0000 0000
1111 1111 1111
1111 1111 1111
Rev. B | Page 24 of 28
Twos Complement Mode, D11 to D0
1000 0000 0000
1000 0000 0000
0000 0000 0000
0111 1111 1111
0111 1111 1111
OR±
1
0
0
0
1
Data Sheet
AD9434
MEMORY MAP
READING THE MEMORY MAP TABLE
RESERVED LOCATIONS
Each row in the memory map table (see Table 13) has eight
address locations. The memory map is roughly divided into
three sections: chip configuration register map (Address 0x00 to
Address 0x02), transfer register map (Address 0xFF), and ADC
functions register map (Address 0x08 to Address 0x2A). Data
written to the ADC functions register addresses also require
setting the SW transfer bit in register Address 0xFF to transfer
the data from the master to slave registers.
Undefined memory locations should not be written to other
than with the default values suggested in this data sheet. Addresses
that have values marked as 0 should be considered reserved and
have a 0 written into their registers during power-up.
DEFAULT VALUES
Exiting out of reset, critical registers are preloaded with default
values. These values are indicated in Table 13. Other registers
do not have default values and retain the previous value when
exiting reset.
The Addr. (Hex) column of the memory map indicates the
register address in hexadecimal, and the Default Value (Hex)
column shows the default hexadecimal value that is already
written into the register. The Bit 7 (MSB) column is the start of
the default hexadecimal value given. For example, Hexadecimal
Address 0x2A, OVR_CONFIG, has a hexadecimal default value
of 0x01. This means that Bit 7 = 0, Bit 6 = 0, Bit 5 = 0, Bit 4 = 0,
Bit 3 = 0, Bit 2 = 0, Bit 1 = 0, and Bit 0 = 1, or 0000 0001 in
binary. The default value enables the OR± output. Overwriting
this default so that Bit 0 = 0 disables the OR± output. For more
information on this and other functions, consult the AN-877
Application Note, Interfacing to High-Speed ADCs via SPI® at
www.analog.com.
LOGIC LEVELS
An explanation of various registers follows: “Bit is set” is
synonymous with “bit is set to Logic 1” or “writing Logic 1 for
the bit.” Similarly, “clear a bit” is synonymous with “bit is set to
Logic 0” or “writing Logic 0 for the bit.”
Table 13. Memory Map Register
Addr.
(Hex) Register Name
Chip Configuration Registers
00
CHIP_PORT_CONFIG
01
CHIP_ID
02
CHIP_GRADE
Bit 7
(MSB)
0
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
LSB
first
Soft
reset
1
1
Soft
reset
LSB
first
Bit 0
(LSB)
Default
Value
(Hex)
0
0x18
Read
only
8-bit chip ID, Bits[7:0] = 0x6A
0
0
0
Speed grade:
00 = 500 MSPS
01 = 370 MSPS
Transfer Register
FF
DEVICE_UPDATE
0
0
0
0
0
ADC Functions Registers
08
Modes
0
0
PDWN:
0 = full
(default)
1=
standby
0
0
Rev. B | Page 25 of 28
Default Notes/
Comments
The nibbles
should be
mirrored by the
user so that LSB
or MSB first
mode registers
correctly,
regardless of
shift mode.
Default is a
unique chip ID,
different for
each device.
This is a readonly register.
Child ID used to
differentiate
graded devices.
X1
X1
X1
Read
only
0
0
SW
transfer
0x00
Synchronously
transfers data
from the master
shift register to
the slave.
Internal power-down mode:
000 = normal (power-up,
default)
001 = full power-down
010 = standby
011 = normal (power-up)
0x00
Determines
various generic
modes of chip
operation.
AD9434
Data Sheet
Addr.
(Hex)
Bit 7
(MSB)
Register Name
10
Offset
0D
TEST_IO
(For user-defined
mode only, set
Bits[3:0] = 1000)
00 = Pattern 1 only
01 = toggle P1/P2
10 = toggle
P1/0000
11 = toggle P1/P2/
0000
Reset
PN23
gen:
1 = on
0 = off
(default)
Reset
PN9
gen:
1 = on
0 = off
(default)
0F
AIN_CONFIG
0
0
0
0
14
OUTPUT_MODE
0
0
0
15
OUTPUT_ADJUST
0
0
0
Output
enable:
0=
enable
(default)
1=
disable
0
16
OUTPUT_PHASE
0
0
0
17
FLEX_OUTPUT_DELAY
Output
clock
polarity
1=
inverted
0=
normal
(default)
0
0
0
0
Bit 6
Bit 0
(LSB)
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Note that external PDWN pin
overrides this setting
8-bit device offset adjustment [7:0]
0111 1111 = +127 codes
0000 0000 = 0 codes
1000 0000 = −128 codes
Default
Value
(Hex)
0x00
Output test mode:
0000 = off (default)
0001 = midscale short
0010 = +FS short
0011 = −FS short
0100 = checkerboard output
0101 = PN23 sequence
0110 = PN9
0111 = one/zero word toggle
1000 = user defined
1001 = unused
1010 = unused
1011 = unused
1100 = unused
(Format determined by OUTPUT_MODE)
Analog
0
0
0
input
disable:
1 = on
0 = off
(default)
Data format select:
Output
DDR:
00 = offset binary
invert:
1=
(default)
enabled 1 = on
01 = twos
0 = off
0=
complement
disabled (default)
10 = Gray code
(default)
0x00
LVDS
course
adjust:
0=
3.5 mA
(default)
1=
2.0 mA
0x00
0
Rev. B | Page 26 of 28
0
LVDS fine adjust:
001 = 3.50 mA
010 = 3.25 mA
011 = 3.00 mA
100 = 2.75 mA
101 = 2.50 mA
110 = 2.25 mA
111 = 2.00 mA
0
0
Output clock delay:
0000 = 0
0001 = −1/10
0010 = −2/10
0011 = −3/10
0100 = reserved
0101 = +5/10
0110 = +4/10
0111 = +3/10
1000 = +2/10
1001 = +1/10
Default Notes/
Comments
Device offset
trim: codes are
relative to the
output
resolution.
When set, the
test data is
placed on the
output pins in
place of normal
data.
Set pattern
values:
P1 = Reg 0x19,
Reg 0x1A
P2 = Reg 0x1B,
Reg 0x1C.
0x00
0x00
0x00
0x00
Shown as
fractional value
of sampling
clock period
that is
subtracted or
added to initial
tSKEW, see
Figure 2
Data Sheet
AD9434
Addr.
(Hex)
18
Bit 7
(MSB)
Bit 6
VREF select
00 = internal VREF
(20 kΩ pull-down)
01 = import VREF
(0.59 V to 0.8 V on
VREF pin)
10 = export VREF
(from internal
reference)
11 = not used
Register Name
FLEX_VREF
19
USER_PATT1_LSB
B7
1A
USER_PATT1_MSB
1B
Bit 0
(LSB)
Bit 5
0
Bit 4
B6
B5
B4
B7
B6
B5
B4
B3
B2
B1
B0
0x00
USER_PATT2_LSB
B7
B6
B5
B4
B3
B2
B1
B0
0x00
1C
USER_PATT2_MSB
B7
B6
B5
B4
B3
B2
B1
B0
0x00
2A
OVR_CONFIG
0
0
0
0
0
0
OR±
enable:
1 = on
(default)
0 = off
0x01
2C
Input coupling
0
0
0
0
0
DC
coupling
enable
OR±
position
(DDR
mode
only):
0=
Pin 9,
Pin 10
1=
Pin 21,
Pin 22
0
0
0x00
1
Bit 3
Bit 2
Bit 1
Input voltage range setting:
11100 = 1.60
00101 = 1.36
11101 = 1.58
00110 = 1.34
11110 = 1.55
00111 = 1.31
11111 = 1.52
01000 = 1.28
00000 = 1.50
01001 = 1.26
00001 = 1.47
01010 = 1.23
00010 = 1.44
01011 = 1.20
00011 = 1.42
01100 = 1.18
00100 = 1.39
B3
B2
B1
B0
Default
Value
(Hex)
0x00
X = don’t care.
Rev. B | Page 27 of 28
0x00
Default Notes/
Comments
User-defined
pattern, 1 LSB.
User-defined
pattern, 1 MSB.
User-defined
pattern, 2 LSBs.
User-defined
pattern, 2 MSBs.
Default is
ac coupling.
AD9434
Data Sheet
OUTLINE DIMENSIONS
0.30
0.23
0.18
0.60 MAX
0.60
MAX
43
1
42
PIN 1
INDICATOR
7.85
7.75 SQ
7.65
0.50
BSC
5.25
5.10 SQ
4.95
EXPOSED
PAD
29
TOP VIEW
1.00
0.85
0.80
0.80 MAX
0.65 TYP
12° MAX
SEATING
PLANE
0.50
0.40
0.30
14
28
15
BOTTOM VIEW
0.25 MIN
6.50 REF
0.05 MAX
0.02 NOM
COPLANARITY
0.20 REF
0.08
SIDE VIEW
PIN 1
INDICATOR
56
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-VLLD-2
06-11-2012-A
8.10
8.00 SQ
7.90
Figure 53. 56-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
8 mm × 8 mm Body, Very Thin Quad
(CP-56-5)
Dimensions shown in millimeters
ORDERING GUIDE
Model 1
AD9434BCPZ-370
AD9434BCPZRL7-370
AD9434BCPZ-500
AD9434BCPZRL7-500
AD9434-370EBZ
AD9434-500EBZ
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
56-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
56-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
56-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
56-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
LVDS Evaluation Board with AD9434BCPZ-370
LVDS Evaluation Board with AD9434BCPZ-500
Z = RoHS Compliant Part.
©2011–2013 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D09383-0-2/13(B)
Rev. B | Page 28 of 28
Package Option
CP-56-5
CP-56-5
CP-56-5
CP-56-5
工商网监
湘ICP备2023018690号
