1.2 GHz Clock Distribution IC, 1.6 GHz Inputs,
Dividers, Delay Adjust, Five Outputs
AD9512
FEATURES
FUNCTIONAL BLOCK DIAGRAM
VS
FUNCTION
DSYNC
DSYNCB
SYNCB,
RESETB
PDB
DETECT
SYNC
GND
RSET
VREF
AD9512
PROGRAMMABLE
DIVIDERS AND
PHASE ADJUST
Low jitter, low phase noise clock distribution
Clocking high speed ADCs, DACs, DDSs, DDCs, DUCs, MxFEs
High performance wireless transceivers
High performance instrumentation
Broadband infrastructure
SYNC
STATUS
LVPECL
OUT0
/1, /2, /3... /31, /32
OUT0B
LVPECL
OUT1
/1, /2, /3... /31, /32
OUT1B
CLK1
LVPECL
CLK1B
OUT2
/1, /2, /3... /31, /32
CLK2
OUT2B
LVDS/CMOS
CLK2B
APPLICATIONS
SYNC
STATUS
OUT3
/1, /2, /3... /31, /32
OUT3B
SCLK
SDIO
SDO
CSB
SERIAL
CONTROL
PORT
LVDS/CMOS
/1, /2, /3... /31, /32
T
DELAY
ADJUST
OUT4
OUT4B
Figure 1.
GENERAL DESCRIPTION
The AD9512 provides a multi-output clock distribution in a
design that emphasizes low jitter and low phase noise to
maximize data converter performance. Other applications with
demanding phase noise and jitter requirements can also benefit
from this part.
There are five independent clock outputs. Three outputs are
LVPECL (1.2 GHz), and two are selectable as either LVDS
(800 MHz) or CMOS (250 MHz) levels.
Each output has a programmable divider that may be bypassed
or set to divide by any integer up to 32. The phase of one clock
output relative to another clock output may be varied by means
of a divider phase select function that serves as a coarse timing
adjustment.
One of the LVDS/CMOS outputs features a programmable
delay element with a range of up to 10 ns of delay. This fine
tuning delay block has 5-bit resolution, giving 32 possible
delays from which to choose.
The AD9512 is ideally suited for data converter clocking
applications where maximum converter performance is
achieved by encode signals with subpicosecond jitter.
The AD9512 is available in a 48-lead LFCSP and can be
operated from a single 3.3 V supply. The temperature range is
−40°C to +85°C.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2005–2020 Analog Devices, Inc. All rights reserved.
05287-001
Two 1.6 GHz, differential clock inputs
5 programmable dividers, 1 to 32, all integers
Phase select for output-to-output coarse delay adjust
3 independent 1.2 GHz LVPECL outputs
Additive output jitter 225 fs rms
2 independent 800 MHz/250 MHz LVDS/CMOS clock outputs
Additive output jitter 275 fs rms
Fine delay adjust on 1 LVDS/CMOS output
Serial control port
Space-saving 48-lead LFCSP
AD9512
TABLE OF CONTENTS
Specifications .................................................................................... 4
Outputs ........................................................................................ 30
Clock Inputs .................................................................................. 4
Power-Down Modes .................................................................. 31
Clock Outputs ............................................................................... 4
Chip Power-Down or Sleep Mode—PDB .......................... 31
Timing Characteristics ................................................................ 5
Distribution Power-Down .................................................... 31
Clock Output Phase Noise .......................................................... 7
Individual Clock Output Power-Down .............................. 31
Clock Output Additive Time Jitter .......................................... 10
Individual Circuit Block Power-Down ............................... 31
Serial Control Port ..................................................................... 12
Reset Modes ................................................................................ 31
FUNCTION Pin ......................................................................... 13
Power-On Reset—Start-Up Conditions when VS is
Applied .................................................................................... 31
SYNC STATUS Pin .................................................................... 13
Asynchronous Reset via the FUNCTION Pin ................... 31
Power ........................................................................................... 14
Soft Reset via the Serial Port ................................................. 31
Timing Diagrams............................................................................ 15
Absolute Maximum Ratings ......................................................... 16
Single-Chip Synchronization ................................................... 32
SYNCB—Hardware SYNC ................................................... 32
Thermal Characteristics ............................................................ 16
Soft SYNC—Register 58h .............................................. 32
ESD Caution................................................................................ 16
Pin Configuration and Function Descriptions .......................... 17
Terminology .................................................................................... 19
Typical Performance Characteristics ........................................... 20
Functional Description .................................................................. 24
Multichip Synchronization ....................................................... 32
Serial Control Port ......................................................................... 33
Serial Control Port Pin Descriptions....................................... 33
General Operation of Serial Control Port .............................. 33
Framing a Communication Cycle with CSB ...................... 33
Overall .......................................................................................... 24
Communication Cycle—Instruction Plus Data ................ 33
FUNCTION Pin ......................................................................... 24
Write ........................................................................................ 33
RESETB: 58h = 00b (Default)..................................... 24
Read ......................................................................................... 34
SYNCB: 58h = 01b ....................................................... 24
PDB: 58h = 11b............................................................. 24
DSYNC and DSYNCB Pins ...................................................... 24
Clock Inputs ................................................................................ 24
Dividers ........................................................................................ 25
Setting the Divide Ratio ........................................................ 25
Setting the Duty Cycle ........................................................... 25
Divider Phase Offset .............................................................. 29
Delay Block.................................................................................. 30
Calculating the Delay............................................................. 30
The Instruction Word (16 Bits) ............................................... 34
MSB/LSB First Transfers ........................................................... 34
Register Map and Description ...................................................... 37
Summary Table .......................................................................... 37
Register Map Description ......................................................... 39
Power Supply .................................................................................. 43
Power Management ................................................................... 43
Applications .................................................................................... 44
Using the AD9512 Outputs for ADC Clock Applications ... 44
CMOS Clock Distribution ........................................................ 44
Rev. B | Page 2 of 48
AD9512
LVPECL Clock Distribution .....................................................45
Ordering Guide ........................................................................... 46
LVDS Clock Distribution ..........................................................45
Power and Grounding Considerations and Power Supply
Rejection .......................................................................................45
Outline Dimensions ........................................................................46
REVISION HISTORY
9/2020—Rev. A to Rev. B
Changed CP-48-1 to CP-48-4 ..................................... Throughout
Changes to Figure 6 ........................................................................17
Updated Outline Dimensions .......................................................46
Changes to Ordering Guide...........................................................46
6/2005—Rev. 0 to Rev. A
Changes to Features .......................................................................... 1
Changes to General Description ..................................................... 1
Changes to Table 1 ............................................................................ 4
Changes to Table 3 ............................................................................ 5
Changes to Table 4 ............................................................................ 7
Changes to Table 5 and Table 6 ....................................................12
Changes to Table 7 ..........................................................................13
Changes to Figure 12 and Figure 14 to Figure 16 .......................21
Changes to Figure 17 Caption .......................................................22
Changes to Figure 23 ......................................................................23
Changes to Divider Phase Offset Section ....................................29
Changes to Chip Power-Down or Sleep Mode—PDB Section.31
Changes to Distribution Power-Down Section ..........................31
Changes to Individual Clock Output Power-Down Section.....31
Changes to Individual Circuit Block Power-Down Section .....31
Changes to Soft Reset via the Serial Port Section .......................31
Changes to SYNCB—Hardware SYNC Section .........................32
Changes to Soft SYNC Register 58h Section ........................ 32
Changes to Multichip Synchronization Section ......................... 32
Changes to Serial Control Port Section ....................................... 33
Changes to Serial Control Port Pin Descriptions Section ......... 33
Changes to General Operation of Serial
Control Port Section ....................................................................... 33
Added Framing a Communication Cycle with CSB Section .... 33
Added Communication Cycle—Instruction Plus
Data Section ..................................................................................... 33
Changes to Write Section .............................................................. 33
Changes to Read Section ................................................................ 34
Changes to Instruction Word (16 Bits) Section ......................... 34
Changes to MSB/LSB First Transfers Section ............................. 34
Changes to Figure 32 and Figure 36 ............................................. 35
Added Figure 38; Renumbered Sequentially .............................. 36
Changes to Table 17........................................................................ 37
Changes to Table 18........................................................................ 39
Changes to Power Supply Section ................................................ 43
Changes to Power Management Section ..................................... 43
4/2005—Revision 0: Initial Version
Rev. B | Page 3 of 48
AD9512
SPECIFICATIONS
Typical (Typ) is given for VS = 3.3 V ± 5%; TA = 25°C, RSET = 4.12 kΩ, unless otherwise noted. Minimum (Min) and Maximum (Max)
values are given over full VS and TA (−40°C to +85°C) variation.
CLOCK INPUTS
Table 1.
Parameter
CLOCK INPUTS (CLK1, CLK2)1
Input Frequency
Input Sensitivity
Min
Typ
0
Unit
1.6
GHz
mV p-p
1502
Input Level
Input Common-Mode Voltage, VCM
Input Common-Mode Range, VCMR
Input Sensitivity, Single-Ended
Input Resistance
Input Capacitance
Max
1.5
1.3
4.0
1.6
150
4.8
2
23
V p-p
1.7
1.8
V
V
mV p-p
kΩ
pF
5.6
Test Conditions/Comments
Jitter performance can be improved with higher slew
rates (greater swing).
Larger swings turn on the protection diodes and can
degrade jitter performance.
Self-biased; enables ac coupling.
With 200 mV p-p signal applied; dc-coupled.
CLK2 ac-coupled; CLK2B ac bypassed to RF ground.
Self-biased.
1
CLK1 and CLK2 are electrically identical; each can be used as either differential or single-ended input.
With a 50 Ω termination, this is −12.5 dBm.
3
With a 50 Ω termination, this is +10 dBm.
2
CLOCK OUTPUTS
Table 2.
Parameter
LVPECL CLOCK OUTPUTS
OUT0, OUT1, OUT2; Differential
Output Frequency
Output High Voltage (VOH)
Output Low Voltage (VOL)
Output Differential Voltage (VOD)
LVDS CLOCK OUTPUTS
OUT3, OUT4; Differential
Output Frequency
Differential Output Voltage (VOD)
Delta VOD
Output Offset Voltage (VOS)
Delta VOS
Short-Circuit Current (ISA, ISB)
CMOS CLOCK OUTPUTS
OUT3, OUT4
Output Frequency
Output Voltage High (VOH)
Output Voltage Low (VOL)
Min
Typ
Max
Unit
VS − 1.22
VS − 2.10
660
VS − 0.98
VS − 1.80
810
1200
VS − 0.93
VS − 1.67
965
MHz
V
V
mV
250
360
1.125
1.23
14
800
450
25
1.375
25
24
250
VS − 0.1
0.1
Rev. B | Page 4 of 48
MHz
mV
mV
V
mV
mA
MHz
V
V
Test Conditions/Comments
Termination = 50 Ω to VS − 2 V
Output level 3Dh (3Eh) (3Fh) = 10b
See Figure 14
Termination = 100 Ω differential; default
Output level 40h (41h) = 01b
3.5 mA termination current
See Figure 15
Output shorted to GND
Single-ended measurements;
B outputs: inverted, termination open
With 5 pF load each output; see Figure 16
@ 1 mA load
@ 1 mA load
AD9512
TIMING CHARACTERISTICS
Table 3.
Parameter
LVPECL
Output Rise Time, tRP
Output Fall Time, tFP
PROPAGATION DELAY, tPECL, CLK-TO-LVPECL OUT1
Divide = Bypass
Divide = 2 − 32
Variation with Temperature
OUTPUT SKEW, LVPECL OUTPUTS
OUT1 to OUT0 on Same Part, tSKP2
OUT1 to OUT2 on Same Part, tSKP2
OUT0 to OUT2 on Same Part, tSKP2
All LVPECL OUT Across Multiple Parts, tSKP_AB3
Same LVPECL OUT Across Multiple Parts, tSKP_AB3
LVDS
Output Rise Time, tRL
Output Fall Time, tFL
PROPAGATION DELAY, tLVDS, CLK-TO-LVDS OUT1
OUT3 to OUT4
Divide = Bypass
Divide = 2 − 32
Variation with Temperature
OUTPUT SKEW, LVDS OUTPUTS
OUT3 to OUT4 on Same Part, tSKV2
All LVDS OUTs Across Multiple Parts, tSKV_AB3
Same LVDS OUT Across Multiple Parts, tSKV_AB3
CMOS
Output Rise Time, tRC
Output Fall Time, tFC
PROPAGATION DELAY, tCMOS, CLK-TO-CMOS OUT1
Divide = Bypass
Divide = 2 − 32
Variation with Temperature
OUTPUT SKEW, CMOS OUTPUTS
OUT3 to OUT4 on Same Part, tSKC2
All CMOS OUT Across Multiple Parts, tSKC_AB3
Same CMOS OUT Across Multiple Parts, tSKC_AB3
LVPECL-TO-LVDS OUT
Output Skew, tSKP_V
LVPECL-TO-CMOS OUT
Output Skew, tSKP_C
LVDS-TO-CMOS OUT
Output Skew, tSKV_C
Min
Typ
Max
Unit
130
130
180
180
ps
ps
335
375
490
545
0.5
635
695
ps
ps
ps/°C
70
15
45
100
45
65
140
80
90
275
130
ps
ps
Ps
ps
ps
200
210
350
350
ps
ps
1.33
1.38
0.9
1.59
1.64
ns
ns
ps/°C
+270
450
325
ps
ps
ps
681
646
865
992
ps
ps
1.02
1.07
1.39
1.44
1
1.71
1.76
ns
ns
ps/°C
−140
+145
+300
650
500
ps
ps
0.99
1.04
Test Conditions/Comments
Termination = 50 Ω to VS − 2 V
Output level 3Dh (3Eh) (3Fh) = 10b
20% to 80%, measured differentially
80% to 20%, measured differentially
Termination = 100 Ω differential
Output level 40h (41h) = 01b
3.5 mA termination current
20% to 80%, measured differentially
80% to 20%, measured differentially
Delay off on OUT4
Delay off on OUT4
−85
B outputs are inverted; termination = open
20% to 80%; CLOAD = 3 pF
80% to 20%; CLOAD = 3 pF
Delay off on OUT4
Delay off on OUT4
0.74
0.92
1.14
ns
0.88
1.14
1.43
ns
158
353
506
ps
Rev. B | Page 5 of 48
Everything the same; different logic type
LVPECL to LVDS on same part
Everything the same; different logic type
LVPECL to CMOS on same part
Everything the same; different logic type
LVDS to CMOS on same part
AD9512
Parameter
DELAY ADJUST
Shortest Delay Range4
Zero Scale
Full Scale
Linearity, DNL
Linearity, INL
Longest Delay Range4
Zero Scale
Full Scale
Linearity, DNL
Linearity, INL
Delay Variation with Temperature
Long Delay Range, 10 ns5
Zero Scale
Full Scale
Short Delay Range, 1 ns5
Zero Scale
Full Scale
Min
Typ
Max
Unit
0.05
0.72
0.36
1.12
0.5
0.8
0.68
1.51
ns
ns
LSB
LSB
0.20
9.0
0.57
10.2
0.3
0.6
0.95
11.6
ns
ns
LSB
LSB
0.35
−0.14
ps/°C
ps/°C
0.51
0.67
ps/°C
ps/°C
1
Test Conditions/Comments
OUT4; LVDS and CMOS
35h 11111b
36h 00000b
36h 11111b
35h 00000b
36h 00000b
36h 11111b
The measurements are for CLK1. For CLK2, add approximately 25 ps.
This is the difference between any two similar delay paths within a single device operating at the same voltage and temperature.
3
This is the difference between any two similar delay paths across multiple devices operating at the same voltage and temperature.
4
Incremental delay; does not include propagation delay.
5
All delays between the zero scale and full scale can be estimated by linear interpolation.
2
Rev. B | Page 6 of 48
AD9512
CLOCK OUTPUT PHASE NOISE
Table 4.
Parameter
CLK1-TO-LVPECL ADDITIVE PHASE NOISE
CLK1 = 622.08 MHz, OUT = 622.08 MHz
Divide Ratio = 1
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
>1 MHz Offset
CLK1 = 622.08 MHz, OUT = 155.52 MHz
Divide Ratio = 4
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
>1 MHz Offset
CLK1 = 622.08 MHz, OUT = 38.88 MHz
Divide Ratio = 16
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
>1 MHz Offset
CLK1 = 491.52 MHz, OUT = 61.44 MHz
Divide Ratio = 8
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
>1 MHz Offset
CLK1 = 491.52 MHz, OUT = 245.76 MHz
Divide Ratio = 2
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
>1 MHz Offset
CLK1 = 245.76 MHz, OUT = 61.44 MHz
Divide Ratio = 4
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
>1 MHz Offset
Min
Typ
Max
Unit
Test Conditions/Comments
Input slew rate > 1 V/ns
−125
−132
−140
−148
−153
−154
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−128
−140
−148
−155
−161
−161
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−135
−145
−158
−165
−165
−166
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−131
−142
−153
−160
−165
−165
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−125
−132
−140
−151
−157
−158
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−138
−144
−154
−163
−164
−165
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Rev. B | Page 7 of 48
AD9512
Parameter
CLK1-TO-LVDS ADDITIVE PHASE NOISE
CLK1 = 622.08 MHz, OUT = 622.08 MHz
Divide Ratio = 1
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
>10 MHz Offset
CLK1 = 622.08 MHz, OUT = 155.52 MHz
Divide Ratio = 4
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
>10 MHz Offset
CLK1 = 491.52 MHz, OUT = 245.76 MHz
Divide Ratio = 2
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
>10 MHz Offset
CLK1 = 491.52 MHz, OUT = 122.88 MHz
Divide Ratio = 4
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
>10 MHz Offset
CLK1 = 245.76 MHz, OUT = 245.76 MHz
Divide Ratio = 1
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
>10 MHz Offset
Min
Typ
Max
Unit
−100
−110
−118
−129
−135
−140
−148
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−112
−122
−132
−142
−148
−152
−155
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−108
−118
−128
−138
−145
−148
−154
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−118
−129
−136
−147
−153
−156
−158
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−108
−118
−128
−138
−145
−148
−155
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Rev. B | Page 8 of 48
Test Conditions/Comments
AD9512
Parameter
CLK1 = 245.76 MHz, OUT = 122.88 MHz
Divide Ratio = 2
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
>10 MHz Offset
CLK1-TO-CMOS ADDITIVE PHASE NOISE
CLK1 = 245.76 MHz, OUT = 245.76 MHz
Divide Ratio = 1
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
> 10 MHz Offset
CLK1 = 245.76 MHz, OUT = 61.44 MHz
Divide Ratio = 4
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
>10 MHz Offset
CLK1 = 78.6432 MHz, OUT = 78.6432 MHz
Divide Ratio = 1
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
@ 1 MHz Offset
>10 MHz Offset
CLK1 = 78.6432 MHz, OUT = 39.3216 MHz
Divide Ratio = 2
@ 10 Hz Offset
@ 100 Hz Offset
@ 1 kHz Offset
@ 10 kHz Offset
@ 100 kHz Offset
>1 MHz Offset
Min
Typ
Max
Unit
−118
−127
−137
−147
−154
−156
−158
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−110
−121
−130
−140
−145
−149
−156
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−122
−132
−143
−152
−158
−160
−162
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−122
−132
−140
−150
−155
−158
−160
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
−128
−136
−146
−155
−161
−162
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Rev. B | Page 9 of 48
Test Conditions/Comments
AD9512
CLOCK OUTPUT ADDITIVE TIME JITTER
Table 5.
Parameter
LVPECL OUTPUT ADDITIVE TIME JITTER
CLK1 = 622.08 MHz
Any LVPECL (OUT0 to OUT2) = 622.08 MHz
Divide Ratio = 1
CLK1 = 622.08 MHz
Any LVPECL (OUT0 to OUT2) = 155.52 MHz
Divide Ratio = 4
CLK1 = 400 MHz
Any LVPECL (OUT0 to OUT2) = 100 MHz
Divide Ratio = 4
CLK1 = 400 MHz
Any LVPECL (OUT0 to OUT2) = 100 MHz
Divide Ratio = 4
Other LVPECL = 100 MHz
Both LVDS (OUT3, OUT4) = 100 MHz
CLK1 = 400 MHz
Any LVPECL (OUT0 to OUT2) = 100 MHz
Divide Ratio = 4
Other LVPECL = 50 MHz
Both LVDS (OUT3, OUT4) = 50 MHz
CLK1 = 400 MHz
Any LVPECL (OUT0 to OUT2) = 100 MHz
Divide Ratio = 4
Other LVPECL = 50 MHz
Both CMOS (OUT3, OUT4) = 50 MHz (B Outputs Off)
CLK1 = 400 MHz
Any LVPECL (OUT0 to OUT2) = 100 MHz
Divide Ratio = 4
Other LVPECL = 50 MHz
Both CMOS (OUT3, OUT4) = 50 MHz (B Outputs On)
LVDS OUTPUT ADDITIVE TIME JITTER
CLK1 = 400 MHz
Min
Typ
Max
Unit
Test Conditions/Comments
40
fs rms
BW = 12 kHz − 20 MHz (OC-12)
55
fs rms
BW = 12 kHz − 20 MHz (OC-3)
215
fs rms
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
215
fs rms
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
222
225
225
fs rms
fs rms
fs rms
Interferer(s)
Interferer(s)
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
Interferer(s)
Interferer(s)
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
Interferer(s)
Interferer(s)
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
Interferer(s)
Interferer(s)
264
fs rms
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
LVDS (OUT3) = 100 MHz
Divide Ratio = 4
CLK1 = 400 MHz
319
fs rms
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
LVDS (OUT4) = 100 MHz
Divide Ratio = 4
CLK1 = 400 MHz
395
fs rms
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
LVDS (OUT3) = 100 MHz
Divide Ratio = 4
LVDS (OUT4) = 50 MHz
All LVPECL = 50 MHz
Interferer(s)
Interferer(s)
Rev. B | Page 10 of 48
AD9512
Parameter
CLK1 = 400 MHz
LVDS (OUT4) = 100 MHz
Divide Ratio = 4
LVDS (OUT3) = 50 MHz
All LVPECL = 50 MHz
CLK1 = 400 MHz
LVDS (OUT3) = 100 MHz
Divide Ratio = 4
CMOS (OUT4) = 50 MHz (B Outputs Off)
All LVPECL = 50 MHz
CLK1 = 400 MHz
LVDS (OUT4) = 100 MHz
Divide Ratio = 4
CMOS (OUT3) = 50 MHz (B Outputs Off)
All LVPECL = 50 MHz
CLK1 = 400 MHz
LVDS (OUT3) = 100 MHz
Divide Ratio = 4
CMOS (OUT4) = 50 MHz (B Outputs On)
All LVPECL = 50 MHz
CLK1 = 400 MHz
LVDS (OUT4) = 100 MHz
Divide Ratio = 4
CMOS (OUT3) = 50 MHz (B Outputs On)
All LVPECL = 50 MHz
CMOS OUTPUT ADDITIVE TIME JITTER
CLK1 = 400 MHz
Both CMOS (OUT3, OUT4) = 100 MHz (B Output On)
Divide Ratio = 4
CLK1 = 400 MHz
CMOS (OUT3) = 100 MHz (B Output On)
Divide Ratio = 4
All LVPECL = 50 MHz
LVDS (OUT4) = 50 MHz
CLK1 = 400 MHz
CMOS (OUT3) = 100 MHz (B Output On)
Divide Ratio = 4
All LVPECL = 50 MHz
CMOS (OUT4) = 50 MHz (B Output Off)
CLK1 = 400 MHz
Min
Typ
395
Max
367
367
548
548
Unit
fs rms
fs rms
fs rms
fs rms
fs rms
Test Conditions/Comments
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
Interferer(s)
Interferer(s)
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
Interferer(s)
Interferer(s)
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
Interferer(s)
Interferer(s)
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
Interferer(s)
Interferer(s)
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
Interferer(s)
Interferer(s)
275
fs rms
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
400
fs rms
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
374
555
CMOS (OUT3) = 100 MHz (B Output On)
Divide Ratio = 4
All LVPECL = 50 MHz
CMOS (OUT4) = 50 MHz (B Output On)
fs rms
fs rms
Interferer(s)
Interferer(s)
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
Interferer(s)
Interferer(s)
Calculated from SNR of ADC method;
FC = 100 MHz with AIN = 170 MHz
Interferer(s)
Interferer(s)
Rev. B | Page 11 of 48
AD9512
Parameter
DELAY BLOCK ADDITIVE TIME JITTER1
100 MHz Output
Delay FS = 1 ns (1600 μA, 1C) Fine Adj. 00000
Delay FS = 1 ns (1600 μA, 1C) Fine Adj. 11111
Delay FS = 2 ns (800 μA, 1C) Fine Adj. 00000
Delay FS = 2 ns (800 μA, 1C) Fine Adj. 11111
Delay FS = 3 ns (800 μA, 4C) Fine Adj. 00000
Delay FS = 3 ns (800 μA, 4C) Fine Adj. 11111
Delay FS = 4 ns (400 μA, 4C) Fine Adj. 00000
Delay FS = 4 ns (400 μA, 4C) Fine Adj. 11111
Delay FS = 5 ns (200 μA, 1C) Fine Adj. 00000
Delay FS = 5 ns (200 μA, 1C) Fine Adj. 11111
Delay FS = 11 ns (200 μA, 4C) Fine Adj. 00000
Delay FS = 11 ns (200 μA, 4C) Fine Adj. 00100
1
Min
Typ
Max
0.61
0.73
0.71
1.2
0.86
1.8
1.2
2.1
1.3
2.7
2.0
2.8
Unit
Test Conditions/Comments
Incremental additive jitter1
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
This value is incremental. That is, it is in addition to the jitter of the LVDS or CMOS output without the delay. To estimate the total jitter, the LVDS or CMOS output jitter
should be added to this value using the root sum of the squares (RSS) method.
SERIAL CONTROL PORT
Table 6.
Parameter
CSB, SCLK (INPUTS)
Min
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
SDIO (WHEN INPUT)
Input Logic 1 Voltage
Input Logic 0 Voltage
Input Logic 1 Current
Input Logic 0 Current
Input Capacitance
SDIO, SDO (OUTPUTS)
Output Logic 1 Voltage
Output Logic 0 Voltage
TIMING
Clock Rate (SCLK, 1/tSCLK)
Pulse Width High, tPWH
Pulse Width Low, tPWL
SDIO to SCLK Setup, tDS
SCLK to SDIO Hold, tDH
SCLK to Valid SDIO and SDO, tDV
CSB to SCLK Setup and Hold, tS, tH
CSB Minimum Pulse Width High, tPWH
2.0
Typ
Max
0.8
110
1
2
2.0
0.8
10
10
2
2.7
0.4
25
16
16
2
1
6
2
3
Rev. B | Page 12 of 48
Unit
V
V
μA
μA
pF
V
V
nA
nA
pF
V
V
MHz
ns
ns
ns
ns
ns
ns
ns
Test Conditions/Comments
CSB and SCLK have 30 kΩ
internal pull-down resistors
AD9512
FUNCTION PIN
Table 7.
Parameter
INPUT CHARACTERISTICS
Min
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Capacitance
RESET TIMING
Pulse Width Low
SYNC TIMING
Pulse Width Low
2.0
Typ
Max
0.8
110
1
2
Unit
Test Conditions/Comments
The FUNCTION pin has a 30 kΩ internal pull-down resistor.
This pin should normally be held high. Do not leave NC.
V
V
μA
μA
pF
50
ns
1.5
High speed clock cycles
High speed clock is CLK1 or CLK2, whichever is being used
for distribution.
SYNC STATUS PIN
Table 8.
Parameter
OUTPUT CHARACTERISTICS
Output Voltage High (VOH)
Output Voltage Low (VOL)
Min
Typ
Max
Unit
0.4
V
V
2.7
Test Conditions/Comments
Rev. B | Page 13 of 48
AD9512
POWER
Table 9.
Parameter
POWER-UP DEFAULT MODE POWER DISSIPATION
Min
Typ
550
POWER DISSIPATION
Max
600
Unit
mW
800
mW
850
mW
Full Sleep Power-Down
35
60
mW
Power-Down (PDB)
60
80
mW
POWER DELTA
CLK1, CLK2 Power-Down
Divider, DIV 2 − 32 to Bypass
LVPECL Output Power-Down (PD2, PD3)
10
23
50
15
27
65
25
33
75
mW
mW
mW
LVDS Output Power-Down
CMOS Output Power-Down (Static)
CMOS Output Power-Down (Dynamic)
80
56
115
92
70
150
110
85
190
mW
mW
mW
CMOS Output Power-Down (Dynamic)
125
165
210
mW
Delay Block Bypass
20
24
60
mW
Rev. B | Page 14 of 48
Test Conditions/Comments
Power-up default state; does not include power
dissipated in output load resistors. No clock.
All outputs on. Three LVPECL outputs @ 800 MHz,
two CMOS out @ 62 MHz (5 pF load). Does not include
power dissipated in external resistors.
All outputs on. Three LVPECL outputs @ 800 MHz,
two CMOS out @ 125 MHz (5 pF load). Does not include
power dissipated in external resistors.
Maximum sleep is entered by setting 0Ah = 01b
and 58h = 1b. This powers off all band gap
references. Does not include power dissipated in
terminations.
Set FUNCTION pin for PDB operation by setting
58h = 11b. Pull PDB low. Does not include
power dissipated in terminations.
For each divider.
For each output. Does not include dissipation
in termination (PD2 only).
For each output.
For each output. Static (no clock).
For each CMOS output, single-ended. Clocking at
62 MHz with 5 pF load.
For each CMOS output, single-ended. Clocking at
125 MHz with 5 pF load.
Vs. delay block operation at 1 ns fs with maximum
delay; output clocking at 25 MHz.
AD9512
TIMING DIAGRAMS
tCLK1
CLK1
DIFFERENTIAL
tPECL
80%
LVDS
tLVDS
tCMOS
tRL
tFL
05287-065
05287-002
20%
Figure 4. LVDS Timing, Differential
Figure 2. CLK1/CLK1B to Clock Output Timing, DIV = 1 Mode
SINGLE-ENDED
DIFFERENTIAL
80%
80%
CMOS
3pF LOAD
LVPECL
tFP
05287-064
tRP
tRC
tFC
Figure 5. CMOS Timing, Single-Ended, 3 pF Load
Figure 3. LVPECL Timing, Differential
Rev. B | Page 15 of 48
05287-066
20%
20%
AD9512
ABSOLUTE MAXIMUM RATINGS
Table 10.
Parameter or Pin
VS
DSYNC/DSYNCB
RSET
CLK1, CLK1B, CLK2, CLK2B
CLK1
CLK2
SCLK, SDIO, SDO, CSB
OUT0, OUT1,
OUT2, OUT3, OUT4
FUNCTION
SYNC STATUS
Junction Temperature
Storage Temperature
Lead Temperature (10 sec)
With
Respect
to
GND
GND
GND
GND
CLK1B
CLK2B
GND
GND
Min
−0.3
−0.3
−0.3
−0.3
−1.2
−1.2
−0.3
−0.3
Max
+3.6
VS + 0.3
VS + 0.3
VS + 0.3
+1.2
+1.2
VS + 0.3
VS + 0.3
Unit
V
V
V
V
V
V
V
V
GND
GND
−0.3
−0.3
VS + 0.3
VS + 0.3
150
+150
300
V
V
°C
°C
°C
−65
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to
absolute maximum ratings for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
Thermal Resistance1
48-Lead LFCSP
θJA = 28.5°C/W
1
Thermal impedance measurements were taken on a 4-layer board in still air,
in accordance with EIA/JESD51-7.
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. B | Page 16 of 48
AD9512
48
47
46
45
44
43
42
41
40
39
38
37
VS
VS
GND
RSET
VS
GND
OUT0
OUT0B
VS
VS
GND
GND
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD9512
TOP VIEW
(Not to Scale)
36
35
34
33
32
31
30
29
28
27
26
25
VS
OUT3
OUT3B
VS
VS
OUT4
OUT4B
VS
VS
OUT1
OUT1B
VS
NOTES
1. DNC = DO NO CONNECT
2. THE EXPOSED PADDLE ON THIS PACKAGE IS AN ELECTRICAL CONNECTION
AS WELL AS A THERMAL ENHANCEMENT. FOR THE DEVICE TO FUNCTION
PROPERLY, THE PADDLE MUST BE ATTACHED TO GROUND, GND.
05287-003
STATUS
SCLK
SDIO
SDO
CSB
VS
GND
OUT2B
OUT2
VS
VS
GND
13
14
15
16
17
18
19
20
21
22
23
24
DSYNC 1
DSYNCB 2
VS 3
VS 4
DNC 5
VS 6
CLK2 7
CLK2B 8
VS 9
CLK1 10
CLK1B 11
FUNCTION 12
Figure 6. 48-Lead LFCSP Pin Configuration
Note that the exposed paddle on this package is an electrical connection as well as a thermal enhancement. For the device to
function properly, the paddle must be attached to ground, GND.
Rev. B | Page 17 of 48
AD9512
Table 11. Pin Function Descriptions
Pin No.
1
2
3, 4, 6, 9, 18,
22, 23, 25, 28,
29, 32, 33, 36,
39, 40, 44, 47, 48
5
7
8
10
11
12
13
14
15
16
17
19, 24, 37,
38, 43, 46
20
21
26
27
30
31
34
35
41
42
45
Mnemonic
DSYNC
DSYNCB
VS
Description
Detect Sync. Used for multichip synchronization.
Detect Sync Complement. Used for multichip synchronization.
Power Supply (3.3 V).
DNC
CLK2
CLK2B
CLK1
CLK1B
FUNCTION
STATUS
SCLK
SDIO
SDO
CSB
GND
Do Not Connect.
Clock Input.
Complementary Clock Input. Used in conjunction with CLK2.
Clock Input.
Complementary Clock Input. Used in conjunction with CLK1.
Multipurpose Input. Can be programmed as a reset (RESETB), sync (SYNCB), or power-down (PDB) pin.
Output Used to Monitor the Status of Multichip Synchronization.
Serial Data Clock.
Serial Data I/O.
Serial Data Output.
Serial Port Chip Select.
Ground.
OUT2B
OUT2
OUT1B
OUT1
OUT4B
OUT4
OUT3B
OUT3
OUT0B
OUT0
RSET
Complementary LVPECL Output.
LVPECL Output.
Complementary LVPECL Output.
LVPECL Output.
Complementary LVDS/Inverted CMOS Output. OUT4 includes a delay block.
LVDS/CMOS Output. OUT4 includes a delay block.
Complementary LVDS/Inverted CMOS Output.
LVDS/CMOS Output.
Complementary LVPECL Output.
LVPECL Output.
Current Set Resistor to Ground. Nominal value = 4.12 kΩ.
Note that the exposed paddle on this package is an electrical connection as well as a thermal enhancement. For the device to
function properly, the paddle must be attached to ground, GND.
Rev. B | Page 18 of 48
AD9512
TERMINOLOGY
Phase Jitter and Phase Noise
An ideal sine wave can be thought of as having a continuous
and even progression of phase with time from 0 degrees to
360 degrees for each cycle. Actual signals, however, display a
certain amount of variation from ideal phase progression over
time. This phenomenon is called phase jitter. Although many
causes can contribute to phase jitter, one major cause is
random noise, which is characterized statistically as being
Gaussian (normal) in distribution.
This phase jitter leads to a spreading out of the energy of the
sine wave in the frequency domain, producing a continuous
power spectrum. This power spectrum is usually reported as a
series of values whose units are dBc/Hz at a given offset in
frequency from the sine wave (carrier). The value is a ratio
(expressed in dB) of the power contained within a 1 Hz
bandwidth with respect to the power at the carrier frequency.
For each measurement, the offset from the carrier frequency is
also given.
It is meaningful to integrate the total power contained within
some interval of offset frequencies (for example, 10 kHz to
10 MHz). This is called the integrated phase noise over that
frequency offset interval and can be readily related to the time
jitter due to the phase noise within that offset frequency
interval.
Phase noise has a detrimental effect on the performance of
ADCs, DACs, and RF mixers. It lowers the achievable dynamic
range of the converters and mixers, although they are affected
in somewhat different ways.
Time Jitter
Phase noise is a frequency domain phenomenon. In the time
domain, the same effect is exhibited as time jitter. When
observing a sine wave, the time of successive zero crossings is
seen to vary. In a square wave, the time jitter is seen as a
displacement of the edges from their ideal (regular) times of
occurrence. In both cases, the variations in timing from the
ideal are the time jitter. Since these variations are random in
nature, the time jitter is specified in units of seconds root mean
square (rms) or 1 sigma of the Gaussian distribution.
Time jitter that occurs on a sampling clock for a DAC or an
ADC decreases the SNR and dynamic range of the converter.
A sampling clock with the lowest possible jitter provides the
highest performance from a given converter.
Additive Phase Noise
It is the amount of phase noise that is attributable to the device
or subsystem being measured. The phase noise of any external
oscillators or clock sources has been subtracted. This makes it
possible to predict the degree to which the device impacts the
total system phase noise when used in conjunction with the
various oscillators and clock sources, each of which contribute
their own phase noise to the total. In many cases, the phase
noise of one element dominates the system phase noise.
Additive Time Jitter
It is the amount of time jitter that is attributable to the device
or subsystem being measured. The time jitter of any external
oscillators or clock sources has been subtracted. This makes it
possible to predict the degree to which the device will impact
the total system time jitter when used in conjunction with the
various oscillators and clock sources, each of which contribute
their own time jitter to the total. In many cases, the time jitter
of the external oscillators and clock sources dominates the
system time jitter.
Rev. B | Page 19 of 48
AD9512
TYPICAL PERFORMANCE CHARACTERISTICS
0.6
0.7
DEFAULT – 3 LVPECL + 2 LVDS (DIV ON)
POWER (W)
0.6
POWER (W)
0.5
3 LVPECL + 2 LVDS (DIV BYPASSED)
0.4
0.5
0
400
OUTPUT FREQUENCY (MHz)
800
0.4
05287-081
2 LVDS (DIV ON)
05287-080
3 LVPECL (DIV ON)
0
Figure 7. Power vs. Frequency—LVPECL, LVDS
40
60
80
OUTPUT FREQUENCY (MHz)
100
120
Figure 9. Power vs. Frequency—LVPECL, CMOS
CLK1 (EVAL BOARD)
3GHz
20
CLK2 (EVAL BOARD)
5MHz
5MHz
05287-044
3GHz
05287-043
0.3
3 LVPECL + 2 CMOS (DIV ON)
Figure 10. CLK2 Smith Chart (Evaluation Board)
Figure 8. CLK1 Smith Chart (Evaluation Board)
Rev. B | Page 20 of 48
AD9512
1.8
DIFFERENTIAL SWING (V p-p)
1.7
1.6
1.5
1.4
VERT 500mV/DIV
05287-056
05287-053
1.3
1.2
100
HORIZ 500ps/DIV
600
1100
1600
OUTPUT FREQUENCY (MHz)
Figure 11. LVPECL Differential Output @ 800 MHz
Figure 14. LVPECL Differential Output Swing vs. Frequency
VERT 100mV/DIV
700
650
600
550
500
100
HORIZ 500ps/DIV
05287-050
05287-054
DIFFERENTIAL SWING (mV p-p)
750
300
500
700
900
OUTPUT FREQUENCY (MHz)
Figure 12. LVDS Differential Output @ 800 MHz
Figure 15. LVDS Differential Output Swing vs. Frequency
3.5
2pF
3.0
OUTPUT (VPK)
2.5
10pF
2.0
1.5
1.0
20pF
VERT 500mV/DIV
0
HORIZ 1ns/DIV
Figure 13. CMOS Single-Ended Output @ 250 MHz with 10 pF Load
05287-047
05287-055
0.5
0
100
200
300
400
500
600
OUTPUT FREQUENCY (MHz)
Figure 16. CMOS Single-Ended Output Swing vs. Frequency and Load
Rev. B | Page 21 of 48
–110
–120
–120
–130
–130
–140
–140
–150
–150
–160
–160
–170
10
100
1k
10k
100k
1M
05287-052
L(f) (dBc/Hz)
–110
05287-051
L(f) (dBc/Hz)
AD9512
–170
10
10M
100
1k
OFFSET (Hz)
–80
–90
–90
–100
–100
–110
–110
–120
–130
–130
–140
–150
–150
–160
–160
10k
100k
1M
–170
10
10M
100
1k
OFFSET (Hz)
–110
–120
–120
–130
–140
10M
–130
–140
–150
–150
–160
–160
10k
1M
100k
1M
10M
–170
10
OFFSET (Hz)
05287-046
L(f) (dBc/Hz)
–110
05287-045
L(f) (dBc/Hz)
–100
1k
100k
Figure 21. Additive Phase Noise—LVDS DIV2, 122.88 MHz
–100
100
10k
OFFSET (Hz)
Figure 18. Additive Phase Noise—LVDS DIV1, 245.76 MHz
–170
10
10M
–120
–140
1k
1M
05287-049
L(f) (dBc/Hz)
–80
100
100k
Figure 20. Additive Phase Noise—LVPECL DIV1, 622.08 MHz
05287-048
L(f) (dBc/Hz)
Figure 17. Additive Phase Noise—LVPECL DIV1, 245.76 MHz
Distribution Section Only
–170
10
10k
OFFSET (Hz)
100
1k
10k
100k
OFFSET (Hz)
1M
Figure 22. Additive Phase Noise—CMOS DIV4, 61.44 MHz
Figure 19. Additive Phase Noise—CMOS DIV1, 245.76 MHz
Rev. B | Page 22 of 48
10M
AD9512
VS
FUNCTION
DSYNC
DSYNCB
SYNCB,
RESETB
PDB
DETECT
SYNC
GND
RSET
VREF
AD9512
PROGRAMMABLE
DIVIDERS AND
PHASE ADJUST
SYNC
STATUS
SYNC
STATUS
LVPECL
OUT0
/1, /2, /3... /31, /32
OUT0B
LVPECL
OUT1
/1, /2, /3... /31, /32
OUT1B
CLK1
LVPECL
CLK1B
OUT2
/1, /2, /3... /31, /32
CLK2
OUT2B
LVDS/CMOS
CLK2B
OUT3
/1, /2, /3... /31, /32
OUT3B
SCLK
SDO
CSB
SERIAL
CONTROL
PORT
LVDS/CMOS
/1, /2, /3... /31, /32
T
DELAY
ADJUST
Figure 23. Functional Block Diagram Showing Maximum Frequencies
Rev. B | Page 23 of 48
OUT4
OUT4B
05287-090
SDIO
AD9512
FUNCTIONAL DESCRIPTION
OVERALL
SYNCB: 58h = 01b
Figure 23 shows a block diagram of the AD9512. The AD9512
accepts inputs on either of two clock inputs (CLK1 or CLK2).
This clock can be divided by any integer value from 1 to 32.
The duty cycle and relative phase of the outputs can be selected.
There are three LVPECL outputs (OUT0, OUT1, OUT2) and
two outputs that can be either LVDS or CMOS level outputs
(OUT3, OUT4). OUT4 can also make use of a variable
delay block.
The FUNCTION pin can be used to cause a synchronization
or alignment of phase among the various clock outputs.
The synchronization applies only to clock outputs that:
The AD9512 provides clock distribution function only; there is
no clock clean-up. The jitter of the input clock signal is passed
along directly to the distribution section and can dominate at
the clock outputs.
See Figure 24 for the equivalent circuit of CLK1 and CLK2.
are not powered down
the divider is not masked (no sync = 0)
are not bypassed (bypass = 0)
SYNCB is level and rising edge sensitive. When SYNCB is low,
the set of affected outputs are held in a predetermined state,
defined by each divider’s start high bit. On a rising edge, the
dividers begin after a predefined number of fast clock cycles
(fast clock is the selected clock input, CLK1 or CLK2) as
determined by the values in the divider’s phase offset bits.
The SYNCB application of the FUNCTION pin is always
active, regardless of whether the pin is also assigned to perform
reset or power-down. When the SYNCB function is selected,
the FUNCTION pin does not act as either RESETB or PDB.
CLOCK INPUT
STAGE
VS
CLK
PDB: 58h = 11b
CLKB
2.5k
The FUNCTION pin can also be programmed to work as an
asynchronous full power-down, PDB. Even in this full powerdown mode, there is still some residual VS current because
some on-chip references continue to operate. In PDB mode, the
FUNCTION pin is active low. The chip remains in a powerdown state until PDB is returned to logic high. The chip returns
to the settings programmed prior to the power-down.
2.5k
5k
05287-016
5k
Figure 24. CLK1, CLK2 Equivalent Input Circuit
See the Chip Power-Down or Sleep Mode—PDB section for more
details on what occurs during a PDB initiated power-down.
FUNCTION PIN
The FUNCTION pin (Pin 12) has three functions that are
selected by the value in Register 58h. There is an internal
30 kΩ pull-down resistor on this pin.
RESETB: 58h = 00b (Default)
In its default mode, the FUNCTION pin acts as RESETB, which
generates an asynchronous reset or hard reset when pulled low.
The resulting reset writes the default values into the serial
control port buffer registers as well as loading them into the
chip control registers. The AD9512 immediately resumes
operation according to the default values. When the pin is
taken high again, an asynchronous sync is issued (see the
SYNCB: 58h = 01b section).
DSYNC AND DSYNCB PINS
The DSYNC and DSYNCB pins (Pin 1 and Pin 2) are used
when the AD9512 is used in a multichip synchronized
configuration (see the Multichip Synchronization section).
CLOCK INPUTS
Two clock inputs (CLK1, CLK2) are available for use on the
AD9512. CLK1 and CLK2 can accept inputs up to 1600 MHz.
See Figure 24 for the CLK1 and CLK2 equivalent input circuit.
The clock inputs are fully differential and self-biased. The
signal should be ac-coupled using capacitors. If a single-ended
input must be used, this can be accommodated by ac coupling
to one side of the differential input only. The other side of the
input should be bypassed to a quiet ac ground by a capacitor.
The unselected clock input (either CLK1 or CLK2) should be
powered down to eliminate any possibility of unwanted
crosstalk between the selected clock input and the unselected
clock input.
Rev. B | Page 24 of 48
AD9512
DIVIDERS
Example 2:
Each of the five clock outputs of the AD9512 has its own
divider. The divider can be bypassed to get an output at the
same frequency as the input (1×). When a divider is bypassed,
it is powered down to save power.
All integer divide ratios from 1 to 32 may be selected. A divide
ratio of 1 is selected by bypassing the divider.
Each divider can be configured for divide ratio, phase, and duty
cycle. The phase and duty cycle values that can be selected
depend on the divide ratio that is chosen.
Set Divide Ratio = 8
high_cycles = 3
low_cycles = 3
Divide Ratio = (3 + 1) + (3 + 1) = 8
Note that a Divide Ratio of 8 may also be obtained by setting:
high_cycles = 2
Setting the Divide Ratio
low_cycles = 4
The divide ratio is determined by the values written via the SCP
to the registers that control each individual output, OUT0 to
OUT4. These are the even numbered registers beginning at
4Ah and going through 52h. Each of these registers is divided
into bits that control the number of clock cycles the divider
output stays high (high_cycles ) and the number of clock
cycles the divider output stays low (low_cycles ). Each
value is 4 bits and has the range of 0 to 15.
Divide Ratio = (2 + 1) + (4 + 1) = 8
The divide ratio is set by
Although the second set of settings produces the same divide
ratio, the resulting duty cycle is not the same.
Setting the Duty Cycle
The duty cycle and the divide ratio are related. Different divide
ratios have different duty cycle options. For example, if Divide
Ratio = 2, the only duty cycle possible is 50%. If the Divide
Ratio = 4, the duty cycle can be 25%, 50%, or 75%.
The duty cycle is set by
Divide Ratio = (high_cycles + 1) + (low_cycles + 1)
Example 1:
Duty Cycle = (high_cycles + 1)/[(high_cycles + 1) + (low_cycles + 1)]
Set the Divide Ratio = 2
See Table 12 for the values of the available duty cycles for each
divide ratio.
high_cycles = 0
low_cycles = 0
Divide Ratio = (0 + 1) + (0 + 1) = 2
Table 12. Duty Cycle and Divide Ratio
4Ah to 52h
Divide Ratio
2
3
3
4
4
4
5
5
5
5
6
6
6
6
6
Duty Cycle (%)
50
67
33
50
75
25
60
40
80
20
50
67
33
83
17
LO
0
0
1
1
0
2
1
2
0
3
2
1
3
0
4
4Ah to 52h
HI
0
1
0
1
2
0
2
1
3
0
2
3
1
4
0
Divide Ratio
7
7
7
7
7
7
8
8
8
8
8
8
8
9
9
Rev. B | Page 25 of 48
Duty Cycle (%)
57
43
71
29
86
14
50
63
38
75
25
88
13
56
44
LO
2
3
1
4
0
5
3
2
4
1
5
0
6
3
4
HI
3
2
4
1
5
0
3
4
2
5
1
6
0
4
3
AD9512
4Ah to 52h
Divide Ratio
9
9
9
9
9
9
10
10
10
10
10
10
10
10
10
11
11
11
11
11
11
11
11
11
11
12
12
12
12
12
12
12
12
12
12
12
13
13
13
13
13
13
13
13
13
13
13
13
14
14
14
Duty Cycle (%)
67
33
78
22
89
11
50
60
40
70
30
80
20
90
10
55
45
64
36
73
27
82
18
91
9
50
58
42
67
33
75
25
83
17
92
8
54
46
62
38
69
31
77
23
85
15
92
8
50
57
43
LO
2
5
1
6
0
7
4
3
5
2
6
1
7
0
8
4
5
3
6
2
7
1
8
0
9
5
4
6
3
7
2
8
1
9
0
A
5
6
4
7
3
8
2
9
1
A
0
B
6
5
7
4Ah to 52h
HI
5
2
6
1
7
0
4
5
3
6
2
7
1
8
0
5
4
6
3
7
2
8
1
9
0
5
6
4
7
3
8
2
9
1
A
0
6
5
7
4
8
3
9
2
A
1
B
0
6
7
5
Divide Ratio
14
14
14
14
14
14
14
14
14
14
15
15
15
15
15
15
15
15
15
15
15
15
15
15
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
17
17
17
17
17
17
17
17
17
17
17
17
Rev. B | Page 26 of 48
Duty Cycle (%)
64
36
71
29
79
21
86
14
93
7
53
47
60
40
67
33
73
27
80
20
87
13
93
7
50
56
44
63
38
69
31
75
25
81
19
88
13
94
6
53
47
59
41
65
35
71
29
76
24
82
18
LO
4
8
3
9
2
A
1
B
0
C
6
7
5
8
4
9
3
A
2
B
1
C
0
D
7
6
8
5
9
4
A
3
B
2
C
1
D
0
E
7
8
6
9
5
A
4
B
3
C
2
D
HI
8
4
9
3
A
2
B
1
C
0
7
6
8
5
9
4
A
3
B
2
C
1
D
0
7
8
6
9
5
A
4
B
3
C
2
D
1
E
0
8
7
9
6
A
5
B
4
C
3
D
2
AD9512
4Ah to 52h
Divide Ratio
17
17
17
17
18
18
18
18
18
18
18
18
18
18
18
18
18
18
18
19
19
19
19
19
19
19
19
19
19
19
19
19
19
20
20
20
20
20
20
20
20
20
20
20
20
20
21
21
21
21
21
Duty Cycle (%)
88
12
94
6
50
56
44
61
39
67
33
72
28
78
22
83
17
89
11
53
47
58
42
63
37
68
32
74
26
79
21
84
16
50
55
45
60
40
65
35
70
30
75
25
80
20
52
48
57
43
62
LO
1
E
0
F
8
7
9
6
A
5
B
4
C
3
D
2
E
1
F
8
9
7
A
6
B
5
C
4
D
3
E
2
F
9
8
A
7
B
6
C
5
D
4
E
3
F
9
A
8
B
7
4Ah to 52h
HI
E
1
F
0
8
9
7
A
6
B
5
C
4
D
3
E
2
F
1
9
8
A
7
B
6
C
5
D
4
E
3
F
2
9
A
8
B
7
C
6
D
5
E
4
F
3
A
9
B
8
C
Divide Ratio
21
21
21
21
21
21
21
22
22
22
22
22
22
22
22
22
22
22
23
23
23
23
23
23
23
23
23
23
24
24
24
24
24
24
24
24
24
25
25
25
25
25
25
25
25
26
26
26
26
26
26
Rev. B | Page 27 of 48
Duty Cycle (%)
38
67
33
71
29
76
24
50
55
45
59
41
64
36
68
32
73
27
52
48
57
43
61
39
65
35
70
30
50
54
46
58
42
63
38
67
33
52
48
56
44
60
40
64
36
50
54
46
58
42
62
LO
C
6
D
5
E
4
F
A
9
B
8
C
7
D
6
E
5
F
A
B
9
C
8
D
7
E
6
F
B
A
C
9
D
8
E
7
F
B
C
A
D
9
E
8
F
C
B
D
A
E
9
HI
7
D
6
E
5
F
4
A
B
9
C
8
D
7
E
6
F
5
B
A
C
9
D
8
E
7
F
6
B
C
A
D
9
E
8
F
7
C
B
D
A
E
9
F
8
C
D
B
E
A
F
AD9512
4Ah to 52h
Divide Ratio
26
27
27
27
27
27
27
28
28
28
28
28
Duty Cycle (%)
38
52
48
56
44
59
41
50
54
46
57
43
LO
F
C
D
B
E
A
F
D
C
E
B
F
4Ah to 52h
HI
9
D
C
E
B
F
A
D
E
C
F
B
Divide Ratio
29
29
29
29
30
30
30
31
31
32
Rev. B | Page 28 of 48
Duty Cycle (%)
52
48
55
45
50
53
47
52
48
50
LO
D
E
C
F
E
D
F
E
F
F
HI
E
D
F
C
E
F
D
F
E
F
AD9512
Divider Phase Offset
The phase of each output may be selected, depending on the
divide ratio chosen. This is selected by writing the appropriate
values to the registers, which set the phase and start high/low
bit for each output. These are the odd numbered registers from
4Bh to 53h. Each divider has a 4-bit phase offset and a
start high or low bit .
Following a sync pulse, the phase offset word determines how
many fast clock (CLK1 or CLK2) cycles to wait before initiating
a clock output edge. The Start H/L bit determines if the divider
output starts low or high. By giving each divider a different
phase offset, output-to-output delays can be set in increments
of the fast clock period, tCLK.
Figure 25 shows three dividers, each set for DIV = 4, 50% duty
cycle. By incrementing the phase offset from 0 to 2, each output
is offset from the initial edge by a multiple of tCLK.
0
1
2
3
4
5
6
7
8
9
10
11 12
13
14
15
CLOCK INPUT
CLK
tCLK
DIVIDER OUTPUTS
DIV = 4, DUTY = 50%
START = 0,
PHASE = 0
START = 0,
PHASE = 1
tCLK
2 tCLK
05287-091
START = 0,
PHASE = 2
Figure 25. Phase Offset—All Dividers Set for DIV = 4, Phase Set from 0 to 2
For example:
CLK1 = 491.52 MHz
tCLK1 = 1/491.52 = 2.0345 ns
For DIV = 4
Phase Offset 0 = 0 ns
In general, by combining the 4-bit phase offset and the Start
H/L bit, there are 32 possible phase offset states (see Table 13).
Table 13. Phase Offset—Start H/L Bit
Phase Offset
(Fast Clock
Rising Edges)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
4Bh to 53h
Phase Offset
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Start H/L
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
The resolution of the phase offset is set by the fast clock period
(tCLK) at CLK1 or CLK2. As a result, every divide ratio does not
have 32 unique phase offsets available. For any divide ratio, the
number of unique phase offsets is numerically equal to the
divide ratio (see Table 13):
Phase Offset 1 = 2.0345 ns
Phase Offset 2 = 4.069 ns
The three outputs may also be described as:
OUT1 = 0°
DIV = 4
OUT2 = 90°
Unique Phase Offsets Are Phase = 0, 1, 2, 3
OUT3 = 180°
DIV= 7
Setting the phase offset to Phase = 4 results in the same relative
phase as the first channel, Phase = 0° or 360°.
Unique Phase Offsets Are Phase = 0, 1, 2, 3, 4, 5, 6
Rev. B | Page 29 of 48
AD9512
DIV = 18
Unique Phase Offsets Are Phase = 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10,
11, 12, 13, 14, 15, 16, 17
Phase offsets may be related to degrees by calculating the phase
step for a particular divide ratio:
Phase Step = 360°/(Divide Ratio) = 360°/DIV
This path adds some jitter greater than that specified for the
nondelay outputs. This means that the delay function should be
used primarily for clocking digital chips, such as FPGA, ASIC,
DUC, and DDC, rather than for data converters. The jitter is
higher for long full scales (~10 ns). This is because the delay
block uses a ramp and trip points to create the variable delay. A
longer ramp means more noise might be introduced.
Calculating the Delay
Using some of the same examples,
The following values and equations are used to calculate the
delay of the delay block.
DIV = 4
Phase Step = 360°/4 = 90°
Value of Ramp Current Control Bits (Register 35h or Register
39h ) = Iramp_bits
Unique Phase Offsets in Degrees Are Phase = 0°, 90°,
180°, 270°
IRAMP (μA) = 200 × (Iramp_bits + 1)
No. of Caps = No. of 0s + 1 in Ramp Control Capacitor
(Register 35h or Register 39h ), that is, 101 = 1 + 1 = 2;
110 = 2; 100 = 2 + 1 = 3; 001 = 2 + 1 = 3; 111 = 0 + 1 = 1)
DIV = 7
Phase Step = 360°/7 = 51.43°
Delay_Range (ns) = 200 × [(No. of Caps + 3)/(IRAMP)] × 1.3286
Unique Phase Offsets in Degrees Are Phase = 0°, 51.43°,
102.86°, 154.29°, 205.71°, 257.15°, 308.57°
No.of Caps 1
6
Offset ns 0.34 1600 I RAMP 10 4
I RAMP
DELAY BLOCK
OUT4 (LVDS/CMOS) includes an analog delay element that
can be programmed (Register 34h to Register 36h) to give
variable time delays (ΔT) in the clock signal passing through
that output.
Delay_Full_Scale (ns) = Delay_Range + Offset
Fine_Adj = Value of Delay Fine Adjust (Register 36h or
Register 3Ah ), that is, 11111 = 31
CLOCK INPUT
Delay (ns) = Offset + Delay_Range × Fine_adj × (1/31)
OUT4 ONLY
OUTPUTS
T
LVDS
CMOS
OUTPUT
DRIVER
05287-092
FINE DELAY ADJUST
(32 STEPS)
FULL-SCALE: 1ns TO 10ns
The AD9512 offers three different output level choices:
LVPECL, LVDS, and CMOS. OUT0 to OUT2 are LVPECL
only. OUT3 and OUT4 can be selected as either LVDS or
CMOS. Each output can be enabled or turned off as needed to
save power.
The simplified equivalent circuit of the LVPECL outputs is
shown in Figure 27.
Figure 26. Analog Delay (OUT4)
The amount of delay that can be used is determined by the
frequency of the clock being delayed. The amount of delay can
approach one-half cycle of the clock period. For example, for a
10 MHz clock, the delay can extend to the full 10 ns maximum
of which the delay element is capable. However, for a 100 MHz
clock (with 50% duty cycle), the maximum delay is less than
5 ns (or half of the period).
3.3V
OUT
OUTB
OUT4 allows a full-scale delay in the range 1 ns to 10 ns. The
full-scale delay is selected by choosing a combination of ramp
current and the number of capacitors by writing the
appropriate values into Register 35h. There are 32 fine delay
settings for each full scale, set by Register 36h.
GND
05287-037
MUX
N
SELECT
Figure 27. LVPECL Output Simplified Equivalent Circuit
Rev. B | Page 30 of 48
AD9512
the LVPECL power-down mode is set to , the LVPECL
output is not protected from reverse bias and can be damaged
under certain termination conditions.
3.5mA
Individual Clock Output Power-Down
OUTB
Any of the five clock distribution outputs may be powered
down individually by writing to the appropriate registers via the
SCP. The register map details the individual power-down
settings for each output. The LVDS/CMOS outputs may be
powered down, regardless of their output load configuration.
3.5mA
05287-038
OUT
Figure 28. LVDS Output Simplified Equivalent Circuit
POWER-DOWN MODES
Chip Power-Down or Sleep Mode—PDB
The PDB chip power-down turns off most of the functions and
currents in the AD9512. When the PDB mode is enabled, a chip
power-down is activated by taking the FUNCTION pin to a
logic low level. The chip remains in this power-down state until
PDB is brought back to logic high. When woken up, the
AD9512 returns to the settings programmed into its registers
prior to the power-down, unless the registers are changed by
new programming while the PDB mode is active.
The PDB power-down mode shuts down the currents on the
chip, except the bias current necessary to maintain the LVPECL
outputs in a safe shutdown mode. This is needed to protect the
LVPECL output circuitry from damage that could be caused by
certain termination and load configurations when tri-stated.
Because this is not a complete power-down, it can be called
sleep mode.
The LVPECL outputs have multiple power-down modes
(see Register 3Dh, Register 3Eh, and Register 3Fh in Table 18).
These give some flexibility in dealing with various output
termination conditions. When the mode is set to , the
LVPECL output is protected from reverse bias to 2 VBE + 1 V. If
the mode is set to , the LVPECL output is not protected
from reverse bias and can be damaged under certain
termination conditions. This setting also affects the operation
when the distribution block is powered down with Register
58h = 1b (see the Distribution Power-Down section).
Individual Circuit Block Power-Down
Several of the AD9512 circuit blocks (such as CLK1 and CLK2)
can be powered down individually. This gives flexibility in
configuring the part for power savings when all chip
functionality is not needed.
RESET MODES
The AD9512 has several ways to force the chip into a reset
condition.
When the AD9512 is in a PDB power-down or sleep mode, the
chip is in the following state:
Power-On Reset—Start-Up Conditions when VS is
Applied
All clocks and sync circuits are off.
All dividers are off.
All LVDS/CMOS outputs are off.
A power-on reset (POR) is issued when the VS power supply is
turned on. This initializes the chip to the power-on conditions
that are determined by the default register settings. These are
indicated in the default value column of Table 17.
All LVPECL outputs are in safe off mode.
The serial control port is active, and the chip responds to
commands.
Asynchronous Reset via the FUNCTION Pin
If the AD9512 clock outputs must be synchronized to each
other, a SYNC (see the Single-Chip Synchronization section) is
required when exiting power-down mode.
Distribution Power-Down
The distribution section can be powered down by writing 1 to
Register 58h. This turns off the bias to the distribution
section. If the LVPECL power-down mode is normal operation
, it is possible for a low impedance load on that LVPECL
output to draw significant current during this power-down. If
As mentioned in the FUNCTION Pin section, a hard reset,
RESETB: 58h = 00b (Default), restores the chip to the
default settings.
Soft Reset via the Serial Port
The serial control port allows a soft reset by writing to
Register 00h = 1b. When this bit is set, the chip executes a
soft reset. This restores the default values to the internal
registers, except for Register 00h itself.
This bit is not self-clearing. The bit must be written to
00h = 0b for the operation of the part to continue.
Rev. B | Page 31 of 48
AD9512
slave must provide this same frequency back to the DSYNCB
input of the slave.
SINGLE-CHIP SYNCHRONIZATION
SYNCB—Hardware SYNC
The AD9512 clocks can be synchronized to each other at any
time. The outputs of the clocks are forced into a known state
with respect to each other and then allowed to continue
clocking from that state in synchronicity. Before a
synchronization is done, the FUNCTION Pin must be set as the
input (58h = 01b). Synchronization is done by forcing the
FUNCTION pin low, creating a SYNCB signal and then
releasing it.
See the SYNCB: 58h = 01b section for a more detailed
description of what happens when the SYNCB: 58h = 01b
signal is issued.
Soft SYNC—Register 58h
A soft SYNC can be issued by means of a bit in
Register 58h. This soft SYNC works the same as the
SYNCB, except that the polarity is reversed. A 1 written to this
bit forces the clock outputs into a known state with respect to
each other. When a 0 is subsequently written to this bit, the
clock outputs continue clocking from that state in
synchronicity.
Multichip synchronization is enabled by writing to
Register 58h = 1b on the slave AD9512. When this bit
is set, the STATUS pin becomes the output for the SYNC
signal. A low signal indicates an in-sync condition, and
a high indicates an out-of-sync condition.
Register 58h selects the number of fast clock cycles that are
the maximum separation of the slow clock edges that are
considered synchronized. When 58h = 0b (default), the
slow clock edges must be coincident within 1 to 1.5 high speed
clock cycles. If the coincidence of the slow clock edges is closer
than this amount, the SYNC flag stays low. If the coincidence of
the slow clock edges is greater than this amount, the SYNC flag
is set high. When Register 58h = 1b, the amount of
coincidence required is 0.5 fast clock cycles to 1 fast clock
cycles.
Whenever the SYNC flag is set (high), indicating an out-ofsync condition, a SYNCB signal applied simultaneously at the
FUNCTION pins of both AD9512s brings the slow clocks into
synchronization.
MULTICHIP SYNCHRONIZATION
AD9512
MASTER
Synchronization of two or more AD9512s requires a fast clock
and a slow clock. The fast clock can be up to 1 GHz and can be
the clock driving the master AD9512 CLK1 input or one of the
outputs of the master. The fast clock acts as the input to the
distribution section of the slave AD9512 and is connected to its
CLK1 input.
FUNCTION
(SYNCB)
SYNCB
The slow clock is the clock that is synchronized across the two
chips. This clock must be no faster than one-fourth of the fast
clock, and no greater than 250 MHz. The slow clock is taken
from one of the outputs of the master AD9512 and acts as a
DSYNC input to the slave AD9512. One of the outputs of the
Rev. B | Page 32 of 48
FAST CLOCK
low transition triggers a sync (Default = 0b).
1 = Power-Down the References for the Distribution Section (Default = 0b).
58
SYNC Power-Down
1 = Power-Down the SYNC (Default = 0b).
58
FUNCTION Pin Select
58
59
5A
5A
END
Update Registers
Function
0
0
RESETB (Default)
0
1
SYNCB
1
0
Test Only; Do Not Use
1
1
PDB
Not Used.
Not Used.
1 written to this bit updates all registers and transfers all serial control port register buffer
contents to the control registers on the next rising SCLK edge. This is a self-clearing bit. 0 does
not have to be written to clear it.
Not Used.
Rev. B | Page 42 of 48
AD9512
POWER SUPPLY
The AD9512 requires a 3.3 V ± 5% power supply for VS.
The tables in the Specifications section give the performance
expected from the AD9512 with the power supply voltage
within this range. The absolute maximum range of −0.3 V to
+3.6 V, with respect to GND, must never be exceeded on
the VS pin.
Good engineering practice should be followed in the layout of
power supply traces and ground plane of the PCB. The power
supply should be bypassed on the PCB with adequate
capacitance (>10 μF). The AD9512 should be bypassed with
adequate capacitors (0.1 μF) at all power pins, as close as
possible to the part. The layout of the AD9512 evaluation board
(AD9512/PCB) is a good example.
The AD9512 is a complex part that is programmed for its
desired operating configuration by on-chip registers. These
registers are not maintained over a shutdown of external
power. This means that the registers can lose their programmed
values if VS is lost long enough for the internal voltages to
collapse. Careful bypassing should protect the part from
memory loss under normal conditions. Nonetheless, it is
important that the VS power supply not become intermittent,
or the AD9512 risks losing its programming.
The internal bias currents of the AD9512 are set by the RSET
resistors. This resistor should be as close as possible to the value
given as conditions in the Specifications section
(RSET = 4.12 kΩ). This is a standard 1% resistor value and
should be readily obtainable. The bias currents set by this
resistor determine the logic levels and operating conditions of
the internal blocks of the AD9512. The performance figures
given in the Specifications section assume that this specific
resistor value is used.
POWER MANAGEMENT
The power usage of the AD9512 can be managed to use only
the power required for the functions that are being used.
Unused features and circuitry can be powered down to save
power. The following circuit blocks can be powered down, or
are powered down when not selected (see the Register Map and
Description section):
Any of the dividers are powered down when bypassed—
equivalent to divide-by-one.
The adjustable delay block on OUT4 is powered down
when not selected.
Any output can be powered down. However, LVPECL
outputs have both a safe and an off condition. When the
LVPECL output is terminated, only the safe shutdown
should be used to protect the LVPECL output devices.
This still consumes some power.
The entire distribution section can be powered down when
not needed.
Powering down a functional block does not cause the
programming information for that block (in the registers) to be
lost. This means that blocks can be powered on and off without
otherwise having to reprogram the AD9512. However,
synchronization is lost. A SYNC must be issued to
resynchronize (see the Single-Chip Synchronization section).
The exposed metal paddle on the AD9512 package is an
electrical connection, as well as a thermal enhancement. For
the device to function properly, the paddle must be properly
attached to ground (GND). The PCB acts as a heat sink for the
AD9512; therefore, this GND connection should provide a
good thermal path to a larger dissipation area, such as a ground
plane on the PCB. See the layout of the AD9512 evaluation
board (AD9512/PCB or AD9512-VCO/PCB) for a good
example.
Rev. B | Page 43 of 48
AD9512
APPLICATIONS
USING THE AD9512 OUTPUTS FOR ADC CLOCK
APPLICATIONS
level, termination) should be considered when selecting the
best clocking/converter solution.
Any high speed analog-to-digital converter (ADC) is extremely
sensitive to the quality of the sampling clock provided by the
user. An ADC can be thought of as a sampling mixer; any
noise, distortion, or timing jitter on the clock is combined with
the desired signal at the A/D output. Clock integrity
requirements scale with the analog input frequency and
resolution, with higher analog input frequency applications at
≥14-bit resolution being the most stringent. The theoretical
SNR of an ADC is limited by the ADC resolution and the jitter
on the sampling clock. Considering an ideal ADC of infinite
resolution where the step size and quantization error can be
ignored, the available SNR can be expressed approximately by
CMOS CLOCK DISTRIBUTION
1
SNR 20 log
2πft j
where f is the highest analog frequency being digitized, and tj is
the rms jitter on the sampling clock. Figure 39 shows the
required sampling clock jitter as a function of the analog
frequency and effective number of bits (ENOB).
1
2ftj
tj = 1ps
MICROSTRIP
50pF
14
12
tj = 10ps
GND
ENOB
80
Figure 40. Series Termination of CMOS Output
10
60
tj = 100ps
8
6
tj = 1ns
4
1
3
10
30
05287-024
40
60.4
1.0 INCH
10
16
100
SNR (dB)
CMOS
18
tj = 0.1ps
20
Point-to-point nets should be designed such that a driver has
one receiver only on the net, if possible. This allows for simple
termination schemes and minimizes ringing due to possible
mismatched impedances on the net. Series termination at the
source is generally required to provide transmission line
matching and/or to reduce current transients at the driver. The
value of the resistor is dependent on the board design and
timing requirements (typically 10 Ω to 100 Ω is used). CMOS
outputs are limited in terms of the capacitive load or trace
length that they can drive. Typically, trace lengths less than
3 inches are recommended to preserve signal rise/fall times and
preserve signal integrity.
100
FULL-SCALE SINE WAVE ANALOG INPUT FREQUENCY (MHz)
Figure 39. ENOB and SNR vs. Analog Input Frequency
See Application Notes AN-756 and AN-501 on the ADI website
at www.analog.com.
Termination at the far end of the PCB trace is a second option.
The CMOS outputs of the AD9512 do not supply enough
current to provide a full voltage swing with a low impedance
resistive, far-end termination, as shown in Figure 41. The farend termination network should match the PCB trace
impedance and provide the desired switching point. The
reduced signal swing can still meet receiver input requirements
in some applications. This can be useful when driving long
trace lengths on less critical nets.
Many high performance ADCs feature differential clock inputs
to simplify the task of providing the required low jitter clock on
a noisy PCB. (Distributing a single-ended clock on a noisy PCB
can result in coupled noise on the sample clock. Differential
distribution has inherent common-mode rejection, which can
provide superior clock performance in a noisy environment.)
The AD9512 features both LVPECL and LVDS outputs that
provide differential clock outputs, which enable clock solutions
that maximize converter SNR performance. The input
requirements of the ADC (differential or single-ended, logic
Rev. B | Page 44 of 48
VPULLUP = 3.3V
CMOS
10
50
OUT3, OUT4
SELECTED AS CMOS
100
100
Figure 41. CMOS Output with Far-End Termination
3pF
05287-097
SNR = 20log10
Whenever single-ended CMOS clocking is used, some of the
following general guidelines should be followed.
05287-096
tj = 50fs
120
The AD9512 provides two clock outputs (OUT3 and OUT4),
which are selectable as either CMOS or LVDS levels. When
selected as CMOS, these outputs provide for driving devices
requiring CMOS level logic at their clock inputs.
AD9512
Because of the limitations of single-ended CMOS clocking,
consider using differential outputs when driving high speed
signals over long traces. The AD9512 offers both LVPECL and
LVDS outputs, which are better suited for driving long traces
where the inherent noise immunity of differential signaling
provides superior performance for clocking converters.
LVPECL CLOCK DISTRIBUTION
The low voltage, positive emitter-coupled, logic (LVPECL)
outputs of the AD9512 provide the lowest jitter clock signals
available from the AD9512. The LVPECL outputs (because they
are open emitter) require a dc termination to bias the output
transistors. A simplified equivalent circuit in Figure 27 shows
the LVPECL output stage.
LVDS CLOCK DISTRIBUTION
Low voltage differential signaling (LVDS) is a second
differential output option for the AD9512. LVDS uses a current
mode output stage with several user-selectable current levels.
The normal value (default) for this current is 3.5 mA, which
yields 350 mV output swing across a 100 Ω resistor. The LVDS
outputs meet or exceed all ANSI/TIA/EIA—644 specifications.
A recommended termination circuit for the LVDS outputs is
shown in Figure 44.
3.3V
LVDS
3.3V
100
100
DIFFERENTIAL (COUPLED)
LVDS
05287-032
In most applications, a standard LVPECL far-end termination
is recommended, as shown in Figure 42. The resistor network is
designed to match the transmission line impedance (50 Ω) and
the desired switching threshold (1.3 V).
Figure 44. LVDS Output Termination
3.3V
3.3V
50
LVPECL
127
127
SINGLE-ENDED
(NOT COUPLED)
3.3V
See Application Note AN-586 on the ADI website at
www.analog.com for more information on LVDS.
LVPECL
POWER AND GROUNDING CONSIDERATIONS AND
POWER SUPPLY REJECTION
50
83
83
05287-030
VT = VCC – 1.3V
Figure 42. LVPECL Far-End Termination
3.3V
3.3V
Many applications seek high speed and performance under less
than ideal operating conditions. In these application circuits,
the implementation and construction of the PCB is as
important as the circuit design. Proper RF techniques must be
used for device selection, placement, and routing, as well as for
power supply bypassing and grounding to ensure optimum
performance.
0.1nF
200
0.1nF
DIFFERENTIAL
(COUPLED)
100
LVPECL
200
05287-031
LVPECL
Figure 43. LVPECL with Parallel Transmission Line
Rev. B | Page 45 of 48
AD9512
OUTLINE DIMENSIONS
PIN 1
INDICATOR
AREA
7.10
7.00 SQ
6.90
DETAIL A
(JEDEC 95)
0.30
0.23
0.18
37
36
48
1
0.50
BSC
P IN 1
IN D IC ATO R AR E A OP T IO N S
(SEE DETAIL A)
5.20
5.10 SQ
5.00
EXPOSED
PAD
12
0.80
0.75
0.70
END VIEW
PKG-004509
SEATING
PLANE
0.45
0.40
0.35
24
13
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.203 REF
0.20 MIN
5.50 REF
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WKKD-4
10-10-2018-C
TOP VIEW
Figure 45. 48-Lead Lead Frame Chip Scale Package [LFCSP]
7 mm × 7 mm Body and 0.75 mm Package Height
(CP-48-4)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD9512BCPZ1
AD9512BCPZ-REEL71
AD9512/PCB
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
48-Lead Lead Frame Chip Scale Package (LFCSP)
48-Lead Lead Frame Chip Scale Package (LFCSP)
Evaluation Board Without VCO, VCXO, or Loop Filter
Z = Pb-free part.
Rev. B | Page 46 of 48
Package Option
CP-48-4
CP-48-4
AD9512
NOTES
Rev. B | Page 47 of 48
AD9512
NOTES
© 2005–2020 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D05287–9/20(B)
Rev. B | Page 48 of 48
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