AD9528/PCBZ

Data Sheet AD9528 JESD204B/JESD204C Clock Generator with 14 LVDS/HSTL Outputs FEATURES ► ► ► ► ► ► ► ► ► ► ► FUNCTIONAL BLOCK DIAGRAM 14 outputs configurable for HSTL or LVDS Maximum output frequency ► 6 outputs up to 1.25 GHz ► 8 outputs up to 1 GHz Dependent on the voltage controlled crystal oscillator (VCXO) frequency accuracy (start-up frequency accuracy: 20 kΩ OUTPUT VOLTAGE High VDD − 0.15 Low 150 mV PLL2 CHARACTERISTICS Table 7. Parameter Min Typ Max Unit 4025 MHz Test Conditions/Comments VCO (ON CHIP) Frequency Range 3450 Gain PLL2 FIGURE OF MERIT (FOM) 48 MHz/V −226 dBc/Hz MAXIMUM PFD FREQUENCY 275 MHz CLOCK DISTRIBUTION OUTPUT CHARACTERISTICS Table 8. Parameter Min Typ Max Unit Test Conditions/Comments 1000 MHz All outputs HSTL MODE Output Frequency Rise Time/Fall Time (20% to 80%) 1250 MHz OUT0 to OUT3, OUT12, OUT13 outputs only 60 160 ps 100 Ω termination across output pair Duty Cycle f < 500 MHz 48 50 53 % f = 500 MHz to 800 MHz 46 51 54 % f = 800 MHz to 1.25 GHz 44 50 62 % f = 800 MHz to 1.25 GHz 50 57 % If using PLL2 Differential Output Voltage Swing 900 1000 1100 mV VOH − VOL for each leg of a differential pair for default amplitude setting with the driver not toggling; the peak-to-peak amplitude measured using a differential probe across the differential pair with the driver toggling is roughly 2× these values (see Figure 5 for variation over frequency) Common-Mode Output Voltage 0.88 0.9 0.94 V LVDS MODE, 3.5 mA 3.5 mA Output Frequency Rise Time/Fall Time (20% to 80%) 50 1000 MHz All outputs 1250 MHz OUT0 to OUT3, OUT12, OUT13 outputs only 216 ps 100 Ω termination across output pair Duty Cycle analog.com Rev. F | 6 of 67 Data Sheet AD9528 SPECIFICATIONS Table 8. Parameter Min Typ Max Unit f < 500 MHz 47 50 53 % f = 500 MHz to 800 MHz 46 51 54 % f = 800 MHz to 1.25 GHz 48 54 58 % 390 mV Voltage swing between output pins; output driver static (see Figure 6 for variation over frequency) 3 mV Absolute difference between voltage swing of normal pin and inverted pin; output driver static 1.35 V 1.2 mV Voltage difference between output pins; output driver static 19 mA Output driver static Balanced, Differential Output Swing (VOD) 345 Unbalanced, ∆VOD Common-Mode Output Voltage 1.15 Common-Mode Difference Short-Circuit Output Current 15 Test Conditions/Comments OUTPUT TIMING ALIGNMENT CHARACTERISTICS Table 9. Parameter Min Typ Max Unit OUTPUT TIMING SKEW Test Conditions/Comments Delay off on all outputs, maximum deviation between rising edges of outputs; all outputs are on and in HSTL mode, unless otherwise noted PLL1 Outputs PLL1 to PLL1 17 100 ps PLL1 clock to PLL1 clock PLL1 to SYSREF 17 100 ps SYSREF retimed by PLL1 clock PLL1 to SYSREF 361 510 ps SYSREF not retimed by any clock PLL1 to SYSREF 253 1150 ps SYSREF retimed by PLL2 clock PLL1 to PLL2 257 1000 ps PLL1 clock to PLL2 clock PLL2 to PLL2 20 165 ps PLL2 clock to PLL2 clock PLL2 to SYSREF 20 165 ps SYSREF retimed by PLL2 clock PLL2 to SYSREF 620 750 ps SYSREF not retimed by any clock PLL2 to SYSREF 253 1150 ps SYSREF retimed by PLL1 clock PLL2 to PLL1 257 1000 ps PLL2 clock to PLL1 clock PLL2 Outputs OUTPUT DELAY ADJUST Enables digital and analog delay capability Coarse Adjustable Delay 32 Steps Resolution step is the period of VCO RF divider (M1) output/2 Fine Adjustable Delay 15 Steps Resolution step Resolution Step 31 ps 425 ps Insertion Delay Analog delay enabled and delay setting equal to zero SYSREF_IN, SYSREF_IN, VCXO_IN, AND VCXO_IN TIMING CHARACTERISTICS Table 10. Parameter Min Typ Max Unit Test Conditions/Comments PROPAGATION LATENCY OF VCXO PATH 1.92 2.3 2.7 ns VCXO input to device clock output, not retimed PROPAGATION LATENCY OF SYSREF PATH 1.83 2.2 2.6 ns SYSREF input to SYSREF output, not retimed Given a SYSREF input clock rate equal to 122.88 MHz RETIMED WITH DEVICE CLOCK Setup Time of External SYSREF Relative to Device Clock Output −1.13 ns Hold Time of External SYSREF Relative to Device Clock Output 0.7 ns analog.com Rev. F | 7 of 67 Data Sheet AD9528 SPECIFICATIONS Table 10. Parameter Min Typ Max Unit Test Conditions/Comments RETIMED WITH VCXO Setup Time of External SYSREF Relative to VCXO Input −0.21 ns Hold Time of External SYSREF Relative to VCXO 0.09 ns CLOCK OUTPUT ABSOLUTE PHASE NOISE—DUAL LOOP MODE Application examples are based on a typical setups (see Table 2) using an external 122.88 MHz VCXO (Crystek CVHD-950); reference = 122.88 MHz; channel divider = 10 or 1; PLL2 loop bandwidth (LBW) = 450 kHz. Table 11. Parameter Min Typ Max Unit Test Conditions/Comments HSTL OUTPUT fOUT = 122.88 MHz 10 Hz Offset −87 dBc/Hz 100 Hz Offset −106 dBc/Hz 1 kHz Offset −126 dBc/Hz 10 kHz Offset −135 dBc/Hz 100 kHz Offset −139 dBc/Hz 800 kHz Offset −147 dBc/Hz 1 MHz Offset −149 dBc/Hz 10 MHz Offset −161 dBc/Hz 40 MHz Offset −162 dBc/Hz 10 Hz Offset −62 dBc/Hz 100 Hz Offset −85 dBc/Hz 1 kHz Offset −106 dBc/Hz 10 kHz Offset −115 dBc/Hz 100 kHz Offset −119 dBc/Hz 800 kHz Offset −127 dBc/Hz 1 MHz Offset −129 dBc/Hz 10 MHz Offset −147 dBc/Hz 100 MHz Offset −153 dBc/Hz 10 Hz Offset −86 dBc/Hz 100 Hz Offset −106 dBc/Hz 1 kHz Offset −126 dBc/Hz 10 kHz Offset −135 dBc/Hz 100 kHz Offset −139 dBc/Hz 800 kHz Offset −147 dBc/Hz 1 MHz Offset −148 dBc/Hz 10 MHz Offset −157 dBc/Hz 40 MHz Offset −158 dBc/Hz fOUT = 1228.8 MHz OUT1 and OUT2 only, channel divider = 1 LVDS OUTPUT fOUT = 122.88 MHz fOUT = 1228.8 MHz OUT1 and OUT2 only, channel divider = 1 10 Hz Offset −66 dBc/Hz 100 Hz Offset −86 dBc/Hz analog.com Rev. F | 8 of 67 Data Sheet AD9528 SPECIFICATIONS Table 11. Parameter Min Typ Max Unit 1 kHz Offset −106 dBc/Hz 10 kHz Offset −115 dBc/Hz 100 kHz Offset −119 dBc/Hz 800 kHz Offset −127 dBc/Hz 1 MHz Offset −129 dBc/Hz 10 MHz Offset −147 dBc/Hz 100 MHz Offset −152 dBc/Hz Test Conditions/Comments CLOCK OUTPUT ABSOLUTE PHASE NOISE—SINGLE LOOP MODE Single loop mode is based on the typical setup (see Table 2) using an external 122.88 MHz reference (SMA100A generator); reference = 122.88 MHz; channel divider = 10; PLL2 LBW = 450 kHz. Table 12. Parameter Min Typ Max Unit Test Conditions/Comments HSTL OUTPUT fOUT = 122.88 MHz 10 Hz Offset −104 dBc/Hz 100 Hz Offset −113 dBc/Hz 1 kHz Offset −123 dBc/Hz 10 kHz Offset −135 dBc/Hz 100 kHz Offset −140 dBc/Hz 800 kHz Offset −147 dBc/Hz 1 MHz Offset −149 dBc/Hz 10 MHz Offset −161 dBc/Hz 40 MHz Offset −162 dBc/Hz 10 Hz Offset −85 dBc/Hz 100 Hz Offset −95 dBc/Hz 1 kHz Offset −103 dBc/Hz 10 kHz Offset −114 dBc/Hz 100 kHz Offset −120 dBc/Hz 800 kHz Offset −126 dBc/Hz 1 MHz Offset −128 dBc/Hz 10 MHz Offset −147 dBc/Hz 100 MHz Offset −153 dBc/Hz 10 Hz Offset −111 dBc/Hz 100 Hz Offset −113 dBc/Hz 1 kHz Offset −123 dBc/Hz 10 kHz Offset −135 dBc/Hz 100 kHz Offset −140 dBc/Hz 800 kHz Offset −147 dBc/Hz 1 MHz Offset −148 dBc/Hz 10 MHz Offset −157 dBc/Hz fOUT = 1228.8 MHz OUT1 and OUT2 only, channel divider = 1 LVDS OUTPUT fOUT = 122.88 MHz analog.com Rev. F | 9 of 67 Data Sheet AD9528 SPECIFICATIONS Table 12. Parameter Min 40 MHz Offset Typ Max −157 Unit Test Conditions/Comments dBc/Hz fOUT = 1228.8 MHz OUT1 and OUT2 only, channel divider = 1 10 Hz Offset −85 dBc/Hz 100 Hz Offset −95 dBc/Hz 1 kHz Offset −103 dBc/Hz 10 kHz Offset −114 dBc/Hz 100 kHz Offset −120 dBc/Hz 800 kHz Offset −126 dBc/Hz 1 MHz Offset −128 dBc/Hz 10 MHz Offset −146 dBc/Hz 100 MHz Offset −152 dBc/Hz CLOCK OUTPUT ABSOLUTE TIME JITTER Table 13. Parameter Min Typ Max Unit Test Conditions/Comments Application examples are based on typical setups (see Table 2) using an external 122.88 MHz VCXO (Crystek CVHD-950); reference = 122.88 MHz; channel divider = 10 or 1; PLL2 LBW = 450 kHz OUTPUT ABSOLUTE RMS TIME JITTER Dual Loop Mode HSTL Output fOUT = 122.88 MHz fOUT = 1228.8 MHz, Channel Divider = 1 LVDS Output fOUT = 122.88 MHz fOUT = 1228.8 MHz, Channel Divider = 1 117 fs Integrated BW = 200 kHz to 5 MHz 123 fs Integrated BW = 200 kHz to 10 MHz 159 fs Integrated BW = 12 kHz to 20 MHz 172 fs Integrated BW = 10 kHz to 40 MHz 177 fs Integrated BW = 1 kHz to 40 MHz 109 fs Integrated BW = 1 MHz to 40 MHz 114 fs Integrated BW = 200 kHz to 5 MHz 116 fs Integrated BW = 200 kHz to 10 MHz 147 fs Integrated BW = 12 kHz to 20 MHz 154 fs Integrated BW = 10 kHz to 100 MHz 160 fs Integrated BW = 1 kHz to 100 MHz 74 fs Integrated BW = 1 MHz to 100 MHz 124 fs Integrated BW = 200 kHz to 5 MHz 136 fs Integrated BW = 200 kHz to 10 MHz 179 fs Integrated BW = 12 kHz to 20 MHz 209 fs Integrated BW = 10 kHz to 40 MHz 213 fs Integrated BW = 1 kHz to 40 MHz 160 fs Integrated BW = 1 MHz to 40 MHz 116 fs Integrated BW = 200 kHz to 5 MHz 118 fs Integrated BW = 200 kHz to 10 MHz 150 fs Integrated BW = 12 kHz to 20 MHz 157 fs Integrated BW = 10 kHz to 100 MHz 163 fs Integrated BW = 1 kHz to 100 MHz 76 fs Integrated BW = 1 MHz to 100 MHz Single Loop Mode analog.com Rev. F | 10 of 67 Data Sheet AD9528 SPECIFICATIONS Table 13. Parameter Min HSTL Output fOUT = 122.88 MHz fOUT = 1228.8 MHz, Channel Divider = 1 LVDS Output fOUT = 122.88 MHz fOUT = 1228.8 MHz, Channel Divider = 1 Typ Max Unit Test Conditions/Comments 115 fs Integrated BW = 200 kHz to 5 MHz 122 fs Integrated BW = 200 kHz to 10 MHz 156 fs Integrated BW = 12 kHz to 20 MHz 171 fs Integrated BW = 10 kHz to 40 MHz 179 fs Integrated BW = 1 kHz to 40 MHz 110 fs Integrated BW = 1 MHz to 40 MHz 116 fs Integrated BW = 200 kHz to 5 MHz 118 fs Integrated BW = 200 kHz to 10 MHz 146 fs Integrated BW = 12 kHz to 20 MHz 153 fs Integrated BW = 10 kHz to 100 MHz 163 fs Integrated BW = 1 kHz to 100 MHz 81 fs Integrated BW = 1 MHz to 100 MHz 123 fs Integrated BW = 200 kHz to 5 MHz 135 fs Integrated BW = 200 kHz to 10 MHz 177 fs Integrated BW = 12 kHz to 20 MHz 207 fs Integrated BW = 10 kHz to 40 MHz 214 fs Integrated BW = 1 kHz to 40 MHz 160 fs Integrated BW = 1 MHz to 40 MHz 117 fs Integrated BW = 200 kHz to 5 MHz 119 fs Integrated BW = 200 kHz to 10 MHz 147 fs Integrated BW = 12 kHz to 20 MHz 155 fs Integrated BW = 10 kHz to 100 MHz 164 fs Integrated BW = 1 kHz to 100 MHz 83 fs Integrated BW = 1 MHz to 100 MHz CLOCK OUTPUT ADDITIVE TIME JITTER (BUFFER MODE) Table 14. Parameter Min Typ Max Unit Test Conditions/Comments Application examples are based on typical performance (see Table 2) using an external 122.88 MHz source driving VCXO inputs (distribution section only, does not include PLL and VCO) OUTPUT ADDITIVE RMS TIME JITTER Buffer Mode HSTL Output fOUT = 122.88 MHz LVDS Output fOUT = 122.88 MHz analog.com 66 fs Integrated BW = 200 kHz to 5 MHz 81 fs Integrated BW = 200 kHz to 10 MHz 112 fs Integrated BW = 12 kHz to 20 MHz 145 fs Integrated BW = 10 kHz to 40 MHz 146 fs Integrated BW = 1 kHz to 40 MHz 132 fs Integrated BW = 1 MHz to 40 MHz 79 fs Integrated BW = 200 kHz to 5 MHz 101 fs Integrated BW = 200 kHz to 10 MHz 140 fs Integrated BW = 12 kHz to 20 MHz 187 fs Integrated BW = 10 kHz to 40 MHz 189 fs Integrated BW = 1 kHz to 40 MHz 176 fs Integrated BW = 1 MHz to 40 MHz Rev. F | 11 of 67 Data Sheet AD9528 SPECIFICATIONS LOGIC INPUT PINS—RESET, REF_SEL, AND SYSREF_REQ Table 15. Parameter Min Typ Max Unit Test Conditions/Comments VOLTAGE Input High 1.3 V Input Low INPUT LOW CURRENT 13 CAPACITANCE 4 0.6 V 14 µA pF RESET TIMING Pulse Width Low 1.0 ns Inactive to Start of Register Programming 2.5 ns STATUS OUTPUT PINS—STATUS0 AND STATUS1 Table 16. Parameter Min Typ Max Unit Test Conditions/Comments OUTPUT VOLTAGE High 3 V Low 0.02 V SERIAL CONTROL PORT—SERIAL PORT INTERFACE (SPI) MODE Table 17. Parameter Symbol Min Typ Max Unit CS (INPUT) Test Conditions/Comments CS has an internal 35 kΩ pull-up resistor Voltage Input Logic 1 1.37 V Input Logic 0 1.33 V Input Logic 1 −52 µA Input Logic 0 −82 µA 2 pF Current Input Capacitance SCLK (INPUT) IN SPI MODE SCLK has an internal 40 kΩ pull-down resistor in SPI mode but not in I2C mode Voltage Input Logic 1 1.76 V Input Logic 0 1.22 V Input Logic 1 0.0037 µA Input Logic 0 0.0012 µA 2 pF Current Input Capacitance SDIO Input is in bidirectional mode Voltage Input Logic 1 1.76 V Input Logic 0 1.22 V Current analog.com Rev. F | 12 of 67 Data Sheet AD9528 SPECIFICATIONS Table 17. Parameter Symbol Min Typ Max Unit Input Logic 1 0.0037 µA Input Logic 0 0.0012 µA 3.5 pF Input Capacitance Test Conditions/Comments SDIO, SDO (OUTPUTS) Voltage Output Logic 1 3.11 V Output Logic 0 0.0018 V 50 MHz TIMING Clock Rate (SCLK, 1/tSCLK) Pulse Width High tHIGH 4 ns Pulse Width Low tLOW 2 ns SDIO to SCLK Setup tDS 2.2 ns SCLK to SDIO Hold tDH −0.9 ns SCLK to Valid SDIO and SDO tDV CS to SCLK Setup tS 1.25 6 ns ns CS to SCLK Hold tC 0 ns CS Minimum Pulse Width High tPWH 0.9 ns SERIAL CONTROL PORT—I2C MODE Table 18. Parameter Symbol Min Typ Max Unit SDA, SCL VOLTAGE Test Conditions/Comments When inputting data Input Logic 1 0.7 × VDD Input Logic 0 Input Current −10 V 0.3 × VDD V +10 µA Input voltage between 0.1 × VDD and 0.9 × VDD Hysteresis of Schmitt Trigger Inputs 0.015 × VDD V SDA When outputting data Output Logic 0 Voltage at 3 mA Sink Current 20 + 0.1 CB1 Output Fall Time from VIHMIN to VILMAX 0.2 V 250 ns Clock Rate (SCL, fI2C) Bus Free Time Between a Stop and Start Condition 400 kHz tIDLE 1.3 µs Setup Time for a Repeated Start Condition tSET; STR 0.6 µs Hold Time (Repeated) Start Condition tHLD; STR 0.6 µs Setup Time for a Stop Condition tSET; STP 0.6 µs Low Period of the SCL Clock tLOW 1.3 µs High Period of the SCL Clock tHIGH 0.6 SCL, SDA Rise Time tRISE 20 + 0.1 CB1 300 SCL, SDA Fall Time tFALL 20 + 0.1 CB1 300 Data Setup Time tSET; DAT 100 analog.com Bus capacitance from 10 pF to 400 pF All I2C timing values are referred to VIHMIN (0.3 × VDD) and VILMAX levels (0.7 × VDD) TIMING After this period, the first clock pulse is generated µs ns ns ns Rev. F | 13 of 67 Data Sheet AD9528 SPECIFICATIONS Table 18. Parameter 1 Symbol Min Data Hold Time tHLD; DAT 0 Capacitive Load for Each Bus Line CB1 Typ Max Unit 400 pF Test Conditions/Comments ns CB is the capacitance of one bus line in picofarads (pF). analog.com Rev. F | 14 of 67 Data Sheet AD9528 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 19. Parameter Rating VDD −0.3 V to +3.6 V REFA, REFA, REFB, REFB, VCXO_IN, VCXO_IN, SYSREF_IN, SYSREF_IN, SYSREF_REQ to GND −0.3 V to +3.6 V SCLK/SCL, SDIO/SDA, SDO, CS to GND −0.3 V to +3.6 V RESET, REF_SEL, SYSREF_REQ to GND −0.3 V to +3.6 V STATUS0/SP0, STATUS1/SP1 to GND −0.3 V to +3.6 V Junction Temperature 125°C Storage Temperature Range −65°C to +150°C Lead Temperature (10 sec) 300°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Thermal performance is directly linked to PCB design and operating environment. Careful attention to PCB thermal design is required. Table 20. Thermal Resistance Airflow Velocity (m/sec) θJA1, 2 θJC1, 3 θJB1, 4 ΨJT1, 2 Unit 72-Lead LFCSP, 10 0 mm × 10 mm 1.0 21.3 1.7 12.6 0.1 °C/W 20.1 0.2 °C/W 2.5 18.1 0.3 °C/W Package Type 1 Per JEDEC 51-7, plus JEDEC 51-5 2S2P test board. 2 Per JEDEC JESD51-2 (still air) or JEDEC JESD51-6 (moving air). 3 Per MIL-Std 883, Method 1012.1. 4 Per JEDEC JESD51-8 (still air). Additional power dissipation information can be found in the Power Dissipation and Thermal Considerations section. ESD CAUTION ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. analog.com Rev. F | 15 of 67 Data Sheet AD9528 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Figure 2. Pin Configuration Table 21. Pin Function Descriptions Pin No.1 Mnemonic Type2 Description 1 VDD P 3.3 V Supply for the PLL1 Input Section. 2 REFA I Reference Clock Input A. Along with REFA, this pin is the differential input for the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input. 3 REFA I Complementary Reference Clock Input A. Along with REFA, this pin is the differential input for the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input. 4 REF_SEL I Reference Input Select. The reference input selection function defaults to software control via internal Register 0x010A, Bits[2:0]. When the REF_SEL pin is active, a logic low selects REFA and logic high selects REFB. 5 REFB I Reference Clock Input B. Along with REFB, this pin is the differential input for the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input. 6 REFB I Complementary Reference Clock Input B. Along with REFB, this pin is the differential input for the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input. 7 LF1 O PLL1 External Loop Filter. 8 VCXO_VT O VCXO Control Voltage. Connect this pin to the voltage control pin of the external VCXO. 9 NIC NIC Not Internally Connected. The pin can be left floating. 10 VDD P 3.3 V Supply for the PLL2 Section. 11 VCXO_IN I PLL1 Oscillator Input. Along with VCXO_IN, this pin is the differential input for the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input. 12 VCXO_IN I Complementary PLL1 Oscillator Input. Along with VCXO_IN, this pin is the differential input for the PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input. 13 NIC NIC Not Internally Connected. The pin can be left floating. 14 LF2_CAP O PLL2 External Loop Filter Capacitor Connection. Connect capacitor between this pin and the LDO_VCO pin. 15 LDO_VCO P/O 2.5 V LDO Internal Regulator Decoupling for the VCO. Connect a 0.47 μF decoupling capacitor from this pin to ground. Note that, for best performance, the LDO bypass capacitor must be placed in close proximity to the device. 16 VDD P 3.3 V Supply for the PLL2 Internal Regulator. 17 NIC NIC Not Internally Connected. The pin can be left floating. 18 NIC NIC Not Internally Connected. The pin can be left floating. analog.com Rev. F | 16 of 67 Data Sheet AD9528 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 21. Pin Function Descriptions Pin No.1 Mnemonic Type2 Description 19 RESET I Digital Input, Active Low. Resets internal logic to default states. 20 VDD P 3.3 V Supply for the PLL2 Internal Regulator. 21 CS 22 SCLK/SCL I Serial Control Port Clock Signal for SPI Mode (SCLK) or I2C Mode (SCL). Data clock for serial programming. 23 SDIO/SDA I/O Serial Control Port Bidirectional Serial Data In/Data Out for SPI Mode (SDIO) or I2C Mode (SDA). 24 SDO O Serial Data Output. Use this pin to read data in 4-wire mode (high impedance in 3-wire mode). There is no internal pull-up or pull-down resistor on this pin. 25 OUT13 O Square Wave Clocking Output 13. 26 OUT13 O Complementary Square Wave Clocking Output 13. High speed output up to 1.25 GHz. 27 VDD13 P 3.3 V Supply for the Output 13 Clock Driver. High speed output up to 1.25 GHz. 28 OUT12 O Square Wave Clocking Output 12. High speed output up to 1.25 GHz. 29 OUT12 O Complementary Square Wave Clocking Output 12. High speed output up to 1.25 GHz. 30 VDD12 P 3.3 V Supply for the Output 12 Clock Divider. 31 OUT11 O Square Wave Clocking Output 11. 32 OUT11 O Complementary Square Wave Clocking Output 11. 33 VDD11 P 3.3 V Supply for the Output 11 Clock Driver. 34 OUT10 O Square Wave Clocking Output 10. 35 OUT10 O Complementary Square Wave Clocking Output 10. 36 VDD10 P 3.3 V Supply for the Output 10 Clock Divider. 37 OUT9 O Square Wave Clocking Output 9. 38 OUT9 O Complementary Square Wave Clocking Output 9. 39 VDD9 P 3.3 V Supply for the Output 9 Clock Driver. 40 OUT8 O Square Wave Clocking Output 8. 41 OUT8 O Complementary Square Wave Clocking Output 8. 42 VDD8 P 3.3 V Supply for the Output 8 Clock Divider. 43 OUT7 O Square Wave Clocking Output 7. 44 OUT7 O Complementary Square Wave Clocking Output 7. 45 VDD7 P 3.3 V Supply for the Output 7 Clock Driver. 46 OUT6 O Square Wave Clocking Output 6. 47 OUT6 O Complementary Square Wave Clocking Output 6. 48 VDD6 P 3.3 V Supply for the Output 6 Clock Divider. 49 OUT5 O Square Wave Clocking Output 5. 50 OUT5 O Complementary Square Wave Clocking Output 5. 51 VDD5 P 3.3 V Supply for the Output 5 Clock Driver. 52 OUT4 O Square Wave Clocking Output 4. 53 OUT4 O Complementary Square Wave Clocking Output 4. 54 VDD4 P 3.3 V Supply for the Output 4 Clock Divider. 55 STATUS0/SP0 I/O Lock Detect and Other Status Signals/I2C Address. This pin has an internal 30 kΩ pull-down resistor. 56 STATUS1/SP1 I/O Lock Detect and Other Status Signals/I2C Address. This pin has an internal 30 kΩ pull-down resistor. 57 SYSREF_REQ I SYSREF Request Input Logic Control. 58 OUT3 O Square Wave Clocking Output 3. 59 OUT3 O Complementary Square Wave Clocking Output 3. High speed output up to 1.25 GHz. 60 VDD3 P 3.3 V Supply for the Output 3 Clock Driver. High speed output up to 1.25 GHz. 61 OUT2 O Square Wave Clocking Output 2. High speed output up to 1.25 GHz. analog.com Serial Control Port Chip Select, Active Low. This pin has an internal 35 kΩ pull-up resistor. Rev. F | 17 of 67 Data Sheet AD9528 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS Table 21. Pin Function Descriptions Pin No.1 Mnemonic Type2 Description 62 OUT2 O Complementary Square Wave Clocking Output 2. High speed output up to 1.25 GHz. 63 VDD2 P 3.3 V Supply for the Output 2 Clock Divider. 64 OUT1 O Square Wave Clocking Output 1. High speed output up to 1.25 GHz. 65 OUT1 O Complementary Square Wave Clocking Output 1. High speed output up to 1.25 GHz. 66 VDD1 P 3.3 V Supply for the Output 1 Clock Driver. 67 OUT0 O Square Wave Clocking Output 0. High speed output up to 1.25 GHz. 68 OUT0 O Complementary Square Wave Clocking Output 0. High speed output up to 1.25 GHz. 69 VDD0 P 3.3 V Supply for the Output 0 Clock Divider. 70 SYSREF_IN I External SYSREF Input Clock. Along with SYSREF_IN, this pin is the differential input for an external SYSREF signal. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input. 71 SYSREF_IN I Complementary External SYSREF Input Clock. Along with SYSREF_IN, this pin is the differential input for an external SYSREF signal. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input. 72 VDD P 3.3 V Supply for the PLL1 Input Section. EP EP, GND GND Exposed Pad. The exposed pad is the ground connection on the chip. It must be soldered to the analog ground of the printed circuit board (PCB) to ensure proper functionality and heat dissipation, noise, and mechanical strength benefits. 1 Supply all VDDx pins even when a certain AD9528 section is not used. 2 P means power, I means input, O means output, I/O means input/output, P/O means power/output, and GND means ground. analog.com Rev. F | 18 of 67 Data Sheet AD9528 TYPICAL PERFORMANCE CHARACTERISTICS fVCXO = 122.88 MHz, REFA differential at 122.88 MHz, fVCO = 3686.4 MHz, and doubler is off, unless otherwise noted. External PLL1 loop filter component values are as follows: RZERO = 10 kΩ, CZERO = 1 μF, CPOLE = 200 pF. External PLL2 external capacitor CZERO = 1 nF. PLL1 charge pump = 5 μA and PLL2 charge pump = 805 μA. Figure 3. VDDx Current (Typical) vs. Output Frequency, HSTL Mode Figure 4. VDDx Current (Typical) vs. Output Frequency, LVDS Mode and LVDS Boost Mode Figure 6. Differential Voltage Swing vs. Output Frequency, LVDS Mode and LVDS Boost Mode Figure 7. Positive Duty Cycle vs. Output Frequency, HSTL, LVDS, and LVDS Boost Modes Figure 5. Differential Voltage Swing vs. Output Frequency, HSTL Mode Figure 8. Output Waveform (Differential), HSTL at 122.88 MHz analog.com Rev. F | 19 of 67 Data Sheet AD9528 TYPICAL PERFORMANCE CHARACTERISTICS Figure 9. Output Waveform (Differential), HSTL at 1228.8 MHz Figure 12. Phase Noise, Output = 122.88 MHz, HSTL Mode, PLL1 Output Sent Directly to Clock Distribution, PLL2 Off (VCXO = 122.88 MHz, Crystek VCXO CVHD-950) Figure 10. Output Waveform (Differential), LVDS and LVDS Boost Mode at 122.88 MHz Figure 13. Phase Noise, Output = 122.88 MHz, HSTL Mode, PLL1 Output Sent Directly to Clock Distribution, PLL2 Off (VCXO = 122.88 MHz, TAITEN VCXO (A0145-0-011-3) Figure 11. Output Waveform (Differential), LVDS and LVDS Boost Mode at 1228.8 MHz Figure 14. Phase Noise, Output = 122.88 MHz, HSTL Mode, Dual Loop Mode (VCXO = 122.88 MHz, Crystek VCXO CVHD-950, VCO = 3686.4 MHz) analog.com Rev. F | 20 of 67 Data Sheet AD9528 TYPICAL PERFORMANCE CHARACTERISTICS Figure 15. Phase Noise, Output = 122.88 MHz, HSTL Mode, Dual Loop Mode (VCXO = 122.88 MHz, TAITEN VCXO (A0145-0-011-3), VCO = 3686.4 MHz) Figure 18. Phase Noise, Output = 1228.8 MHz, HSTL Mode, Dual Loop Mode(VCXO = 122.88 MHz, Crystek VCXO CVHD-950, VCO = 3686.4 MHz) Figure 16. Phase Noise, Output = 245.76 MHz, HSTL Mode, Dual Loop Mode (VCXO = 122.88 MHz, Crystek VCXO CVHD-950, VCO = 3686.4 MHz) Figure 19. RMS Jitter in Buffer Mode with Both PLL1 and PLL2 Off vs. Slew Rate; Input Applied to the VCXO Input and Output Taken from Clock Distribution, Phase Noise Integration Range from 12 kHz to 20 MHz to Derive Jitter Number Figure 17. Phase Noise, Output = 983.04 MHz, HSTL Mode, Dual Loop Mode(VCXO = 122.88 MHz, Crystek VCXO CVHD-950, VCO = 3932.16 MHz) analog.com Rev. F | 21 of 67 Data Sheet AD9528 INPUT/OUTPUT TERMINATION RECOMMENDATIONS Figure 20. AC-Coupled LVDS Output Driver Figure 24. REFx, VCXO Input Differential Mode Receiver Figure 21. DC-Coupled LVDS Output Driver Figure 25. REFx, VCXO Input, Single-Ended Mode Receiver Figure 22. AC-Coupled HSTL Output Driver Figure 23. DC-Coupled HSTL Output Driver analog.com Rev. F | 22 of 67 Data Sheet AD9528 TYPICAL APPLICATION CIRCUIT The AD9528 is capable of synchronizing multiple devices designed to the JESD204B/JESD204C JEDEC standard. Figure 26 illustrates the AD9528 synchronizing to the system reference clock. The AD9528 first jitter cleans the system reference clock and multiples up to a higher frequency in dual loop mode. The clock distribution of the AD9528 is used to clock and synchronize all the surrounding JESD204B/JESD204C devices together in the system. Figure 26. Synchronizing Multiple JESD204B/JESD204C Devices analog.com Rev. F | 23 of 67 Data Sheet AD9528 TERMINOLOGY Phase Jitter An ideal sine wave has a continuous and even progression of phase with time from 0° to 360° for each cycle. Actual signals, however, display a certain amount of variation from ideal phase progression over time. This phenomenon is called phase jitter. Although many causes can contribute to phase jitter, one major cause is random noise, which is characterized statistically as being Gaussian (normal) in distribution. Phase jitter leads to a spreading out of the energy of the sine wave in the frequency domain, producing a continuous power spectrum. This power spectrum is usually reported as a series of values with the units dBc/Hz at a given offset in frequency from the sine wave (carrier). The value is a ratio (expressed in decibels) of the power contained within a 1 Hz bandwidth with respect to the power at the carrier frequency. For each measurement, the offset from the carrier frequency is also given. various oscillators and clock sources, each of which contributes its own phase noise to the total. In many cases, the phase noise of one element dominates the system phase noise. When there are multiple contributors to phase noise, the total is the square root of the sum of squares of the individual contributors. Additive Time Jitter Additive time jitter is the amount of time jitter that is attributable to the device or subsystem being measured. The time jitter of any external oscillators or clock sources is subtracted. This makes it possible to predict the degree to which the device impacts the total system time jitter when used in conjunction with the various oscillators and clock sources, each of which contributes its own time jitter to the total. In many cases, the time jitter of the external oscillators and clock sources dominates the system time jitter. In some applications, it is meaningful to integrate only the total power contained within some interval of offset frequencies (for example, 10 kHz to 10 MHz). This is called the integrated phase noise over that frequency offset interval and can be readily related to the time jitter due to the phase noise within that offset frequency interval. Phase Noise Phase noise has a detrimental effect on the performance of analogto-digital converters (ADCs), digital-to-analog converters (DACs), and radio frequency (RF) mixers. It lowers the achievable dynamic range of the converters and mixers, although they are affected in somewhat different ways. Time Jitter Phase noise is a frequency domain phenomenon. In the time domain, the same effect is exhibited as time jitter. When observing a sine wave, the time of successive zero crossings varies. In a square wave, the time jitter is a displacement of the edges from their ideal (regular) times of occurrence. In both cases, the variations in timing from the ideal are the time jitter. Because these variations are random in nature, the time jitter is specified in seconds root mean square (rms) or 1 sigma of the Gaussian distribution. Time jitter that occurs on a sampling clock for a DAC or an ADC decreases the SNR and dynamic range of the converter. A sampling clock with the lowest possible jitter provides the highest performance from a given converter. Additive Phase Noise Additive phase noise is the amount of phase noise that is attributable to the device or subsystem being measured. The phase noise of any external oscillators or clock sources is subtracted. This makes it possible to predict the degree to which the device impacts the total system phase noise when used in conjunction with the analog.com Rev. F | 24 of 67 Data Sheet AD9528 THEORY OF OPERATION DETAILED BLOCK DIAGRAM Figure 27. Top Level Diagram OVERVIEW The AD9528 is a clock generator that employs integer-N based phase-locked loops (PLL). The device architecture consists of two cascaded PLL stages. PLL1 consists of an integer division PLL that uses an external voltage controlled crystal oscillator (VCXO). PLL1 has a narrow loop bandwidth that provides initial jitter cleanup of the input reference signal for the input stage of PLL2. Conversely, the output of PLL1 is also routable to any clock distribution output, if desired. PLL2 is a frequency multiplying PLL that translates the first PLL stage output frequency to a range of 3.450 GHz to 4.025 GHz. PLL2 incorporates an integer based feedback divider that enables integer frequency multiplication. An RF VCO divider (3, 4, or 5) divides the VCO output of PLL2 before being routed to the input of the clock distribution section. Programmable integer dividers (1 to 256) in the clock distribution follow the RF VCO divider, establishing a final output frequency up to 1 GHz or less for the 8 available outputs. The OUT0 to OUT3, OUT12, and OUT13 outputs can run up to 1.25 GHz. All of the divider settings in the clock distribution section are configurable via the serial programming port, enabling a wide range of input/output frequency ratios under program control. The dividers also include a programmable coarse delay to adjust timing of the output signals, if required. In addition, a fine delay adjust is available in the clock distribution path. also receive an externally generated SYSREF signal and buffer to the outputs, with or without retiming. The AD9528 operates over the extended industrial temperature range of −40°C to +85°C. The AD9528 includes reference monitoring and automatic/manual switchover and holdover. A reference select pin is available to manually select which input reference is active. The accuracy of the holdover is dependent on the external VCXO frequency stability. All power supply pins on the AD9528 operate on a 3.3 V ±5% supply domain. However, each power supply pin has a dedicated internal LDO regulator that provides approximately 1.8 V for standard operation of the device. These independent regulators provide extra supply rejection and help with output to output coupling, since none of the output drivers or dividers share a supply. COMPONENT BLOCKS—PLL1 PLL1 General Description PLL1 consists of a phase/frequency detector (PFD), a charge pump, an external VCXO, and a partially external loop filter operating in a closed loop. PLL1 has the flexibility to operate with a narrow loop bandwidth. This relatively narrow loop bandwidth gives the AD9528 the ability to suppress jitter that appears on the input references (REFA and REFB). The low phase noise output of PLL1 acts as the reference to PLL2 and can be routed to the clock distribution section. The outputs are compatible with LVDS and HSTL logic levels. The AD9528 can produce a JESD204B/JESD204C SYSREF signal. This signal can be routed to any of the 14 outputs. The AD9528 can analog.com Rev. F | 25 of 67 Data Sheet AD9528 THEORY OF OPERATION PLL1 Reference Clock Inputs PLL1 Input Dividers The AD9528 features two separate reference clock inputs, REFA and REFB. These inputs can be configured to accept differential or single-ended signals. REFA and REFB are self biased in differential mode and high impedance in single-ended CMOS mode. If REFA or REFB is driven single-ended, decouple the unused side (REFA, REFB) via a suitable capacitor to a quiet ground. These inputs may be dc-coupled, but set the dc operation point as specified in the Specifications section. Each reference input has a dedicated reference divider block. The input dividers provide division of the reference frequency in integer steps from 1 to 1023. The differential reference input receiver is powered down when the differential reference input is not selected, or when the PLL1 is powered down. The single-ended buffers power down when the PLL1 is powered down, when their respective individual power-down registers are set, or when the differential receiver is selected. PLL1 Loop Filter The PLL1 loop filter is mostly external from LF1 (Pin 7) to ground. The value of the external components depend on the external VCXO and the configuration parameters, such as input clock rate and desired PLL1 loop bandwidth. Figure 28. PLL1 Loop Filter An external RC low-pass filter is recommended at the VCXO_VT output for the best noise performance at 1 kHz offset. The pole of this filter must be sufficiently high enough in frequency to avoid stability problems with the PLL loop bandwidth. VCXO Input The VCXO receiver provides the low phase noise oscillator input for PLL1. This signal is also the reference input for PLL2. In addition, the VCXO input is used when either PLL1 is bypassed, or PLL1 and PLL2 are bypassed to use the AD9528 as a buffer. PLL1 Reference Switchover The reference monitor verifies the presence or absence of the REFA and REFB signals. The status of the reference monitor guides the activity of the switchover control logic. The AD9528 supports automatic and manual PLL reference clock switching between REFA (the REFA and REFA pins) and REFB (the REFB and REFB pins). There are several configurable modes of reference switchover. The manual switchover is achieved either via programming a register setting or by using the REF_SEL pin. If manually selecting REFB, REFB must be present prior to when the switchover to REFB occurs. The automatic switchover occurs when REFA disappears and a reference is on REFB. PLL1 operates with REFA as the primary reference input; this is relevant to the switchover operation of the device. The reference switchover circuitry recognizes that REFA is the master reference. For the reference monitoring circuitry to work properly, REFA must be present during initial locking, regardless of whether REFB is present or not. When both references are used, REFA and REFB must be present. When a single reference is used, the reference must be REFA. The reference automatic switchover can be set to work as follows: Nonrevertive. Stay on REFB. Switch from REFA to REFB when REFA disappears, but do not switch back to REFA if it reappears. If REFB disappears, then go back to REFA. ► Revert to REFA. Switch from REFA to REFB when REFA disappears. Return to REFA from REFB when REFA returns. ► If a switchover event occurs in nonrevertive mode and the missing input to REFA is reestablished, the return of the missing reference does not reset the nonrevertive switchover logic. The result of this setup is that, if REFB is selected during nonrevertive switchover mode and nonrevertive switchover is disabled and reenabled, REFB is still the active reference, regardless if REFA is present. The switchover logic can be reset by issuing a device reset. ► Figure 29. Input PLL (PLL1) Block Diagram analog.com Rev. F | 26 of 67 Data Sheet AD9528 THEORY OF OPERATION PLL1_TO = 10/LBWPLL1 PLL1 Holdover In the absence of both input references, the device enters holdover mode. When the device switches to holdover mode, the charge pump tristates, allowing VCXO_VT to maintain its existing value for a period of time. Optionally, the charge pump can be programmed to force VCXO_VT to VDD/2. The device continues operating in this mode until a reference signal becomes available. Then the device exits holdover mode, and PLL1 resynchronizes with the active reference. Automatic holdover mode can be disabled with a register bit. PLL2 remains locked to the VCXO signal even when PLL1 is in holdover. PLL1 Lock Time The typical PLL1 lock time occurs within 5× the period of the loop bandwidth, assuming a third-order loop filter with a phase margin of 55°. It may take up to 10× the period of the loop bandwidth for the PLL1 lock detector circuit to show locked status. where: PLL1_TO is the PLL1 timeout. LBWPLL1 is the loop bandwidth of PLL1. COMPONENT BLOCKS—PLL2 PLL2 General Description PLL2 consists of an optional input reference 2× multiplier, reference divider, a PFD, a mostly integrated analog loop filter, an integrated voltage controlled oscillator (VCO), and a feedback divider. The VCO produces a nominal 3.8 GHz signal with an output divider that is capable of division ratios of 3, 4, and 5. PLL2 has a VCO with multiple bands spanning a range of 3.450 GHz to 4.025 GHz. The device automatically selects the appropriate band as part of its calibration process. Calculate PLL1_TO in Figure 52 as Figure 30. PLL2 Block Diagram analog.com Rev. F | 27 of 67 Data Sheet AD9528 THEORY OF OPERATION PLL2 Input 2× Frequency Multiplier The 2× frequency multiplier provides the option to double the frequency at the PLL2 reference input. A higher frequency at the input to the PLL2 (PFD) allows reduced in-band phase noise and greater separation between the frequency generated by the PLL and the modulation spur associated with the PFD. Note that, as the input duty cycle deviates from 50%, harmonic distortion may increase. As such, beneficial use of the frequency multiplier is application specific. Typically, a VCXO with proper interfacing has a duty cycle that is approximately 50% at the VCXO_IN inputs. Note that the maximum output frequency of the 2× frequency multipliers must not exceed the maximum PFD rate specified in Table 7. If the 2× frequency multiplier is used, a fixed phase offset can occur from power-up to power-up between the input to the 2× frequency multiplier and the PLL2 PFD reference input. This presents the possibility for a fixed phase offset between the VCXO_IN frequency and PLL2 output of ½ the period of the signal applied to the VCXO_IN and VCXO_IN pins. If the internal SYSREF generator is used, choose the PLL2 feedback path as the input signal of the SYSREF generator to ensure fixed phase alignment of the SYSREF generator from power-up to power-up. PLL2 Input Reference Divider The VCO CAL divider consists of a prescaler (P) divider and two counters, A and B. The total divider value is VCO CAL divider = (P × B) + A where P = 4. The VCO CAL feedback divider has a dual modulus prescaler architecture with a nonprogrammable P that is equal to 4. The value of the B counter can be from 3 to 63, and the value of the A counter can be from 0 to 3. 16 is the minimum supported divide value. The VCO RF divider (M1) provides frequency division between the internal VCO and the clock distribution. The VCO RF divider can be set to divide by 3, 4, or 5. The VCO RF divider is part of the total PLL2 feedback path value for normal operation. PLL2 Loop Filter The PLL2 loop filter requires the connection of an external capacitor from LF2_CAP (Pin 14) to LDO_VCO (Pin 15). The value of the external capacitor depends on the operating mode and the desired phase noise performance. For example, a loop bandwidth of approximately 500 kHz produces the lowest integrated jitter. A lower bandwidth produces lower phase noise at 1 MHz but increases the total integrated jitter The input reference divider (R1) provides division in integer steps from 1 to 31 with a maximum input frequency of 275 MHz. The divider provides an option to prescale the PFD rate of PLL2 for output frequency planning and to accommodate more flexibility for setting the desired loop bandwidth for PLL2. If the R1 divider is used along with the SYSREF generator, choose the PLL2 feedback path as the input signal of the SYSREF generator to ensure fixed phase alignment of the SYSREF generator from power-up to power-up. Figure 31. PLL2 Loop Filter PLL2 Feedback Dividers Table 22. PLL2 Loop Filter Programmable Values (Register 0x0205) PLL2 has two feedback paths as shown in Figure 30. In normal PLL2 operation mode, the PLL2 feedback path consists of N2 (an 8-bit divider) and M1 (a VCO RF divider). The product of N2 and M1 establishes the total PLL multiplication value for PLL2. RZERO (Ω) CPOLE1 (pF) RPOLE2 (Ω) CPOLE2 (pF) 3250 48 900 Fixed at 16 Typical at 1000 3000 40 450 N/A2 N/A2 2750 32 300 N/A2 N/A2 N/A2 The second feedback path for PLL2 uses the VCO CAL divider (see Figure 30). The VCO CAL divider is exclusively used to calibrate the internal VCO of PLL2. Register 0x0201, Register 0x0204, Register 0x0207, and Register 0x0208 program the PLL multiplication values for both PLL2 feedback paths. The total PLL multiplication in both feedback paths must equal one another for proper VCO calibration. After each VCO calibration, the VCO CAL divider feedback path automatically disables and reverts back to the feedback path with N2 and M1 dividers for normal operation. The VCO CAL divider is not available outside of VCO calibration. analog.com LF2_CAP1 (pF) 2500 24 225 N/A2 2250 16 N/A2 N/A2 N/A2 2100 8 N/A2 N/A2 N/A2 2000 0 N/A2 N/A2 N/A2 N/A2 N/A2 N/A2 1850 1 External loop filter capacitor. 2 N/A means not applicable. VCO The VCO is tunable from 3.450 GHz to 4.025 GHz. The VCO operates off the VCO LDO supply. This LDO requires an external Rev. F | 28 of 67 Data Sheet AD9528 THEORY OF OPERATION compensation cap of 0.47 μF to ground. The VCO requires calibration prior to use. VCO Calibration The AD9528 on-chip VCO must be manually calibrated to ensure proper PLL2 operation over process, supply, and temperature. VCO calibration requires a valid VCXO input clock and applicable preprogrammed PLL1 and PLL2 register values prior to issuing the VCO calibration to ensure a PLL2 phase lock condition. In addition, the value of the VCO CAL feedback divider (see Figure 30) must equal the combined divider values of both the 8-bit N2 divider and RF VCO divider (M1). For example, if the N2 divide value is 10 and the M1 divide value is 3, the total PLL2 multiplication value is 30 in normal operation, so the VCO CAL divider value must be set to 30 prior to initiating a VCO calibration. See the PLL2 Feedback Dividers section for more details. When total PLL2 feedback divider value is 15, see Figure 53 for the detailed procedure. VCO calibration is initiated by transitioning the calibrate VCO bit (Bit 0 of Register 0x0203) from 0 to 1 (this bit is not self clearing). The setting can be performed as part of the initial setup before executing the IO_UPDATE bit (Register 0x000F, Bit 0 = 1). A readback bit, VCO calibration in progress (Register 0x0509, Bit 0), indicates when a VCO calibration is in progress by returning a logic true (that is, Bit 0 = 1), however this bit is automatically cleared after the calibration is finished, so it tells if the calibration started but did not finish. After calibration, initiate a sync (see the Clock Distribution Synchronization section). Synchronization occurs automatically on the first VCO calibration following a power-up or reset. See Figure 53 for the detailed procedure. During power-up or reset, channels driven by the RF VCO driver are automatically held in sync until the first VCO calibration is finished. Therefore, none of those channel outputs can occur until VCO calibration is complete. Initiate a VCO calibration under the following conditions: After changing the PLL2 N2 or M1 divider settings or after a change in the PLL2 reference clock frequency. This means that a VCO calibration must be initiated any time that a PLL2 register or reference clock changes such that a different VCO frequency is the result. ► Whenever system calibration is desired. The VCO is designed to operate properly over temperature extremes, even when it is first calibrated at the opposite extreme. However, a VCO calibration can be initiated at any time. ► To calibrate using the 2× multiplier, the total feedback divide must be >16. If the application requires the use of a feedback divide value