AD9576/PCBZ

Dual PLL, Asynchronous Clock Generator AD9576 Data Sheet FUNCTIONAL BLOCK DIAGRAM APPLICATIONS Ethernet line cards, switches, and routers Baseband units SATA and PCI express Low jitter, low phase noise clock generation Asynchronous clock generation Rev. A SPI/I2C AND PPRx CONTROL OPTIONAL REF2 MUX REF2 GENERALPURPOSE PLL OPTIONAL STATUS MONITOR DIV OUT10 DIV OUT9 OUT8 DIV OUT0 OUT1 OUT2 OUT3 REF0 OPTIONAL REF1 REF1 FRACTIONAL-N PLL REF0 SWITCHOVER AND MONITOR Single, low phase noise, fully integrated VCO/fractional-N PLL core VCO range: 2375 MHz to 2725 MHz Integrated loop filter (requires a single external capacitor) 2 differential, XTAL, or single-ended reference inputs Reference monitoring capability Automatic redundant XTAL switchover Minimal transient, smooth switching Typical RMS jitter 4.7 kHz 1 MHz 255. The 1.8 V charge pump current is user-programmable in increments of 4 µA up to 1.02 mA via the PLL0 charge pump current bits (Register 0x102, Bits[7:0]). The charge pump current is determined by multiplying the bit field value of the PLL0 charge pump current bits by 4 µA. For example, the default setting of 0x8D produces a charge pump current of 141 × 4 µA = 564 µA. PLL0 Loop Filter The loop filter affects the dynamic characteristics of a PLL (for example, lock time and stability). The AD9576 provides both internal and external partially integrated loop filter capabilities for VCO0. The loop filter used is specified by the PLL0 loop filter bypass bit (Register 0x104, Bit 0). Setting this bit to Logic 0 uses the internal loop filter, whereas Logic 1 uses an external loop filter for VCO0. For both the external and internal loop filter, the value of CPOLE2 is fixed internally to 16 pF. Operating VCO0 with the internal loop filter requires a single 4.7 nF external capacitor connected between the LF and LDO_BYP pins. The other loop filter components are internal and can be programmed through the PLL0 loop filter bits (Register 0x103, Bits[7:0]). Note PLL0 uses a static charge pump current; therefore, the nominal bandwidth of 400 kHz varies slightly as the feedback divide ratio deviates from a value of 50. When VCO0 uses the external loop filter, the value of RPOLE2 is internal and set by the PLL0 loop filter RPOLE2 bits (Register 0x103, Bits[7:6]). The remaining components, RZERO, CZERO, and CPOLE1 are external to the AD9576 and are configured by the user. Rev. A | Page 32 of 65 Data Sheet AD9576 LF 660Ω 19 The dual VCO dividers provide flexibility for the output frequencies. VCO Divider M0 drives the Q0, Q1, Q2, Q3, and QZD channel output drivers, whereas VCO Divider M1 only drives the Q1 and Q2 channel dividers. AD9576 INTERNAL 15kΩ 3.9nF 16pF 120nF PLL0 Internal VCO 1. LDO_BYP 13993-025 When using an 8 kHz PFD rate, an external loop filter must be used. Figure 25 shows the recommended external loop filter design for an 8 kHz PFD rate. With a VCO0 frequency of 2500 MHz and a charge pump current of 888 μA (Register 0x102, Bits[7:0] = 0xDE), the loop filter has a bandwidth of 520 Hz with 70° of phase margin. The VCO dividers, M0 and M1, have a synchronous reset function that must be exercised after power-up or a change in divide value to guarantee proper operation. Under normal operation, there is no need for the user to reset the M0 or M1 dividers manually because they are automatically reset by the VCO0 calibration process. However, when the user wants to change the M0 or M1 divider value after the VCO0 calibration, the user must either reissue a VCO0 calibration (see the PLL0 VCO Calibration section) or manually reset the VCO dividers by executing the following sequence: 20 Figure 25. 8 kHz PFD PLL0 External Loop Filter PLL0 incorporates a low phase noise LC tank VCO0. This VCO has 256 frequency bands spanning from 2.375 GHz to 2.75 GHz. A VCO calibration is required to select the appropriate operating frequency band for the programmed divider configuration (see the PLL0 VCO Calibration section). VCO0 has an integrated low dropout (LDO) linear voltage regulator that isolates VCO0 from possible external supply voltage variations. The regulated LDO voltage appears at the LDO_BYP pin. To ensure stability, connect a 0.47 μF chip monolithic ceramic capacitor between this pin and ground. Note that using the LDO_BYP pin to power an external circuit may degrade VCO0 performance. PLL0 VCO Dividers (M0 and M1) The internal VCO of PLL0 operates in the 2.5 GHz range, which is too high to clock the output channel dividers directly. The AD9576 has two independent VCO dividers, M0 and M1, used to scale down the internal VCO frequency to an acceptable range for the output channel dividers. Both the M0 and M1 dividers are programmable over the range of 2 to 11 using the M0 divide ratio and M1 divider ratio bits, Register 0x121, Bits[3:0] and Register 0x121, Bits[7:4], respectively. The values of these bits and their corresponding functions are shown in Table 27. Table 27. VCO Divider Ratio Decode M0 or M1 Divider Ratio Bit Field Value 0 to 1 2 to 11 12 to 15 Divider Operation Power down Divide by this value Power down 2. 3. 4. 5. 6. Force a reset on the M0 VCO divider. Set Register 0x120, Bit 0 = 1. Force a reset on the M1 VCO divider. Set Register 0x120, Bit 4 = 1. Issue an input/output (I/O) update. Write Register 0x00F = 0x01. Clear the M0 VCO divider reset state. Set Register 0x120, Bit 0 = 0. Clear the M1 VCO divider reset state. Set Register 0x120, Bit 4 = 0. Issue an I/O update. Write Register 0x00F = 0x01. Note that, if only a single VCO divider value is changed, only that divider must be reset. However, resetting both dividers simultaneously ensures synchronization between the respective downstream dividers. PLL0 VCO Calibration The AD9576 on-chip VCO0 must be calibrated to ensure proper operation over process and temperature. Calibration centers the VCO0 control voltage at the VCO0 frequency established after PLL0 locks, allowing VCO0 a sufficient operating range to maintain lock over extremes of temperature and voltage. The VCO calibration routine works by comparing the VCO feedback clock to the reference input clock. This requires that a valid reference input clock is present at the time of calibration. Therefore, the LOR status indicator of the PLL0 active reference input is used to gate the VCO calibration operation so that it waits for the presence of a reference input clock. Note that, in Loop Mode 1, the REF0/REF1 frequency may be lower than the detection threshold of the LOR status indicator, causing the LOR status to remain Logic 1 even with a fully valid reference. In this case, the VCO calibration cannot be gated by the PLL0 active reference input LOR status. Therefore, the LOR gating of the calibration is removed when operating in Loop Mode 1 with a total feedback divide value equal to or greater than a value of divide by 512. When these conditions are met, the calibration still waits for the presence of a reference input clock, but no assessment of the frequency accuracy of the signal is made prior to the execution of the calibration. Rev. A | Page 33 of 65 AD9576 Data Sheet When a PPR load is executed on power-up, an automatic calibration sequence is issued following the completion of the load. Otherwise, a manual VCO0 calibration must be initiated via the PLL0 calibration bit (Register 0x100, Bit 3). Setting the PLL0 calibration bit to Logic 1 initiates a calibration of VCO0. The PLL0 calibration bit is not a self clearing bit. Therefore, the bit must be reset to Logic 0 before a subsequent manual calibration can be initiated. The PLL0 calibration in progress bit (Register 0x020, Bit 2) indicates when a VCO0 calibration is occurring. A Logic 1 reported on the PLL0 calibration in progress bit indicates a VCO0 calibration is active, whereas a Logic 0 indicates normal PLL0 operation. After a successful calibration, the VCO operates in a condition with optimal margin to maintain lock in operation across the entire specified temperature range, which includes margin for a deviation in the reference input clock carrier up to ±200 ppm. However, if the active reference clock frequency exceeds this limit, or if the user alters the nominal VCO operating frequency by reconfiguring the reference scaling section or feedback divider, the ability for the PLL to maintain lock over temperature may be compromised. If this occurs, an additional VCO calibration is necessary. To accomplish this, write the following register sequence: 1. 2. 3. 4. Clear the VCO0 calibration bit. Write Register 0x100, Bit 3 = 0. Issue an I/O update. Write Register 0x00F = 0x01. Initiate a manual VCO0 calibration. Write Register 0x100, Bit 3 = 1. Issue an I/O update. Write Register 0x00F = 0x01. Note that, during the first VCO0 calibration sequence after a PLL0 reset or chip level reset, the calibration controller holds the distribution section in sync mode (the channel dividers are held in reset and the output drivers are static) until the calibration terminates. Therefore, no output signals appear until the VCO0 calibration sequence terminates, as indicated by a Logic 1 to Logic 0 transition of the PLL0 calibration in progress bit (Register 0x020, Bit 2). The VCO0 calibration process requires approximately 98,500 cycles of the PFD to complete. Therefore, the calibration time (tVCO_CAL) depends on the input frequency to the PFD (fPFD) as follows: tVCO_CAL = Loop Mode 2 Calibration Considerations When using the PLL0 Loop 2 feedback configuration, the VCO0 calibration requires special treatment because the M0 and QZD dividers stop during VCO0 calibration (a result of the automatic synchronization function imposed during calibration), which prevents the calibration circuitry from receiving the required feedback clock edges. Therefore, the calibration controller detects that Loop 2 is in effect and automatically switches to the Loop 0 configuration to perform the VCO0 calibration sequence. Upon completion of the calibration sequence, the calibration controller automatically restores the Loop 2 configuration. Because the calibration controller uses the Loop 0 configuration, the N0 divider is necessarily in the feedback path during the calibration sequence. Therefore, the user must program the value of the N0 divider before initiating a calibration sequence in the Loop 2 configuration, where N0 = M0 × QZD That is, N0 must match the product of the M0 divider and the QZD channel divider. The N0 divider is programmed via the N0 divider integer value bits (Register 0x107, Bits[7:0]). If M0 × QZD > 255, the N0 feedback divider alone is not large enough to be used during calibration. To properly calibrate VCO0, manually force the AD9576 to operate in Loop 1 during calibration and, following the completion of the calibration, manually force the AD9576 back to Loop 2. Perform these actions using the following sequence: 5. Clear the VCO0 calibration bit. Write Register 0x100, Bit 3 = 0. 6. Set Loop Mode 1. Write Register 0x101, Bits[2:1] = 1. 7. Issue an I/O update. Write Register 0x00F = 0x01. 8. Initiate a manual VCO0 calibration. Write Register 0x100, Bit 3 = 1. 9. Issue an I/O update. Write Register 0x00F = 0x01. 10. Wait for the calibration to complete, the poll until Register 0x020, Bit 2 = 0. 11. Set Loop Mode 2. Write Register 0x101, Bits[2:1] = 2. 12. Issue an I/O update. Write Register 0x00F = 0x01. Note that, in this case, the calibration feedback path consists of the cascade of the N0 and N0A dividers. Therefore, the user must program the N0 and N0A dividers such that N0 × N0A = M0 × QZD 9.85 × 10 4 f PFD Rev. A | Page 34 of 65 Data Sheet AD9576 PLL0 Lock Detect The PLL0 lock detector is a frequency detector that evaluates the frequency difference between the feedback and reference inputs to the PFD. A lock condition is indicated when the average difference between the feedback and reference inputs is less than a magnitude of 16 ppm. The PLL0 lock detect process requires approximately 65,500 cycles of the PFD to complete. Therefore, the lock detect time (tLDET) depends on the input frequency to the PFD (fPFD) as follows: tLDET = 6.5  104 PLL1 INTEGER-N PLL The VCO1 frequency is a function of the PFD1 input frequency and the values programmed into the registers associated with the N1 feedback divider. fVCO1 = fPFD1 × N1 The overall frequency translation is as follows: PLL1 is a fully integrated integer-N PLL consisting of six functional elements: a reference frequency prescalar, a PFD, a charge pump, an internal loop filter, a VCO, and a feedback divider. PLL1 allows two independent reference clock input signals. PLL1 provides up to three outputs segregated into two groups. Each group has a dedicated channel divider allowing the device to produce two different output frequencies simultaneously. Figure 26 shows the functional block diagram of PLL1. CHARGE PUMP VCO1 f REF N1  R1 Qx where: fOUT is the frequency at the output driver, OUTx (OUT8, OUT9, or OUT10). fREF is the frequency of the active reference (REF0, REF1, or REF2). Qx is the channel divider (Q3 or Q4) associated with OUTx. N1 is an element of the following set: {4, 5, …, 255}. LPF 13993-026 PFD ÷N1 ×2 fOUT = R1 is the divider value used to scale the input reference frequency and is an element of the following set: {½, 1, 1.5, 2, 3, 4, 6, 8}. Note the value of ½ is the result of selecting the ×2 reference multiplier (see the PLL1 Reference Frequency Scaling section). PLL1 INTEGER-N REF2 PLL1 Loop Configuration The divider value of N1 is set by programming the N1 divider ratio bits (Register 0x201, Bits[7:0]) to a value between 4 and 255. f PFD PLL0 ACTIVE REFERENCE Note that, when the ×2 frequency multiplier is in use, the active reference signal must have a duty cycle close to 50%. Otherwise, spurious artifacts (harmonics) may propagate through the signal path and appear at the output of PLL1. ÷R1 Figure 26. PLL1 Block Diagram Qx is the divide value of the channel divider and is an element of the following set: {1, 2, …, 64}. PLL1 PFD, Charge Pump, and Loop Filter PLL1 Reference Frequency Scaling The frequency of the active input reference (REF0, REF1, or REF2) is scalable via the PLL1 doubler enable bit (Register 0x202, Bit 0) and the R1 divider ratio bits (Register 0x202, Bits[3:1]). This scaling allows the user to scale the input reference frequency to satisfy the input range of the PFD. When the PLL1 doubler enable bit is set to Logic 0, the frequency appearing at the input to the PFD, fPFD1, is a function of the active reference frequency scaled by the reference input divider. fREF fPFD1 = R1 where: fREF is the frequency of the active reference (REF0, REF1, or REF2). R1 is the value of the R1 reference input divider value. When the PLL1 doubler enable bit is set to Logic 1, the frequency appearing at the input to the PFD, fPFD1, is the active reference frequency multiplied by a factor of 2. fPFD1 = fREF × 2 where fREF is the frequency of the active reference (REF0, REF1, or REF2). The PFD determines the phase difference between the edges of the reference divider output and the feedback divider output. The circuit provides two pulse-width modulated output signals: up and down. These up/down pulses drive the charge pump circuit. The instantaneous phase error determines the amount of charge delivered from the charge pump to the loop filter. The closed-loop of the PLL typically drives the frequency and phase difference between the two PFD input signals towards zero. The loop filter affects the dynamic characteristics of a PLL (for example, lock time and stability). PLL1 has a fully integrated internal loop filter that establishes the loop dynamics for a PFD frequency between 10 MHz and 50 MHz. The charge pump current and loop filter components are automatically adjusted based on the programmed N1 feedback divide value to maintain a nearly constant loop bandwidth over a range of feedback dividers values. Table 28 shows the PLL1 closed-loop bandwidth as a function of the N1 divide value. Table 28. PLL1 Closed-Loop Bandwidth N1 Divide Value 4 to 23 24 to 47 48 to 255 Rev. A | Page 35 of 65 Nominal Closed Loop Bandwidth (MHz) 3.5 1.75 1 AD9576 Data Sheet PLL1 Internal VCO The PLL1 internal VCO has a frequency range of 750 MHz to 825 MHz and a nominal gain of 750 MHz/V, allowing the PLL to support ±3.125% clock margining for an 800 MHz VCO frequency and a 25 MHz PFD frequency by updating the feedback divider on-the-fly. PLL1 Lock Detect The PLL1 lock detect is a phase detector that evaluates the phase difference between the feedback and reference inputs to PFD1. The lock detector operates at the PFD rate, which is of the input clock period. For Output Group 0, if the M0 output clock is 625 MHz, the LSB of this bit field corresponds to 800 ps of phase delay and an initial phase offset value of 23 delays the first edge of the Q0 divider output by 18.4 ns relative to an initial phase offset value of 0. To guarantee the initial phase offset of the Qx channel divider, a synchronization command must be executed on Qx after the corresponding Qx initial phase bit field is programmed by the user. Refer to the Synchronization section for additional information regarding this process. A lock condition is indicated when the phase error between the feedback and reference inputs to PFD1 is less than 3.25 ns. Typically, a lock condition for PLL1 is declared 420 µs after the release of RESET, assuming a valid input clock is available. Each channel divider can be independently powered down using the respective power-down bits. These bits are the Q0 PD (Register 0x140, Bit 6), Q1 PD (Register 0x146, Bit 6), Q2 PD (Register 0x14A, Bit 6), Q3 PD (Register 0x240, Bit 6), and Q4 PD (Register 0x244, Bit 6) bits in the serial register. When the channel divider power-down bit is set to Logic 1, the respective channel divider powers down, whereas Logic 0 powers up the channel divider for normal operation. OUTPUT DISTRIBUTION Input Sources fVCO1 fPFD1 = N1 The output distribution is segmented into five groups of outputs (Output Group 0, Output Group 1, Output Group 2, Output Group 3, and Output Group 4) with each group having several output drivers that share a channel divider. The output groups, corresponding channel dividers, output drivers, and input clock source(s) are shown in Table 29. Table 29. Distribution Output Groups Output Group 0 Channel Divider Q0 1 2 3 Q1 Q2 Q3 Output Driver(s) OUT0, OUT1, OUT2, OUT3 OUT4, OUT5 OUT6, OUT7 OUT8, OUT9 4 Q4 OUT10 Frequency Source(s) PLL0 (M0) PLL0 (M0 and M1) PLL0 (M0 and M1) PLL0 (M0), PLL1 output, PLL1 reference PLL1 output, PLL1 reference Channel Dividers There are a total of six, 6-bit integer channel dividers: Q0, Q1, Q2, Q3, Q4, and QZD. The divider ratio is programmable using the Qx divider ratio bits, Register 0x140, Bits[5:0], Register 0x146, Bits[5:0], Register 0x14A, Bits[5:0], Register 0x240, Bits[5:0], Register 0x244, Bits[5:0], and Register 0x110, Bits[5:0] for Q0, Q1, Q2, Q3, Q4, and QZD, respectively. Each channel divider can operate in divide ratios of 1 to 64. The default divide ratio for each channel divider is divide by 4, with the exception of QZD, which has a default value of 1. The initial phase offset for each channel divider is programmable through the Qx initial phase bit fields: Register 0x141, Bits[5:0], Register 0x147, Bits[5:0], Register 0x14B, Bits[5:0], Register 0x241, Bits[5:0], Register 0x245, Bits[5:0], and Register 0x110, Bits[5:0] for Q0, Q1, Q2, Q3, Q4, and QZD, respectively. The bit fields each have a programming range of 0 to 63 in units of half cycles The Q0 and QZD channel dividers are driven solely by the M0 VCO divider output clock. The Q1 and Q2 channel dividers can be driven by the output clock from either VCO divider, M0 or M1. The user must select which VCO divider is driving the Q1 and Q2 channel dividers using the Qx source bits (Register 0x147, Bit 6 for the Q1 source and Register 0x14B, Bit 6 for the Q2 source). Programming either Qx source bit to Logic 0 selects the M0 output clock as the input clock for the channel divider, whereas Logic 1 selects the M1 output clock as the channel divider input clock. The Q3 channel divider can be driven by the output clock from the M0 VCO divider or the output of PLL1, fVCO1. The user must select which input is driving the Q3 channel divider using the Q3 source bit (Register 0x241, Bit 6). Programming this bit to Logic 0 selects the PLL1 output as the Q3 input, whereas a Logic 1 selects the M0 output as the Q3 input. The Q4 channel divider is driven solely by the output of PLL1, fVCO1. Synchronization Each channel divider has a sync input that allows the divider to be placed into a known phase, determined by its initial phase bit field. When the sync input is Logic 1, the divider is held in reset, which establishes the initial phase of the divider. When the sync input is logic low, the divider is in normal operation. Coordinating the Logic 1 to Logic 0 transition of the sync input of multiple channel dividers to occur simultaneously results in a deterministic initial phase alignment between the outputs of said dividers. Provided the set of synchronized dividers share a common input clock, the initial phase alignment is repeated at a rate equal to the GCD between all channel divider outputs. Rev. A | Page 36 of 65 Data Sheet AD9576 As an example, assume the Q0 output is 50 MHz and the Q1 output is 100 MHz. The outputs have a GCD equal to 50 MHz; therefore, the initial phase relationship between the Q0 and Q1 channel divider outputs repeats every 20 ns (for example, at a 50 MHz rate). Consider another example: assume that the Q0 output is 50 MHz, the Q1 output is 100 MHz, and the Q2 output is 125 MHz. The outputs have a GCD equal to 25 MHz; therefore, the initial phase relationship between the Q0, Q1, and Q2 channel divider outputs repeats every 40 ns (for example, at a 25 MHz rate). Four synchronization domains exist to facilitate the synchronization of multiple channel dividers. A single synchronization domain is a grouping of channel dividers in which the sync inputs of each channel divider are tied to a common control bit. The channel dividers are grouped based on their selected input source, and the four domains are as follows: • • • • M0 sync domain. This domain includes all channel dividers that are configured to use the M0 VCO divider as the input clock source. M1 sync domain. This domain includes all channel dividers that are configured to use the M1 VCO divider as the input clock source. PLL0 sync domain. This domain includes consists of the aggregate of the M0 and M1 sync domains. PLL1 sync domain. This domain includes includes all channel dividers that are configured to use the PLL1 output as the input clock source Each sync domain has an associated manual sync bit— Register 0x120, Bit 2, Register 0x120, Bit 6, Register 0x100, Bit 2, and Register 0x200, Bit 2 for the M0, M1, PLL0, and PLL1 sync domains, respectively. Each manual sync bit allows user control of the divider sync inputs, but there are also automatically generated signals that are logically OR’ed with the manual sync bits of the individual sync domains. The actions that generate these automatically generated sync signals are described as follows, for the sync domains they affect: • • • • M0 sync domain. Deassertion of the M0 reset bit (Register 0x120, Bit 0) and deassertion of the M0 power-down bit (Register 0x120, Bit 1). M1 sync domain. Deassertion of the M1 reset bit (Register 0x120, Bit 4) and deassertion of the M1 powerdown bit (Register 0x120, Bit 5). PLL0 sync domain. Completion of the first VCO0 calibration routine issued after the deassertion of any chip level reset or deassertion of the PLL0 reset bit (Register 0x100, Bit 0). Note that this automatic sync affects both the M0 and M1 sync domains. PLL1 sync domain. Deassertion of the PLL1 reset bit (Register 0x200, Bit 0). To manually synchronize a sync domain, the user must program the associated manual sync bit to a Logic 1 followed by a Logic 0. The following example shows the required sequence for the PLL0 synchronization domain: 13. 14. 15. 16. Set the PLL0 sync bit. Write Register 0x100, Bit 2 = 1. Issue an I/O update. Write Register 0x00F = 0x01. Clear the PLL0 sync bit. Write Register 0x100, Bit 2 = 0. Issue an I/O update. Write Register 0x00F = 0x01. Note that the M0 and M1 sync domains (and therefore the PLL0 sync domain) have mask sync bits (see the Register 0x122 description in Table 48). Setting a channel divider mask sync bit for a particular sync domain precludes said sync domain from affecting the operation of that channel divider. For example, if the Q1, Q2, and Q3 source bits are all programmed to Logic 0, the M0 sync domain includes the Q0, Q1, Q2, and QZD channel dividers, the M1 sync domain does not include channel dividers, and the PLL1 sync domain includes the Q3 and Q4 channel dividers. Programming the M0 mask sync Q2 (Register 0x122, Bit 2) to Logic 1 results in the Q2 channel divider being unaffected by a M0 or PLL0 sync command. Programming the M1 mask sync Q2 (Register 0x122, Bit 6) to Logic 1 has no functional impact because Q2 is not a part of the M1 sync domain in this configuration. Output Driver Sources The output drivers in Output Group 0, Output Group 1, and Output Group 2 (see Table 29) are driven by the outputs of their respective channel divider. For example, OUT4 and OUT5 in Output Group 1 are driven by the output of the Q1 channel divider. Output Group 3 or Output Group 4 can be driven by the output of their respective channel divider or by the PLL1 active input reference. The user must select which source is driving the outputs in Output Group 3 and Output Group 4. For Output Group 3, this is accomplished by programming the OUT89 source bit (Register 0x241, Bit 7). Programming this bit to Logic 0 selects the Q3 output as the input for the OUT8/OUT9 output drivers, whereas a Logic 1 selects the PLL1 active input reference as the input to the output drivers. Note that, if the PLL1 active input reference is selected as the source to an output group and the PLL1 active input reference is configured for a XTAL, the PLL1 active input reference loss of reference signal gates the output drivers of the output group. The input clock source for OUT10 is selected via the OUT10 source bit (Register 0x245, Bit 6). Programming this bit to Logic 0 selects the output of the Q4 divider as the clock source for OUT10, whereas a Logic 1 selects the PLL1 active input reference as the OUT10 clock source. Note that, if none of the 3-channel output drivers, OUT8, OUT9, or OUT10, use the PLL1 output as their input, then the PLL1 power-down signal is automatically asserted, and PLL1 is powered down. Rev. A | Page 37 of 65 AD9576 Data Sheet Output Power-Down The eight output drivers, OUT0 through OUT7, have independent power-down control via the corresponding OUTx PD bits in the serial register. For example, the OUT0 output driver is powered down via the OUT0 PD bit (Register 0x142, Bit 2). When the corresponding OUTx PD bit is set to Logic 1, OUTx is powered down; otherwise, it is powered on and functionally operational. The three output drivers, OUT8, OUT9, and OUT10 have independent power-down control via the corresponding OUTx enable bits. For example, the OUT8 output driver is powered down via the OUT8 enable bit (Register 0x242, Bit 0). When the corresponding driver enable bit is set to Logic 0, the OUTx output driver is powered down. Likewise, OUTx is powered up when the corresponding OUTx PD bit is set to Logic 1. Output Driver Format The OUT0 through OUT7 output channels support HSTL, LVDS, and 1.8 V CMOS outputs. The user has independent control of the operating mode of each of the eight output channels via the OUTx driver format bits in the serial register (for example, Register 0x142, Bits[1:0] for OUT0). Table 49 contains a detailed description of the OUTx driver format bit fields for OUT0 through OUT7. The differential resistive load termination is removed for 1.8 V CMOS outputs. When an OUT0 through OUT7 driver is configured as 1.8 V CMOS, the positive and negative pins are in a complimentary phase relationship (for example, 180° offset). Use HSTL format and ac couple the output signal for an LVPECL-compatible output. The OUT8, OUT9, and OUT10 output channels also support HSTL, LVDS, and 1.8 V CMOS outputs as well as HCSL and full swing CMOS outputs. The user has independent control of the operating mode of OUT8, OUT9, and OUT10 through the OUTx driver format bits (Register 0x242, Bits[6:4], Register 0x243, Bits[6:4], and Register 0x246, Bits[6:4]). Table 51 contains a detailed description of the OUTx driver format bit fields for OUT8, OUT9, and OUT10. When OUT8, OUT9, or OUT10 are operating in the CMOS output format, the user must select the output swing level via the OUTx CMOS enable full swing bits (Register 0x242, Bit 7, Register 0x243, Bit 7, and Register 0x246, Bit 7). For example, OUT8 is controlled via the OUT8 CMOS enable full swing bit (Register 0x242, Bit 7). When the OUTx CMOS enable full swing bit is set to Logic 0, the CMOS ouput of the corresponding driver has a 1.8 V swing. When the OUTx CMOS enable full swing bit is set to Logic 1, the CMOS swing is determined by the voltage applied to VDD_OUTx. Only set the OUTx CMOS enable full swing bits to Logic 1 if the associated output format is configured as CMOS. When OUT8, OUT9, or OUT10 is operating in the CMOS output format, the user must also select the polarity of the output driver via the OUTx CMOS polarity bits (Register 0x242, Bits[3:2], Register 0x243, Bits[3:2], and Register 0x246, Bits[3:2]). For example, the polarity of OUT8 is controlled via the OUT8 CMOS polarity bits (Register 0x242, Bits[3:2]). Table 51 contains a detailed description of the OUTx CMOS polarity bit fields for OUT8, OUT9, and OUT10. Additionally, when the output format for OUT8, OUT9, or OUT10 is configured for either LVDS or full swing CMOS, the driver strength of the output is determined by the OUTx drive strength bits (Register 0x242, Bit 1, Register 0x243, Bit 1, and Register 0x246, Bit 1 for OUT8, OUT9, and OUT10, respectively). When operating in the LVDS output format (OUTx driver format bit = 010), programming this bit to Logic 0 results in an output drive strength of 3.5 mA, whereas a Logic 1 produces a drive strength of 4.5 mA. When operating in the full swing CMOS output format, programming this bit to Logic 0 results in nominal output drive strength, whereas a Logic 1 results in low output drive strength that can be used to minimize coupling effects. The drive strength bit only applies to the full swing CMOS format. The 1.8 V swing CMOS output drivers only operate in a low drive strength mode. PPRx PINS The AD9576 makes use of four PPRx pins to configure the device. Internal circuitry scans the PPRx pins for the presence of resistor terminations and configures the device accordingly. A PPRx pin scan occurs automatically as part of the power-on reset sequence (see the Power-On Reset (POR) section) or following the assertion of the RESET pin. Each PPRx pin controls a specific function or functional block within the device (see Table 30). The power-on configuration of a functional block depends on the scanned state of the corresponding PPRx pin. The scan of a PPRx pin identifies one of eight possible states based on an external pull-up or pull-down resistor (maximum 10% tolerance) per Table 31. Table 30. PPRx Pin Function Assignments Mnemonic PPR0 Pin No. 24 PPR1 PPR2, PPR3 26 32, 56 Rev. A | Page 38 of 65 Function Assignment Input receiver configurations, PLL1 source, and PLL input doubler states OUT10 configuration PLL0 frequency translation and OUT0 to OUT9 configuration Data Sheet AD9576 Device programming consists of connecting the appropriate value programming resistors to the PPRx pins and terminating the resistors to VDD_x or GND (per Table 31). For example, Figure 27 shows how to program PPR0 to State 3. For details regarding the device configuration based on the scanned PPRx states, refer to the description of each PPRx pin in the following sections. Table 31. PPRx State The PPR0 pin controls the configuration of the reference clock inputs (REF0, REF1, REF2) and the select line of the PLL1 reference input mux. Table 32 associates each PPR0 state with a particular reference input configuration and PLL1 source combination. PPRx State 0 1 2 3 4 5 6 7 Resistance 820 Ω 1.8 kΩ 3.9 kΩ 8.2 kΩ 820 Ω 1.8 kΩ 3.9 kΩ 8.2 kΩ Terminus GND GND GND GND VDD VDD VDD VDD PPR1—OUT10 Configuration The PPR1 pin controls the frequency, driver format, and source of OUT10, which requires the PLL1 reference input, and therefore REF2, if used, to be 25 MHz. Note that, if REF0/REF1 is configured to a frequency other than 25 MHz, the PLL1 source must be configured as REF2. Table 33 associates each PPR1 state with a particular OUT10 configuration. AD9576 PPR0 8.2kΩ PPR2 and PPR3—REF0/REF1 Frequency and OUT0 to OUT9 Configuration The PPR2 and PPR3 pins control the configuration of the REF0 and REF1 input frequency, PLL0, OUT0 to OUT9 driver format and frequency, and the OUT8 to OUT9 source. Table 34 associates each combination of PPR2 and PPR3 states with a particular predefined frequency translation. 13993-027 24 PPR0—Reference Clock Input Configuration Figure 27. PPRx Programming Resistor Example Table 32. PPR0—Input Receiver Formats and PLL1 Source PPR0 State 0 1 2 3 4 5 6 7 REF0/REF1 Input Configuration XTAL 2.5 V/3.3 V CMOS 2.5 V/3.3 V CMOS Differential/1.8 V LVCMOS XTAL 2.5 V/3.3 V CMOS Differential/1.8 V LVCMOS Differential/1.8 V LVCMOS REF2 Input Configuration 2.5 V/3.3 V CMOS 2.5 V/3.3 V CMOS 2.5 V/3.3 V CMOS 2.5 V/3.3 V CMOS XTAL 2.5 V/3.3 V CMOS XTAL 2.5 V/3.3 V CMOS PLL1 Source PLL0 active reference PLL0 active reference PLL0 active reference PLL0 active reference REF2 REF2 REF2 REF2 PLL0 Doubler Enabled Enabled Disabled Disabled Enabled Enabled Enabled Enabled PLL1 Doubler Disabled Disabled Disabled Disabled Disabled Disabled Disabled Disabled Table 33. PPR1—OUT10 Configuration PPR1 State 0 1 2 3 4 5 6 7 OUT10 Frequency (MHz) 25 33.3 (100/3) 50 66.67 (200/3) 100 133.3 (400/3) 200 400 OUT10 Format 2.5 V/3.3 V CMOS 2.5 V/3.3 V CMOS 2.5 V/3.3 V CMOS 2.5 V/3.3 V CMOS LVDS LVDS LVDS LVDS Rev. A | Page 39 of 65 OUT10 Source PLL1 reference PLL1 output PLL1 output PLL1 output PLL1 output PLL1 output PLL1 output PLL1 output AD9576 Data Sheet Table 34. PPR2 and PPR3—REF0/REF1 Frequency and OUT0 to OUT9 Configuration 1 PPR2 State 0 0 0 0 PPR3 State 0 1 2 3 REF0/REF1 Frequency (MHz) 25 25 25 25 OUT0 to OUT3 Frequency (MHz) Format Disabled N/A 156.25 HSTL 156.25 LVDS 156.25 HSTL OUT4 to OUT5 Frequency (MHz) Format Disabled N/A 156.25 HSTL 156.25 LVDS 156.25 HSTL OUT6 to OUT7 Frequency (MHz) Format Disabled N/A 156.25 HSTL 156.25 LVDS 100 HSTL Frequency (MHz) Disabled 156.25 156.25 25 0 4 25 156.25 LVDS 156.25 LVDS 100 HSTL 25 0 5 25 156.25 HSTL 125 HSTL 100 HSTL 50 0 6 25 156.25 HSTL 125 HSTL 100 HSTL 25 0 7 25 156.25 LVDS 125 LVDS 100 HSTL 25 1 0 25 156.25 LVDS 125 LVDS 25 HSTL 25 1 1 25 156.25 HSTL 125 HSTL 25 HSTL 25 1 1 1 2 3 4 25 25 25 156.25 156.25 156.25 HSTL LVDS LVDS 100 100 100 HSTL LVDS LVDS 50 50 100 HSTL HSTL LVDS 125 125 25 1 5 25 156.25 HSTL 100 HSTL 25 HSTL 25 1 6 25 156.25 LVDS 100 LVDS 25 HSTL 25 1 2 2 7 0 1 25 25 25 156.25 156.25 156.25 HSTL LVDS HSTL 100 100 312.5 HSTL LVDS HSTL 125 125 125 HSTL LVDS HSTL 312.5 312.5 25 Format N/A HSTL LVDS 2.5 V/3.3 V CMOS 2.5 V/3.3 V CMOS 2.5 V/3.3 V CMOS 2.5 V/3.3 V CMOS 2.5 V/3.3 V CMOS 2.5 V/3.3 V CMOS 2.5 V/3.3 V CMOS HSTL HSTL 2.5 V/3.3 V CMOS 2.5 V/3.3 V CMOS 2.5 V/3.3 V CMOS HSTL LVDS HSTL 2 2 25 156.25 LVDS 312.5 LVDS 125 LVDS 25 LVDS 2 2 2 2 2 3 3 3 3 3 3 4 5 6 7 0 1 2 3 4 25 25 25 25 25 25 25 25 25 25 312.5 312.5 312.5 312.5 312.5 312.5 625 100 100 100 HSTL LVDS HSTL LVDS HSTL LVDS HSTL HSTL LVDS HSTL 100 100 100 100 100 100 100 312.5 312.5 312.5 HSTL LVDS HSTL LVDS HSTL LVDS LVDS HSTL LVDS HSTL 100 100 125 125 156.25 156.25 100 156.25 156.25 156.25 HSTL LVDS HSTL LVDS HSTL LVDS LVDS HSTL LVDS HSTL 156.25 156.25 156.25 156.25 156.25 156.25 156.25 125 125 25 HSTL LVDS HSTL LVDS HSTL LVDS HSTL HSTL LVDS HSTL 3 5 25 100 LVDS 312.5 LVDS 156.25 LVDS 25 LVDS 3 3 4 4 4 4 4 6 7 0 1 2 3 4 25 25 25 25 25 25 25 100 100 125 125 125 125 125 HSTL LVDS HSTL LVDS HSTL LVDS HSTL 100 100 125 125 100 100 100 HSTL LVDS HSTL LVDS HSTL LVDS HSTL 100 100 125 125 100 100 25 HSTL LVDS HSTL LVDS HSTL LVDS HSTL 100 100 125 125 100/3 100/3 25 HCSL HCSL HSTL LVDS HSTL LVDS HSTL 4 5 25 125 LVDS 100 LVDS 25 LVDS 25 LVDS 4 4 6 7 25 25 25 100 LVDS LVDS 25 100 LVDS LVDS 125 125 LVDS HSTL 100 25 5 0 25 100 HSTL 100 HSTL 125 HSTL 25 HCSL 2.5 V/3.3 V CMOS 2.5 V/3.3 V CMOS Rev. A | Page 40 of 65 OUT8 to OUT9 Source N/A PLL0 PLL0 PLL1 source PLL1 source PLL1 PLL1 source PLL1 source PLL1 source PLL1 source PLL0 PLL0 PLL1 source PLL1 source PLL1 source PLL0 PLL0 PLL1 source PLL1 source PLL0 PLL0 PLL0 PLL0 PLL0 PLL0 PLL0 PLL0 PLL0 PLL1 source PLL1 source PLL0 PLL0 PLL0 PLL0 PLL1 PLL1 PLL1 source PLL1 source PLL0 PLL1 source PLL1 source Data Sheet AD9576 PPR2 State 5 PPR3 State 1 REF0/REF1 Frequency (MHz) 25 OUT0 to OUT3 Frequency (MHz) Format 156.25 HSTL OUT4 to OUT5 Frequency (MHz) Format 50 HSTL OUT6 to OUT7 Frequency (MHz) Format 125 HSTL Frequency (MHz) 25 5 2 25 156.25 LVDS 50 LVDS 125 LVDS 25 5 5 5 5 5 62 3 4 5 6 7 02 25 25 25 25 25 25 100 100 25 156.25 156.25 70.656 HSTL LVDS HSTL HSTL LVDS HSTL 100 100 25 50 50 70.656 HSTL LVDS HSTL HSTL LVDS HSTL 100 100 25 125 125 70.656 HSTL LVDS HSTL HSTL LVDS HSTL 100 100 400 400 400 25 62 12 25 24.576 HSTL 24.576 HSTL 24.576 HSTL 100 HCSL Source PLL1 source PLL1 source PLL1 PLL1 PLL1 PLL1 PLL1 PLL1 source PLL1 2 2 25 24.576 LVDS 24.576 LVDS 24.576 LVDS 100 HCSL PLL1 6 2 3 25 HSTL HSTL HSTL 100 HCSL PLL1 62 42 25 LVDS 100 HCSL PLL1 62 52 2 6 2 2 OUT8 to OUT9 Format 2.5 V/3.3 V CMOS 2.5 V/3.3 V CMOS HCSL HCSL LVDS HCSL HCSL HSTL 25 312.5 × (33/32) 312.5 × (33/32) 148.5 HSTL 156.25 × (33/32) 156.25 × (33/32) 148.5 HSTL 156.25 × (33/32) 156.25 × (33/32) 148.5 HSTL 100 HCSL PLL1 6 63 62 25 148.5 LVDS 148.5 LVDS 148.5 LVDS 100 HCSL PLL1 73 19.44 625 × (33/32) HSTL HSTL 100 HCSL PLL1 03 19.44 625 × (33/32) LVDS LVDS 100 HCSL PLL1 73 13 19.44 156.25 HSTL HSTL 156.25 × (33/32) 156.25 × (33/32) 50 HSTL 73 156.25 × (33/32) 156.25 × (33/32) 125 HSTL 100 LVDS PLL1 3 7 23 19.44 156.25 LVDS 125 LVDS 50 LVDS 100 LVDS PLL1 73 33 30.72 156.25 HSTL 50 HSTL 125 HSTL 25 PLL0 73 43 30.72 156.25 LVDS 50 LVDS 125 LVDS 25 PLL0 73 53 30.72 156.25 HSTL 125 HSTL 50 HSTL 100 2.5 V/3.3 V CMOS 2.5 V/3.3 V CMOS HCSL 3 63 7 30.72 156.25 LVDS 125 LVDS 50 LVDS 100 HCSL PLL1 7 7 1 2 3 LVDS LVDS LVDS PLL1 Reserved N/A means not applicable. Frequency translation requires the PLL0 input doubler to be enabled. Only valid if PPR0 = 0, 1, 4, 5, 6, or 7. PLL1 input must be 25 MHz. Only valid if PPR0 = 4, 5, 6, or 7. POWER-ON RESET (POR) Applying power to the AD9576 causes an internal power-on reset (POR) event. A POR event allows the device to initialize to a known state at power-up by initiating a scan of the PPRx pins (see the PPRx Pins section). In general, the AD9576 follows an orderly power-on sequence beginning with the POR circuit detecting a valid 2.5 V or 3.3 V supply. This activates the internal LDO regulators. Detection of valid LDO voltages by the POR circuit triggers a PPRx scan sequence, which results in the configuration of the internal registers. With a reference signal applied to the input of each PLL, the VCO0 calibration sequence initiates, while PLL1 immediately begins locking to the reference. Assuming a valid input reference signal, the PLLs eventually locks to the reference signal(s), as indicated by assertion of the LD_0 pin and the LD_1 pin. These lock signals enable the prescale dividers at the output of each VCO, which starts the output drivers toggling (that is, those output drivers enabled per the PPRx settings). Rev. A | Page 41 of 65 AD9576 Data Sheet SERIAL CONTROL PORT The AD9576 serial control port is a flexible, synchronous serial communications port that provides a convenient interface to many industry-standard microcontrollers and microprocessors. The AD9576 serial control port is compatible with I²C and SPI. The serial control port allows read/write access to the AD9576 register map. The AD9576 uses the Analog Devices unified SPI protocol (see the Analog Devices Serial Control Interface Standard) implementation, but does not support a 4-wire protocol with dedicated input and output data pins. Rather, only a 3-wire mode with a single, bidirectional data pin is supported. The SPI port configuration is programmable via Register 0x000. This register is a part of the SPI control logic rather than in the register map and is distinct from the I2C Register 0x000. Although the AD9576 supports both the SPI and I C serial port protocols, only one is active following power-up (as determined by the SP0 and SP1 pins during the start-up sequence). The only way to change the serial port protocol is to reset (or power cycle) the device. 2 SPI/I²C PORT SELECTION Because the AD9576 supports both SPI and I2C protocols, the active serial port protocol depends on the logic state of the SP0 and SP1 pins at reset or power-on. See Table 35 for the serial port configuration decode. Table 35. SPI/I²C Serial Port Setup SP1 Floating 0 1 Floating 0 1 Floating 0 1 SP0 Floating Floating Floating 0 0 0 1 1 1 SPI/I²C Address SPI with PPRx load I²C, 0111001 (0x39) I²C, 0111010 (0x3A) I²C, 0111011 (0x3B) I²C, 0111100 (0x3C) I²C, 0111101 (0x3D) I²C, 0111110 (0x3E) I²C, 0111111 (0x3F) SPI The CS (chip select) pin is an active low control that gates read and write operations. Assertion (active low) of the CS pin initiates a write or read operation to the AD9576 SPI port. Any number of data bytes can be transferred in a continuous stream. The register address is automatically incremented or decremented based on the setting of the address ascension bit (Register 0x000). CS must be deasserted at the end of the last byte transferred, thereby ending the stream mode. When CS is high, the SDIO pin goes into a high impedance state. Implementation Specific Details The following product specific items are defined in the unified SPI protocol: • • • • • • • Analog Devices unified SPI protocol revision: 1.0 Chip type: 0x5 Product ID: 0x014F Physical layer: 3-wire supported and 2.5 V and 3.3 V operation supported Optional single-byte instruction mode: not supported Data link: not used Control: not used Communication Cycle—Instruction Plus Data The unified SPI protocol consists of a two part communication cycle. The first part is a 16-bit instruction word that is coincident with the first 16 SCLK rising edges and a payload. The instruction word provides the AD9576 serial control port with information regarding the payload. The instruction word includes the R/W bit that indicates the direction of the payload transfer (that is, a read or write operation). The instruction word also indicates the starting register address of the first payload byte. Write SPI SERIAL PORT OPERATION Pin Descriptions The SCLK (serial clock) pin serves as the serial shift clock. This pin is an input. SCLK synchronizes serial control port read and write operations. The rising edge SCLK registers write data bits, and the falling edge registers read data bits. The SCLK pin supports a maximum clock rate of 50 MHz. The SPI port supports only a 3-wire (bidirectional) hardware configuration. This 3-wire mode uses the SDIO (serial data input/output) pin for transferring data in both directions. Both MSB first and LSB first data formats are supported and are software programmable. If the instruction word indicates a write operation, the payload is written into the serial control port buffer of the AD9576. Data bits are registered on the rising edge of SCLK. Generally, it does not matter what data is written to blank registers; however, it is customary to use 0s. Note that the user must verify that all reserved registers within a specific range have a default value of 0x00; however, Analog Devices makes every effort to avoid having reserved registers with nonzero default values. Most of the serial port registers are buffered. Therefore, data written into buffered registers does not take effect immediately. An additional operation is needed to transfer buffered serial control port contents to the registers that actually control the device. This transfer is accomplished with an I/O update operation, which is performed by writing a Logic 1 to Register 0x00F, Bit 0 (this bit is an autoclearing bit). The user can change as many register bits as desired before executing an I/O update. The I/O update operation transfers the buffer register contents to their active register counterparts. Rev. A | Page 42 of 65 Data Sheet AD9576 Read 1. Immediately after the LSB first bit(s) is set, subsequent serial control port operations are LSB first. If the instruction word indicates a read operation, the next N × 8 SCLK cycles clock out the data starting from the address specified in the instruction word. N is the number of data bytes read. The read back data is driven to the pin on the falling edge and must be latched on the rising edge of SCLK. Blank registers are not skipped over during read back. Address Ascension If the address ascension bits (Register 0x0000, Bit 5 and Bit 2) are zero, the serial control port register address decrements from the specified starting address toward Address 0x0000. If the address ascension bits (Register 0x0000, Bit 5 and Bit 2) are one, the serial control port register address increments from the starting address toward Address 0x7FFF. Reserved addresses are not skipped during multi-byte input/output operations; therefore, write the default value to a reserved register and 0s to unmapped registers. Note that it is more efficient to issue a new write command than to write the default value to more than two consecutive reserved (or unmapped) registers. A read back operation takes data from either the serial control port buffer registers or the active registers, as determined by Register 0x001, Bit 5. SPI Instruction Word (16 Bits) The MSB of the 16-bit instruction word is R/W, which indicates whether the instruction is a read or a write. The next 15 bits are the register address (A14 to A0), which indicates the starting register address of the read/write operation (see Table 37). Table 36. Streaming Mode (No Addresses Skipped) SPI MSB/LSB First Transfers Address Ascension Increment Decrement The AD9576 instruction word and payload can be MSB first or LSB first. The default for the AD9576 is MSB first. The LSB first mode can be set by writing a 1 to Register 0x0000, Bit 6 and Bit Stop Sequence 0x0000 … 0x7FFF 0x7FFF … 0x0000 Table 37. Serial Control Port, 16-Bit Instruction Word MSB I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 LSB I0 R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Table 38. Serial Control Port Timing Parameter tDS tDH tSCLK tS tC tHIGH tLOW tDV Description Setup time between data and the rising edge of SCLK Hold time between data and the rising edge of SCLK Period of the clock Setup time between the CS falling edge and the SCLK rising edge (start of the communication cycle) Setup time between the SCLK rising edge and CS rising edge (end of the communication cycle) Minimum period that SCLK should be in a logic high state Minimum period that SCLK should be in a logic low state SCLK to valid SDIO (see Figure 36) CS SCLK DON'T CARE R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 16-BIT INSTRUCTION HEADER A1 A0 D7 D6 D5 D4 D3 D2 D1 REGISTER (N) DATA D0 D7 D6 D5 Figure 28. Serial Control Port Write—MSB First, Address Decrement, Two Bytes of Data Rev. A | Page 43 of 65 D4 D3 D2 D1 D0 REGISTER (N – 1) DATA DON'T CARE 13993-028 SDIO DON'T CARE DON'T CARE AD9576 Data Sheet tDS tHIGH tS tDH CS DON'T CARE SDIO DON'T CARE DON'T CARE R/W A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 D4 D3 D2 D1 D0 DON'T CARE 13993-029 SCLK tC tSCLK tLOW Figure 29. Timing Diagram for Serial Control Port Write—MSB First CS SCLK SDIO DATA BIT N 13993-030 tDV DATA BIT N – 1 Figure 30. Timing Diagram for Serial Control Port Register Read—MSB First CS SCLK DON'T CARE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 R/W D0 D1 D2 D3 D4 16-BIT INSTRUCTION HEADER D5 D6 REGISTER (N) DATA D7 D0 D1 D2 D3 D4 D5 D6 D7 DON'T CARE 13993-031 SDIO DON'T CARE DON'T CARE REGISTER (N + 1) DATA Figure 31. Serial Control Port Write—LSB First, Address Increment, Two Bytes of Data CS tS tC tSCLK tHIGH tLOW tDS SCLK SDIO BIT N BIT N + 1 13993-032 tDH Figure 32. Timing Diagram for Serial Control Port—Write I2C SERIAL PORT OPERATION The I2C interface is popular because it requires only two pins and easily supports multiple devices on the same bus. Its main disadvantage is programming speed, which is 400 kbps maximum. The AD9576 I2C port design uses the I2C fast mode; however, it supports both the 100 kHz standard mode and 400 kHz fast mode. The AD9576 I2C port consists of a serial data line (SDA) and a serial clock line (SCL). In an I2C bus system, the AD9576 is connected to the serial bus (data bus SDA and clock bus SCL) as a slave device; that is, no clock is generated by the AD9576. The AD9576 uses direct 16-bit memory addressing instead of more common 8-bit memory addressing. The AD9576 does not strictly adhere to every requirement in the original I2C specification. In particular, specifications such as slew rate limiting and glitch filtering are not implemented. Therefore, the AD9576 is I2C-compatible, but may not be fully I2C compliant. The AD9576 allows up to seven unique slave devices to occupy the I2C bus. These are accessed via a 7-bit slave address transmitted as part of an I2C packet. Only the device with a matching slave address responds to subsequent I2C commands. Table 35 lists the supported device slave addresses. Rev. A | Page 44 of 65 Data Sheet AD9576 I2C Bus Characteristics Data Transfer Process 2 A summary of the various I C abbreviations appears in Table 39. The master initiates data transfer by asserting a start condition, which indicates that a data stream follows. All I2C slave devices connected to the serial bus respond to the start condition. Table 39. I2C Bus Abbreviation Definitions Abbreviation S Sr P A A W R Definition Start Repeated start Stop Acknowledge No acknowledge Write Read The master then sends an 8-bit address byte over the SDA line, consisting of a 7-bit slave address (MSB first) plus an R/W bit. This bit determines the direction of the data transfer, that is, whether data is written to or read from the slave device (0 = write and 1 = read). The peripheral whose address corresponds to the transmitted address responds by sending an acknowledge bit. All other devices on the bus remain idle while the selected device waits for data to be read from or written to it. If the R/W bit is 0, the master (transmitter) writes to the slave device (receiver). If the R/W bit is 1, the master (receiver) reads from the slave device (transmitter). The transfer of data is shown in Figure 33. One clock pulse is generated for each data bit transferred. The data on the SDA line must be stable during the high period of the clock. The high or low state of the data line can change only when the clock signal on the SCL line is low. The format for these commands is described in the Data Transfer Format section. SDA DATA LINE STABLE; DATA VALID 13993-033 SCL CHANGE OF DATA ALLOWED Figure 33. Valid Bit Transfer Start/stop functionality is shown in Figure 33. The start condition is characterized by a high to low transition on the SDA line while SCL is high. The master always generates the start condition to initialize a data transfer. The stop condition is characterized by a low to high transition on the SDA line while SCL is high. The master always generates the stop condition to terminate a data transfer. Every byte on the SDA line must be eight bits long. Each byte must be followed by an acknowledge bit; bytes are sent MSB first. The acknowledge bit (A) is the ninth bit attached to any 8-bit data byte. An acknowledge bit is always generated by the receiving device (receiver) to inform the transmitter that the byte has been received. It is done by pulling the SDA line low during the ninth clock pulse after each 8-bit data byte. The no acknowledge bit (A) is the ninth bit attached to any 8-bit data byte. A no acknowledge bit is always generated by the receiving device (receiver) to inform the transmitter that the byte has not been received. It is done by leaving the SDA line high during the ninth clock pulse after each 8-bit data byte. After issuing a nonacknowledge bit, the AD9576 I2C state machine goes into an idle state. Data is then sent over the serial bus in the format of nine clock pulses, one data byte (eight bits) from either master (write mode) or slave (read mode) followed by an acknowledge bit from the receiving device. The number of bytes that can be transmitted per transfer is unrestricted. In write mode, the first two data bytes immediately after the slave address byte are the internal memory (control registers) address bytes, with the high address byte first. This addressing scheme gives a memory address of up to 216 − 1 = 65,535. The data bytes after these two memory address bytes are register data written to or read from the control registers. In read mode, the data bytes after the slave address byte are register data written to or read from the control registers. When all the data bytes are read or written, stop conditions are established. In write mode, the master (transmitter) asserts a stop condition to end data transfer during the clock pulse following the acknowledge bit for the last data byte from the slave device (receiver). In read mode, the master device (receiver) receives the last data byte from the slave device (transmitter) but does not pull SDA low during the ninth clock pulse. This is known as a nonacknowledge bit. By receiving the non-acknowledge bit, the slave device knows that the data transfer is finished and enters idle mode. The master then takes the data line low during the low period before the 10th clock pulse, and high during the 10th clock pulse to assert a stop condition. A start condition can be used in place of a stop condition. Furthermore, a start or stop condition can occur at any time, and partially transferred bytes are discarded. Rev. A | Page 45 of 65 AD9576 Data Sheet SDA SCL S START CONDITION 13993-034 P STOP CONDITION Figure 34. Start and Stop Conditions MSB ACK FROM SLAVE RECEIVER 1 SCL 2 3 TO 7 8 ACK FROM SLAVE RECEIVER 9 1 2 3 TO 7 8 9 S 10 P 13993-035 SDA Figure 35. Acknowledge Bit MSB ACK FROM SLAVE RECEIVER 1 SCL 2 3 TO 7 8 9 ACK FROM SLAVE RECEIVER 1 2 3 TO 7 8 9 S 10 P 13993-036 SDA Figure 36. Data Transfer Process (Master Write Mode, 2-Byte Transfer) SDA ACK FROM MASTER RECEIVER 1 2 3 TO 7 8 9 1 2 3 TO 7 8 S 9 10 P Figure 37. Data Transfer Process (Master Read Mode, 2-Byte Transfer), First Acknowledge From Slave Rev. A | Page 46 of 65 13993-037 SCL NONACK FROM MASTER RECEIVER Data Sheet AD9576 Data Transfer Format The write byte format is used to write a register address to the RAM starting from the specified RAM address. S Slave address A W RAM address high byte A RAM address low byte A RAM Data 0 A A RAM Data 1 A RAM Data 2 P The send byte format is used to set up the register address for subsequent reads. S Slave address A W RAM address high byte A RAM address low byte A P A P The receive byte format is used to read the data byte(s) from RAM starting from the current address. S Slave address R A RAM Data 0 A RAM Data 1 A RAM Data 2 The read byte format is the combined format of the send byte and the receive byte. S Slave address W A RAM address high byte A RAM address low byte A Sr R Slave address A RAM Data 0 A RAM Data 1 A RAM Data 2 A I²C Serial Port Timing SDA tLOW tF tR tSU; DAT tHD; STA tF tSP tBUF tR tHD; STA S tHD; DAT tHIGH tSU; STO tSU; STA Sr Figure 38. I²C Serial Port Timing Table 40. I2C Timing Definitions Parameter fSCL tBUF tHD; STA tSU; STA tSU; STO tHD; DAT tSU; DAT tLOW tHIGH tR tF tSP Description Serial clock Bus free time between stop and start conditions Repeated hold time start condition Repeated start condition setup time Stop condition setup time Data hold time Data setup time SCL clock low period SCL clock high period Minimum/maximum receive SCL and SDA rise time Minimum/maximum receive SCL and SDA fall time Pulse width of voltage spikes that must be suppressed by the input filter Rev. A | Page 47 of 65 P S 13993-038 SCL P AD9576 Data Sheet CONTROL REGISTER MAP Table 41. Register Summary Address (Hex) Register Name Bit 7 (MSB) Serial Port Configuration Registers 0x000 SPI Soft reset Configuration A 0x001 SPI Single Configuration B instruction 0x003 Chip type 0x004 Product ID1 0x005 Product ID2 0x006 Revision 0x00B SPI version 0x00C Vendor ID 0x00D 0x00F I/O update Status Indicator Registers 0x020 PLL status 0x021 Reference Bit 6 Bit 5 LSB first Address ascension Reserved Read buffer registers Reserved Serial ID[3:0] Reserved Device revision Reference status Active reference REF1 format REF1 powerdown Reserved Enable reference monitor Reserved Monitored frequency PLL0 Configuration Registers 0x100 PLL0 controls Reserved 0x101 PLL0 configuration Reserved 0x102 PLL0 charge pump current PLL0 loop filter PLL0 input divider PLL0 fractional feedback divider (integer) I/O update PLL0 calibration in progress REF2 LOR Reserved Reserved Reserved Reference monitor control Bit 0 (LSB) Address LSB first Soft reset ascension Reset sans Reserved register map Chip type Reserved Reserved Reference Switchover Registers 0x082 Reference switchover 0x107 Reserved Bit 1 SPI version Vendor ID[7:0] Vendor ID[15:8] Reserved 0x081 0x105 Bit 2 Serial ID[11:4] Reserved Reference Input Configuration Registers 0x080 Reference Reserved inputs 0x103 0x104 Bit 3 Device version Chip Mode Register 0x040 Mode selection 0x083 Bit 4 PLL0 RPOLE2 loop filter Reference monitor 8 kHz operation PLL0 doubler enable PLL0 charge pump current 0x00 R/W 0x05 0x4F 0x01 0x11 0x00 0x56 0x04 0x00 R R R R R R R R/W PLL0 lock detect 0x00 R REF1 LOR REF0 LOR 0x00 R Chip powerdown PLL1 reference select 0x02 R/W 0x00 R/W REF2 powerdown REF2 format 0x00 R/W 0x00 R/W 0x00 R/W PLL0 reset 0x00 R/W N0 SDM powerdown 0x01 R/W 0x8D R/W 0xE8 0x00 R/W R/W 0x01 R/W 0x64 R/W PLL0 sync Enable soft Soft reference reference select select Error window PLL0 powerdown PLL0 loop mode R0 divider ratio Rev. A | Page 48 of 65 R/W PLL1 lock detect PLL0 CPOLE1 loop filter PLL0 loop filter bypass N0 divider integer value 0x00 REF0 format PLL0 RZERO loop filter Reserved Reserved R/W REF0 powerdown Enable XTAL Disable redundancy smooth switchover switchover Reference monitor clock frequency PLL0 calibration Default (Hex) Data Sheet Address (Hex) Register Name 0x108 PLL0 fractional feedback divider 0x109 (fractional) 0x10A 0x10B PLL0 fractional feedback divider 0x10C (modulus) 0x10D 0x10E PLL0 cascaded feedback divider 0x10F 0x110 PLL0 zero delay feedback divider 0x111 PLL0 VCO Dividers Registers 0x120 VCO dividers control 0x121 VCO dividers ratios 0x122 VCO dividers sync mask PLL0 Distribution Registers 0x140 Q0 divider 0x141 0x142 0x143 0x144 0x145 0x146 0x147 0x148 0x149 0x14A 0x14B 0x14C 0x14D Channel 0 driver configuration Channel 1 driver configuration Channel 2 driver configuration Channel 3 driver configuration Q1 divider AD9576 Bit 7 (MSB) Reserved Reserved Reserved M1 sync M1 powerdown M1 divider ratio M1 mask sync Q2 M1 mask sync Q1 0x20 R/W 0x44 R/W 0x00 R/W 0x03 R/W OUT0 driver format 0x00 0x00 R/W R/W M1 reset M0 reset M0 mask sync QZD Reserved M0 mask sync Q3 M0 sync M0 powerdown M0 divider ratio M0 mask sync Q2 M0 mask sync Q1 M0 mask sync Q0 Q0 divider ratio Q0 initial phase OUT0 powerdown Reserved Reserved OUT1 powerdown OUT1 driver format 0x00 R/W Reserved OUT2 powerdown OUT2 driver format 0x00 R/W Reserved OUT3 powerdown OUT3 driver format 0x00 R/W 0x03 R/W OUT4 driver format 0x00 0x00 R/W R/W OUT5 driver format 0x00 R/W 0x03 R/W OUT6 driver format 0x00 0x00 R/W R/W OUT7 driver format 0x00 R/W Q1 powerdown Q1 source Q1 divide ratio Q1 initial phase OUT4 powerdown Reserved Reserved Reserved R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Bit 0 (LSB) Q0 powerdown Reserved Reserved Default (Hex) 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 Bit 4 Bit 3 Bit 2 Bit 1 N0 divider fractional value N0 divider fractional value N0 divider fractional value N0 divider modulus value N0 divider modulus value N0 divider modulus value N0A Divider Ratio N0A Divider Ratio[11:8] QZD divider ratio QZD initial phase Reserved Reserved Channel 6 driver configuration Channel 7 driver configuration Bit 5 Reserved Reserved Reserved Channel 4 driver configuration Channel 5 driver configuration Q2 Divider Bit 6 OUT5 powerdown Q2 powerdown Q2 source Q2 divide ratio Q2 initial phase OUT6 powerdown Reserved Reserved OUT7 powerdown Rev. A | Page 49 of 65 AD9576 Data Sheet Address (Hex) Register Name Bit 7 (MSB) PLL1 Configuration Registers 0x200 PLL1 controls 0x201 0x202 PLL1 feedback divider PLL1 input dividers PLL1 Distribution Registers 0x240 Q3 divider 0x241 0x242 0x243 0x244 Channel 8 driver configuration Channel 9 driver configuration Q4 divider 0x245 0x246 Bit 5 Bit 4 Bit 2 Bit 1 Bit 0 (LSB) Default (Hex) R/W PLL1 sync PLL1 powerdown PLL1 reset 0x00 R/W 0x10 R/W 0x01 R/W Q3 divider ratio 0x83 R/W Q3 initial phase 0x00 R/W Bit 3 Reserved N1 divider ratio Reserved Reserved OUT89 source OUT8 CMOS enable full swing OUT9 CMOS enable full swing Reserved Reserved Channel 10 driver configuration Bit 6 OUT10 CMOS enable full swing R1 divider ratio Q3 powerdown Q3 source PLL1 doubler enable OUT8 driver format OUT8 CMOS polarity OUT8 drive strength OUT8 enable 0xC1 R/W OUT9 driver format OUT9 CMOS polarity OUT9 drive strength OUT9 enable 0xC1 R/W Q4 divider ratio 0x83 R/W Q4 initial phase 0x80 R/W 0xC1 R/W Q4 powerdown OUT10 source OUT10 driver format OUT10 CMOS polarity Rev. A | Page 50 of 65 OUT10 drive strength OUT10 enable Data Sheet AD9576 CONTROL REGISTER DESCRIPTIONS SERIAL PORT CONFIGURATION REGISTERS (REGISTER 0x000 TO REGISTER 0x00F) Table 42. Serial Port Configuration Registers Address 0x000 Bits 7 6 5 [4:3] 2 Bit Name Soft reset LSB first Address ascension Reserved Address ascension Settings 0 1 1 LSB first 0 1 0x001 0 7 Soft reset Single instruction 6 5 Reserved Read buffer registers Reserved Reset sans register map [4:3] 2 0x004 [1:0] [7:4] [3:0] [7:4] Reserved Reserved Chip type Serial ID[3:0] 0x005 [3:0] [7:0] Reserved Serial ID[11:4] 0x00B [7:4] [3:0] [7:0] Device version Device revision SPI version 0x00C [7:0] Vendor ID[7:0] 0x00D [7:0] Vendor ID[15:8] 0x00F [7:1] 0 Reserved I/O update 0x003 0x006 0 1 Description Mirror of Bit 0. Mirror of Bit 1. Mirror of Bit 2. Reset 0x0 0x0 0x0 Access R/W R/W R/W Reserved. This bit determines how the register address pointer is automatically changed in a multibyte transfer. Decrement. Increment. This bit determines the bit order for data readback. This bit has no effect in I2C mode. Serial data stream starts with the LSB. Serial data stream starts with the MSB. This bit issues a chip level reset. This bit is autoclearing. This bit disables streaming operation. For SPI transfers, this bit forces each data byte to be preceded by a new instruction. Reserved. This bit specifies the data source for serial port read commands. 0x0 0x0 R R/W 0x0 R/W 0x0 0x0 R/W R/W 0x0 0x0 R/W R/W 0x0 0x0 R R/W 0x0 0x0 0x5 0x4 R R R R 0xF 0x1 R R 0x1 0x1 0x0 R R R 0x56 R 0x4 R 0x0 0x0 R R/W Reserved. This bit issues a chip level reset, but does not reset register map values. Normal operation. Chip held in reset. Reserved. Reserved. These bits are the unique identifier for the type of device. These bits are a unique identifier, when combined with chip type, for an individual device supporting the Analog Devices serial control interface standard. Reserved. These bits are a unique identifier, when combined with chip type, for an individual device supporting the Analog Devices serial control interface standard. These bits indicate the silicon variant of the device These bits indicate the silicon revision of the device. These bits indicate the version of the analog devices serial control interface standard implemented on the device. These bits are the unique vendor ID and are reflective of the Analog Devices allocated USB vendor ID. These bits are the unique vendor ID and are reflective of the Analog Devices allocated USB vendor ID. Reserved. This bit initiates a transfer of the buffered registers to the active registers. This is an autoclearing bit. Rev. A | Page 51 of 65 AD9576 Data Sheet STATUS INDICATOR REGISTERS (REGISTER 0x020 TO REGISTER 0x021) Table 43. Status Indicator Registers Address 0x020 Bits [7:3] 2 1 Bit Name Reserved PLL0 calibration in progress Settings Description Reserved. This bit indicates the status of the PLL0 VCO calibration. PLL normal operation. VCO calibration active. PLL1 lock detect status. Unlocked. Locked. PLL0 lock detect status. Unlocked. Locked. Reserved. PLL0 active reference frequency indicator. If the reference monitor is Inactive, this bit field indicates the relationship between the requested reference input and the currently active reference. Agreement. Disagreement. If the reference monitor is active, the following settings apply: Valid. Slow. Fast. Indeterminate fault. PLL0 active reference indicator. REF0. REF1. Reference status indicator. Reference present. Loss of reference. Reference status indicator. Reference present. Loss of reference. Reference status indicator. Loss of reference. Reference present. 0 1 PLL1 lock detect 0 1 0 PLL0 lock detect 0 1 0x021 [7:6] [5:4] Reserved Reference status 00 11 00 01 10 11 3 Active reference 0 1 2 REF2 LOR 0 1 1 REF1 LOR 0 1 0 REF0 LOR 1 0 Reset 0x0 0x0 Access R R 0x0 R 0x0 R 0x0 0x0 R R 0x0 R 0x0 R 0x0 R 0x0 R CHIP MODE REGISTER (REGISTER 0x040) Table 44. Chip Mode Register Address 0x040 Bits [7:2] 1 Bit Name Reserved Chip power-down Settings 0 1 0 PLL1 reference select 0 1 Description Reserved. Chip level power-down control. Enabled. Powered down. This bit determines the PLL1 reference input source. PLL0 active reference. REF2. Rev. A | Page 52 of 65 Reset 0x0 0x1 Access R R/W 0x0 R/W Data Sheet AD9576 REFERENCE INPUT CONFIGURATION REGISTERS (REGISTER 0x080 TO REGISTER 0x081) Table 45. Reference Input Configuration Registers Address 0x080 Bits 7 6 Bit Name Reserved REF1 power-down Settings 0 1 [5:4] REF1 format 00 01 10 11 3 2 Reserved REF0 power-down 1 0 [1:0] REF0 format 00 01 10 11 0x081 [7:3] 2 Reserved REF2 power-down 1 0 [1:0] REF2 format 00 01 10 11 Description Reserved. Input receiver power-down control. Normal operation. Powered down. Input receiver format. CMOS (VDD_x swing). AC-coupled differential. XTAL. Reserved. Reserved. Input receiver power-down control. Powered down. Normal operation. Input receiver format. CMOS (VDD_x swing). AC-coupled differential. XTAL. Reserved. Reserved. Input receiver power-down control. Powered down. Normal operation. Input receiver format. CMOS (VDD_x swing). AC-coupled differential. XTAL. Reserved. Rev. A | Page 53 of 65 Reset 0x0 0x0 Access R R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W AD9576 Data Sheet REFERENCE SWITCHOVER REGISTERS (REGISTER 0x082 TO REGISTER 0x083) Table 46. Reference Switchover Registers Address 0x082 Bits [7:4] 3 2 1 Bit Name Reserved Disable smooth switchover Settings Description Reserved. This bit sets the reference switchover mode. 0 1 Bounded phase transient. Immediate. This bit requires the reference monitor to be enabled and both REF0 and REF1 to be configured as XTAL inputs. This bit establishes the control source of the PLL0 reference input mux select line. Not applicable when XTAL redundancy switchover is enabled. REF_SEL pin (Pin 3). Soft reference select (Register 0x082, Bit 0). This bit controls the PLL0 reference input mux select line. Applicable only when the enable soft reference select = 1. REF0 select. REF1 select. The REF2 input clock serves as the reference monitor frequency reference. Reserved. This bit determines the frequency being monitored by the reference monitor. REF0 and REF1 input frequency is 25 MHz. REF0 and REF1 input frequency is 19.44 MHz. This bit configures the reference monitor for an 8 kHz frequency reference and overrides the reference monitor clock frequency bit field (Register 0x083, Bits[3:2]). These bits designate the reference monitor frequency reference carrier. 10 MHz. 19.44 MHz. 25 MHz. 38.88 MHz. These bits set the frequency tolerance for a reference monitor decision. ±10 ppm. ±25 ppm. ±50 ppm. ±100 ppm. Enable XTAL redundancy switchover Enable soft reference select 0 1 0 Soft reference select 0 1 0x083 7 6 5 Enable reference monitor Reserved Monitored frequency 0 1 4 Reference monitor 8 kHz operation [3:2] Reference monitor clock frequency 00 01 10 11 [1:0] Error window 00 01 10 11 Rev. A | Page 54 of 65 Reset 0x0 0x0 Access R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x0 R/W Data Sheet AD9576 PLL0 CONFIGURATION REGISTERS (REGISTER 0x100 TO REGISTER 0x111) Table 47. PLL0 Configuration Registers Address 0x100 Bits [7:4] 3 Bit Name Reserved PLL0 calibration 2 PLL0 sync Settings 0 1 1 PLL0 power-down 0 1 0 PLL0 reset 0 1 0x101 [7:4] 3 Reserved PLL0 doubler enable 0 1 [2:1] PLL0 loop mode 00 01 10 11 0 N0 SDM power-down 0 1 0x102 [7:0] PLL0 charge pump current 0x103 [7:6] PLL0 RPOLE2 loop filter 00 01 10 11 [5:3] PLL0 RZERO loop filter 000 001 010 011 100 101 110 111 [2:0] PLL0 CPOLE1 loop filter 000 001 010 011 100 101 110 111 Description Reserved. This bit issues a manual VCO calibration on a low to high transition. This bit issues a distribution sync command to the dividers driven by PLL0. Normal operation. Dividers held in sync. PLL0 power-down control. Normal operation. Powered down. PLL0 reset control. Normal operation. Reset. Reserved. This bit selects the PLL0 input divider path used. R0 divider output. ×2. These bits select the PLL0 feedback path. Loop Mode 0 (single feedback divider). Loop Mode 1 (cascaded feedback dividers). Loop Mode 2 (fixed delay divider). Reserved. N0 SDM power-down control Normal operation. Powered down. These bits control the magnitude of the PLL0 charge pump current. Total current (µA) = 4 × the bit field value. Internal loop filter Pole 2 resistor setting. 2000 Ω. 666 Ω. 400 Ω. 285 Ω. Internal loop filter zero resistor setting. 1500 Ω. 1875 Ω. 2250 Ω. 2650 Ω. 3000 Ω. 3375 Ω. 3750 Ω. 4125 Ω. Internal loop filter Pole 1 capacitor setting. 2 pF. 8 pF. 42 pF. 48 pF. 82 pF. 88 pF. 122 pF. 128 pF. Rev. A | Page 55 of 65 Reset 0x0 0x0 Access R R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x1 R/W 0x8D R/W 0x3 R/W 0x5 R/W 0x0 R/W AD9576 Address 0x104 0x105 Bits [7:1] 0 [7:6] [5:0] Data Sheet Bit Name Reserved PLL0 loop filter bypass Reserved R0 divider ratio Settings 0 1 to 63 0x107 [7:0] N0 divider integer value 0 to 11 12 to 14 15 to 252 253 to 255 0x108 0x109 0x10A 0x10B [7:0] [7:0] [7:0] [7:0] 0x10C [7:0] 0x10D [7:0] 0x10E [7:0] N0 divider fractional value N0 divider modulus value N0A Divider Ratio[7:0] 0 to 3 4 to 4095 0x10F [7:4] [3:0] Reserved N0A Divider Ratio[11:8] 0 to 3 4 to 4095 0x110 [7:6] [5:0] Reserved QZD divider ratio 0x111 [7:6] [5:0] Reserved QZD initial phase Description Reserved. This bit bypasses the internal loop filter. Reserved. PLL0 reference input divide ratio. Reserved. Divide ratio = bit field value. These bits set the operating divide ratio. Divide ratio = bit field value. Invalid. Valid if the SDM is disabled. Valid. Valid if the SDM is disabled. These bits set the SDM fractional value, Bits[7:0]. These bits set the SDM fractional value, Bits[15:8]. These bits set the SDM fractional value, Bits[23:16]. These bits set the SDM modulus value, Bits[7:0]. These bits must be greater than fractional value. These bits set the SDM modulus value, Bits[15:8]. These bits must be greater than fractional value. These bits set the SDM modulus value, Bits[23:16]. These bits must be greater than fractional value. These bits set the operating divide ratio. Divide ratio = bit field value. Invalid. Valid. Reserved. These bits set the operating divide ratio. Divide ratio = bit field value. Invalid. Valid. Reserved. PLL0 fixed delay feedback divider ratio. Divide ratio = bit field value + 1. Reserved. PLL0 fixed delay feedback divider static phase offset. Phase offset in units of half cycles of the input clock. Rev. A | Page 56 of 65 Reset 0x0 0x0 0x0 0x1 Access R R/W R R/W 0x64 R/W 0x0 0x0 0x0 0x0 R/W R/W R/W R/W 0x0 R/W 0x0 R/W 0x0 R/W 0x0 0x0 R R/W 0x0 0x0 R R/W 0x0 0x0 R R/W Data Sheet AD9576 PLL0 VCO DIVIDERS REGISTERS (REGISTER 0x120 TO REGISTER 0x122) Table 48. PLL0 VCO Dividers Registers Address 0x120 Bits 7 6 Bit Name Reserved M1 sync Settings 0 1 5 M1 power-down 0 1 4 M1 reset 0 1 3 2 Reserved M0 sync 0 1 1 M0 power-down 0 1 0 M0 reset 0 1 0x121 [7:4] M1 divider ratio 0 to 1 2 to 11 12 to 15 [3:0] M0 divide ratio 0 to 1 2 to 11 12 to 15 0x122 7 6 5 4 3 2 1 0 Reserved M1 mask sync Q2 M1 mask sync Q1 M0 mask sync QZD M0 mask sync Q3 M0 mask sync Q2 M0 mask sync Q1 M0 mask sync Q0 Description Reserved. This bit issues a distribution sync command to the dividers driven by M1. Normal operation. Dividers held in reset. Divider power-down control. Normal operation. Powered down. Divider reset control Normal operation. Divider held in reset. Reserved. This bit issues a distribution sync command to the dividers driven by M0. Normal operation. Dividers held in reset. Divider power-down control. Normal operation. Powered down. Divider reset control Normal operation. Divider held in reset. Sets operating divide ratio. Powered down. Divide = bit field value. Powered down. These bits set the operating divide ratio. Powered down. Divide = bit field value. Powered down. Reserved. This bit sets the Divider Q2 ignore and M1 sync signal flag. This bit sets the Divider Q1 ignore and M1 sync signal flag. This bit sets the Divider QZD ignore and M0 sync signal flag. This bit sets the Divider Q3 ignore and M0 sync signal flag. This bit sets the Divider Q2 ignore and M0 sync signal flag. This bit sets the Divider Q1 ignore and M0 sync signal flag. This bit sets the Divider Q0 ignore and M0 sync signal flag. Rev. A | Page 57 of 65 Reset 0x0 0x0 Access R R/W 0x1 R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 R/W 0x4 R/W 0x4 R/W 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 R R/W R/W R/W R/W R/W R/W R/W AD9576 Data Sheet PLL0 DISTRIBUTION REGISTERS (REGISTER 0x140 TO REGISTER 0x14D) Table 49. PLL0 Distribution Registers Address 0x140 Bits 7 6 Bit Name Reserved Q0 power-down Settings 0 1 0x141 0x142 [5:0] [7:6] [5:0] Q0 divider ratio Reserved Q0 initial phase [7:3] 2 Reserved OUT0 power-down 0 1 [1:0] OUT0 driver format 00 01 10 11 0x143 [7:3] 2 Reserved OUT1 power-down 0 1 [1:0] OUT1 driver format 00 01 10 11 0x144 [7:3] 2 Reserved OUT2 power-down 0 1 [1:0] OUT2 driver format 00 01 10 11 0x145 [7:3] 2 Reserved OUT3 power-down 0 1 [1:0] OUT3 driver format 00 01 10 11 0x146 7 6 Reserved Q1 power-down 0 1 [5:0] Q1 divide ratio Description Reserved. Divider power-down control. Normal operation. Powered down. These bits set the operating divide ratio. Divide ratio = bit field value + 1. Reserved. These bits set the divider static phase offset. The phase offset is in units of half cycles of the input clock. Reserved. Driver power-down control. Normal operation. Powered down. These bits select the driver format of OUT0. LVDS, 3.5 mA. LVDS, 4.2 mA. HSTL, 8 mA. 1.8 V CMOS. Reserved. Driver power-down control. Normal operation. Powered down. These bits select the driver format of OUT1. LVDS, 3.5 mA. LVDS, 4.2 mA. HSTL, 8 mA. 1.8 V CMOS. Reserved. Driver power-down control. Normal operation. Powered down. These bits select the driver format of OUT2. LVDS, 3.5 mA. LVDS, 4.2 mA. HSTL, 8 mA. 1.8 V CMOS. Reserved. Driver power-down control. Normal operation. Powered down. These bits select the driver format of OUT3. LVDS 3.5 mA. LVDS 4.2 mA. HSTL 8 mA. 1.8 V CMOS. Reserved. Divider power-down control. Normal operation. Powered down. These bits set the operating divide ratio. Divide ratio = bit field value + 1. Rev. A | Page 58 of 65 Reset 0x0 0x0 Access R R/W 0x3 0x0 0x0 R/W R R/W 0x0 0x0 R R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 0x0 R R/W 0x3 R/W Data Sheet Address 0x147 Bits 7 6 AD9576 Bit Name Reserved Q1 source Settings 0 1 0x148 [5:0] Q1 initial phase [7:3] 2 Reserved OUT4 power-down 0 1 [1:0] OUT4 driver format 00 01 10 11 0x149 [7:3] 2 Reserved OUT5 power-down 0 1 [1:0] OUT5 driver format 00 01 10 11 0x14A 7 6 Reserved Q2 power-down 0 1 0x14B [5:0] 7 6 Q2 divide ratio Reserved Q2 source 0 1 0x14C [5:0] Q2 initial phase [7:3] 2 Reserved OUT6 power-down 0 1 [1:0] OUT6 driver format 00 01 10 11 0x14D [7:3] 2 Reserved OUT7 power-down 0 1 [1:0] OUT7 driver format 00 01 10 11 Description Reserved. This bit selects the divider input clock. M0 output. M1 output. These bits set the divider static phase offset. The phase offset is in units of half cycles of the input clock. Reserved. Driver power-down control. Normal operation. Powered down. These bits select the driver format of OUT4. LVDS, 3.5 mA. LVDS, 4.2 mA. HSTL, 8 mA. 1.8 V CMOS. Reserved. Driver power-down control. Normal operation. Powered down. These bits select the driver format of OUT5. LVDS, 3.5 mA. LVDS, 4.2 mA. HSTL, 8 mA. 1.8 V CMOS. Reserved. Divider power-down control. Normal operation. Powered down. These bits set the operating divide ratio. Divide ratio = bit field value + 1. Reserved. This bit selects the divider input clock. M0 output. M1 output. These bits set the divider static phase offset. The phase offset is in units of half cycles of the input clock. Reserved. Driver power-down control. Normal operation. Powered down. These bits select the driver format of OUT6. LVDS, 3.5 mA. LVDS, 4.2 mA. HSTL, 8 mA. 1.8 V CMOS. Reserved. Driver power-down control. Normal operation. Powered down. These bits select the driver format of OUT7. LVDS, 3.5 mA. LVDS, 4.2 mA. HSTL, 8 mA. 1.8 V CMOS. Rev. A | Page 59 of 65 Reset 0x0 0x0 Access R R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 0x0 R R/W 0x3 0x0 0x0 R/W R R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W 0x0 0x0 R R/W 0x0 R/W AD9576 Data Sheet PLL1 CONFIGURATION REGISTERS (REGISTER 0x200 TO REGISTER 0x202) Table 50. PLL1 Configuration Registers Address 0x200 Bits [7:3] 2 Bit Name Reserved PLL1 sync Settings 0 1 1 PLL1 power-down 0 1 0 PLL1 reset 0 1 0x201 [7:0] N1 divider ratio 0 to 3 4 to 255 0x202 [7:4] [3:1] Reserved R1 divider ratio 0 1 10 11 100 101 110 111 0 PLL1 doubler enable 0 1 Description Reserved. Issues a distribution sync command to dividers driven by PLL1. Normal operation. Dividers held in sync. PLL power-down control. Normal operation. Power down. PLL reset control. Normal operation. PLL1 held in reset. These bits set the operating divide ratio. Divide value = bit field value. Invalid values. Valid values. Reserved. PLL1 reference input divider. Power down. ÷1. ÷1.5. ÷2. ÷3. ÷4. ÷6. ÷8. This bit selects the PLL1 input divider path used. R1 divider output. ×2. Reset 0x0 0x0 Access R R/W 0x0 R/W 0x0 R/W 0x10 R/W 0x0 0x0 R R/W 0x1 R/W Reset 0x1 0x0 Access R/W R/W 0x3 R/W 0x0 R/W 0x0 R/W 0x0 R/W PLL1 DISTRIBUTION REGISTERS (REGISTER 0x240 TO REGISTER 0x246) Table 51. PLL1 Distribution Registers Address 0x240 Bits 7 6 Bit Name Reserved Q3 power-down Settings 0 1 0x241 [5:0] Q3 divider ratio 7 OUT89 source 0 1 6 OUT10 source 0 1 [5:0] Q3 initial phase Description Reserved. Always configure this bit to the default value. Divider power-down control. Normal operation. Powered down. These bits set the operating divide ratio. Divide ratio = bit field value + 1. This bit selects the OUT8 and OUT9 input clock. Q3 divider output. PLL1 active reference. This bit selects the divider input clock. PLL1 output. M0 output. These bits select the divider static phase offset. The phase offset is in units of half cycles of the input clock. Rev. A | Page 60 of 65 Data Sheet Address 0x242 Bits 7 AD9576 Bit Name OUT8 CMOS enable full swing Settings 0 1 [6:4] OUT8 driver format 000 001 010 011 100 101 110 111 [3:2] 1 OUT8 CMOS polarity 00 01 10 11 OUT8 drive strength 0 1 0 OUT8 enable 0 1 0x243 7 OUT9 CMOS enable full swing 0 1 [6:4] [3:2] 1 OUT9 driver format OUT9 CMOS polarity 000 001 010 011 100 101 110 111 00 01 10 11 OUT9 drive strength 0 1 0 OUT9 enable 0 1 Description This bit determines the full swing of the OUT8 CMOS driver. Set this bit only if the associated output format is configured as CMOS. 1.8 V swing. Full swing. These bits select the driver format of OUT8. Tristate. HSTL. LVDS. HCSL. CMOS (both outputs active). CMOS (positive output only). CMOS (negative output only). Reserved. These bits set the polarity of the full swing CMOS output driver. Noninverted, inverted. Inverted, inverted. Noninverted, noninverted. Inverted, noninverted. This bit selects the drive strength of the OUT8 driver and is only applicable when the output format is configured as LVDS or full swing CMOS. CMOS—nominal drive; LVDS—3.5 mA. CMOS—low drive; LVDS—4.5 mA. Output driver enable control. Power down. Enable. This bit determines the swing of the OUT9 CMOS driver. Set this bit only if the associated output format is configured as CMOS. 1.8 V swing. Full swing. These bits select the driver format of OUT9. Tristate. HSTL. LVDS. HCSL. CMOS (both outputs active). CMOS (positive output only). CMOS (negative output only). Reserved. These bits set the polarity of the full swing CMOS output driver. Noninverted, inverted. Inverted, inverted. Noninverted, noninverted. Inverted, noninverted. This bit selects the drive strength of the OUT9 driver and is only applicable when the output format is configured as LVDS or full swing CMOS. CMOS—nominal drive; LVDS—3.5 mA. CMOS—low drive; LVDS—4.5 mA. Output driver enable control. Power down. Enable. Rev. A | Page 61 of 65 Reset 0x1 Access R/W 0x4 R/W 0x0 R/W 0x0 R/W 0x1 R/W 0x1 R/W 0x4 R/W 0x0 R/W 0x0 R/W 0x1 R/W AD9576 Address 0x244 Bits 7 6 Data Sheet Bit Name Reserved Q4 power-down Settings 0 1 0x245 [5:0] 7 6 Q4 divider ratio Reserved Q4 source 1 0 0x246 [5:0] Q4 initial phase 7 OUT10 CMOS enable full swing 0 1 [6:4] [3:2] 1 OUT10 driver format OUT10 CMOS polarity 000 001 010 011 100 101 110 111 00 01 10 11 OUT10 drive strength 0 1 0 OUT10 enable 0 1 Description Reserved. Always configure this bit to the default value. Divider power-down control. Normal operation (default). The Q4 divider works normally. Powered down. The Q0 divider is powered down. These bits set the operating divide ratio. Divide ratio = bit field value + 1. Reserved. Always configure this bit to the default value. This bit selects the OUT10 input clock source. PLL1 selected reference input. Divider, Q4, output. These bits set the divider static phase offset. The phase offset in units of half cycles of the input clock. This bit determines the full swing of the OUT10 CMOS driver. Only set this bit if the associated output format is configured as CMOS. 1.8 V swing. Full swing. These bits select the driver format of OUT10. Tristate. HSTL. LVDS. HCSL. CMOS (both outputs active). CMOS (positive output only). CMOS (negative output only). Reserved. These bits set the polarity of the full swing CMOS output driver. Noninverted, inverted. Inverted, inverted. Noninverted, noninverted. Inverted, noninverted. This bit selects the drive strength of the OUT10 driver and is only applicable when the output format is configured as LVDS or full swing CMOS. CMOS—nominal drive; LVDS—3.5 mA. CMOS—low drive; LVDS—4.5 mA. Output driver enable control. Power down. Enable. Rev. A | Page 62 of 65 Reset 0x1 0x0 Access R/W R/W 0x3 0x1 0x0 R/W R/W R/W 0x0 R/W 0x1 R/W 0x4 R/W 0x0 R/W 0x0 R/W 0x1 R/W Data Sheet AD9576 APPLICATIONS INFORMATION Apply the following general guidelines when using the singleended 1.8 V or 3.3 V CMOS clock output drivers. Design point to point nets such that a driver has only one receiver on the net, if possible. This allows simple termination schemes and minimizes ringing due to possible mismatched impedances on the net. Series termination at the source is generally required to provide transmission line matching and/or to reduce current transients at the driver. The value of the series termination depends on the board design and timing requirements (typically 10 Ω to 100 Ω). CMOS outputs are limited in terms of the capacitive load or trace length that they can drive. Typically, trace lengths less than 6 inches are recommended to preserve signal rise/fall times and signal integrity. 10Ω INTERFACING TO HCSL CLOCK OUTPUTS HCSL uses a differential open-drain architecture. The opendrain architecture necessitates the use of an external termination resistor. Figure 42 shows the typical method for interfacing to HCSL drivers. 13993-039 INDEPENDENT UNCOUPLED 50Ω TRANSMISSION LINES HCSL Termination at the far end of the PCB trace is a second option. The CMOS outputs of the AD9576 do not supply enough current to provide a full voltage swing with a low impedance resistive, far end termination, as shown in Figure 40. Ensure that the impedance of the far end termination network matches the PCB trace impedance and provides the desired switching point. The reduced signal swing may still meet receiver input requirements in some applications. This can be useful when driving long trace lengths on less critical nets. RECEIVER 50Ω 50Ω Figure 42. HCSL Output Termination In some cases, the fast switching capability of HCSL drivers results in overshoot and ringing. The alternative HCSL interface shown in Figure 43 can mitigate this problem via a small series resistor, typically in the 10 Ω to 30 Ω range. INDEPENDENT UNCOUPLED 50Ω TRANSMISSION LINES HCSL 13993-040 100Ω RECEIVER 5pF 100Ω Figure 39. Series Termination of CMOS Output HSTL/LVDS DRIVER 100Ω 50Ω See the AN-586 Application Note for more information about LVDS. MICROSTRIP GND CMOS Figure 41. CMOS Output with Far End Termination 60.4Ω 1.0 INCH 5pF 3.3V 13993-042 10Ω LVDS and HSTL both employ a differential output driver. The recommended termination circuit for LVDS and HSTL drivers appears in Figure 41. INDEPENDENT UNCOUPLED 50Ω TRANSMISSION LINES 10Ω TO 30Ω 10Ω TO 30Ω 50Ω RECEIVER 50Ω Figure 40. LVDS or HSTL Output Termination Figure 43. Alternate HCSL Output Termination Rev. A | Page 63 of 65 13993-043 CMOS INTERFACING TO LVDS AND HSTL CLOCK OUTPUTS 13993-041 INTERFACING TO CMOS CLOCK OUTPUTS AD9576 Data Sheet POWER SUPPLY The AD9576 requires a power supply of 2.5 V ± 5% or 3.3 V ± 10%. The Specifications section gives the performance expected from the AD9576 with the power supply voltage within this range. The absolute maximum range of −0.3 V to +3.6 V, with respect to GND, must never be exceeded on the VDD_x pins. Follow good engineering practice in the layout of power supply traces and the ground plane of the PCB. Bypass the power supply on the PCB with adequate capacitance (>10 µF). Bypass the AD9576 with adequate capacitors (0.1 µF) at all power pins as close as possible to the device. In addition to these bypass capacitors, the AD9576 evaluation board uses six ferrite beads between the 2.5 V (or 3.3 V) source and Pin 29, Pin 35, Pin 41, Pin 46, Pin 52, and Pin 57. Although these ferrite beads may not be needed for every application, the use of these ferrite beads is strongly recommended. At a minimum, include a place for the ferrite beads (as close to the bypass capacitors as possible) and populate the board with 0402, 0 Ω resistors. By doing so, there is a place for the ferrite beads, if needed. Ferrite beads with low (