14-Bit, 160 MSPS TxDAC+
with 2× Interpolation Filter
AD9772A
FEATURES
APPLICATIONS
FUNCTIONAL BLOCK DIAGRAM
CLKCOM CLKVDD MOD0 MOD1 RESET PLLLOCK DIV0 DIV1
CLK+
AD9772A
CLOCK DISTRIBUTION
AND MODE SELECT
CLK–
1×
DATA
INPUTS
(DB13 TO
DB0)
1×/2×
EDGETRIGGERED
LATCHES
FILTER
MUX
CONTROL CONTROL
2× FIR
INTERPOLATION
FILTER
ZEROSTUFF
MUX
PLL CLOCK
MULTIPLIER
PLLVDD
2×/4×
14-BIT DAC
1.2V REFERENCE
AND CONTROL AMP
SLEEP
DCOM DVDD
ACOM AVDD
PLLCOM
LPF
IOUTA
IOUTB
REFIO
FSADJ
REFLO
02253-001
Single 3.1 V to 3.5 V supply
14-bit DAC resolution and input data width
160 MSPS input data rate
67.5 MHz reconstruction pass band @ 160 MSPS
74 dBc SFDR @ 25 MHz
2× interpolation filter with high- or low-pass response
73 dB image rejection with 0.005 dB pass-band ripple
Zero-stuffing option for enhanced direct IF performance
Internal 2×/4× clock multiplier
250 mW power dissipation; 13 mW with power-down mode
48-lead LQFP package
Figure 1.
Communication transmit channel
W-CDMA base stations, multicarrier base stations,
direct IF synthesis, wideband cable systems
Instrumentation
GENERAL DESCRIPTION
The AD9772A is a single-supply, oversampling, 14-bit digitalto-analog converter (DAC) optimized for baseband or IF
waveform reconstruction applications requiring exceptional
dynamic range. Manufactured on an advanced CMOS process,
it integrates a complete, low distortion 14-bit DAC with a 2×
digital interpolation filter and clock multiplier. The on-chip PLL
clock multiplier provides all the necessary clocks for the digital
filter and the 14-bit DAC. A flexible differential clock input
allows for a single-ended or differential clock driver for
optimum jitter performance.
For baseband applications, the 2× digital interpolation filter
provides a low-pass response, thus providing as much as a
threefold reduction in the complexity of the analog reconstruction filter. It does so by multiplying the input data rate by a
factor of 2 while suppressing the original upper in-band image
by more than 73 dB. For direct IF applications, the 2× digital
interpolation filter response can be reconfigured to select the
upper in-band image (that is, the high-pass response) while
suppressing the original baseband image. To increase the signal
level of the higher IF images and their pass-band flatness in
direct IF applications, the AD9772A also features a zero-stuffing
option in which the data following the 2× interpolation filter is
upsampled by a factor of 2 by inserting midscale data samples.
The AD9772A can reconstruct full-scale waveforms with bandwidths of up to 67.5 MHz while operating at an input data rate
of 160 MSPS. The 14-bit DAC provides differential current
outputs to support differential or single-ended applications.
A segmented current source architecture is combined with a
proprietary switching technique to reduce spurious components
and enhance dynamic performance. Matching between the two
current outputs ensures enhanced dynamic performance in a
differential output configuration. The differential current
outputs can be fed into a transformer or a differential op amp
topology to obtain a single-ended output voltage using an
appropriate resistive load.
The on-chip band gap reference and control amplifier are configured for maximum accuracy and flexibility. The AD9772A
can be driven by the on-chip reference or by a variety of
external reference voltages. The full-scale current of the
AD9772A can be adjusted over a 2 mA to 20 mA range, thus
providing additional gain-ranging capabilities.
The AD9772A is available in a 48-lead LQFP package and is
specified for operation over the industrial temperature range of
–40°C to +85°C.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
AD9772A
TABLE OF CONTENTS
Features .............................................................................................. 1
DAC Transfer Function ............................................................. 22
Applications....................................................................................... 1
Reference Operation .................................................................. 22
Functional Block Diagram .............................................................. 1
Reference Control Amplifier .................................................... 23
General Description ......................................................................... 1
Analog Outputs .......................................................................... 23
Revision History ............................................................................... 2
Digital Inputs/Outputs .............................................................. 24
Product Highlights ........................................................................... 3
Sleep Mode Operation............................................................... 25
Specifications..................................................................................... 4
Power Dissipation....................................................................... 25
DC Specifications ......................................................................... 4
Applying the AD9772A ................................................................. 26
Dynamic Specifications ............................................................... 6
Output Configurations .............................................................. 26
Digital Specifications ................................................................... 7
Differential Coupling Using a Transformer ............................... 26
Digital Filter Specifications ......................................................... 8
Differential Coupling Using an Op Amp................................ 26
Absolute Maximum Ratings............................................................ 9
Single-Ended, Unbuffered Voltage Output............................. 26
Thermal Characteristics .............................................................. 9
Single-Ended, Buffered Voltage Output.................................. 27
ESD Caution.................................................................................. 9
Power and Grounding Considerations.................................... 27
Pin Configuration and Function Descriptions........................... 10
Applications Information .............................................................. 29
Terminology .................................................................................... 12
Multicarrier ................................................................................. 29
Typical Performance Characteristics ........................................... 14
Baseband Single-Carrier Applications .................................... 30
Theory of Operation ...................................................................... 17
Direct IF....................................................................................... 30
Functional Description.............................................................. 17
AD9772A Evaluation Board ......................................................... 32
Digital Modes of Operation ...................................................... 17
Schematics................................................................................... 33
PLL Clock Multiplier Operation .............................................. 19
Evaluation Board Layout........................................................... 35
Synchronization of Clock/Data
Using Reset with PLL Disabled................................................. 21
Outline Dimensions ....................................................................... 38
Ordering Guide .......................................................................... 38
DAC Operation........................................................................... 22
REVISION HISTORY
2/08—Rev. B to Rev. C
Changes to DVDD Parameter......................................................... 4
Changes to PLL Clock Enabled Parameter ................................... 7
Changes to PLL Clock Disabled Parameter .................................. 7
Changes to Table 8.......................................................................... 10
Changes to Functional Description ............................................. 17
Change to Power Dissipation Section.......................................... 25
Changes to Power and Grounding Considerations Section ..... 27
Change to Figure 53 ....................................................................... 29
Change to Direct IF Section.......................................................... 30
Changes to Figure 61...................................................................... 34
Updated Outline Dimensions ....................................................... 38
Changes to Ordering Guide .......................................................... 38
6/03—Rev. A to Rev. B
Change to Features .......................................................................... 1
Change to DC Specifications .......................................................... 2
Change to Digital Filter Specifications ...........................................5
Ordering Guide Updated .................................................................6
Change to Pin Function Descriptions ............................................7
Change to Figure 13a and Figure 13b.......................................... 15
Change to Digital Inputs/Outputs................................................ 18
Change to Sleep Mode Operation ................................................ 19
Change to Figure 22 ....................................................................... 19
Change to Figure 23 ....................................................................... 19
Change to Power and Ground Considerations .......................... 21
Change to Figure 29 ....................................................................... 21
Update to Outline Dimensions..................................................... 30
3/02—Rev. 0 to Rev. A
Edits to Digital Specifications..........................................................4
Edits to Absolute Maximum Ratings ..............................................6
Change to TPC 11 .......................................................................... 10
Change to Figure 9 Caption .......................................................... 14
Change to Figure 13a and Figure 13b.......................................... 15
Rev. C | Page 2 of 40
AD9772A
4.
PRODUCT HIGHLIGHTS
1.
2.
3.
A flexible, low power 2× interpolation filter supporting
reconstruction bandwidths of up to 67.5 MHz can be
configured for a low- or high-pass response with 73 dB
of image rejection for traditional baseband or direct IF
applications.
A zero-stuffing option enhances direct IF applications.
A low glitch, fast settling 14-bit DAC provides exceptional
dynamic range for both baseband and direct IF waveform
reconstruction applications.
5.
6.
Rev. C | Page 3 of 40
The AD9772A digital interface, consisting of edge-triggered
latches and a flexible differential or single-ended clock input,
can support input data rates up to 160 MSPS.
An on-chip PLL clock multiplier generates all of the
internal high speed clocks required by the interpolation
filter and DAC.
The current output(s) of the AD9772A can easily be
configured for various single-ended or differential circuit
topologies.
AD9772A
SPECIFICATIONS
DC SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.
Table 1.
Parameter
RESOLUTION
DC ACCURACY 1
Integral Linearity Error (INL)
Differential Nonlinearity (DNL)
Monotonicity (12-Bit)
ANALOG OUTPUT
Offset Error
Gain Error
Without Internal Reference
With Internal Reference
Full-Scale Output Current 2
Output Compliance Range
Output Resistance
Output Capacitance
REFERENCE OUTPUT
Reference Voltage
Reference Output Current 3
REFERENCE INPUT
Input Compliance Range
Reference Input Resistance (REFLO = 3 V)
Small-Signal Bandwidth
TEMPERATURE COEFFICIENTS
Unipolar Offset Drift
Gain Drift
Without Internal Reference
With Internal Reference
Reference Voltage Drift
POWER SUPPLY
AVDD
Voltage Range
Analog Supply Current (IAVDD)
Analog Supply Current in Sleep Mode (IAVDD)
DVDD
Voltage Range
Digital Supply Current (IDVDD)
CLKVDD, PLLVDD 4 (PLLVDD = 3.3 V)
Voltage Range
Clock Supply Current (ICLKVDD + IPLLVDD)
Min
14
Typ
Max
±3.5
±2.0
Guaranteed over specified temperature range
−0.025
−2
−5
±0.5
±1.5
20
−1.0
% of FSR
+2
+5
% of FSR
% of FSR
mA
V
kΩ
pF
+1.25
1.20
1
LSB
LSB
+0.025
200
3
1.14
Unit
Bits
1.26
V
μA
1.25
10
0.5
V
MΩ
MHz
0
ppm of FSR/°C
±50
±100
±50
ppm of FSR/°C
ppm of FSR/°C
ppm/°C
0.1
3.1
3.3
34
4.3
3.5
37
6
V
mA
mA
3.1
3.3
37
3.5
40
V
mA
3.1
3.3
25
3.5
30
V
mA
Rev. C | Page 4 of 40
AD9772A
Parameter
CLKVDD (PLLVDD = 0 V)
Voltage Range
Clock Supply Current (ICLKVDD)
Nominal Power Dissipation 5
Power Supply Rejection Ratio (PSRR) 6
PSRR − AVDD
PSRR − DVDD
OPERATING RANGE
Min
Typ
Max
Unit
3.1
3.3
6.0
253
3.5
272
V
mA
mW
+0.6
+0.025
+85
% of FSR/V
% of FSR/V
°C
−0.6
−0.025
−40
1
Measured at IOUTA driving a virtual ground.
Nominal full-scale current, IOUTFS, is 32× the IREF current.
3
Use an external amplifier to drive any external load.
4
Measured at fDATA = 100 MSPS and fOUT = 1 MHz with DIV1 and DIV0 = 0 V.
5
Measured with PLL enabled at fDATA = 50 MSPS and fOUT = 1 MHz.
6
Measured over a 3.0 V to 3.6 V range.
2
Rev. C | Page 5 of 40
AD9772A
DYNAMIC SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, DVDD = 3.3 V, PLLVDD = 3.3 V, IOUTFS = 20 mA, differential transformer-coupled
output, 50 Ω doubly terminated, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
Maximum DAC Output Update Rate (fDAC)
Output Settling Time (tST) (to 0.025%)
Output Propagation Delay 1 (tPD)
Output Rise Time (10% to 90%) 2
Output Fall Time (10% to 90%)
Output Noise (IOUTFS = 20 mA)
AC LINEARITY—BASEBAND MODE
Spurious-Free Dynamic Range (SFDR) to Nyquist (fOUT = 0 dBFS)
fDATA = 65 MSPS; fOUT = 1.01 MHz
fDATA = 65 MSPS; fOUT = 10.01 MHz
fDATA = 65 MSPS; fOUT = 25.01 MHz
fDATA = 160 MSPS; fOUT = 5.02 MHz
fDATA = 160 MSPS; fOUT = 20.02 MHz
fDATA = 160 MSPS; fOUT = 50.02 MHz
Two-Tone Intermodulation (IMD) to Nyquist (fOUT1 = fOUT2 = −6 dBFS)
fDATA = 65 MSPS; fOUT1 = 5.01 MHz; fOUT2 = 6.01 MHz
fDATA = 65 MSPS; fOUT1 = 15.01 MHz; fOUT2 = 17.51 MHz
fDATA = 65 MSPS; fOUT1 = 24.1 MHz; fOUT2 = 26.2 MHz
fDATA = 160 MSPS; fOUT1 = 10.02 MHz; fOUT2 = 12.02 MHz
fDATA = 160 MSPS; fOUT1 = 30.02 MHz; fOUT2 = 35.02 MHz
fDATA = 160 MSPS; fOUT1 = 48.2 MHz; fOUT2 = 52.4 MHz
Total Harmonic Distortion (THD)
fDATA = 65 MSPS; fOUT = 1.0 MHz; 0 dBFS
fDATA = 78 MSPS; fOUT = 10.01 MHz; 0 dBFS
Signal-to-Noise Ratio (SNR)
fDATA = 65 MSPS; fOUT = 16.26 MHz; 0 dBFS
fDATA = 100 MSPS; fOUT = 25.1 MHz; 0 dBFS
Adjacent Channel Power Ratio (ACPR)
WCDMA with 4.1 MHz BW, 5 MHz Channel Spacing
IF = 16 MHz, fDATA = 65.536 MSPS
IF = 32 MHz, fDATA = 131.072 MSPS
Four-Tone Intermodulation
15.6 MHz, 15.8 MHz, 16.2 MHz, and 16.4 MHz at −12 dBFS
fDATA = 65 MSPS, Missing Center
AC LINEARITY—IF MODE
Four-Tone Intermodulation at IF = 70 MHz
68.1 MHz, 69.3 MHz, 71.2 MHz, and 72.0 MHz at −20 dBFS
fDATA = 52 MSPS, fDAC = 208 MHz
1
2
Propagation delay is delay from the CLK+/CLK− input to the DAC update.
Measured single-ended into 50 Ω load.
Rev. C | Page 6 of 40
Min
Typ
400
Max
Unit
11
17
0.8
0.8
50
MSPS
ns
ns
ns
ns
pA√Hz
82
75
73
82
75
65
dBc
dBc
dBc
dBc
dBc
dBc
85
75
68
85
70
65
dBc
dBc
dBc
dBc
dBc
dBc
−80
−74
dB
dB
71
71
dB
dB
78
68
dBc
dBc
88
dBFS
77
dBFS
AD9772A
DIGITAL SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, IOUTFS = 20 mA, unless otherwise noted.
Table 3.
Parameter
DIGITAL INPUTS
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current 1
Logic 0 Current
Input Capacitance
CLOCK INPUTS
Input Voltage Range
Common-Mode Voltage
Differential Voltage
PLL CLOCK ENABLED (SEE Figure 2)
Input Setup Time (tS)
TA = 25°C
TA = −40 to +85°C
Input Hold Time (tH)
TA = 25°C
TA = −40 to +85°C
Latch Pulse Width (tLPW), TA = 25°C
PLL CLOCK DISABLED (SEE Figure 3)
Input Setup Time (tS)
TA = 25°C
TA = −40 to +85°C
Input Hold Time (tH)
TA = 25°C
TA = −40 to +85°C
Latch Pulse Width (tLPW), TA = 25°C
CLK+/CLK− to PLLLOCK Delay (tOD)
TA = 25°C
TA = −40 to +85°C
PLLLOCK (VOH), TA = 25°C
PLLLOCK (VOL), TA = 25°C
Typ
2.1
3
0
−10
−10
Max
Unit
0.9
+10
+10
V
V
μA
μA
pF
5
0
0.75
0.5
3
2.25
1.5
1.5
V
V
V
1.5
2.1
ns
ns
1.3
1.6
1.5
ns
ns
ns
−0.7
−0.4
ns
ns
3.3
3.7
1.5
ns
ns
ns
1.9
1.8
3.0
2.8
3.3
0.3
ns
ns
V
V
MOD0, MOD1, DIV0, DIV1, SLEEP, RESET have typical input currents of 15 μA.
DB0 TO DB13
DB0 TO DB13
CLK+ – CLK–
IOUTA
OR
IOUTB
PLLLOCK
tLPW
tPD
tH
tS
tST
CLK+ – CLK–
0.025%
0.025%
Figure 2. Timing Diagram—PLL Clock Multiplier Enabled
tOD
tLPW
tPD
IOUTA
OR
IOUTB
tST
0.025%
0.025%
Figure 3. Timing Diagram—PLL Clock Multiplier Disabled
Rev. C | Page 7 of 40
02253-003
tS
tH
02253-002
1
Min
AD9772A
DIGITAL FILTER SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V, CLKVDD = 3.3 V, PLLVDD = 0 V, DVDD = 3.3 V, IOUTFS = 20 mA, differential transformer-coupled output,
50 Ω doubly terminated, unless otherwise noted.
Table 4.
Parameter
MAXIMUM INPUT DATA RATE (fDATA)
DIGITAL FILTER CHARACTERISTICS
Pass-Bandwidth 1 : 0.005 dB
Pass-Bandwidth: 0.01 dB
Pass-Bandwidth: 0.1 dB
Pass-Bandwidth: −3 dB
LINEAR PHASE (FIR IMPLEMENTATION)
STOP BAND REJECTION
0.606 fCLOCK to 1.394 fCLOCK
GROUP DELAY 2
IMPULSE RESPONSE DURATION
−40 dB
−60 dB
Typ
Max
Unit
MSPS
0.401
0.404
0.422
0.479
fOUT/fDATA
fOUT/fDATA
fOUT/fDATA
fOUT/fDATA
73
11
dB
Input clocks
36
42
Input clocks
Input clocks
Excludes sin(x)/x characteristic of DAC.
Defined as the number of data clock cycles between impulse input and peak of output response.
0
Table 5. Integer Filter Coefficients for Interpolation Filter
(43-Tap Half-Band FIR Filter)
–20
–40
OUTPUT (dB)
–60
–80
–100
–140
0
0. 1
0. 2
0.3 0. 4
0.5 0.6
0.7
FREQUENCY (DC TO fDATA )
0.8
0.9
1.0
02253-004
–120
Figure 4. FIR Filter Frequency Response—Baseband Mode
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
0
5
10
15
20
25
30
TIME (Samples)
35
40
45
Lower
Coefficient
H(1)
H(2)
H(3)
H(4)
H(5)
H(6)
H(7)
H(8)
H(9)
H(10)
H(11)
H(12)
H(13)
H(14)
H(15)
H(16)
H(17)
H(18)
H(19)
H(20)
H(21)
H(22)
02253-005
2
NORMALIZED OUTPUT
1
Min
150
Figure 5. FIR Filter Impulse Response—Baseband Mode
Rev. C | Page 8 of 40
Upper
Coefficient
H(43)
H(42)
H(41)
H(40)
H(39)
H(38)
H(37)
H(36)
H(35)
H(34)
H(33)
H(32)
H(31)
H(30)
H(29)
H(28)
H(27)
H(26)
H(25)
H(24)
H(23)
Integer
Value
10
0
−31
0
69
0
−138
0
248
0
−419
0
678
0
−1083
0
1776
0
−3282
0
10,364
16,384
AD9772A
ABSOLUTE MAXIMUM RATINGS
Table 6.
Parameter
AVDD, DVDD, CLKVDD,
PLLVDD
AVDD, DVDD, CLKVDD,
PLLVDD
ACOM, DCOM,
CLKCOM, PLLCOM
REFIO, REFLO, FSADJ,
SLEEP
IOUTA, IOUTB
With Respect to
ACOM, DCOM,
CLKCOM, PLLCOM
AVDD, DVDD,
CLKVDD, PLLVDD
ACOM, DCOM,
CLKCOM, PLLCOM
ACOM
DB0 to DB13, MOD0,
MOD1, PLLLOCK
CLK+, CLK−
DCOM
DIV0, DIV1, RESET
CLKCOM
LPF
PLLCOM
Junction Temperature
Storage Temperature
Lead Temperature
(10 sec)
ACOM
CLKCOM
Rating
−0.3 V to +4.0 V
−4.0 V to +4.0 V
−0.3 V to +0.3 V
−0.3 V to
AVDD + 0.3 V
−1.0 V to
AVDD + 0.3 V
−0.3 V to
DVDD + 0.3 V
−0.3 V to
CLKVDD + 0.3 V
−0.3 V to
CLKVDD + 0.3 V
−0.3 V to
PLLVDD + 0.3 V
125°C
−65°C to +150°C
300°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL CHARACTERISTICS
θJA is specified for the worst-case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 7. Thermal Resistance
Package Type
48-Lead LQFP
ESD CAUTION
Rev. C | Page 9 of 40
θJA
91
θJC
28
Unit
°C/W
AD9772A
ACOM
REFLO
ACOM
FSADJ
REFIO
IOUTB
IOUTA
ACOM
AVDD
DVDD
AVDD
DVDD
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
48 47 46 45 44 43 42 41 40 39 38 37
DCOM
DCOM 2
1
36 SLEEP
PIN 1
IDENTIFIER
35 LPF
(MSB) DB13 3
DB12 4
34 PLLVDD
33 PLLCOM
DB11 5
DB10 6
32 CLKVDD
AD9772A
31 CLKCOM
TOP VIEW
(Not to Scale)
DB9 7
DB8 8
30 CLK–
29 CLK+
DB7 9
28 DIV0
DB6 10
27 DIV1
DB5 11
26 RESET
DB4 12
25 PLLLOCK
02253-006
NC
NC
DVDD
DVDD
MOD1
DCOM
DCOM
MOD0
(LSB) DB0
NC = NO CONNECT
DB2
DB1
DB3
13 14 15 16 17 18 19 20 21 22 23 24
Figure 6. Pin Configuration
Table 8. Pin Function Descriptions
Pin No.
1, 2, 19, 20
3
4 to 15
16
17
Mnemonic
DCOM
DB13
DB12 to DB1
DB0
MOD0
18
MOD1
23, 24
21, 22, 47, 48
25
NC
DVDD
PLLLOCK
26
RESET
27, 28
29
30
31
32
33
34
DIV1, DIV0
CLK+
CLK−
CLKCOM
CLKVDD
PLLCOM
PLLVDD
35
LPF
36
37, 41, 44
38
SLEEP
ACOM
REFLO
Description
Digital Common.
Most Significant Data Bit (MSB).
Data Bit 1 to Data Bit 12.
Least Significant Data Bit (LSB).
Digital High-Pass Filter Response. Active high. This pin invokes the digital high-pass filter response (that is,
half-wave digital mixing mode). Note that quarter-wave digital mixing occurs if this pin and the MOD1 pin
are set high.
Zero-Stuffing Mode. Active high. This pin invokes zero-stuffing mode. Note that quarter-wave digital mixing
occurs if this pin and the MOD0 pin are set high.
No Connect. Leave open.
Digital Supply Voltage (3.1 V to 3.5 V).
Lock Signal of the Phase-Lock Loop. This pin provides the lock signal of the phase-lock loop when the PLL
clock multiplier is enabled, and provides the 1× clock output when the PLL clock multiplier is disabled. High
indicates that PLL is locked to the input clock. The maximum fanout is 1 (that is, 73 dBc) if
the maximum channel assignment is kept below 0.400 × fDATA.
4.
To simplify the filter requirements (that is, mixer image
and LO rejection) of the subsequent IF stages, it is often
advantageous to offset the frequency band from dc to relax
the transition band requirements of the IF filter.
5.
Oversampling the frequency band often results in improved
SFDR and CNR performance. This implies that the data input
rate to the AD9772A is greater than fPASSBAND/0.4 Hz, where
fPASSBAND is the maximum bandwidth that the AD9772A is
required to reconstruct and place carriers. The improved noise
performance results in a reduction in the TxDAC’s noise
spectral density due to the added process gain realized with
oversampling, and higher oversampling ratios provide greater
flexibility in the frequency planning.
AMPLITUDE (dBm)
–80
30
02253-054
–90
25
25
The AD9772A achieves its optimum noise and distortion
performance when the device is configured for baseband
operation and the differential output and full-scale current,
IOUTFS, are set to approximately 20 mA.
–70
15
20
FREQUENCY (MHz)
20
2.
–60
10
10
15
FREQUENCY (MHz)
To achieve the highest possible CNR, the PLL clock
multiplier should be disabled (that is, PLLVDD to
PLLCOM) and the AD9772A clock input should be driven
with a low jitter, low phase noise clock source at twice the
input data rate. In this case, the divide-by-2 clock
appearing at PLLLOCK should serve as the master clock
for the digital upconverter IC(s), such as the AD6622.
PLLLOCK should be limited to a fanout of 1.
–50
5
5
1.
–30
0
0
Although the above IS-136 and GSM spectral plots are
representative of the AD9772A’s performance for a set of test
conditions, the following recommendations are offered to
maximize the performance and system integration of the
AD9772A into multicarrier applications:
–20
–100
–80
Figure 55. Spectral Plot of AD9772A Reconstructing Four GSM-Modulated
Carriers @ fDATA = 52 MSPS, PLLVDD = 0
Figure 53. Generic Multicarrier Signal Chain Using the AD6622 and AD9772A
–40
–70
–110
OTHER AD6622s FOR
INCREASED CHANNEL
CAPACITY
02253-053
SPORT
–60
–100
CLK+/
CLK–
SUMMATION
–50
–90
CLK
AD6622
–40
02253-055
The AD9772A’s wide dynamic range performance makes it well
suited for next-generation base station applications in which it
reconstructs multiple modulated carriers over a designated frequency band. Cellular multicarrier and multimode radios are
often referred to as software radios because the carrier tuning
and modulation scheme is software programmable and performed
digitally. The AD9772A is the recommended TxDAC® in the
Analog Devices, Inc., SoftCell® chipset, which comprises the
AD6622 (a quadrature digital upconverter IC), the AD6624
(an Rx digital downconverter IC that acts as a companion to the
AD6622), and the AD6644 (a 14-bit, 65 MSPS ADC). Figure 53
shows a generic software radio Tx signal chain using the
AD9772A and AD6622.
–20
Figure 54. Spectral Plot of AD9772A Reconstructing Eight IS-136-Modulated
Carriers @ fDATA = 64.54 MSPS, PLLVDD = 0
Rev. C | Page 29 of 40
AD9772A
Figure 56 shows a spectral plot of the AD9772A reconstructing a
test vector similar to those encountered in WCDMA applications.
However, WCDMA applications prescribe a root raised cosine
filter with an alpha = 0.22, which limits the theoretical ACPR of
the TxDAC to about 70 dB, whereas the test vector represents
white noise that has been band-limited by a brick wall bandpass filter with a pass band for which the maximum ACPR
performance is theoretically 83 dB and the peak-to-rms ratio
is 12.4 dB. As Figure 56 reveals, the AD9772A is capable of
approximately 78 dB ACPR performance when one accounts for
the additive noise/distortion contributed by the Rohde & Schwarz
FSEA30 spectrum analyzer.
Figure 57 shows the actual output spectrum of the AD9772A
reconstructing a 16-QAM test vector with a symbol rate of
5 MSPS. The particular test vector was centered at fDATA/4 with
fDATA = 100 MSPS and fDAC = 400 MHz. For many applications,
the pair of images appearing around fDATA will be more attractive
because this pair has the flattest pass band and highest signal
power. Higher frequency images can also be used, but such
images will have reduced pass-band flatness, dynamic range,
and signal power, thus reducing the CNR and ACP performance.
Figure 58 shows a dual-tone SFDR amplitude sweep at the various
IF images with fDATA = 100 MSPS, fDAC = 400 MHz, and the two
tones centered around fDATA/4. Note that because an IF filter is
assumed to precede the AD9772A, the SFDR was measured
over a 25 MHz window around the images occurring at 75 MHz,
125 MHz, 275 MHz, and 325 MHz.
–20
–30
–40
–60
–70
–80
–30
–40
–90
–50
–100
100
0
–60
–70
300
400
90
–90
75MHz
85
C0
–120
C11
C0
Cu1
C11
CENTER 16.25MHz
600kHz
Cu1
SPAN 6MHz
Figure 56. AD9772A Achieves 78 dB ACPR Performance Reconstructing a
WCDMA-Like Test Vector with fDATA = 65.536 MSPS and PLLVDD = 0
DIRECT IF
As discussed in the Digital Modes of Operation section, the
AD9772A can be configured to transform digital data representing
baseband signals into IF signals appearing at odd multiples of
the input data rate (that is, N × fDATA, where N = 1, 3, and so on).
This is accomplished by configuring the MOD1 and MOD0 digital
inputs high. Note that the maximum DAC update rate of 400 MSPS
limits the data input rate in this mode to 100 MSPS when the
Rev. C | Page 30 of 40
125MHz
80
275MHz
75
70
325MHz
65
60
55
50
–14
–12
–10
–8
–6
AOUT (dBFS)
–4
–2
0
Figure 58. Dual-Tone Windowed SFDR vs. AOUT @ fDATA = 100 MSPS
02253-058
–110
SFDR (IN 25MHz WINDOW) (dBFS)
–100
–130
200
FREQUENCY (MHz)
Figure 57. Spectral Plot of 16-QAM Signal in Direct IF Mode at
fDATA = 100 MSPS
–80
02253-056
AMPLITUDE (dBm)
–50
02253-057
The AD9772A is also well suited for wideband single-carrier
applications, such as WCDMA and multilevel quadrature
amplitude modulation (QAM), whose modulation scheme
requires wide dynamic range from the reconstruction DAC to
achieve the out-of-band spectral mask as well as the in-band
CNR performance. Many of these applications strategically
place the carrier frequency at one quarter of the DAC’s input
data rate (that is, fDATA/4) to simplify the digital modulator
design. Because this constitutes the first fixed IF frequency, the
frequency tuning is accomplished at a later IF stage. To enhance
the modulation accuracy and reduce the shape factor of the
second IF SAW filter, many applications specify that the pass
band of the IF SAW filter be greater than the channel
bandwidth; however, the trade-off is that this requires that the
TxDAC meet the spectral mask requirements of the application
within the extended pass band of the second IF, which may
include two or more adjacent channels.
zero-stuffing operation is enabled (that is, when MOD1 is high).
Applications requiring higher IFs (that is, 140 MHz) using
higher data rates should disable the zero-stuffing operation. In
addition, to minimize the effects of the PLL clock multipliers
phase noise as shown in Figure 31, an external low jitter/phase
noise clock source equal to 4 × fDATA is recommended.
AMPLITUDE (dBm)
BASEBAND SINGLE-CARRIER APPLICATIONS
AD9772A
–20
–30
–40
–50
–60
–70
–80
–90
–110
66
68
70
FREQUENCY (MHz)
72
74
02253-059
For many applications, the data update rate for the DAC (that is,
fDATA) must be a fixed integer multiple of a system reference
clock (for example, GSM − 13 MHz). Furthermore, these
applications prefer to use standard IF frequencies, which offer a
large selection of SAW filter choices with various pass bands
(for example, 70 MHz). In addition, these applications may
benefit from the AD9772A’s direct IF mode capabilities when used
in conjunction with a digital upconverter, such as the AD6622.
Because the AD6622 can digitally synthesize and tune up to four
modulated carriers, it is possible to judiciously tune these carriers
in a region falling within the pass band an IF filter while the
AD9772A is reconstructing a waveform. Figure 59 shows an
example in which four carriers are tuned around 18 MHz with a
digital upconverter operating at 52 MSPS such that when
reconstructed by the AD9772A in the IF mode, these carriers fall
around a 70 MHz IF.
–10
AMPLITUDE (dBm)
Regardless of which image is selected for a given application, the
adjacent images must be sufficiently filtered. In most cases, a SAW
filter providing differential inputs represents the optimum device
for this purpose. For single-ended SAW filters, a balanced-tounbalanced RF transformer is recommended. The high output
impedance of the AD9772A provides a certain amount of
flexibility in selecting the optimum resistive load, RLOAD, as well
as any matching network.
Figure 59. Spectral Plot of Four Carriers at 60 MHz IF with fDATA = 52 MSPS,
PLLVDD = 0
Rev. C | Page 31 of 40
AD9772A
AD9772A EVALUATION BOARD
The AD9772A-EB is an evaluation board for the AD9772A
TxDAC. Careful attention to the layout and circuit design,
along with the prototyping area, allows the user to easily and
effectively evaluate the AD9772A in different modes of operation.
Referring to Figure 60 and Figure 61, the performance of
AD9772A can be evaluated differentially or in a single-ended
fashion using a transformer, differential amplifier, or directly
coupled output. To evaluate the output differentially using the
transformer, remove Jumper JP12 and Jumper JP13 and
monitor the output at J6 (IOUT). To evaluate the output
differentially, remove the transformer (T2) and install jumpers
JP12 and JP13. The output of the amplifier can be evaluated at
J13 (AMPOUT). To evaluate the AD9772A in a single-ended
fashion with a directly coupled output, remove the transformer
and Jumper JP12 and Jumper JP13, and install Resistor R16 or
Resistor R17 with 0 Ω.
The digital data to the AD9772A comes across a ribbon cable
that interfaces to a 40-pin IDC connector. Proper termination
or voltage scaling can be accomplished by installing the RN2
and/or RN3 SIP resistor networks. The 22 Ω DIP resistor
network, RN1, must be installed and helps reduce the digital
data edge rates. A single-ended clock input can be supplied via
the ribbon cable by installing JP8, or, more preferably, via the
SMA connector, J3 (CLOCK). If the clock is supplied by J3, the
AD9772A can be configured for a differential clock interface by
installing Jumper JP1 and configuring JP2, JP3, and JP9 in the
DF position. To configure the AD9772A clock input for a
single-ended clock interface, remove JP1 and configure JP2,
JP3, and JP9 in the SE position.
The AD9772A PLL clock multiplier can be disabled by configuring Jumper JP5 in the L position. In this case, the user must
supply a clock input at twice (2×) the data rate via J3 (CLOCK).
The 1× clock is available on the SMA connector J1 (PLLLOCK),
and should be used to trigger a pattern generator directly or via
a programmable pulse generator. Note that PLLLOCK is capable
of providing a 0 V to 0.85 V output into a 50 Ω load. To enable
the PLL clock multiplier, JP5 must be configured for the
H position. In this case, the clock can be supplied via the ribbon
cable (that is, JP8 installed) or J3 (CLOCK). The divide-by-N
ratio can be set by configuring JP6 (DIV0) and JP7 (DIV1).
The AD9772A can be configured for baseband or direct IF
mode operation by configuring Jumper JP11 (MOD0) and
Jumper JP10 (MOD1). For baseband operation, JP10 and JP11
should be configured in the L position. For direct IF operation,
JP10 and JP11 should be configured in the H position. For direct
IF operation without zero-stuffing, JP11 should be configured in
the H position while JP10 should be configured in the low position.
The AD9772A voltage reference can be enabled or disabled via
JP4. To enable the reference, configure JP4 in the internal position.
A voltage of approximately 1.2 V will appear at the TP6 (REFIO)
test point. To disable the internal reference, configure JP4 in the
external position and drive TP6 with an external voltage reference.
Lastly, the AD9772A can be placed in the sleep mode by driving
the TP11 test point with a logic level high input signal.
Rev. C | Page 32 of 40
AD9772A
SCHEMATICS
P1 1
4 P1
P1 3
6 P1
P1 5
8 P1
10 P1
P1 7
P1 9
12 P1
P1 11
14 P1
P1 13
16 P1
P1 15
IN13
DB13
2
IN12
2
15
DB12
3
IN11
3
14
DB11
4
IN10
4
13
DB10
5
IN9
5
12
DB9
6
IN8
6
11
DB8
7
IN7
7
10
DB7
8
IN6
8
9
DB6
9
MSB
RN3
VALUE
1
MSB
IN13
IN12
IN11
IN10
IN9
IN8
IN7
IN6
10
18 P1
20 P1
P1 17
P1 19
22 P1
P1 21
24 P1
P1 23
26 P1
28 P1
P1 25
P1 27
30 P1
P1 29
32 P1
P1 31
34 P1
P1 33
36 P1
P1 35
38 P1
P1 37
40 P1
P1 39
1
16
DB5
2
IN4
2
15
DB4
3
IN3
3
14
DB3
4
IN2
4
13
DB2
5
IN1
5
12
DB1
6
IN0
6
11
DB0
7
7
10
CLOCK
8
8
9
RESET
9
LSB
INCLOCK
IN4
IN3
IN2
IN1
IN0
LSB
INCLOCK
INRESET
6
7
8
9
2
3
4
5
6
7
8
9
10
INRESET
R15
500Ω
+VS
R4
500Ω
IA
IB
5
1
IN5
10
JP12
AMP-A
JP13
AMP-B
4
RN6
VALUE
1
IN5
3
10
RN5
VALUE
RN4
VALUE
2
C16
100pF
2
R12
500Ω
R13
50Ω
3
R11
50Ω
R14
500Ω
–IN
7
AD8055
+V
6
OUT
U2
+IN
–V
4
AMPOUT
1
J13
2
C18
0.1µF
–VS
C17
0.1µF
J7
J8
1 DVDD_IN
TP22
DVDD
C13
10µF
10V
1 DGND
BLK
TP19
RED
FBEAD
2
L1
1
RED
TP20
TP23
BLK
J9
J10
1 AVDD_IN
RED
FBEAD
2
L2
1
TP24
AVDD
C14
10µF
10V
1 AGND
TP25
BLK
J11
J12
RED
FBEAD
2
L3
1 CLKVDD_IN 1
TP26
CLKVDD
C15
10µF
10V
1 CLKGND
TP27
c
BLK
Figure 60. Drafting Schematic of Evaluation Board
Rev. C | Page 33 of 40
02253-060
2 P1
RN2
VALUE
1
RN1
VALUE
1
16
AD9772A
RED
TP16
BLK
TP17
WHT
TP5
WHT
TP6
AVDD
C5
0.1µF
DB8
DB7
DB6
DB5
DB4
REFLO
REFIO
3
34
4
33
5
32
U1
PLLVDD
29
9
28
DIV0
10
27
DIV1
11
26
12
25
30
c
DB2
DB1
(LSB) DB0
DB3
C11
0.1µF
PLLLOCK
3
B
B
H
JP11 2
A L
H
JP10 2
A L
1
1
J1
2
B
2A
TP10
WHT
1
SE B
DF
CLKVDD
JP8
EDGE
2
SE B
1
4
2
2
DF A
J6
C2
10pF
R7
50Ω
R3
1kΩ
JP3
T1
1
S
C19
0.1µF
c
6
2
4
3
1
c
1
P
IOUT
c
2
R1
50Ω
6
IB
JP1
DF
JP2
2A
R2
1kΩ
CLOCK
S
WHT
TP12 CLOCK
J3
3
T2
P
R9
OPT
JP7
A
DVDD
TP2
WHT
3
B
2
3
IA
3
1
1
R16
VAL
R8
50Ω
JP6
2A
TP28
WHT
NOTE:
LOCATE ALL DECOUPLING CAPACITORS (C5 TO C12) AS CLOSE AS POSSIBLE TO DUT,
PREFERABLY UNDER DUT ON THE BOTTOM SIGNAL LAYER.
C3
10pF
3
B
c
MOD1
DGND
JP5
1
TP7 RED
c
TP1
WHT
3
3
TP4
WHT
C12
1µF
MOD0
DVDD
TP3
WHT
CLKVDD
CLKVDD
1
c
C10
0.1µF
RESET
13 14 15 16 17 18 19 20 21 22 23 24
c
C9
1µF
31
AD9772A
8
C1
VAL
R5
VAL
LPF
CLK–
CLK+
7
NOTE:
SHIELD AROUND R5, C1
CONNECTED TO PLLVDD
TP11
SLEEP WHT
35
6
JP4
INT REF 1
1
R17
VAL
3
DF B
SE
JP9
2A
1
c
Figure 61. Drafting Schematic of Evaluation Board (Continued)
Rev. C | Page 34 of 40
02253-061
DB10
DB9
B
2A
REFLO
36
PIN 1
IDENTIFIER
2
DB12
DB11
FSADJ
48 47 46 45 44 43 42 41 40 39 38 37
1
(MSB) DB13
R10
1.91kΩ
R6
50Ω
C8
0.1µF
TP15
BLK
OUTB
DVDD
C7
0.1µF
C4
0.1µF
IOUTA
AVDD
RED
TP14
EXT REF 3
C6
1µF
AD9772A
02253-062
EVALUATION BOARD LAYOUT
02253-063
Figure 62. Silkscreen Layer—Top
Figure 63. Component-Side PCB Layout (Layer 1)
Rev. C | Page 35 of 40
02253-064
AD9772A
02253-065
Figure 64. Ground Plane PCB Layout (Layer 2)
Figure 65. Power Plane PCB Layout (Layer 3)
Rev. C | Page 36 of 40
02253-066
AD9772A
02253-067
Figure 66. Solder-Side PCB Layout (Layer 4)
Figure 67. Silkscreen Layer—Bottom
Rev. C | Page 37 of 40
AD9772A
OUTLINE DIMENSIONS
9.20
9.00 SQ
8.80
1.60
MAX
37
48
36
1
PIN 1
0.15
0.05
7.20
7.00 SQ
6.80
TOP VIEW
1.45
1.40
1.35
0.20
0.09
7°
3.5°
0°
0.08
COPLANARITY
SEATING
PLANE
VIEW A
(PINS DOWN)
25
12
13
VIEW A
0.50
BSC
LEAD PITCH
ROTATED 90° CCW
COMPLIANT TO JEDEC STANDARDS MS-026-BBC
24
0.27
0.22
0.17
051706-A
0.75
0.60
0.45
Figure 68. 48-Lead Low Profile Quad Flat Package [LQFP]
(ST-48)
Dimensions shown in millimeters
ORDERING GUIDE
Model
AD9772AAST
AD9772AASTZ 1
AD9772AASTRL
AD9772AASTZRL1
AD9772A-EB
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
48-Lead LQFP
48-Lead LQFP
48-Lead LQFP
48-Lead LQFP
Evaluation Board
Z = RoHS Compliant Part.
Rev. C | Page 38 of 40
Package Option
ST-48
ST-48
ST-48
ST-48
AD9772A
NOTES
Rev. C | Page 39 of 40
AD9772A
NOTES
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02253-0-2/08(C)
Rev. C | Page 40 of 40
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