Low Power 250 MSPS 10-Bit DAC 1.8 V
CMOS Direct Digital Synthesizer
AD9913
Data Sheet
FEATURES
GENERAL DESCRIPTION
50 mW at up to 250 MSPS internal clock speed
100 MHz analog output
Integrated 10-bit DAC
0.058 Hz or better frequency resolution
0.022° phase tuning resolution
Programmable modulus in frequency equation
Phase noise ≤ –135 dBc per Hz @ 1 kHz offset (DAC output)
(80 dB SFDR @ 100 MHz (±100 kHz offset) AOUT
Automatic linear frequency sweeping capability
8 frequency or phase offset profiles
1.8 V power supply
Software and hardware controlled power-down
Parallel and serial programming options
32-lead LFCSP package
Optional PLL REF_CLK multiplier
Internal oscillator (can be driven by a single crystal)
Phase modulation capability
The AD9913 is a complete direct digital synthesizer (DDS)
designed to meet the stringent power consumption limits of
portable, handheld, and battery-powered equipment. The
AD9913 features a 10-bit digital-to-analog converter (DAC)
operating up to 250 MSPS. The AD9913 uses advanced DDS
technology, coupled with an internal high speed, high
performance DAC to form a complete, digitally-programmable, high frequency synthesizer capable of generating a
frequency agile analog output sinusoidal waveform at up to
100 MHz.
The AD9913 provides fast frequency hopping and fine tuning
resolution. The AD9913 also offers fine resolution phase offset
control. Control words are loaded into the AD9913 through the
serial or parallel I/O port. The AD9913 also supports a userdefined linear sweep mode of operation for generating highly
linearized swept waveforms of frequency. To support various
methods of generating a system clock, the AD9913 includes an
oscillator, allowing a simple crystal to be used as the frequency
reference, as well as a high speed clock multiplier to convert the
reference clock frequency up to the full system clock rate. For
power saving considerations, many of the individual blocks of
the AD9913 can be powered down when not in use.
APPLICATIONS
Portable and handheld equipment
Agile LO frequency synthesis
Programmable clock generator
FM chirp source for radar and scanning systems
The AD9913 operates over the extended industrial temperature
range of −40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
AD9913
10-BIT
DAC
DDS
TIMING AND
CONTROL LOGIC
USER INTERFACE
07002-001
REF_CLK INPUT
CIRCUITRY
Figure 1.
Rev. E
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AD9913
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Direct Switch Mode ................................................................... 14
Applications ...................................................................................... 1
Programmable Modulus Mode ................................................ 14
General Description ......................................................................... 1
Linear Sweep Mode .................................................................... 14
Functional Block Diagram .............................................................. 1
Clock Input (REF_CLK) ............................................................... 18
Revision History ............................................................................... 2
REF_CLK Overview................................................................... 18
Specifications .................................................................................... 3
Crystal-Driven REF_CLK ......................................................... 18
Electrical Specifications ............................................................... 3
Direct-Driven REF_CLK .......................................................... 18
Absolute Maximum Ratings ........................................................... 5
CMOS-Driven REF_CLK ......................................................... 18
ESD Caution.................................................................................. 5
Phase-Locked Loop (PLL) Multiplier ..................................... 18
Equivalent Circuits ....................................................................... 5
PLL Lock Indication .................................................................. 19
Pin Configuration and Function Descriptions ............................ 6
Power-Down Features ............................................................... 21
Typical Performance Characteristics ............................................. 8
I/O Programming ........................................................................... 22
Applications Circuits ..................................................................... 11
Serial Programming ................................................................... 22
Theory of Operation ...................................................................... 12
Parallel I/O Programming ........................................................ 23
DDS Core .................................................................................... 12
Register Update (I/O Update) .................................................. 25
Auxiliary Accumulator .............................................................. 13
Register Map and Bit Descriptions .............................................. 26
10-Bit DAC.................................................................................. 13
Register Map ............................................................................... 26
I/O Port ........................................................................................ 13
Register Bit Descriptions ........................................................... 28
Profile Selections ........................................................................ 13
Outline Dimensions ....................................................................... 32
Modes of Operation ....................................................................... 14
Ordering Guide .......................................................................... 32
Single Tone Mode ...................................................................... 14
REVISION HISTORY
11/2020—Rev. D to Rev. E
Changed CP-32-2 to CP-32-7 ...................................... Throughout
Changes to Figure 3.......................................................................... 6
Updated Outline Dimensions ....................................................... 32
Changes to Ordering Guide .......................................................... 32
3/2019—Rev. C to Rev. D
Change to DAC Control Register (0x02), Table 9 ..................... 26
Updated Outline Dimensions ....................................................... 32
11/2017—Rev. B to Rev. C
Changed CP-32-7 to CP-32-2 ...................................... Throughout
Updated Outline Dimensions ....................................................... 32
Changes to Ordering Guide .......................................................... 32
6/2010—Rev. 0 to Rev. A
Added Digital Input Voltage to Table 2 .........................................5
Added Exposed Pad Notation to Figure 3 and Table 3 ...............5
Changes to Programmable Modulus Mode Section ................. 14
Changes to Serial Programming Section .................................... 22
Changes to Data Write Operation Section ................................. 24
Added Register Update (I/O Update) section and Figure 35 .. 25
Added Endnote 1 to Table 9 ......................................................... 26
Changes to Register Bit Descriptions Section and Bit 7
Description in Table 10 ................................................................. 28
Changes to Table 15 and Table 16 ............................................... 31
Added Exposed Pad Notation to Outline Dimensions ............. 32
10/2007—Revision 0: Initial Version
8/2016—Rev. A to Rev. B
Changes to Table 7 ......................................................................... 20
Updated Outline Dimensions ....................................................... 32
Changes to Ordering Guide .......................................................... 32
Rev. E | Page 2 of 32
Data Sheet
AD9913
SPECIFICATIONS
ELECTRICAL SPECIFICATIONS
AVDD (1.8 V), DVDD (1.8 V), and DVDD_I/O = 1.8 V ± 5%, T = 25°C, RSET = 4.64 kΩ, DAC full-scale current = 2 mA, external
reference clock frequency = 250 MHz with REF_CLK multiplier disabled, unless otherwise noted.
Table 1.
Parameter
REF_CLK INPUT CHARACTERISTICS
Frequency Range
REF_CLK Multiplier
REF_CLK Input Divider Frequency
VCO Oscillation Frequency
PLL Lock Time
External Crystal Mode
CMOS Mode
Input Capacitance
Input Impedance (Differential)
Input Impedance (Single-Ended)
Duty Cycle
REF_CLK Input Level
DAC OUTPUT CHARACTERISTICS
Full-Scale Output Current
Gain Error
Output Offset
Differential Nonlinearity
Integral Nonlinearity
AC Voltage Compliance Range
SPURIOUS-FREE DYNAMIC RANGE
SERIAL PORT TIMING CHARACTERISTICS
SCLK Frequency
SCLK Pulse Width
SCLK Rise/Fall Time
Data Setup Time to SCLK
Data Hold Time to SCLK
Data Valid Time in Read Mode
PARALLEL PORT TIMING CHARACTERISTICS
PCLK Frequency
PCLK Pulse Width
Conditions/Comments
Disabled
Enabled
Full temperature range
VCO1
VCO2
25 MHz reference clock, 10× PLL
VIH
VIL
Min
Typ
16
100
Max
Unit
250
250
83
250
250
MHz
MHz
MHz
MHz
MHz
μs
MHz
V
V
pF
kΩ
kΩ
%
mV p-p
60
25
0.9
0.65
3
2.7
1.35
45
355
55
1000
−14
−0.4
−0.5
4.6
−6
+0.1
+0.4
+0.5
mA
%FS
μA
LSB
LSB
mV
32
MHz
ns
ns
ns
ns
ns
ns
±400
Refer to Figure 6
Low
High
17.5
3.5
2
5.5
0
22
33
Low
High
PCLK Rise/Fall Time
Address/Data Setup Time to PCLK
Address/Data Hold Time to PCLK
Data Valid Time in Read Mode
IO_UPDATE/PROFILE(2:0) TIMING
Setup Time to SYNC_CLK
Hold Time to SYNC_CLK
10
20
2
3.0
0.3
8
0.5
1
Rev. E | Page 3 of 32
MHz
ns
ns
ns
ns
ns
ns
ns
SYNC_CLK cycles
AD9913
Parameter
MISCELLANEOUS TIMING CHARACTERISTICS
Wake-Up Time1
Fast Recovery Mode
Full Sleep Mode
Reset Pulse Width High
DATA LATENCY (PIPELINE DELAY)
Frequency, Phase-to-DAC Output
Frequency-to-DAC Output
Phase-to-DAC Output
Delta Tuning Word-to-DAC Output (Linear Sweep)
CMOS LOGIC INPUTS
Logic 1 Voltage
Logic 0 Voltage
Logic 1 Current
Logic 0 Current
Input Capacitance
CMOS LOGIC OUTPUTS
Logic 1 Voltage
Logic 0 Voltage
POWER SUPPLY CURRENT
DVDD (1.8 V) Pin Current Consumption
DAC_CLK_AVDD (1.8 V)
DAC_AVDD (1.8 V) Pin Current Consumption
PLL_AVDD (1.8 V)
CLK_AVDD (1.8 V) Pin Current Consumption
POWER CONSUMPTION
Single Tone Mode
Modulus Mode
Linear Sweep Mode
Power-Down
Full
Safe
PLL Modes
VCO 1
Differential Input Mode
CMOS Input Mode
Crystal Mode
VCO 2
Differential Input Mode
CMOS Input Mode
Crystal Mode
1
2
Data Sheet
Conditions/Comments
Min
Typ
Max
Unit
1
60
SYSCLK cycles2
μs
SYSCLK cycles
5
Matched latency enabled
Matched latency disabled
Matched latency disabled
11
11
10
14
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
SYSCLK cycles
1.2
0.4
+700
+700
−700
−700
3
V
V
nA
nA
pF
1 mA load
1.5
PLL enabled, CMOS input
PLL disabled, differential input
PLL enabled, XTAL input
PLL disabled
PLL disabled
PLL enabled
50
57
52
0.125
V
V
46.5
4.7
6.2
1.8
4.3
mA
mA
mA
mA
mA
66.5
70.5
68.5
94.6
98.4
mW
mW
mW
mW
mW
15
44.8
mW
mW
11
7.5
5.4
mW
mW
mW
15
11.5
9.4
mW
mW
mW
Refer to the Power-Down Features section.
SYSCLK cycle refers to the actual clock frequency used on-chip by the DDS. If the reference clock multiplier is used to multiply the external reference clock frequency,
the SYSCLK frequency is the external frequency multiplied by the reference clock multiplication factor. If the reference clock multiplier and divider are not used, the
SYSCLK frequency is the same as the external reference clock frequency.
Rev. E | Page 4 of 32
Data Sheet
AD9913
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
Maximum Junction Temperature
AVDD, DVDD
Digital Input Voltage
Digital Output Current
Storage Temperature
Operating Temperature
Lead Temperature (Soldering, 10 sec)
θJA
θJC
Rating
150°C
2V
−0.7 V to +2.2 V
5 mA
–65°C to +150°C
–40°C to +105°C
300°C
36.1°C/W
4.2°C/W
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the
operational section of this specification is not implied.
Operation beyond the maximum operating conditions for
extended periods may affect product reliability.
ESD CAUTION
EQUIVALENT CIRCUITS
DIGITAL INPUTS
DAC OUTPUTS
AVDD
DVDD_I/O
INPUT
AVOID OVERDRIVING DIGITAL INPUTS.
FORWARD BIASING ESD DIODES MAY
COUPLE DIGITAL NOISE ONTO POWER
PINS.
IOUT
MUST TERMINATE OUTPUTS TO AGND
FOR CURRENT FLOW. DO NOT EXCEED
THE OUTPUT VOLTAGE COMPLIANCE
RATING.
Figure 2. Equivalent Input and Output Circuits
Rev. E | Page 5 of 32
07002-002
IOUT
AD9913
Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
AD9913
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
RSET
AGND
AVDD
AGND
IOUT
IOUT
AGND
AVDD
NOTES
1. EXPOSED PAD SHOULD BE SOLDERED TO GROUND.
07002-003
PS2/ADR5/D5
PS1/ADR4/D4
PS0/ADR3/D3
DVDD
DGND
ADR2/D2
ADR1/D1
ADR0/D0
Figure 3. Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1
Mnemonic
PS2/ADR5/D5
I/O
I/O
2
PS1/ADR4/D4
I/O
3
PS0/ADR3/D3
I/O
4
5
6
7
8
9
DVDD
DGND
ADR2/D2
ADR1/D1
ADR0/D0
SYNC_CLK
I
I
I/O
I/O
I/O
O
10
11, 15,
18, 21,
23
12, 16,
17, 22
13
14
19
20
24
SER/PAR
AGND
I
I
Description
Multipurpose pin: Profile Select Pin (PS2) in Direct Switch Mode, Parallel Port Address Line (ADR5), and
Data Line (D5) to program registers.
Multipurpose pin: Profile Select Pin (PS1) in Direct Switch Mode or Linear Sweeping Mode, Parallel Port
Address Line (ADR4), and Data Line (D4) to program registers.
Multipurpose pin: Profile Select Pin (PS0) in Direct Switch Mode or Linear Sweeping Mode, Parallel Port
Address Line (ADR3), and Data Line (D3) to program registers.
Digital Power Supply (1.8 V).
Digital Ground.
Parallel Port Address Line 2 and Data Line 2.
Parallel Port Address Line 1and Data Line 1.
Parallel Port Address Line 0 and Data Line 0.
Clock Out. The profile pins [PS0:PS2] and the IO_UPDATE pin (Pin 27) should be set up to the rising
edge of this signal to maintain constant pipe line delay through the device.
Serial Port and Parallel Port Selection. Logic low = serial mode; logic high = parallel mode.
Analog Ground.
AVDD
I
Analog Power Supply (1.8 V).
REF_CLK
REF_CLK
IOUT
IOUT
RSET
I
I
O
O
I
25
MASTER_RESET
I
Reference Clock Input. See the REF_CLK Overview section for more details.
Complementary Reference Clock Input. See the REF_CLK Overview section for more details.
Open Source DAC Complementary Output Source. Current mode. Connect through 50 Ω to AGND.
Open Source DAC Output Source. Current mode. Connect through 50 Ω to AGND.
Analog Reference. This pin programs the DAC output full-scale reference current. Attach a 4.64 kΩ
resistor to AGND.
Master Reset, Digital Input (Active High). This pin clears all memory elements and reprograms registers
to default values.
Rev. E | Page 6 of 32
Data Sheet
AD9913
Pin No.
26
Mnemonic
PWR_DWN_CTL
I/O
I
27
IO_UPDATE
I
28
CS
I
29
30
31
32
33
SDIO(WR/RD)
SCLK/PCLK
ADR7/D7
ADR6/D6
Exposed Paddle
I/O
I
I/O
I/O
Description
External Power-Down, Digital Input (Active High). A high level on this pin initiates the currently
programmed power-down mode. See the Power-Down Features section for further details. If unused,
tie to ground.
I/O Update; Digital Input. A high on this pin indicates a transfer of the contents of the I/O buffers to the
corresponding internal registers.
Chip Select for Serial and Parallel Port. Digital input (active low). Bringing this pin low enables the
AD9913 to detect serial (SCLK) or parallel (PCLK) clock rising/falling edges. Bringing this pin high
causes the AD9913 to ignore input on the data pins.
Bidirectional Data Line for Serial Port Operation and Write/Read Enable for Parallel Port Operation.
Input Clock for Serial and Parallel Port.
Parallel Port Address Line 7 and Data Line 7.
Parallel Port Address Line 6 and Data Line 6.
The EPAD should be soldered to ground.
Rev. E | Page 7 of 32
AD9913
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
0
0
−10
−20
−20
−40
−40
SFDR (dBm)
−50
−60
−60
−80
−70
−80
07002-004
−100
−90
−100
0
20
40
60
80
100
−120
99.758381
120
07002-007
POWER (dBm)
−30
99.763381
99.768381
99.773381
99.778381
99.783381
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 4. Wideband SFDR @ 99.76 MHz fOUT
(250 MHz Clock, 4 mA DAC Full-Scale Current, PLL Bypassed)
Figure 7. Narrow-Band SFDR @ 99.76 MHz fOUT
(250 MHz Clock, 4 mA DAC Full-Scale Current, PLL Bypassed)
0
0
−10
−20
−20
−40
−40
SFDR (dBm)
POWER (dBc)
−30
−50
−60
−60
−80
−70
−80
−100
0
20
40
60
80
100
07002-008
07002-005
−100
−90
−120
25.124918 25.134918 25.144918 25.154918 25.164918 25.174918
25.129918 25.139918 25.149918 25.159918 25.169918
120
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 5. Wideband SFDR @ 25.14 MHz fOUT
(250 MHz Clock, 4 mA DAC Full-Scale Current, PLL Bypassed)
Figure 8. Narrow-Band SFDR @ 25.14 MHz fOUT
(250 MHz Clock, 4 mA DAC Full-Scale Current, PLL Bypassed)
–50
–50
–55
–55
1.7V
+85ºC
–60
–60
1.9V
–75
–65
–70
–75
–80
–80
–85
–85
–90
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
–90
0.45
fOUT (% of System Clock)
07002-032
SFDR (dBc)
–70
–40°C
+25°C
07002-031
SFDR (dBc)
1.8V
–65
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
fOUT (% of System Clock)
Figure 6. SFDR vs. Supply Variation
(250 MHz Clock, 4 mA DAC Full-Scale Current, PLL Bypassed)
Figure 9. SFDR vs. Temperature
(250 MHz Clock, 4 mA DAC Full-Scale Current, PLL Bypassed)
Rev. E | Page 8 of 32
Data Sheet
AD9913
–50
−50
−60
–55
−70
PHASE NOISE (dBc/Hz)
SFDR (dBc)
–60
–65
39.88%
–70
26.58%
–75
10.21%
–80
−80
−90
99MHz
−100
49MHz
−110
−120
25MHz
−130
0
50
100
150
−140
−150
100
250
200
12.5MHz
07002-012
–90
07002-033
–85
1k
10k
SYSTEM CLOCK (MHz)
Figure 10. SFDR vs. System Clock Frequency (PLL Bypassed)
–100
10M
100M
–50
PLL ×10
REFSPUR
–55
–60
–120
SFDR (dBc)
BYPASS
–130
–140
–150
–65
–70
–75
–80
–85
100
1k
10k
100k
1M
10M
–90
100M
FREQUENCY (MHz)
Figure 11. Residual Phase Noise vs. fOUT (PLL Bypassed)
07002-034
–160
07002-042
PHASE NOISE (dBc/Hz)
1M
Figure 12. Absolute Phase Noise vs. fOUT Using the Internal PLL
(REF_CLK 25 MHz × 10 = 250 MHz Using PLL)
92.3MHz
48.9MHz
23.1MHz
6.1MHz
–110
–170
10
100k
FREQUENCY (MHz)
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
fOUT (% of System Clock)
Figure 13. SFDR Without the Internal PLL
(REF_CLK = 25 MHz × 10 = 250 MHz Using PLL, 4 mA DAC Full-Scale Current)
Rev. E | Page 9 of 32
AD9913
Data Sheet
80
70
TOTAL POWER DISSIPATED (mW)
−80
VCO 1
−100
VCO 2
−120
−140
1k
10k
100k
1M
DVDD
AVDD (PLL)
AVDD (CLK)
AVDD (DAC)
AVDD (DAC CLK)
25
20
15
10
5
0
50
07002-035
POWER DISSIPATION (mW)
30
70
90
110
130
150
170
30
DIFF INPUT SINGLE TONE
20
CMOS INPUT SINGLE TONE
70
90
110
130
150
170
190
210
230
Figure 16. Power Dissipation vs. System Clock Frequency
vs. Clock Input Mode
Figure 14. Absolute Phase Noise, VCO1 vs. VCO2
35
40
SYSTEM CLOCK FREQUENCY (MHz)
FREQUENCY (MHz)
40
CMOS INPUT LINEAR SWEEP
50
0
50
100M
10M
60
10
07002-011
−160
100
DIFF INPUT LINEAR SWEEP
07002-036
PHASE NOISE (dBc/Hz)
−60
190
210
230
250
SYSTEM CLOCK FREQUENCY (MHz)
Figure 15. Power Supply Current Domains
(CMOS Input Mode, 4 mA DAC Full-Scale Current, Single Tone)
Rev. E | Page 10 of 32
250
Data Sheet
AD9913
APPLICATIONS CIRCUITS
LO
SPLITTER
+
–
SIDEBAND
SELECTION
FILTER
+
–
+
–
07002-013
AD9913
+
–
ADC
Figure 17. RFID Block Diagram (Only I-Channel of Receiver Shown)
INPUT
LOW-PASS
FILTER
SIGNAL
BAND-PASS
FILTER
VGA
+
–
VIDEO
FILTER
INPUT
ATTENUATOR
LOCAL
OSCILLATOR
CRT DISPLAY
Figure 18. Handheld Spectrum Analyzer
Rev. E | Page 11 of 32
07002-014
AD9913 AS
SWEEP
GENERATOR
AD9913
Data Sheet
THEORY OF OPERATION
The FTW required to generate a desired value of fOUT is found
by solving Equation 1 for FTW as given in Equation 2
DDS CORE
The DDS block generates a reference signal (sine or cosine
based on the selected DDS sine output bit). The parameters of
the reference signal (frequency and phase), are applied to the
DDS at its frequency and phase offset control inputs, as shown
in Figure 19.
f
FTW round 232 OUT
f SYSCLK
R
MSBs
ANGLE
TO
AMPLITUDE
CONVERSION
(SINE OR
COSINE)
The relative phase of the DDS signal can be digitally controlled
by means of a 14-bit phase offset word (POW). The phase offset
is applied prior to the angle-to-amplitude conversion block
internal to the DDS core. The relative phase offset (Δθ) is given by
10
TO DAC
ACCUMULATOR
RESET
POW
2 14
2
POW
360 14
2
Figure 19. DDS Block Diagram
The output frequency (fOUT) of the AD9913 is controlled by the
frequency tuning word (FTW) at the frequency control input to
the DDS. In all modes except for programmable modulus, the
relationship between fOUT, FTW, and fSYSCLK is:
FTW
f OUT 32 f SYSCLK
2
where the upper quantity is for the phase offset expressed as
radian units and the lower quantity as degrees. To find the
POW value necessary to develop an arbitrary Δθ, solve the
above equation for POW and round the result (in a manner
similar to that described for finding an arbitrary FTW in
Equation 1 and Equation 2).
(1)
where FTW is a 32-bit integer ranging in value from 0 to
2,147,483,647 (231 − 1), which represents the lower half of the
full 32-bit range. This range constitutes frequencies from dc to
Nyquist (that is, ½ fSYSCLK).
PHASE
ACCUMULATOR
AUXILIARY
ACCUMULATOR
32
0
1
+
PHASE
OFFSET
0
1
Z–1
DDS CORE
ANGLE TO
AMPLITUDE
32
IOUT
RSET
0
1
0
1
32
IOUT
DAC
14
32
32
EXTERNAL
2
0
1
14
10
PROFILE
SELECTIONS
INTERNAL
FTW
POW
REGISTER MAP AND TIMING CONTROL
CLOCK
SELECTION
Figure 20. Detailed Block Diagram
Rev. E | Page 12 of 32
SYNC_CLK
IO_UPDATE
PWR_DWN_CTL
MASTER RESET
07002-015
I/O PORT
CS
PLL
MULTIPLIER
SER/PAR
REF_CLK
REF_CLK
CLOCK PORT
AD[7:0]/PS[2:0]
SYSTEM
CLOCK
15
SDIO (WR/RD)
DQ
32 15
SCLK/PCLK
32
07002-030
FREQUENCY 32
CONTROL
For applications where rounding to the nearest available frequency is not acceptable, programmable modulus mode
enables additional options.
MSB ALIGNED
32-BIT
ACCUMULATOR
32
(2)
where the round(x) function rounds the argument (the value of
x) to the nearest integer. This is required because the FTW is
constrained to be an integer value.
DDS SIGNAL CONTROL PARAMETERS
PHASE 14
OFFSET
CONTROL
Data Sheet
AD9913
5
10-BIT DAC
The AD9913 incorporates an integrated 10-bit, current output
DAC. The output current is delivered as a balanced signal using
two outputs. The use of balanced outputs reduces the potential
amount of common-mode noise present at the DAC output,
offering the advantage of an increased signal-to-noise ratio. An
external resistor (RSET) connected between the RSET pin and
AGND establishes the reference current. The full-scale output
current of the DAC (IOUT) is produced as a scaled version of the
reference current. The recommended value of RSET is 4.62 kΩ.
The following equation computes the typical full-scale current
with respect to the Rset resistor value and the gain control
setting:
IOUT ( x , RSET )
0.0206
1 x
RSET
The DAC is designed to operate with full-scale current values
up to 4.58 mA. Based on the equation and assuming a 4.62 kΩ
resistor value for RSET, and x = 0x1FF, the nominal output
current for the DAC is 2.28 mA.
Figure 21 shows the range of DAC output current vs. the DAC
FS value assuming an RSET value of 4.62 kΩ.
4
3
2
1
0
07002-016
In addition to the phase accumulator of the DDS, the AD9913
has an auxiliary accumulator. This accumulator can be configured to support either an automatic sweep of one of the
programmable characteristics of the DDS output (frequency or
phase), or it can be configured to implement a change in the
denominator of the frequency equation given in the DDS Core
section. For further details, refer to the Programmable Modulus
Mode section.
DAC FULL-SCALE CURRENT (mA)
AUXILIARY ACCUMULATOR
0
200
400
600
800
1000
1200
DAC CODE
Figure 21. DAC Output Current vs. DAC FS Bits
Pay careful attention to the load termination to ensure that the
output voltage remains within the specified compliance range;
voltages developed beyond this range cause excessive distortion
and can damage the DAC output circuitry.
I/O PORT
The AD9913 I/O port can be configured as a synchronous serial
communications port that allows easy interface to many industrystandard microcontrollers and microprocessors. The serial I/O
port is compatible with most synchronous transfer formats,
including both the Motorola 6905/11 SPI and Intel 8051 SSR
protocols. For faster programming requirements, a parallel mode is
also provided.
PROFILE SELECTIONS
The AD9913 supports the use of profiles, which consist of a group
of eight registers containing pertinent operating parameters for a
particular operating mode. Profiles enable rapid switching
between parameter sets. Profile parameters are programmed via
the I/O port. Once programmed, a specific profile is activated
by means of Register CFR1 Bits [22:20], or three external
profile select pins. The external profile pins option is only
available in serial mode.
Rev. E | Page 13 of 32
AD9913
Data Sheet
PROGRAMMABLE MODULUS MODE
MODES OF OPERATION
In programmable modulus mode, the auxiliary accumulator is
used to alter the frequency equation of the DDS core, making it
possible to implement fractions which are not restricted to a
power of 2 in the denominator.
The AD9913 operates in four modes:
•
•
•
•
Single tone
Direct switch
Programmable modulus
Linear sweep
The modes relate to the data source used to supply the DDS
with its signal control parameters: frequency, phase, or amplitude. The partitioning of the data into different combinations
of frequency, phase, and amplitude is handled automatically
based on the mode and/or specific control bits.
SINGLE TONE MODE
Single tone mode is the default operational mode and is active
when both the direct switch mode bit and the auxiliary
accumulator enable bit are not set. This mode outputs a single
frequency as programmed by the user in the frequency tuning
word (FTW) register. A phase offset value is also available in
single tone mode via the POW register.
DIRECT SWITCH MODE
Direct switch mode enables FSK or PSK modulation. This
mode simply selects the frequency or phase value programmed
into the profile registers. Frequency or phase is determined by
the destination bits in CFR1 [13:12]. Direct switch mode is
enabled using the direct switch mode active bit in register CFR1
[16].
Two approaches are designed for switching between profile
registers. The first is programming the internal profile control
bits, CFR1 [22:20], to the desired value and issuing an
IO_UPDATE. The second approach, with higher data
throughput, is achieved by changing the profile control pins
[2:0]. Control bit CFR1 [27] is for selection between the two
approaches. The default state uses the profile pins.
To perform 8-tone FSK or PSK, program the FTW word or
phase offset word in each profile. The internal profile control
bits or the profile pins are used for the FSK or PSK data.
Table 4 shows the relationship between the profile selection pin
or bit approach.
Table 4. Profile Selection
Profile Pins PS [2:0] or CFR1 Bits [22:20]
000
001
010
011
100
101
110
111
Profile Selection
Profile 0
Profile 1
Profile 2
Profile 3
Profile 4
Profile 5
Profile 6
Profile 7
A standard DDS is restricted to powers of 2 as a denominator
because the phase accumulator is a set of bits as wide as the
frequency tuning word. When in programmable modulus
mode, the frequency equation becomes
f0 = (FTW)(fS)/x with 0 ≤ FTW ≤ 231
f0 = fS × (1 − (FTW/x)) with 231 < FTW < 232 − 1
where 0 ≤ x ≤ 232.
When in programmable modulus mode, the auxiliary accumulator is set up to roll over before it reaches full capacity. Every
time it rolls over, an extra LSB value is added to the phase
accumulator. In order to determine the values that must be
programmed in the registers, the user must define the desired
output to sampling clock frequency as a ratio of integers (M/N,
where N must not exceed 232).
Refer to the AN-953 Application Note for detailed steps of how
to implement a programmable modulus. The AN-953 defines
how to calculate the three required values (A, B, and X) used
for programmable modulus. The following assigns the required
values to the appropriate register.
Register 0x06 [63:32] holds the B value.
Register 0x06 [31:0] holds the X value.
Register 0x07 [31:0] holds the A value.
LINEAR SWEEP MODE
One purpose of linear sweep mode is to provide better
bandwidth containment compared to direct switch mode by
enabling more gradual, user-defined changes between a starting
point (S0) to an endpoint (E0). The auxiliary accumulator
enable bit is located in Register CFR1 [11]. Linear sweep uses
the auxiliary accumulator to sweep frequency or phase from S0
to E0. A frequency or phase sweep is determined by the
destination bits in CFR1 [13:12]. The trigger to initiate the
sweep can be edge or level triggered. This is determined by
Register CFR1 [9]. Note that, in level triggered mode, the sweep
automatically repeats as long as the appropriate profile pin is
held high.
In linear sweep mode, S0 and E0 (upper and lower limits) are
loaded into the linear sweep parameter register (Register 0x06).
If configured for frequency sweep, the resolution is 32-bits. For
phase sweep, the resolution is 14 bits. When sweeping the
phase, the word value must be MSB-aligned; unused bits are
ignored. The profile pins or the internal profile bits trigger and
control the direction (up/down) of the linear sweep for
frequency or phase. Table 5 depicts the direction of the sweep.
Rev. E | Page 14 of 32
Data Sheet
AD9913
Table 5. Determining the Direction of the Linear Sweep
Profile Pins [2:0] or CFR1 Bits [22:20]
x001
x011
x101
x111
1
Linear Sweep Mode
Sweep off
Ramp up
Ramp down
Bidirectional ramp
For a piecemeal or a nonlinear transition between S0 and E0,
the delta tuning words and ramp rate words can be reprogrammed during the transition.
The formulas for calculating the step size of RDW or FDW are
RDW
Frequency Step 32 f SYSCLK
2
x = don’t care.
Note that if the part is used in parallel port programming
mode, the sweep mode is only determined by the internal
profile control bits, CFR1 [22:20]. If the part is used in serial
port programming mode, either the internal profile control bits
or the external profile select pins can work as the sweep control.
CFR1 [27] selects between these two approaches.
In linear sweep mode, the user programs a rising delta word
(RDW, Register 0x07) and a rising sweep ramp rate (RSRR,
Register 0x08). These settings apply when sweeping from S0 to
E0. The falling delta word (FDW, Register 0x07) and falling
sweep ramp rate (FSRR, Register 0x08) apply when sweeping
from E0 to S0.
Note that if the auxiliary accumulator is allowed to overflow, an
uncontrolled, continuous sweep operation occurs. To avoid
this, the magnitude of the rising or falling delta word should be
smaller than the difference between full-scale and the E0 value
(full-scale − E0). For a frequency sweep, full-scale is 232 − 1. For
a phase sweep, full-scale is 214 − 1.
Figure 22 displays a linear sweep up and then down. This
depicts the dwell mode (see CRF1 [8]). If the no-dwell bit,
CFR1 [8], is set, the sweep accumulator returns to 0 upon
reaching E0.
E0
LINEAR SWEEP
(FREQUENCY/PHASE)
(radians)
45RDW
Phase Step
211
(degrees)
t RSRR / f SYSCLK (Hz)
The slope of the linear sweep is set by the intermediate step size
(delta tuning word) between S0 and E0 (see Figure 22) and the
time spent (sweep ramp rate word) at each step. The resolution
of the delta tuning word is 32 bits for frequency and 14 bits for
phase. The resolution for the delta ramp rate word is 16 bits.
RDW
At 250 MSPS operation, (fSYSCLK =250 MHz). The minimum time
interval between steps is 1/250 MHz × 1 = 4 ns. The maximum
time interval is (1/250 MHz) × 65,535= 262 μs.
Frequency Linear Sweep Example
In linear sweep mode, when sweeping from low to high, the
RDW is applied to the input of the auxiliary accumulator and
the RSRR register is loaded into the sweep rate timer.
The RDW accumulates at the rate given by the ramp rate
(RSRR) until the output equals the upper limit in the linear
sweep parameter register (Register 0x06). The sweep is then
complete.
When sweeping from high to low, the FDW is applied to the
input of the auxiliary accumulator and the FSRR register is
loaded into the sweep rate timer.
The FDW accumulates at the rate given by the ramp rate
(FSRR) until the output equals the lower limit in the linear
sweep parameter register value (Register 0x06). The sweep is
then complete. A phase sweep works in the same manner with
fewer bits.
To view sweep capabilities using the profile pins and the nodwell bit, refer to Figure 23, Figure 24, and Figure 25.
FDW
Δf, p
Δf, p
FSRR
Δt
RDW
Phase Step
213
The formula for calculating delta time from RSRR or FSRR is
Setting the Slope of the Linear Sweep
RSRR
(MHz)
Δt
TIME
07002-037
S0
Figure 22. Linear Sweep Mode
Rev. E | Page 15 of 32
AD9913
Data Sheet
RAMP-DOWN MODE (EDGE TRIGGERED)
RAMP-UP MODE (EDGE TRIGGERED)
E0
E0
S0
S0
NO-DWELL BIT = 0
NO-DWELL BIT = 0
PS[0]
PS[0]
PS[1]
PS[1]
E0
E0
S0
S0
NO-DWELL BIT = 1
NO-DWELL BIT = 1
PS[0]
PS[0]
PS[1]
PS[1]
RAMP-UP MODE (LEVEL TRIGGERED)
RAMP-DOWN MODE (LEVEL TRIGGERED)
E0
E0
S0
S0
NO-DWELL BIT = 0
NO-DWELL
BIT = 0
PS[0]
PS[0]
PS[1]
PS[1]
E0
E0
S0
S0
PS[1]
07002-040
PS[0]
PS[0]
PS[1]
Figure 23. Display of Ramp-Up and Ramp-Down Capability Using the External Profile Pins
Rev. E | Page 16 of 32
07002-041
NO-DWELL BIT = 1
NO-DWELL
BIT = 1
Data Sheet
AD9913
BIDIRECTIONAL MODE (EDGE TRIGGERED)
COMBINATION OF MODES (EDGE TRIGGERED)
RAMP DOWN
MODE
E0
E0
S0
NO-DWELL BIT = x
S0
PS[0]
PS[1]
PS[1]
BIDIRECTIONAL RAMP UP
MODE
MODE
07002-044
RAMP UP
MODE
PS[0]
Figure 25. Combination of Sweep Modes Using the External Profile Pins
BIDIRECTIONAL MODE (LEVEL TRIGGERED)
Clear Functions
E0
The AD9913 allows for a programmable continuous zeroing of
the sweep logic and the phase accumulator as well as clear-andrelease, or automatic zeroing function. Each feature is
individually controlled via bits in the control registers.
S0
NO-DWELL BIT = 0
PS[0]
PS[1]
Continuous Clear Bits
The continuous clear bits are simply static control signals that
hold the respective accumulator (and associated logic) at zero
for the entire time the bit is active.
E0
S0
NO-DWELL BIT = 1
07002-043
PS[0]
Clear-and-Release Function
PS[1]
Figure 24. Display of Bidirectional Ramp Capability
Using the External Profile Pins
The auto clear auxiliary accumulator bit, when active, clears
and releases the auxiliary accumulator upon receiving an
I/O_UPDATE or change in profile bits.
The auto clear phase accumulator, when active, clears and
releases the phase accumulator upon receiving a I/O_UPDATE
or a change in profile bits.
The automatic clearing function is repeated for every
subsequent I/O_UPDATE or change in profile bits until the
control bit is cleared.
These bits are programmed independently and do not have to
be active at the same time. For example, one accumulator may
be using the clear and release function while the other is
continuously cleared.
Rev. E | Page 17 of 32
AD9913
Data Sheet
CLOCK INPUT (REF_CLK)
REF_CLK OVERVIEW
The AD9913 supports a number of options for producing the
internal SYSCLK signal (that is, the DAC sample clock) via the
REF_CLK input pins. The REF_CLK input can be driven
directly from a differential or single-ended source, or it can
accept a crystal connected across the two input pins. There is
also an internal phase-locked loop (PLL) multiplier that can be
independently enabled. The various input configurations are
controlled by means of the control bits in the CFR2 [7:5]
register.
Table 6. Clock Input Mode Configuration
0.1µF
DIFFERENTIAL SOURCE,
DIFFERENTIAL INPUT
Mode Configuration
Differential Input, PLL Enabled
Differential Input, PLL Disabled (Default)
XTAL Input, PLL Enabled
XTAL Input, PLL Disabled
CMOS Input, PLL Enabled
CMOS Input PLL Disabled
LVPECL,
OR
LVDS
DRIVER
14
REF_CLK
13
REF_CLK
SINGLE-ENDED SOURCE,
DIFFERENTIAL INPUT
14
REF_CLK
13
REF_CLK
14
REF_CLK
0.1µF
50Ω
0.1µF
CFR2[5]
CFR2[6]
0.1µF
CFR2[7:6]
XTAL
DIFFERENTIAL/
SINGLE
CFR2[3]
00
10
0
1
÷2
1
0
PLL
CONTROL
1
0
DIVIDE
REF_CLK 14
REF_CLK
TERMINATION
BALUN
(1:1)
x = don’t care.
REF_CLK 13
13
0.1µF
CFR2[15]
÷2
SYSTEM
CLOCK
SINGLE-ENDED SOURCE,
SINGLE-ENDED INPUT
50Ω
0
1
0.1µF
07002-020
1
The REF_CLK input resistance is ~2.7 kΩ differential (~1.35 kΩ
single-ended). Most signal sources have relatively low output
impedances. The REF_CLK input resistance is relatively high,
therefore, its effect on the termination impedance is negligible
and can usually be chosen to be the same as the output impedance of the signal source. The bottom two examples in Figure
28 assume a signal source with a 50 Ω output impedance.
CMOS
CFR2[14:9] CFR2[5:0]
Figure 26. Internal Clock Path Functional Block Diagram
CRYSTAL-DRIVEN REF_CLK
When using a crystal at the REF_CLK input, the resonant
frequency should be approximately 25 MHz. Figure 27 shows
the recommended circuit configuration.
07002-022
CFR2 [7:5]
000
001
x101
x111
100
101
pins to avoid disturbing the internal dc bias voltage of ~1.35 V.
See Figure 28 for more details.
Figure 28. Direct Connection Diagram
CMOS-DRIVEN REF_CLK
This mode is enabled by writing CFR2 [7] to be true. In this
state, the AD9913 must be driven at Pin 13 with the reference
clock source. Additionally, it is recommended that Pin 14 in
CMOS mode be tied to ground through a 10 kΩ resistor.
13 REF_CLK
REFCLK
14 REF_CLK
10kΩ
XTAL
39pF
REFCLK
07002-021
14
39pF
07002-023
13
CMOS
DRIVER
Figure 29. CMOS-Driven Diagram
PHASE-LOCKED LOOP (PLL) MULTIPLIER
Figure 27. Crystal Connection Diagram
DIRECT-DRIVEN REF_CLK
When driving the REF_CLK inputs directly from a signal
source, either single-ended or differential signals can be used.
With a differential signal source, the REF_CLK pins are driven
with complementary signals and ac-coupled with 0.1 μF
capacitors. With a single-ended signal source, either a singleended-to-differential conversion can be employed or the
REF_CLK input can be driven single-ended directly. In either
case, 0.1 μF capacitors are used to ac couple both REF_CLK
An internal phase-locked loop (PLL) provides users of the
AD9913 the option to use a reference clock frequency that is
lower than the system clock frequency. The PLL supports a wide
range of programmable frequency multiplication factors (1× to
64×). See Table 7 for details on configuring the PLL multiplication factor. The PLL is also equipped with a PLL_LOCK bit.
CFR2 [15:8] and CFR2 [5:1] control the PLL operation. Upon
power-up, the PLL is off. To initialize the PLL, CFR2 [5] must
be cleared and CFR2 [1] must be set. The function of CFR2 [1]
Rev. E | Page 18 of 32
Data Sheet
AD9913
is to reset digital logic in the PLL circuit with an active low
signal. The function of CFR2 [5] is to power up or power down
the PLL.
PLL. The bits CFR [14:9] control the feedback divider. The
feedback divider is composed of two stages: ÷ N (1:31) selected
by CFR2 [13:9]; 1 or 2 selected by CFR2 [14].
CFR2 [4] is the PLL LO range bit. When operating the AD9913
with the PLL enabled, CFR2 [4] adjusts PLL loop filter
components to allow low frequency reference clock inputs.
Note that the same system clock frequency can be obtained
with different combinations of CFR2 [15:9] and CFR2 [3]. One
combination may work better in a given application either to
run at lower power or to satisfy the VCOs minimum oscillation
frequency.
CFR2 [3] enables a divide-by-two circuit at the input of the PLL
phase detector. If this bit is enabled the reference clock signal is
divided by 2 prior to multiplication in the PLL. Refer to the
electrical specifications for the maximum reference clock input
frequency when utilizing the PLL with the divide by 2 circuit
enabled. If the divide by 2 circuit is disabled and the PLL is
enabled, then the maximum reference clock input frequency is
one-half the maximum rate indicated in the electrical
specifications table for the maximum input divider frequency.
The AD9913 PLL uses one of two VCOs for producing the
system clock signal. CFR2 Bit 2 is a select bit that enables an
alternative VCO in the PLL. The basic operation of the PLL is
not affected by the state of this bit. The purpose of offering two
VCOs is to provide performance options. The two VCOs have
approximately the same gain characteristics, but differ in other
aspects. The overall spurious performance, phase noise, and
power consumption may change based on the setting of CFR2
Bit 2. It is important to consider that for either VCO, the
minimum oscillation frequency must be satisfied, and that
minimum oscillation frequency is significantly different
between the two oscillators.
CFR2 [15:9], along with CFR2 [3], determine the multiplication
of the PLL. CFR2 [15] enables a divider at the output of the
Note that the AD9913 maximum system clock frequency is
250 MHz. If the user intends to use high values for the PLL
feedback divider ratio, then care should be taken that the
system clock frequency does not exceed 250 MHz.
PLL LOCK INDICATION
CFR2 [0] is a read-only bit that displays the status of the PLL
lock signal.
When the AD9913 is programmed to use the PLL, there is some
amount of time required for the loop to lock. While the loop is
not locked, the chip system clock operates at the reference clock
frequency presented to the part at the pins. Once the PLL lock
signal goes high, the system clock frequency switches
asynchronously to operate at the PLL output frequency. To
maintain a system clock frequency with or without a locked
loop if the PLL lock signal transistions low, the chip reverts to
the reference clock signal while the loop attempts to acquire
lock once again.
Table 7 describes how to configure the PLL multiplication
factor using the appropriated register bits.
Rev. E | Page 19 of 32
AD9913
Data Sheet
Table 7. PLL Multiplication Factor Configuration
CFR2 [13:9]
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
10100
10101
10110
10111
11000
11001
11010
11011
11100
11101
11110
11111
= 000
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
= 001
16
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5
10
10.5
11
11.5
12
12.5
13
13.5
14
14.5
15
15.5
= 100
16
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5
10
10.5
11
11.5
12
12.5
13
13.5
14
14.5
15
15.5
CFR2 [15:14], CFR2 [3]
= 101
= 010
8
64
0.25
2
0.5
4
0.75
6
1
8
1.25
10
1.5
12
1.75
14
2
16
2.25
18
2.5
20
2.75
22
3
24
3.25
26
3.5
28
3.75
30
4
32
4.25
34
4.5
36
4.75
38
5
40
5.25
42
5.5
44
5.75
46
6
48
6.25
50
6.5
52
6.75
54
7
56
7.25
58
7.5
60
7.75
62
Rev. E | Page 20 of 32
= 011
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
= 110
32
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
= 111
16
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
5.5
6
6.5
7
7.5
8
8.5
9
9.5
10
10.5
11
11.5
12
12.5
13
13.5
14
14.5
15
15.5
Data Sheet
AD9913
POWER-DOWN FEATURES
The AD9913 supports an externally controlled power-down
feature as well as software programmable power-down bits
consistent with other Analog Devices, Inc. DDS products.
Table 8. Power-Down Controls
The external PWR_DWN_CTL pin determines the powerdown scheme. A low on this pin allows the user to power down
DAC, PLL, input clock circuitry, and the digital section of the
chip individually via the unique control bits, CFR1 [6:4]. In this
mode, CFR1 [7] is inactive.
When the PWR_DWN_CTL is set, CFR1 [6:4] lose their
meaning. At the same time, the AD9913 provides two different
power-down modes based on the value of CFR1 [7]: a fast
recovery power-down mode in which only the digital logic and
the DAC digital logic are powered down, and a full powerdown mode in which all functions are powered down. A
significant amount of time is required to recover from powerdown mode.
Control
PWR_DWN_CTL = 0
CFR1 [7] = don’t
care
Mode Active
Software
Control
PWRDWNCTL = 1
CFR1 [7] = 0
External
Control,
Fast recovery
power-down
mode
External
Control,
Full powerdown mode
PWRDWNCTL = 1
CFR1 [7] = 1
Table 8 indicates the logic level for each power-down bit that
drives out of the AD9913 core logic to the analog section and
the digital clock generation section of the chip for the external
power-down operation.
Rev. E | Page 21 of 32
Description
Digital power-down = CFR1 [6]
DAC power-down = CFR1 [5]
Input clock power-down =
CFR1 [4]
N/A
N/A
AD9913
Data Sheet
upcoming data transfer is read or write and the serial address of
the register being accessed.
I/O PROGRAMMING
SERIAL PROGRAMMING
The first eight SCLK rising edges of each communication cycle
are used to write the instruction byte into the AD9913. The
remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the AD9913
and the system controller. The number of bytes transferred
during Phase 2 of the communication cycle is a function of the
register accessed. For example, when accessing the Control
Function Register 2, which is two bytes wide, Phase 2 requires
that two bytes be transferred. If accessing one of the profile
registers, which are six bytes wide, Phase 2 requires that six
bytes be transferred. After transferring all data bytes per the
instruction, the communication cycle is completed.
The AD9913 serial port is a flexible, synchronous serial
communications port allowing an easy interface to many
industry standard microcontrollers and microprocessors.
The interface allows read/write access to all registers that
configure the AD9913. MSB first or LSB first transfer formats
are supported. The AD9913 serial interface port is configured
as a single pin I/O (SDIO), which allows a two-wire interface.
The AD9913 does not have a SDO pin for 3-wire operation.
With the AD9913, the instruction byte specifies read/write
operation and the register address. Serial operations on the
AD9913 occur only at the register level, not the byte level.
At the completion of any communication cycle, the AD9913
serial port controller expects the next eight rising SCLK edges
to be the instruction byte of the next communication cycle.
For the AD9913, the serial port controller recognizes the
instruction byte register address and automatically generates
the proper register byte address. In addition, the controller
expects that all bytes of that register are accessed. It is a
requirement that all bytes of a register be accessed during
serial I/O operations.
All data input to the AD9913 is registered on the rising edge
of SCLK. All data is driven out of the AD9913 on the falling
edge of SCLK. Figure 30 through Figure 32 illustrate the general
operation of serial ports.
There are two phases to a communication cycle with the
AD9913. Phase 1 is the instruction cycle, which is the writing of
an instruction byte into the AD9913, coincident with the first
eight SCLK rising edges. The instruction byte provides the
AD9913 serial port controller with information regarding the
data transfer cycle, which is Phase 2 of the communication
cycle. The Phase 1 instruction byte defines whether the
Note that IO_UPDATE is not shown in Figure 30 and Figure
31. The IO_UPDATE transfers the contents of the write
sequence to the active register. See the Register Update (I/O
Update) section.
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CS
SDIO
I7
I5
I6
I4
I3
I2
I1
I0
D7
D6
D5
D4
D3
D2
D1
07002-025
SCLK
D0
Figure 30. Serial Port Writing Timing—Clock Stall Low
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CS
SDIO
I7
I6
I5
I4
I3
I2
I1
I0
D7
D6
D5
D4
D3
D2
D1
D0
07002-026
SCLK
Figure 31. Serial Port Write Timing—Clock Stall High
INSTRUCTION CYCLE
DATA TRANSFER CYCLE
CS
SDIO
I7
I6
I5
I4
I3
I2
I1
I0
DO7
DO6
DO5
DO4
DO3
Figure 32. Two-Wire Serial Port Read Timing—Clock Stall High
Rev. E | Page 22 of 32
DO2
DO1
DO0
07002-027
SCLK
Data Sheet
AD9913
Instruction Byte
For MSB first operation, the serial port controller generates the
most significant byte (of the specified register) address first
followed by the next less significant byte addresses until the I/O
operation is complete. All data written to (read from) the
AD9913 must be in MSB first order.
The instruction byte contains the following information as
shown in the instruction byte bit map.
Instruction Byte Information Bit Map
MSB
LSB
D7
D6
D5
D4
D3
D2
D1
D0
R/W
X
X
A4
A3
A2
A1
A0
R/W—Bit 7 of the instruction byte determines whether a read
or write data transfer occurs after the instruction byte write.
Logic high indicates read operation. Logic 0 indicates a write
operation.
X, X—Bit 6 and Bit 5 of the instruction byte are don’t care.
A4, A3, A2, A1, A0—Bit 4, Bit 3, Bit 2, Bit 1, and Bit 0 of the
instruction byte determine which register is accessed during the
data transfer portion of the communications cycle.
Serial Interface Port Pin Description
SCLK—Serial Port Clock
If the LSB mode is active, the serial port controller generates the
least significant byte address first followed by the next greater
significant byte addresses until the I/O operation is complete.
All data written to (read from) the AD9913 must be in LSB
first order.
Notes on Serial Port Operation
The LSB first bit resides in CFR1 [23]. Note that the
configuration changes immediately upon writing to the byte
containing the LSB first bit. Therefore, care must be taken to
compensate for this new configuration for the remainder of the
current communication cycle.
Reading profile registers requires that the external profile select
pins (PS[2:0]) be configured to select the corresponding
register.
The serial clock pin is used to synchronize data to and from the
AD9913 and to run the internal state machines.
PARALLEL I/O PROGRAMMING
CS—Chip Select
CS—Chip Select
Active low input that allows more than one device on the same
serial communications line. The SDIO pin goes to a high
impedance state when this input is high. If driven high during
any communications cycle, that cycle is suspended until chip
select is reactivated low. Chip select can be tied low in systems
that maintain control of SCLK.
An active low on this pin indicates that a read/write operation
is about to be performed. If this pin goes high during an access,
the parallel port is reset to its initial condition.
SDIO—Serial Data I/O.
Parallel Port Interface Pin Description
R/W—Read/Write
A high on Pin 29 combined with CS active low indicates a read
operation. A low on this pin indicates a write operation.
PCLK—Parallel Port Clock
Data is always written into and read from the AD9913 on
this pin.
The parallel clock pin is used to synchronize data to and from
the AD9913 and to run the internal state machines.
MSB/LSB Transfers
The AD9913 serial port can support both most significant bit
(MSB) first or least significant bit (LSB) first data formats. This
functionality is controlled by the CFR1 [23]. The default value
is MSB first. The instruction byte must be written in the format
indicated by Control Register 0x00 Bit 8. That is, if the AD9913
is in LSB first mode, the instruction byte must be written from
least significant bit to most significant bit.
ADDR/DATA [7:0]
The 8-bit address/data bus. It works in a bidirectional fashion
to support both read and write operations.
Notes on Parallel Port Operation
Each operation works in a 3-PCLK cycle with the first clock
cycle for addressing, the second for reading or writing, and the
third for re-initialization. In parallel port operation, each byte is
programmed individually.
Rev. E | Page 23 of 32
AD9913
Data Sheet
1.
Data Read Operation
A typical read operation follows the steps shown in Figure 33.
1.
2.
3.
4.
5.
The user supplies PCLK, CS, R/W, and the parallel address
of the register using the address pins (ADR0 through
ADR7) for the read operation.
CS, R/W, and the address lines must meet the setup and
hold times relative to the 1st PCLK rising edge.
The user releases the bus to read.
The AD9913 drives data onto the bus after the second
PCLK rising edge.
CS must meet the set up and hold times to the 3rd PCLK
rising edge.
2.
3.
4.
5.
The user supplies the PCLK, CS, R/W, and the parallel
address of the register and using the address pins
(ADR0/D0 through ADR7/D7).
CS, R/W, and the address lines must meet the set up and
hold times relative to the 1st PCLK rising edge.
Data lines must meet the set up and hold times relative to
the 2nd PCLK rising edge.
CS must meet the set up and hold times relative to the 3rd
PCK rising edge.
The IO_UPDATE is not shown in Figure 34. The
IO_UPDATE transfers the contents from a write sequence
to the active register. See the Register Update (I/O Update)
section.
Data Write Operation
Write operations work in a similar fashion as read operations
except that the user drives the bus for both PCLK cycles. A
typical write access follows the steps shown in Figure 34.
READ OPERATION
PCLK
CS
R/W
ADDR0
3ns
0.3ns
tASU
tAHD
DATA0
8ns
ADDR1
DATA1
3ns 0.3ns
07002-028
ADDR/DATA
tDVLD tCSU tCHD
Figure 33. Parallel Port Read Timing
WRITE OPERATION
PCLK
CS
R/W
ADDR0
DATA0
ADDR1
DATA1
3ns 0.3ns 3ns 0.3ns 3ns 0.3ns
07002-029
ADDR/DATA
tASU tAHD tDSU tDHD tCSU tCHD
Figure 34. Parallel Port Write Timing
Rev. E | Page 24 of 32
Data Sheet
AD9913
REGISTER UPDATE (I/O UPDATE)
Functionality of the I/O UPDATE and SYNC_CLK
Data from a write sequence is stored in a buffer register (data
inactive). An active register exists for every buffer register. The
I/O update signal and SYNC_CLK are used to transfer the
contents from the buffer register into the active register.
I/O_UPDATE initiates the start of a buffer transfer. It can be
sent synchronously or asynchronously relative to the SYNC_CLK.
If the setup time between the two signals is met, then constant
latency (pipeline) to the DAC output exists. For example, if
constant propagation delay of phase offset changes via the SPI
A
or parallel port is desired, the setup time must be met,
otherwise, a time uncertainty of one SYNC_CLK period is present.
The I/O_UPDATE is sampled by the SYNC_CLK. Therefore,
I/O_UPDATE must have a minimum pulse width greater than one
SYNC_CLK period.
The timing diagram shown in Figure 35 depicts how data in the
buffer is transferred to the active registers. An I/O_UPDATE is
not required for every register write, it can be sent after
multiple register writes.
B
SYNC_CLK
I/O_UPDATE
DATA IN
BUFFER REGISTER
N
N–1
N
N+1
THE DEVICE REGISTERS AN I/O UPDATE AT POINT A. THE DATA IS TRANSFERRED FROM
THE ASYNCHRONOUSLY LOADED I/O BUFFERS AT POINT B.
Figure 35. I/O Synchronization Timing Diagram
Rev. E | Page 25 of 32
N+1
N+2
07002-045
DATA IN
ACTIVE REGISTER
AD9913
Data Sheet
REGISTER MAP AND BIT DESCRIPTIONS
REGISTER MAP
Note that the highest number found in the Serial Bit Range column for each register in the following tables is the MSB and the lowest
number is the LSB for that register.
Table 9. Control Registers
Register Name
(Serial
Address)
[Serial Bit
Range]/Parallel
Address
CFR1—Control
Function
Register 1
(0x00)
[7:0]/0x00
[15:8]/0x01
MSB
Bit 7
External
PowerDown
Mode
Clear
Auxiliary
Accum.
Bit 6
Bit 5
Digital
PowerDown
DAC
PowerDown
Clear
Phase
Accum.
Bit 4
Clock
Input
PowerDown
Destination [1:0]
00: Frequency Word
01: Phase Word
Bit 2
Bit 1
LSB
Bit 0
Default
Value
Load SRR @
IO_UPDATE
Autoclear
Auxiliary
Accum.
Autoclear
Phase
Accum.
Enable
Sine
Output
0x00
Auxiliary
Accumulator
Enable
DC
Output
Active
Open
Match
Pipe
Delays
Active
VCO2 Sel
Linear
Sweep
NoDwell
Active
Direct
Switch
Mode
Active
Open
0x00
Sync Clock
Disable
Linear
Sweep
State
Trigger
Active
Open
[23:16]/0x02
LSB First
[31:24]/0x03
Open
Open
Open
Modulus
Enable
Use Internal
Profile
CFR2—Control
Function Register
2
(0x01)
[7:0]/0x04
CMOS
Clock
Mode1
Crystal
Clock
Mode1
PLL
PowerDown1
PLL LO
Range
PLL Input Div
by 2
[15:8]/0x05
PLL
Output
Div by 2
DAC Control
Register
(0x02)
[7:0]/0x06
[15:8]/0x07
[23:16]/0x08
[31:24]/0x09
[7:0]/0x0A
[15:8]/0x0B
[23:16]/0x0C
[31:24]/0x0D
[7:0]/0x0E
[15:8]/0x0F
[7:0]/0x12
[15:8]/0x13
[23:16]/0x14
[31:24]/0x15
[39:32]/0x16
[47:40]/0x17
[55:48]/0x18
[63:56]/0x19
[7:0]/0x1A
[15:8]/0x1B
[23:16]/0x1C
[31:24]/0x1D
[39:32]/0x1E
[47:40]/0x1F
[55:48]/0x20
[63:56]/0x21
FTW
(0x03)
POW
(0x04)
Linear Sweep
Parameter
Register
(0x06)
Linear Sweep
Delta Parameter
Register
(0x07)
Open
Internal Profile Control [2:0]
Bit 3
PLL Multiplication Factor [5:0]
Open
Open [1:0]
FS C [7:0]
Reserved
Open
Reserved
Reserved
Frequency Tuning Word [7:0]
Frequency Tuning Word [15:8]
Frequency Tuning Word [23:16]
Frequency Tuning Word [31:24]
Phase Offset Word [7:0]
Phase Offset Word [13:8]
Sweep Parameter Word 0 [7:0]
Sweep Parameter Word 0 [15:8]
Sweep Parameter Word 0 [23:16]
Sweep Parameter Word 0 [31:24]
Sweep Parameter Word 1 [7:0]
Sweep Parameter Word 1 [15:8]
Sweep Parameter Word 1 [23:16]
Sweep Parameter Word 1 [31:24]
Rising Delta Word [7:0]
Rising Delta Word [15:8]
Rising Delta Word [23:16]
Rising Delta Word [31:24]
Falling Delta Word [7:0]
Falling Delta Word [15:8]
Falling Delta Word [23:16]
Falling Delta Word [31:24]
Rev. E | Page 26 of 32
Open
PLL Reset
0x00
0x00
PLL
Lock
0x32
Open
0x14
FSC [9:8]
0xFF
0x11
0x7F
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
Data Sheet
AD9913
Register Name
(Serial
Address)
[Serial Bit
Range]/Parallel
Address
Linear Sweep
Ramp Rate
Register
(0x08)
[7:0]/0x22
[15:8]/0x23
[23:16]/0x24
[31:24]/0x25
[7:0]/0x26
[15:8]/0x27
[23:16]/0x28
[31:24]/0x29
[39:32]/0x2A
[47:40]/0x2B
[7:0]/0x2C
[15:8]/0x2D
[23:16]/0x2E
[31:24]/0x2F
[39:32]/0x30
[47:40]/0x31
[7:0]/0x32
[15:8]/0x33
[23:16]/0x34
[31:24]/0x35
[39:32]/0x36
[47:40]/0x37
[7:0]/0x38
[15:8]/0x39
[23:16]/0x3A
[31:24]/0x3B
[39:32]/0x3C
[47:40]/0x3D
[7:0]/0x3E
[15:8]/0x3F
[23:16]/0x40
[31:24]/0x41
[39:32]/0x42
[47:40]/0x43
[7:0]/0x44
[15:8]/0x45
[23:16]/0x46
[31:24]/0x47
[39:32]/0x48
[47:40]/0x49
[7:0]/0x4A
[15:8]/0x4B
[23:16]/0x4C
[31:24]/0x4D
[39:32]/0x4E
[47:40]/0x4F
[7:0]/0x50
[15:8]/0x51
[23:16]/0x52
[31:24]/0x53
[39:32]/0x54
[47:40]/0x55
Profile 0
(0x09)
Profile 1
(0x0A)
Profile 2
(0x0B)
Profile 3
(0x0C)
Profile 4
(0x0D)
Profile 5
(0x0E)
Profile 6
(0x0F)
Profile 7
(0x10)
1
MSB
Bit 7
Bit 6
Open [1:0]
Open [1:0]
Open [1:0]
Open [1:0]
Open [1:0]
Open [1:0]
Open
Open
Open
Open
Bit 5
Bit 4
Bit 3
Bit 2
Rising Sweep Ramp Rate Word [7:0]
Rising Sweep Ramp Rate Word [15:8]
Falling Sweep Ramp Rate Word [7:0]
Falling Sweep Ramp Rate Word [15:8]
Frequency Tuning Word [7:0]
Frequency Tuning Word [15:8]
Frequency Tuning Word [23:16]
Frequency Tuning Word [31:24]
Phase Offset Word [7:0]
Phase Offset Word [13:8]
Frequency Tuning Word [7:0]
Frequency Tuning Word [15:8]
Frequency Tuning Word [23:16]
Frequency Tuning Word [31:24]
Phase Offset Word [7:0]
Phase Offset Word [13:8]
Frequency Tuning Word [7:0]
Frequency Tuning Word [15:8]
Frequency Tuning Word [23:16]
Frequency Tuning Word [31:24]
Phase Offset Word [7:0]
Phase Offset Word [13:8]
Frequency Tuning Word [7:0]
Frequency Tuning Word [15:8]
Frequency Tuning Word [23:16]
Frequency Tuning Word [31:24]
Phase Offset Word [7:0]
Phase Offset Word [13:8]
Frequency Tuning Word [7:0]
Frequency Tuning Word [15:8]
Frequency Tuning Word [23:16]
Frequency Tuning Word [31:24]
Phase Offset Word [7:0]
Phase Offset Word [13:8]
Frequency Tuning Word [7:0]
Frequency Tuning Word [15:8]
Frequency Tuning Word [23:16]
Frequency Tuning Word [31:24]
Phase Offset Word [7:0]
Phase Offset Word [13:8]
Frequency Tuning Word [7:0]
Frequency Tuning Word [15:8]
Frequency Tuning Word [23:16]
Frequency Tuning Word [31:24]
Phase Offset Word [7:0]
Phase Offset Word [13:8]
Frequency Tuning Word [7:0]
Frequency Tuning Word [15:8]
Frequency Tuning Word [23:16]
Frequency Tuning Word [31:24]
Phase Offset Word [7:0]
Phase Offset Word [13:8]
Bit 1
LSB
Bit 0
Default
Value
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
These bits are active immediately following the write sequence of the byte in which they reside in. As a result, they do not require an I/O_UPDATE to enable/disable.
Rev. E | Page 27 of 32
AD9913
Data Sheet
REGISTER BIT DESCRIPTIONS
The serial I/O port registers span an address range of 0 to 16
(0x00 to 0x10 in hexadecimal notation). This represents a total
of 17 registers. However, one of these registers (0x05) is
unused, yielding a total of 16 available registers.
The registers are not of uniform depth; each contains the
number of bytes necessary for its particular function.
Additionally, the registers are assigned names according to
their functionality. In some cases, a register is given a
mnemonic descriptor. For example, the register at Serial
Address 0x00 is named Control Function Register 1 and is
assigned the mnemonic CFR1.
The following section provides a detailed description of each bit
in the AD9913 register map. For cases in which a group of bits
serve a specific function, the entire group is considered as a
binary word and described in aggregate.
This section is organized in sequential order of the serial
addresses of the registers. Each subheading includes the register
name and optional register mnemonic (in parentheses). Also
given is the serial address in hexadecimal format and the
number of bytes assigned to the register.
Following each subheading is a table containing the individual
bit descriptions for that particular register. The location of the
bit(s) in the register are indicated by a single number or a pair
of numbers separated by a colon. A pair of numbers (A:B)
indicates a range of bits from the most significant (A) to the
least significant (B). For example, 5:2 implies Bit Position 5
down to Bit Position 2, inclusive, with Bit 0 identifying the LSB
of the register.
Unless otherwise stated, programmed bits are not transferred to their internal destinations until the assertion of
the I/O_UPDATE pin.
Control Function Register 1 (CFR1)
Address 0x00; 4 bytes are assigned to this register.
Table 10. Bit Description for CFR1
Bit(s)
31:29
28
Bit Name
Open
Modulus Enable
27
Use Internal Profile
26
Match Pipeline Delays Active
25:24
23
Open
LSB First
22:20
Internal Profile Control
19
Sync Clock Disable
18:17
16
Open
Direct Switch Mode Active
15
Clear Auxiliary Accumulator
14
Clear Phase Accumulator
Description
Leave these bits at their default values.
This bit is ignored if linear sweep is disabled.
0 = the auxiliary accumulator is used for linear sweep generation.
1 = the auxiliary accumulator is used for programmable modulus.
0 = profiles are controlled by profile pins; only valid in serial mode.
1 = profiles are controlled by CFR1 [22:20].
0 = the latency across the auxiliary accumulator, the phase offset word, and phase
accumulator are matched.
1 = the latency across the auxiliary accumulator, the phase offset word, and phase
accumulator are not matched.
Leave these bits at the default values.
0 = MSB first format is used.
1 = LSB first format is used.
Ineffective unless Bit 27 = 1. Default is 0002. Refer to the Linear Sweep Mode section for
details on how to program these registers during linear sweep, and refer to the Direct
Switch Mode section for details on how to program these registers in direct switch mode.
0 = the SYNC_CLK pin is active.
1 = the SYNC_CLK pin assumes a static Logic 0 state (disabled). In this state, the pin drive
logic is shut down, minimizing the noise generated by the digital circuitry.
Leave these bits in their default values.
0 = direct switch mode is disabled.
1 = direct switch mode is enabled.
0 = normal operation of the auxiliary accumulator (default).
1 = asynchronous, static reset of the auxiliary accumulator. The ramp accumulator remains
reset as long as this bit remains set. This bit is synchronized with either an I/O update or a
profile change and the next rising edge of SYNC_CLK.
0 = normal operation of the DDS phase accumulator (default).
1 = asynchronous, static reset of the DDS phase accumulator.
Rev. E | Page 28 of 32
Data Sheet
AD9913
Bit(s)
13:12
Bit Name
Destination
Description
00 = In direct switch mode, use this setting for FSK.
In linear sweep mode, the auxiliary accumulator is used for frequency sweeping.
In programmable modulus mode, these bits must be 00.
01 = In direct switch mode, use this setting for PSK.
In linear sweep mode, the auxiliary accumulator is used for phase sweeping.
0 = auxiliary accumulator is inactive.
1 = auxiliary accumulator is active.
This bit is ignored if linear sweep is disabled (see CFR1 [11]).
0 = normal operating state.
1 = the output of the DAC is driven to full-scale and the DDS output is disabled.
0 = edge triggered mode active.
1 = state triggered mode active.
This bit is ignored if linear sweep is disabled (see CFR1[11]).
0 = when a sweep is completed, the device holds at the final state.
1 = when a sweep is completed, the device reverts to the initial state.
0 = the external power-down mode selected is the fast recovery power-down mode. In this
mode, when the PWR_DWN_CTL input pin is high, the digital logic and the DAC digital
logic are powered down. The DAC bias circuitry, PLL, oscillator, and clock input circuitry are
not powered down.
1 = the external power-down mode selected is the full power-down mode. In this mode,
when the PWR_DWN_CTL pin is high, all functions are powered down. This includes the
DAC and PLL, which take a significant amount of time to power up.
0 = the digital core is enabled for operation.
1 = the digital core is disabled and is in a low power dissipation state.
0 = the DAC is enabled for operation.
1 = the DAC is disabled and is in its lowest power dissipation state.
0 = normal operation.
1 = shut down all clock generation including the system clock signal going into the digital
section.
0 = every time the linear sweep rate register is updated, the ramp rate timer keeps its
operation until it times out and then loads the update value into the timer.
1 = the timer is interrupted immediately upon the assertion of IO_UPDATE and the value is
loaded.
11
Auxiliary Accumulator Enable
10
DC Output Active
9
8
Linear Sweep State Trigger
Active
Linear Sweep No-Dwell Active
7
External Power-Down Mode
6
Digital Power-Down
5
DAC Power-Down
4
Clock Input Power-Down
3
LOAD SRR @ IO_UPDATE
2
Autoclear Auxiliary
Accumulator
0 = normal operation.
1 = the auxiliary accumulator is synchronously cleared (zero is loaded) for one cycle upon
receipt of the IO_UPDATE sequence indicator.
1
Autoclear Phase Accumulator
0 = normal operation.
1 = the phase accumulator is synchronously cleared for one cycle upon receipt of the
IO_UPDATE sequence indicator.
0
Enable Sine Output
0 = the angle-to-amplitude conversion logic employs a cosine function.
1 = the angle-to-amplitude conversion logic employs a sine function.
Rev. E | Page 29 of 32
AD9913
Data Sheet
Control Function Register 2 (CFR2)
Address 0x01; 2 bytes are assigned to this register.
Table 11. Bit Descriptions for CFR2
Bit(s)
15
14:9
8
7
6
5
Bit Name
PLL Output Div by 2
PLL Multiplication Factor
Open
CMOS Clock Mode
Crystal Clock Mode
PLL Power-Down
4
PLL LO Range
3
PLL Input Div by 2
2
VCO2 Sel
1
PLL Reset
0
PLL Lock
Description
See Table 7 for details on multiplication factor configuration.
Leave this bit at the default state.
See Table 6 for directions on programming this bit.
See Table 6 for directions on programming this bit.
0 = PLL is active
1 = PLL is inactive and in its lowest power state
0 = use this setting for PLL if the PLL reference frequency is >5 MHz.
1 = use this setting for PLL if the PLL reference frequency is
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