Dual-Channel, 14-Bit, CCD Signal
Processor with Precision Timing Core
AD9974
FEATURES
GENERAL DESCRIPTION
1.8 V analog and digital core supply voltage
Correlated double sampler (CDS) with
−3 dB, 0 dB, +3 dB, and +6 dB gain
6 dB to 42 dB, 10-bit variable gain amplifier (VGA)
14-bit, 65 MHz analog-to-digital converter (ADC)
Black level clamp with variable level control
Complete on-chip timing generator
Precision Timing core with 240 ps resolution @ 65 MHz
On-chip 3 V horizontal and RG drivers
100-lead, 9 mm × 9 mm, 0.8 mm pitch, CSP_BGA package
Internal low dropout (LDO) regulator circuitry
The AD9974 is a highly integrated, dual-channel, chargecoupled device (CCD) signal processor for high speed digital
video camera applications. Each channel is specified at pixel
rates of up to 65 MHz. The AD9974 consists of a complete
analog front end (AFE) with analog-to-digital conversion,
combined with a programmable timing driver. The Precision
Timing™ core allows adjustment of high speed clocks with
approximately 240 ps resolution at 65 MHz operation.
Each AFE includes black level clamping, CDS, VGA, and
a 65 MSPS, 14-bit ADC. The timing driver provides the high
speed CCD clock drivers for the RG_A, RG_B, H1_A to H4_A,
and H1_B to H4_B outputs. A 3-wire serial interface is used to
program each channel of the AD9974.
APPLICATIONS
Professional HDTV camcorders
Professional/high end digital cameras
Broadcast cameras
Industrial high speed cameras
Available in a space-saving, 9 mm × 9 mm, CSP_BGA package,
the AD9974 is specified over an operating temperature range of
−25°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
REFT_A REFB_A
REFT_B REFB_B
VREF_A
VREF_B
AD9974
CCDINP_A
14
CDS
CCDINM_A
DOUT_A
ADC
VGA
6dB TO 42dB
–3, 0, +3, +6dB
CLAMP
CLAMP
6dB TO 42dB
–3, 0, +3, +6dB
CCDINP_B
CDS
14
ADC
VGA
DOUT_B
CCDINM_B
1.8V OUTPUT
LDO A
1.8V OUTPUT
LDO B
RG_A
RG_B
H1_B TO H4_B
PRECISION
TIMING
CORE
4
4
CLI_A
CLI_B
HORIZONTAL
DRIVERS
SYNC
GENERATOR
INTERNAL
REGISTERS
HD_A VD_A HD_B VD_B
SL_A SDATA_A SL_B SDATA_B
SCK_A
SCK_B
05955-001
H1_A TO H4_A
INTERNAL CLOCKS
Figure 1.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
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Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2009 Analog Devices, Inc. All rights reserved.
AD9974
TABLE OF CONTENTS
Features .............................................................................................. 1
Precision Timing High Speed Timing Core ............................. 15
Applications ....................................................................................... 1
Horizontal Clamping and Blanking ......................................... 18
General Description ......................................................................... 1
Complete Field—Combining H-Patterns ............................... 25
Functional Block Diagram .............................................................. 1
Mode Registers ........................................................................... 26
Revision History ............................................................................... 2
Horizontal Timing Sequence Example.................................... 28
Specifications..................................................................................... 3
Analog Front End Description and Operation ...................... 29
Channel-to-Channel Specifications ........................................... 3
Applications Information .............................................................. 33
Timing Specifications .................................................................. 4
Recommended Power-Up Sequence ....................................... 33
Digital Specifications ................................................................... 5
Standby Mode Operation .......................................................... 36
Analog Specifications ................................................................... 6
CLI Frequency Change .............................................................. 36
Absolute Maximum Ratings............................................................ 8
Circuit Configuration ................................................................ 37
Thermal Characteristics .............................................................. 8
Grounding and Decoupling Recommendations .................... 37
ESD Caution .................................................................................. 8
3-Wire Serial Interface Timing ..................................................... 39
Pin Configuration and Function Descriptions ............................. 9
Layout of Internal Registers ...................................................... 40
Typical Performance Characteristics ........................................... 11
Updating of Register Values ...................................................... 41
Equivalent Input/Output Circuits ................................................ 12
Complete Register Listing ............................................................. 42
Terminology .................................................................................... 13
Outline Dimensions ....................................................................... 50
Theory of Operation ...................................................................... 14
Ordering Guide .......................................................................... 50
Programmable Timing Generation .............................................. 15
REVISION HISTORY
10/09—Revision A: Initial Version
Changes to Table 1 ............................................................................ 3
Changes to Table 3 ............................................................................ 4
Changes to Pin Function Descriptions Table ............................... 9
Changes to Figure 11 ...................................................................... 12
Changes to Individual HBLK Pattern Section ............................ 20
Changes to Table 14 ........................................................................ 25
Added Example Register Setting for Power-Up Section ........... 34
Added Additional Restrictions Section ....................................... 35
Changes to Table 2 .......................................................................... 36
Changes to 3 V System Compatibility Section ........................... 37
Changes to Grounding and Decoupling
Recommendations Section ............................................................ 37
Changes to Table 30 ........................................................................ 48
Changes to Table 31 ........................................................................ 49
Changes to Ordering Guide .......................................................... 50
Rev. A | Page 2 of 52
AD9974
SPECIFICATIONS
X = A = B, unless otherwise noted.
Table 1.
Parameter
TEMPERATURE RANGE
Operating
Storage
POWER SUPPLY VOLTAGE
AVDD_X (AFE, Timing Core)
RGVDD_X (RG_X Driver)
HVDD_X (H1_X to H4_X Drivers)
DVDD_X (All Other Digital)
DRVDD_X (Parallel Data Output Drivers)
IOVDD_X (I/O Supply Without the Use of LDO)
POWER SUPPLY CURRENTS—65 MHz OPERATION
AVDD_X (1.8 V)
RGVDD_X (3.3 V, 20 pF RG Load)
HVDD_X 1 (3.3 V, 200 pF Total Load on H1 to H4)
DVDD_X (1.8 V)
DRVDD_X (3.0 V)
IOVDD_X (1.8 V)
POWER SUPPLY CURRENTS—STANDBY MODE OPERATION
Reference Standby
Total Shutdown
LDO 2
IOVDD_X (I/O Supply When Using LDO)
Output Voltage
Output Current
CLOCK RATE (CLI)
Min
Typ
−25
−65
1.6
2.7
2.7
1.6
1.6
1.6
8
1.8
3.3
3.3
1.8
3.0
1.8
Max
Unit
+85
+150
°C
°C
2.0
3.6
3.6
2.0
3.6
3.6
V
V
V
V
V
V
55
5
40
15
3
2
mA
mA
mA
mA
mA
mA
10
0.5
mA
mA
3.0
1.85
60
V
V
mA
MHz
100
65
1
The total power dissipated by the HVDD (or RGVDD) supply can be approximated as follows: Total HVDD Power = [CLOAD × HVDD × Pixel Frequency] × HVDD.
Reducing the capacitive load and/or reducing the HVDD supply reduces the power dissipation. CLOAD is the total capacitance seen by all H-outputs.
2
LDO should be used to supply only AVDD and DVDD.
CHANNEL-TO-CHANNEL SPECIFICATIONS
X = A = B, TMIN to TMAX, AVDD_X = DVDD_X = 1.8 V, fCLI = 65 MHz, typical timing specifications, unless otherwise noted.
Table 2.
Parameter
LINEARITY MISMATCH 1
CROSSTALK ERROR
Channel A to Channel B
Channel B to Channel A
1
Min
Typ
Vx, VSG1 > VSGx, SUBCK
H1_A TO H4_A, RG_A
H1_B TO H4_B, RG_B
The H-drivers for H1 to H4 and RG are included in the
AD9974, allowing these clocks to be directly connected to the
CCD. An H-driver voltage of 3 V is supported in the AD9974.
DOUT_A
DOUT_B
CCDINP_A
CCDINM_A
CCD
CCDINP_B
AD9974
INTEGRATED
HD_A, VD_A,
AFE + TD
HD_B, VD_B
DIGITAL IMAGE
PROCESSING
ASIC
CCDINM_B
05955-014
CLI_A, CLI_B
SERIAL
INTERFACE
Figure 15 and Figure 16 show the maximum horizontal and
vertical counter dimensions for the AD9974. All internal horizontal
and vertical clocking is controlled by these counters, which specify
line and pixel locations. Maximum HD length is 8191 pixels per
line, and maximum VD length is 8191 lines per field.
MAXIMUM COUNTER DIMENSIONS
Figure 14. Typical Application
13-BIT HORIZONTAL = 8192 PIXELS MAX
13-BIT VERTICAL = 8192 LINES MAX
05955-015
Figure 14 shows the typical system block diagram for the AD9974.
The charge-coupled device (CCD) output is processed by the
analog front-end (AFE) circuitry of the AD9974, consisting of a
CDS, VGA, black level clamp, and ADC. The digitized pixel
information is sent to the digital image processor chip, which
performs the postprocessing and compression. To operate the
CCD, all CCD timing parameters are programmed into the
AD9974 from the system ASIC through the 3-wire serial
interface. From the system master clock, CLI_X, which is provided
by the image processor or external crystal, the AD9974 generates
the horizontal clocks of the CCD and all internal AFE clocks.
Figure 15. Vertical and Horizontal Counters
MAX VD LENGTH IS 8192 LINES
VD
MAX HD LENGTH IS 8192 PIXELS
HD
05955-016
CLI
Figure 16. Maximum VD/HD Dimensions
Rev. A | Page 14 of 52
AD9974
PROGRAMMABLE TIMING GENERATION
Using a 65 MHz CLI frequency, the edge resolution of the
Precision Timing core is approximately 240 ps. If a 1× system
clock is not available, it is possible to use a 2× reference clock
by programming the CLIDIVIDE register (Address 0x0D). The
AD9974 then internally divides the CLI frequency by 2.
PRECISION TIMING HIGH SPEED TIMING CORE
The AD9974 generates flexible high speed timing signals using
the Precision Timing core. This core, composed of the Reset
Gate RG, Horizontal Driver H1 to Horizontal Driver H4, and
SHP/SHD sample clocks, is the foundation for generating the
timing for both the CCD and the AFE. A unique architecture
makes it routine for the system designer to optimize image
quality by providing precise control over the horizontal CCD
readout and the AFE correlated double sampling.
High Speed Clock Programmability
Figure 18 shows when the high speed clocks, RG, H1 to H4,
SHP, and SHD, are generated. The RG pulse has programmable
rising and falling edges and can be inverted using the polarity
control. The H1 and H2 horizontal clocks have separate programmable rising and falling edges, as well as separate polarity control.
The AD9974 provides additional HCLK-mode programmability,
as described in Table 9.
Timing Resolution
The Precision Timing core uses a master clock input (CLI_X)
as a reference. This clock input should be the same as the CCD
pixel clock frequency. Figure 17 illustrates how the internal timing
core divides the master clock period into 64 steps or edge positions;
therefore, the edge resolution of the Precision Timing core is
(tCLI/64). For more information on using the CLI input, refer to
the Applications Information section.
POSITION
P[0]
P[16]
The edge location registers are each six bits wide, allowing the
selection of all 64 edge locations. Figure 21 shows the default
timing locations for all of the high speed clock signals.
P[32]
P[48]
P[64] = P[0]
CLI
tCLIDLY
1 PIXEL
PERIOD
05955-017
NOTES
1. THE PIXEL CLOCK PERIOD IS DIVIDED INTO 64 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.
2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITION (tCLIDLY).
Figure 17. High Speed Clock Resolution from CLI Master Clock Input
1
2
CCD
SIGNAL
3
4
RG
5
6
H1, H3
H2, H4
05955-018
PROGRAMMABLE CLOCK POSITIONS:
1SHP SAMPLE LOCATION.
2SHD SAMPLE LOCATION.
3RG RISING EDGE.
4RG FALLING EDGE.
5H1 RISING EDGE.
6H1 FALLING EDGE.
Figure 18. High Speed Clock Programmable Locations (HCLK Mode 1)
Rev. A | Page 15 of 52
AD9974
1
2
H1, H3
4
3
H2, H4
05955-019
H1 TO H4 PROGRAMMABLE LOCATIONS:
1H1 RISING EDGE.
2H1 FALLING EDGE.
3H2 RISING EDGE.
4H2 FALLING EDGE.
Figure 19. HCLK Mode 2 Operation
1
2
H1
H2
3
4
H3
H4
05955-020
H1 TO H4 PROGRAMMABLE LOCATIONS:
1H1 RISING EDGE.
2H1 FALLING EDGE.
3H3 RISING EDGE.
4H3 FALLING EDGE.
Figure 20. HCLK Mode 3 Operation
POSITION
P[0]
P[16]
RGr[0]
RGf[16]
P[32]
P[48]
P[64] = P[0]
CLI
RG
H1r[0]
H1f[32]
H1
H2
tS1
CCD
SIGNAL
SHPLOC[32]
SHP
tSHPINH
SHDLOC[0]
tSHDINH
SHD
DATAPHASEP[32]
tDOUTINH
NOTES
1. ALL SIGNAL EDGES ARE FULLY PROGRAMMABLE TO ANY OF THE 64 POSITIONS WITHIN ONE PIXEL PERIOD.
TYPICAL POSITIONS FOR EACH SIGNAL ARE SHOWN. HCLK MODE 1 IS SHOWN.
2. CERTAIN POSITIONS SHOULD BE AVOIDED FOR EACH SIGNAL, SHOWN ABOVE AS INHIBIT REGIONS.
3. IF A SETTING IN THE INHIBIT REGION IS USED, AN UNSTABLE PIXEL SHIFT CAN OCCUR IN THE HBLK LOCATION OR AFE PIPELINE.
Figure 21. High Speed Timing Default Locations
Rev. A | Page 16 of 52
05955-021
DOUTPHASEP
AD9974
Table 9. HCLK Modes, Selected by HCLKMODE Register (Address 0x23[7:5])
HCLK Mode
Mode 1
Mode 2
Register Value
001
010
Mode 3
100
Invalid Selection
000, 011, 101, 110, 111
Description
H1 edges are programmable, with H3 = H1 and H2 = H4 = inverse of H1.
H1 edges are programmable, with H3 = H1.
H2 edges are programmable, with H4 = H2.
H1 edges are programmable, with H2 = inverse of H1.
H3 edges are programmable, with H4 = inverse of H3.
Invalid register settings.
Table 10. H1, H2, RGCONTROL, DRVCONTROL, and SAMPCONTROL Register Parameters
Parameter
Polarity
Length (Bits)
1
Range
High/low
Positive Edge
Negative Edge
Sample Location
Drive Control
6
6
6
3
0 to 63 edge location
0 to 63 edge location
0 to 63 sample location
0 to 7 current steps
Description
Polarity control for H1/H3 and RG.
0 = no inversion.
1 = inversion.
Positive edge location for H1/H3 and RG.
Negative edge location for H1/H3 and RG.
Sampling location for SHP and SHD.
Drive current for H1 to H4 and RG outputs, 0 to 7 steps of 4.3 mA each.
CLI
tCLIDLY
N
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N–14
N–13
N–12
N–11
N–10
N+8
N+9
N+10
N+11
N+12
N+13
N+14
N+15
N+16
N+17
N–9
N–8
N–7
N–6
N–5
N–4
N–3
N–2
N–1
N
CCDIN
SAMPLE PIXEL N
SHD
(INTERNAL)
ADC OUT
(INTERNAL)
N–17
N–16
N–15
N+1
tDOUTINH
DOUTPHASE
CLK
PIPELINE LATENCY = 16 CYCLES
N–16
N–15
N–14
N–13
N–12
N–11
N–10
N–9
N–8
N–7
N–6
N–5
N–4
N–3
N–2
N–1
NOTES
1. EXAMPLE SHOWN FOR SHDLOC = 0.
2. HIGHER VALUES OF SHD AND/OR DOUTPHASE WILL SHIFT DOUT TRANSITION TO THE RIGHT, WITH RESPECT TO CLI LOCATION.
N
N+1
05955-022
DOUT
N–17
Figure 22. Pipeline Delay of AFE Data Outputs
H-Driver and RG Outputs
Digital Data Outputs
In addition to the programmable timing positions, the AD9974
features on-chip output drivers for the RG and H1 to H4 outputs.
These drivers are powerful enough to drive the CCD inputs
directly. The H-driver and RG-driver current can be adjusted
for optimum rise/fall time into a particular load by using the
drive strength control registers (Address 0x35). Use the register
to adjust the drive strength in 4.3 mA increments. The minimum
setting of 0 is equal to off or three-state, and the maximum setting
of 7 is equal to 30.1 mA.
For maximum system flexibility, the AD9974 uses the
DOUTPHASE registers (Address 0x37[11:0]) to select the
location for the start of each new pixel data value. Any edge
location from 0 to 63 can be programmed. These registers
determine the start location of the data output and the DCLK
rising edge with respect to the master clock input, CLI_X.
The pipeline delay through the AD9974 is shown in Figure 22.
After the CCD input is sampled by SHD, there is a 16-cycle
delay until the data is available.
Rev. A | Page 17 of 52
AD9974
HORIZONTAL CLAMPING AND BLANKING
CLPOB and PBLK Masking Area
The horizontal clamping and blanking pulses of the AD9974 are
fully programmable to suit a variety of applications. Individual
control is provided for CLPOB, PBLK, and HBLK during the
different regions of each field. This allows the dark pixel clamping
and blanking patterns to be changed at each stage of the readout
to accommodate different image transfer timing and high speed
line shifts.
Additionally, the AD9974 allows the CLPOB and PBLK signals
to be disabled during certain lines in the field without changing
any of the existing pattern settings. There are three sets of start
and end registers for both CLPOB and PBLK that allow the
creation of up to three masking areas for each signal.
Individual CLPOB and PBLK Patterns
The AFE horizontal timing consists of CLPOB and PBLK, as
shown in Figure 23. These two signals are programmed independently using the registers in Table 11. The start polarity for
the CLPOB or PBLK signal is CLPOB_POL (PBLK_POL), and the
first and second toggle positions of the pulse are CLPOB_TOG1
(PBLK_TOG1) and CLPOB_TOG2 (PBLK_TOG2). Both signals
are active low and need to be programmed accordingly.
Two separate patterns for CLPOB and PBLK can be programmed
for each H-pattern, CLPOB0, CLPOB1, PBLK0, and PBLK1.
The CLPOB_PAT and PBLK_PAT field registers select which
of the two patterns is used in each field.
For example, to use the CLPOB masking, program the
CLPOBMASKSTART and CLPOBMASKEND registers to
specify the starting and ending lines in the field where the CLPOB
patterns are to be ignored. Figure 24 illustrates this feature.
The masking registers are not specific to a certain H-pattern;
they are always active for any existing field of timing. To disable
the CLPOB and PBLK masking feature, set these registers to the
maximum value of 0x1FFF.
Note that to disable CLPOB and PBLK masking during
power-up, it is recommended that CLPOBMASKSTART
(PBLKMASKSTART) be set to 8191 and CLPOBMASKEND
(PBLKMASKEND) be set to 0. This prevents any accidental
masking caused by different register update events.
Figure 34 shows how the sequence change positions divide the
readout field into different regions. By assigning a different
H-pattern to each region, the CLPOB and PBLK signals can
change with each change in the vertical timing.
HD
2
CLPOB 1
PBLK
3
ACTIVE
ACTIVE
PROGRAMMABLE SETTINGS:
BLANK REGION ARE ACTIVE LOW).
05955-023
1START POLARITY (CLAMP AND
2FIRST TOGGLE POSITION.
3SECOND TOGGLE POSITION.
Figure 23. Clamp and Preblank Pulse Placement
NO CLPOB SIGNAL
FOR LINE 600
NO CLPOB SIGNAL
FOR LINES 6 TO 8
VD
0
1
2
597 598
HD
CLPOBMASKSTART1 = 6
CLPOBMASKEND1 = 8
CLPOBMASKSTART2 = CLPOBMASKEND2 = 600
Figure 24. CLPOB Masking Example
Rev. A | Page 18 of 52
05957-024
CLPOB
AD9974
Table 11. CLPOB and PBLK Pattern Registers
Parameter
CLPOB0_TOG1
CLPOB0_TOG2
CLPOB1_TOG1
CLPOB1_TOG2
CLPOB_POL
CLPOB_PAT
CLPOBMASKSTART
CLPOBMASKEND
PBLK0_TOG1
PBLK0_TOG2
PBLK1_TOG1
PBLK1_TOG2
PBLK_POL
PBLK_PAT
PBLKMASKSTART
PBLKMASKEND
Length (Bits)
13
13
13
13
9
9
13
13
13
13
13
13
9
9
13
13
Range
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
High/low
0 to 9 settings
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
High/low
0 to 9 settings
0 to 8191 pixel location
0 to 8191 pixel location
Description
First CLPOB0 toggle position within the line for each V-sequence.
Second CLPOB0 toggle position within the line for each V-sequence.
First CLPOB1 toggle position within the line for each V-sequence.
Second CLPOB1 toggle position within the line for each V-sequence.
Starting polarity of CLPOB for each V-sequence [8:0] (in field registers).
CLPOB pattern selection for each V-sequence [8:0] (in field registers).
CLPOB mask start position: three values available (in field registers).
CLPOB mask end position: three values available (in field registers).
First PBLK0 toggle position within the line for each V-sequence.
Second PBLK0 toggle position within the line for each V-sequence.
First PBLK1 toggle position within the line for each V-sequence.
Second toggle position within the line for each V-sequence.
Starting polarity of PBLK for each V-sequence [8:0] (in field registers).
PBLK pattern selection for each V-sequence [8:0] (in field registers).
PBLK mask start position: three values available (in field registers).
PBLK mask end position: three values available (in field registers).
HD
HBLK
HBLKTOGE2
BLANK
BLANK
BASIC HBLK PULSE IS GENERATED USING HBLKTOGE1 AND HBLKTOGE2 REGISTERS (HBLKALT = 0).
05955-025
HBLKTOGE1
Figure 25. Typical Horizontal Blanking Pulse Placement (HBLKMODE = 0)
HD
HBLK
H1/H3
THE POLARITY OF H1/H3 DURING BLANKING IS PROGRAMMABLE
(H2/H4 POLARITY IS SEPARATELY PROGRAMMABLE)
05955-026
H1/H3
H2/H4
Figure 26. HBLK Masking Control
Rev. A | Page 19 of 52
AD9974
Individual HBLK Patterns
HBLK Mode 0 Operation
The HBLK programmable timing shown in Figure 25 is similar
to CLPOB and PBLK; however, there is no start polarity control.
Only the toggle positions designate the start and the stop positions
of the blanking period. Additionally, as shown in Figure 26, there
is a polarity control, HBLKMASK, for H1/H3 and H2/H4 that
designates the polarity of the horizontal clock signals during the
blanking period. Setting HBLKMASK_H1 low sets H1 = H3 =
low and HBLKMASK_H2 high sets H2 = H4 = high during the
blanking. As with the CLPOB and PBLK signals, HBLK registers
are available in each H-pattern group, allowing unique blanking
signals to be used with different vertical timing sequences.
There are six toggle positions available for HBLK. Normally,
only two of the toggle positions are used to generate the standard
HBLK interval. However, the additional toggle positions can be
used to generate special HBLK patterns, as shown in Figure 27.
The pattern in this example uses all six toggle positions to generate
two extra groups of pulses during the HBLK interval. By changing
the toggle positions, different patterns are created.
Separate toggle positions are available for even and odd lines.
If alternation is not needed, load the same values into the registers
for even (HBLKTOGE) and odd (HBLKTOGO) lines.
The AD9974 supports three modes of HBLK operation. HBLK
Mode 0 supports basic operation and provides some support for
special HBLK patterns. HBLK Mode 1 supports pixel mixing
HBLK operation. HBLK Mode 2 supports advanced HBLK operation. The following sections describe each mode. Register
parameters are detailed in Table 12.
HBLKTOGE2
HBLKTOGE1
HBLKTOGE4
HBLKTOGE3
HBLKTOGE6
HBLKTOGE5
HBLK
H1/H3
SPECIAL H-BLANK PATTERN IS CREATED USING MULTIPLE HBLK TOGGLE POSITIONS (HBLKALT = 0).
05955-027
H2/H4
Figure 27. Generating Special HBLK Patterns
Table 12. HBLK Pattern Registers
Register
HBLK_MODE
Length (Bits)
2
Range
0 to 2 HBLK modes
HBLKSTART
HBLKEND
HBLKLEN
HBLKREP
HBLKMASK_H1
HBLKMASK_H2
13
13
13
13
1
1
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixels
0 to 8191 repetitions
High/low
High/low
Description
Enables different HBLK toggle position operations.
0 = normal mode. Six toggle positions available for even and odd lines.
If even/odd alternation is not needed, set toggles for even/odd the same.
1 = pixel mixing mode. In addition to six toggle positions, the HBLKSTART,
HBLKEND, HBLKLEN, and HBLKREP registers can be used to generate HBLK
patterns. If even/odd alternation is not needed, set toggles for even/odd
the same.
2 = advanced HBLK mode. Divides HBLK interval into six different repeat
areas. Uses HBLKSTARTA/B/C and RA*H*REPA/B/C registers.
3 = test mode only. Do not access.
Start location for HBLK in HBLK Mode 1 and HBLK Mode 2.
End location for HBLK in HBLK Mode 1 and HBLK Mode 2.
HBLK length in HBLK Mode 1 and HBLK Mode 2.
Number of HBLK repetitions in HBLK Mode 1 and HBLK Mode 2.
Masking polarity for H1 and H3 during HBLK.
Masking polarity for H2 and H4 during HBLK.
Rev. A | Page 20 of 52
AD9974
Register
HBLKTOGO1
HBLKTOGO2
HBLKTOGO3
HBLKTOGO4
HBLKTOGO5
HBLKTOGO6
HBLKTOGE1
HBLKTOGE2
HBLKTOGE3
HBLKTOGE4
HBLKTOGE5
HBLKTOGE6
RA0H1REPA/B/C
Length (Bits)
13
13
13
13
13
13
13
13
13
13
13
13
12
Range
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
0 to 15 HCLK pulses
for each A, B, and C
RA1H1REPA/B/C
RA2H1REPA/B/C
RA3H1REPA/B/C
RA4H1REPA/B/C
RA5H1REPA/B/C
RA0H2REPA/B/C
12
12
12
12
12
12
0 to 15 HCLK pulses
0 to 15 HCLK pulses
0 to 15 HCLK pulses
0 to 15 HCLK pulses
0 to 15 HCLK pulses
0 to 15 HCLK pulses
for each A, B, and C
RA1H2REPA/B/C
RA2H2REPA/B/C
RA3H2REPA/B/C
RA4H2REPA/B/C
RA5H2REPA/B/C
HBLKSTARTA
HBLKSTARTB
HBLKSTARTC
HBLKALT_PAT1
12
12
12
12
12
13
13
13
3
0 to 15 HCLK pulses
0 to 15 HCLK pulses
0 to 15 HCLK pulses
0 to 15 HCLK pulses
0 to 15 HCLK pulses
0 to 8191 pixel location
0 to 8191 pixel location
0 to 8191 pixel location
0 to 5 even repeat area
HBLKALT_PAT2
HBLKALT_PAT3
HBLKALT_PAT4
HBLKALT_PAT5
HBLKALT_PAT6
3
3
3
3
3
0 to 5 even repeat area
0 to 5 even repeat area
0 to 5 even repeat area
0 to 5 even repeat area
0 to 5 even repeat area
Description
First HBLK toggle position for odd lines in HBLK Mode 0 and HBLK Mode 1.
Second HBLK toggle position for odd lines in HBLK Mode 0 and HBLK Mode 1.
Third HBLK toggle position for odd lines in HBLK Mode 0 and HBLK Mode 1.
Fourth HBLK toggle position for odd lines in HBLK Mode 0 and HBLK Mode 1.
Fifth HBLK toggle position for odd lines in HBLK Mode 0 and HBLK Mode 1.
Sixth HBLK toggle position for odd lines in HBLK Mode 0 and HBLK Mode 1.
First HBLK toggle position for even lines in HBLK Mode 0 and HBLK Mode 1.
Second HBLK toggle position for even lines in HBLK Mode 0 and HBLK Mode 1.
Third HBLK toggle position for even lines in HBLK Mode 0 and HBLK Mode 1.
Fourth HBLK toggle position for even lines in HBLK Mode 0 and HBLK Mode 1.
Fifth HBLK toggle position for even lines in HBLK Mode 0 and HBLK Mode 1.
Sixth HBLK toggle position for even lines in HBLK Mode 0 and HBLK Mode 1.
HBLK Repeat Area 0. Number of H1 repetitions for HBLKSTARTA/B/C in
HBLK Mode 2 for even lines; odd lines are defined using HBLKALT_PAT.
[3:0] RA0H1REPA. Number of H1 pulses following HBLKSTARTA.
[7:4] RA0H1REPB. Number of H1 pulses following HBLKSTARTB.
[11:8] RA0H1REPC. Number of H1 pulses following HBLKSTARTC.
HBLK Repeat Area 1. Number of H1 repetitions for HBLKSTARTA/B/C.
HBLK Repeat Area 2. Number of H1 repetitions for HBLKSTARTA/B/C.
HBLK Repeat Area 3. Number of H1 repetitions for HBLKSTARTA/B/C.
HBLK Repeat Area 4. Number of H1 repetitions for HBLKSTARTA/B/C.
HBLK Repeat Area 5. Number of H1 repetitions for HBLKSTARTA/B/C.
HBLK Repeat Area 0. Number of H2 repetitions for HBLKSTARTA/B/C in
HBLK Mode 2 for even lines; odd lines are defined using HBLKALT_PAT.
[3:0] RA0H2REPA. Number of H2 pulses following HBLKSTARTA.
[7:4] RA0H2REPB. Number of H2 pulses following HBLKSTARTB.
[11:8] RA0H2REPC. Number of H2 pulses following HBLKSTARTC.
HBLK Repeat Area 1. Number of H2 repetitions for HBLKSTARTA/B/C.
HBLK Repeat Area 2. Number of H2 repetitions for HBLKSTARTA/B/C.
HBLK Repeat Area 3. Number of H2 repetitions for HBLKSTARTA/B/C.
HBLK Repeat Area 4. Number of H2 repetitions for HBLKSTARTA/B/C.
HBLK Repeat Area 5. Number of H2 repetitions for HBLKSTARTA/B/C.
HBLK Repeat Area Start Position A for HBLK Mode 2.
HBLK Repeat Area Start Position B for HBLK Mode 2.
HBLK Repeat Area Start Position C for HBLK Mode 2.
HBLK Mode 2, Odd Field Repeat Area 0 pattern, selected from even field.
Repeat areas previously defined.
HBLK Mode 2, Odd Field Repeat Area 1 pattern.
HBLK Mode 2, Odd Field Repeat Area 2 pattern.
HBLK Mode 2, Odd Field Repeat Area 3 pattern.
HBLK Mode 2, Odd Field Repeat Area 4 pattern.
HBLK Mode 2, Odd Field Repeat Area 5 pattern.
Rev. A | Page 21 of 52
AD9974
HBLK Mode 1 Operation
Increasing H-Clock Width During HBLK
Enable multiple repeats of the HBLK signal by setting
HBLK_MODE to 1. In this mode, the HBLK pattern can be
generated using a different set of registers: HBLKSTART,
HBLKEND, HBLKLEN, and HBLKREP, along with the six
toggle positions (see Figure 28).
HBLK Mode 0 and HBLK Mode 1 allow the H1 to H4 pulse
width to be increased during the HBLK interval. As shown in
Figure 29, the H-clock frequency can be reduced by a factor of
1/2, 1/4, 1/6, 1/8, 1/10, 1/12, and so on, up to 1/30. To enable this
feature, the HCLK_WIDTH register (Address 0x34[7:4]) is set to
a value between 1 and 15. When this register is set to 0, the wide
HCLK feature is disabled. The reduced frequency occurs only for
H1 to H4 pulses that are located within the HBLK area.
Separate toggle positions are available for even and odd lines.
If alternation is not needed, load the same values into the registers
for even (HBLKTOGE) and odd (HBLKTOGO) lines.
Generating HBLK Line Alternation
HBLK Mode 0 and HBLK Mode 1 provide the ability to
alternate different HBLK toggle positions on even and odd
lines. Separate toggle positions are available for even and odd
lines. If even/odd line alternation is not required, load the same
values into the registers for even (HBLKTOGE) and odd
(HBLKTOGO) lines.
The HCLK_WIDTH register is generally used in conjunction
with special HBLK patterns to generate vertical and horizontal
mixing in the CCD.
Note that the wide HCLK feature is available only in HBLK Mode 0
and HBLK Mode 1, not in HBLK Mode 2.
Table 13. HCLK Width Register
Register
HCLK_WIDTH
Length (Bits)
4
Description
Controls H1 to H4 width during HBLK as a fraction of pixel rate.
0 = same frequency as pixel rate.
1 = 1/2 pixel frequency, that is, doubles the HCLK pulse width.
2 = 1/4 pixel frequency.
3 = 1/6 pixel frequency.
4 = 1/8 pixel frequency.
5 = 1/10 pixel frequency.
…
15 = 1/30 pixel frequency.
HBLKTOGE2
HBLKTOGE4
HBLKSTART HBLKTOGE1
HBLKTOGE3
HBLKEND
HBLK
HBLKLEN
HBLKREP = 3
H1/H3
HBLKREP NUMBER 1
HBLKREP NUMBER 2
05955-028
H2/H4
HBLKREP NUMBER 3
H-BLANK REPEATING PATTERN IS CREATED USING HBLKLEN AND HBLKREP REGISTERS.
Figure 28. HBLK Repeating Pattern Using HBLKMODE = 1
HBLK
H1/H3
1/FPIX
2 × (1/FPIX)
H-CLOCK FREQUENCY CAN BE REDUCED DURING HBLK BY 1/2 (AS SHOWN),
1/4, 1/6, 1/8, 1/10, 1/12, AND SO ON, UP TO 1/30 USING HBLKWIDTH REGISTER.
Figure 29. Generating Wide H-Clock Pulses During HBLK Interval
Rev. A | Page 22 of 52
05955-029
H2/H4
AD9974
Figure 31 shows the following example:
HBLK Mode 2 Operation
RA0H1REPA/RA0H1REPB/RA0H1REPC =
RA0H2REPA/RA0H2REPB/RA0H2REPC =
RA1H1REPA/RA1H1REPB/RA1H1REPC =
RA1H2REPA/RA1H2REPB/RA1H2REPC = 2.
HBLK Mode 2 allows more advanced HBLK pattern operation.
If unevenly spaced HCLK pulses in multiple areas are needed,
HBLK Mode 2 can be used. Using a separate set of registers,
HBLK Mode 2 can divide the HBLK region into up to six repeat
areas (see Table 12). As shown in Figure 31, each repeat area
shares a common group of toggle positions, HBLKSTARTA,
HBLKSTARTB, and HBLKSTARTC. However, the number of
toggles following each start position can be unique in each
repeat area by using the RAH1REP and RAH2REP registers.
As shown in Figure 30, setting the RAH1REPA/RAH1REPB/
RAH1REPC or RAH2REPA/RAH2REPB/RAH2REPC registers
to 0 masks HCLK groups from appearing in a particular repeat
area. Figure 31 shows only two repeat areas being used, although
six are available. It is possible to program a separate number of
repeat area repetitions for H1 and H2, but generally the same
value is used for both H1 and H2.
HD
CREATE UP TO 3 GROUPS OF TOGGLES
A, B, C COMMON IN ALL REPEAT AREAS
A
Furthermore, HBLK Mode 2 allows a different HBLK pattern
on even and odd lines. The HBLKSTARTA, HBLKSTARTB, and
HBLKSTARTC registers, as well as the RAH1REPA/RAH1REPB/
RAH1REPC and RAH2REPA/RAH2REPB/RAH2REPC registers,
define operation for the even lines. For separate control of the
odd lines, the HBLKALT_PAT registers specify up to six repeat
areas on the odd lines by reordering the repeat areas used for the
even lines. New patterns are not available, but the order of the
previously defined repeat areas on the even lines can be changed
for the odd lines to accommodate advanced CCD operation.
CHANGE NUMBER OF A, B, C PULSES IN ANY
REPEAT AREA USING RA*H*REP* REGISTERS
MASK A, B, C PULSES IN ANY REPEAT
AREA BY SETTING RA*H*REP* = 0
B
C
H1
REPEAT AREA 0
REPEAT AREA 1
REPEAT AREA 2
REPEAT AREA 3
REPEAT AREA 4
REPEAT AREA 5
HBLKSTART
HBLKEND
05955-030
H2
Figure 30. HBLK Mode 2 Operation
HD
HBLKLEN
HBLK
HBLKSTARTA
ALL RA*H*REPA, B, C REGISTERS = 2, TO CREATE 2 HCLK PULSES
HBLKSTARTB
HBLKSTARTC
H1
RA0H1REPA RA0H1REPB
RA0H1REPC
RA1H1REPA RA1H1REPB
RA1H1REPC
RA1H2REPA RA1H2REPB
RA1H2REPC
H2
RA0H2REPA RA0H2REPB
RA0H2REPC
REPEAT AREA 1
REPEAT AREA 0
HBLKREP = 2
TO CREATE 2 REPEAT AREAS
Figure 31. HBLK Mode 2 Registers
Rev. A | Page 23 of 52
HBLKEND
05955-031
HBLKSTART
AD9974
For example, if the desired toggle position is 100, CLPOB_TOG
should be set to 88 (that is, 100 − 12). Figure 49 shows the 12-cycle
pipeline delay referenced to the falling edge of HD.
HBLK, PBLK, and CLPOB Toggle Positions
The AD9974 uses an internal horizontal pixel counter to position
the HBLK, PBLK, and CLPOB toggle positions. The horizontal
counter does not reset to 0 until 12 CLI periods after the falling
edge of HD. This 12-cycle pipeline delay must be considered
when determining the register toggle positions. For example, if
CLPOB_TOG1 is 100 and the pipeline delay is not considered,
the final toggle position is applied at 112. To obtain the correct
toggle positions, the toggle position registers must be set to the
desired toggle position minus 12.
PIXEL NO.
Caution
Toggle positions cannot be programmed during the 12-cycle
delay from the HD falling edge until the H-counter has reset.
See Figure 33 for an example of this restriction.
0
60
100 103
112
HD
1
2
H1
3
1.
2.
3.
4.
HBLKTOG1
HBLKTOG2
CLPOB_TOG1
CLPOB_TOG2
DESIRED
TOGGLE
POSITION
ACTUAL
REGISTER
VALUE
60
100
103
112
(60 – 12) = 48
(100 – 12) = 88
(103 – 12) = 91
(112 – 12) = 100
4
05955-032
CLPOB
Figure 32. Example of Register Setting to Obtain Desired Toggle Positions
VD
H-COUNTER
RESET
HD
NO TOGGLE POSITIONS ALLOWED IN THIS AREA
X
X
X
X
N-12 N-11 N-10
N-9
N-8
N-7
N-6
N-5
N-4
N-3
N-2
N-1
N
0
NOTES
1. TOGGLE POSITIONS CANNOT BE PROGRAMMED WITHIN 12 PIXELS OF PIXEL 0 LOCATION.
Figure 33. Restriction for Toggle Position Placement
Rev. A | Page 24 of 52
1
2
05955-033
H-COUNTER
(PIXEL COUNTER)
AD9974
COMPLETE FIELD—COMBINING H-PATTERNS
H-Pattern Selection
After the H-patterns are created, they combine to create different
readout fields. A field consists of up to nine different regions
determined by the SCP registers. Within each region, a different
H-pattern group can be selected up to a maximum of 32 groups.
Registers to control the H-patterns are located in the field registers.
Table 31 describes the field registers.
The H-patterns are stored in the HPAT memory, as described in
Table 20. The user decides how many H-pattern groups are
required, up to a maximum of 32, and then uses the HPAT_SEL
registers to select which H-pattern group is output in each
region of the field. Figure 34 shows how to use the HPAT_SEL
and SCP registers. The SCP registers create the line boundaries
for each region.
SCP 1
SCP 0
SCP 2
SCP 3
SCP 4
SCP 5
SCP 8
VD
REGION 0
REGION 1
REGION 2
REGION 3
REGION 4
REGION 8
HPAT_SEL0
HPAT_SEL1
HPAT_SEL2
HPAT_SEL3
HPAT_SEL4
HPAT_SEL8
H-PATTERNS
FIELD SETTINGS:
1. SEQUENCE CHANGE POSITIONS (SCP0-8) DEFINE EACH OF THE NINE AVAILABLE REGIONS IN THE FIELD.
2. HPAT_SEL SELECTS THE DESIRED H-PATTERN FOR EACH REGION.
05955-034
HD
Figure 34. Complete Field Divided into Regions
Table 14. Field Registers
Register
SCPx
HPAT_SELx
CLPOB_POL
CLPOB_PAT
CLPOBMASKSTARTx,
CLPOBMASKENDx
PBLK_POL
PBLK_PAT
PBLKMASKSTARTx,
PBLKMASKENDx,
Length (Bits)
13
5
9
9
13
Range
0 to 8191 line number
0 to 31 H-patterns
High/low
0 to 9 patterns
Number of lines
Description
Sequence change position for each region. Selects an individual line.
Selected H-pattern for each region of the field.
CLPOB start polarity settings for each region of the field.
CLPOB pattern selector for each region of the field.
CLPOB mask positions for up to three masking configurations.
9
9
13
High/low
0 to 9 patterns
Number of lines
PBLK start polarity settings for each region of the field.
PBLK pattern selector for each region of the field.
PBLK mask positions for up to three masking configurations.
Rev. A | Page 25 of 52
AD9974
MODE REGISTERS
The mode registers contain registers to select the final field timing
of the AD9974. Typically, all of the field and H-pattern group
information is programmed into the AD9974 at startup. During
operation, the mode registers allow the user to select any combination of field timing to meet the current requirements of the
system. The advantage of using the mode registers in conjunction
with preprogrammed timing is that they greatly reduce the system
programming requirements during camera operation. Only a few
register writes are required when the camera operating mode is
changed, rather than having to write in all of the vertical timing
information with each camera mode change.
A basic still camera application can require five fields of horizontal timing: one for draft mode operation, one for autofocusing,
and three for still image readout. With the AD9974, all of the
register timing information for the five fields is loaded at startup.
Then, during camera operation, the mode registers select
which field timing to activate, depending on how the camera
is being used.
The AD9974 supports up to seven field sequences selected from
up to 31 preprogrammed field groups using the FIELD_SEL
registers. When FIELDNUM is greater than 1, the AD9974 starts
with Field 1 and increments to each Field n at the start of each VD.
Figure 35 provides examples of mode configuration settings.
This example assumes to have four field groups, Field Group 0
to Field Group 3, stored in memory.
Table 15. Mode Registers
Register
HPATNUM
FIELDNUM
FIELD_SEL1
FIELD_SEL2
FIELD_SEL3
FIELD_SEL4
FIELD_SEL5
FIELD_SEL6
FIELD_SEL7
Length (Bits)
5
3
5
5
5
5
5
5
5
Range
0 to 31 H-pattern groups
0 to 7 fields
0 to 31 field groups
0 to 31 field groups
0 to 31 field groups
0 to 31 field groups
0 to 31 field groups
0 to 31 field groups
0 to 31 field groups
Description
Total number of H-pattern groups, starting at Address 0x800.
Total number of applied fields. Set to 1 for single-field operation.
Selected first field.
Selected second field.
Selected third field.
Selected fourth field.
Selected fifth field.
Selected sixth field.
Selected seventh field.
Rev. A | Page 26 of 52
AD9974
H-PATTERN MEMORY
FIELD 0
FIELD 1
FIELD 2
FIELD 3
EXAMPLE 1:
TOTAL FIELDS = 3, FIRST FIELD = FIELD 0, SECOND FIELD = FIELD 1, THIRD FIELD = FIELD 2
FIELD_SEL1 = 0
FIELD 0
FIELD_SEL2 = 1
FIELD 1
FIELD_SEL3 = 2
FIELD 2
EXAMPLE 2:
TOTAL FIELDS = 1, FIRST FIELD = FIELD 3
FIELD_SEL1 = 3
FIELD 3
EXAMPLE 3:
TOTAL FIELDS = 4, FIRST FIELD = FIELD 5, SECOND FIELD = FIELD 1, THIRD FIELD = FIELD 4, FOURTH FIELD = FIELD 2
FIELD 5
FIELD_SEL2 = 1
FIELD 1
FIELD_SEL3 = 4
FIELD 4
FIELD_SEL4 = 2
FIELD 2
05955-035
FIELD_SEL1 = 5
Figure 35. Example of Mode Configurations
Rev. A | Page 27 of 52
AD9974
Figure 36 shows an example of a CCD layout. The horizontal
register contains 28 dummy pixels that occur on each line
clocked from the CCD. In the vertical direction, there are
10 optical black (OB) lines at the front of the readout and two
at the back of the readout. The horizontal direction has four
OB pixels in the front and 48 in the back.
Figure 37 shows the basic sequence layout to use during the
effective pixel readout. The 48 OB pixels at the end of each line
are used for the CLPOB signals. PBLK is optional and is often
used to blank the digital outputs during the HBLK time. HBLK
is used during the vertical shift interval.
The CLPOBMASK registers are also useful for disabling the
CLPOB on a few lines without affecting the setup of the
clamping sequences. It is important to use CLPOB only during
valid OB pixels. During other portions on the frame timing,
such as vertical blanking or SG line timing, the CCD does not
output valid OB pixels. Any CLPOB pulse that occurs during
this time causes errors in clamping operation and, therefore,
changes in the black level of the image.
2 VERTICAL
OB LINES
Because PBLK is used to isolate the CDS input (see the Analog
Front End Description and Operation section), do not use the
PBLK signal during CLPOB operation. The change in the offset
behavior that occurs during PBLK impacts the accuracy of the
CLPOB circuitry.
V
EFFECTIVE IMAGE AREA
10 VERTICAL
OB LINES
The HBLK, CLPOB, and PBLK parameters are programmed
in the V-sequence registers. More elaborate clamping schemes,
such as adding a separate sequence to clamp all the shielded
OB lines, can be used. This requires configuring a separate
V-sequence for clocking out the OB lines.
H
48 OB PIXELS
4 OB PIXELS
HORIZONTAL CCD REGISTER
05955-036
HORIZONTAL TIMING SEQUENCE EXAMPLE
28 DUMMY PIXELS
Figure 36. Example CCD Configuration
OPTICAL BLACK
OB
HD
CCD OUTPUT
VERTICAL SHIFT
DUMMY
EFFECTIVE PIXELS
OPTICAL BLACK
VERT. SHIFT
SHP
SHD
H1/H3
H2/H4
HBLK
PBLK
NOTES
1. PBLK ACTIVE (LOW) SHOULD NOT BE USED DURING CLPOB ACTIVE (LOW).
Figure 37. Horizontal Sequence Example
Rev. A | Page 28 of 52
05955-037
CLPOB
AD9974
ANALOG FRONT END DESCRIPTION AND OPERATION
0.1µF 0.1µF
REFB REFT
0.4V
1.4V
AD9974
DC RESTORE
SHP
PBLK (WHEN DCBYP = 1)
SHP
SHD
0.1µF
CCDIN
DOUT PHASE
INTERNAL
VREF
2V FULL SCALE
6dB ~ 42dB
S11
–3dB, 0dB,
+3dB, +6dB
S22
PBLK
1S1
2S2
CDS GAIN
REGISTER
CLI
VGA GAIN
REGISTER
DAC
PRECISION
TIMING
GENERATION
DOUT
OPTICAL BLACK
CLAMP
DIGITAL
FILTER
CLPOB
14
CLPOB PBLK
IS NORMALLY CLOSED.
IS NORMALLY OPEN.
DOUT
SHP SHD PHASE
OUTPUT
DATA
LATCH
14-BIT
ADC
VGA
CDS
BLANK TO
ZERO OR
CLAMP LEVEL
CLAMP LEVEL
REGISTER
PBLK
VD
V-H
TIMING
GENERATION
HD
05955-038
1.2V
Figure 38. Channel A and Channel B Analog Front End Functional Block Diagram
During the PBLK active time, the ADC outputs can be
programmed to output all 0s or the programmed clamp level.
The AD9974 signal processing chain is shown in Figure 38.
Each processing step is essential for achieving a high quality
image from the raw CCD pixel data.
DC Restore
To reduce the large dc offset of the CCD output signal, a dc
restore circuit is used with an external 0.1 μF series coupling
capacitor. This restores the dc level of the CCD signal to approximately 1.2 V, making it compatible with the 1.8 V core supply
voltage of the AD9974. The dc restore switch is active during
the SHP sample pulse time.
The dc restore circuit can be disabled when the optional PBLK
signal is used to isolate large-signal swings from the CCD input
(see the Analog Preblanking section). Bit 6 of Address 0x00
controls whether the dc restore is active during the PBLK interval.
Analog Preblanking
During certain CCD blanking or substrate clocking intervals,
the CCD input signal to the AD9974 may increase in amplitude
beyond the recommended input range. The PBLK signal can be
used to isolate the CDS input from large-signal swings. As shown
in Figure 38, when PBLK is active (low), the CDS input is isolated
from the CCDIN pin (S1 open) and is internally shorted to
ground (S2 closed).
Note that because the CDS input is shorted during PBLK, the
CLPOB pulse should not be used during the same active time as
the PBLK pulse.
Correlated Double Sampler (CDS)
The CDS circuit samples each CCD pixel twice to extract the
video information and to reject low frequency noise. The timing
shown in Figure 21 illustrates how the two internally generated
CDS clocks, SHP and SHD, are used to sample the reference
level and data level of the CCD signal, respectively. The placement
of the SHP and SHD sampling edges is determined by the setting
of the SHPLOC and SHDLOC register located at Address 0x36.
Placement of these two clock signals is critical for achieving the
best performance from the CCD. The CDS gain is variable in
four steps by using the AFE Register Address 0x04: −3 dB, 0 dB
(default), +3 dB, and +6 dB. Improved noise performance results
from using the +3 dB and +6 dB settings, but the input range is
reduced (see Table 5).
Rev. A | Page 29 of 52
AD9974
(N) SIGNAL SAMPLE
Input Configurations
(N) RESET SAMPLE
The CDS circuit samples each CCD pixel twice to extract the video
information and reject low frequency noise (see Figure 39). There
are three possible configurations for the CDS: inverting CDS mode,
noninverting CDS mode, and SHA mode. The CDSMODE
register (Address 0x00[9:8]) selects which configuration is used.
(N + 1) RESET SAMPLE
VDD
RESET LEVEL
(VRST )
05955-041
SHP
SIGNAL LEVEL
(VFS)
CCDINP
SHA1
Figure 41. Traditional Inverting CDS Signal
DIFF
AMP
CCDINM
CDS_OUT
Table 16. Inverting Voltage Levels
Signal Level
Saturation
Reset
Supply Voltage
05955-039
SHA2
SHD
Figure 39. CDS Block Diagram (Conceptual)
Symbol
VFS
VRST
VDD
Min (mV)
VDD − 500
1600
Typ (mV)
1000
VDD − 300
1800
Max (mV)
1400
VDD
2000
Inverting CDS Mode
Noninverting Input
For this configuration, the signal from the CCD is applied to the
positive input of the (CCDINP) CDS system with the minus
side (CCDINM) grounded (see Figure 40). The CDSMODE
register setting for this configuration is 0x00. Traditional CCD
applications use this configuration with the reset level established
below the AVDD supply level by the AD9974 dc restore circuit,
at approximately 1.5 V. The maximum saturation level is 1.0 V
below the reset level, as shown in Figure 41 and Table 16. A maximum saturation voltage of 1.4 V is also possible when using the
minimum CDS gain setting.
If the noninverting input is desired, the reset (or black) level
signal is established at a voltage above ground potential.
Saturation (or white) level is approximately 1 V. Samples are
taken at each signal level. See Figure 42 and Table 17.
SIGNAL LEVEL
(VFS)
(N) RESET SAMPLE
AD9974
GND
(N) SIGNAL SAMPLE
05955-042
RESET LEVEL
(VRST)
CCDINP
IMAGE
SENSOR
(N + 1) RESET SAMPLE
Figure 42. Noninverting CDS Signal
SHA/
CDS
CCDINM
Figure 40. Single Input CDS Configuration
05955-040
Table 17. Noninverting Voltage Levels
NOTES
1. COUPLING CAPACITOR IS NOT REQUIRED FOR CERTAIN
BLACK LEVEL REFERENCE VOLTAGES.
Signal Level
Saturation
Reset
Rev. A | Page 30 of 52
Symbol
VFS
VRST
Min (mV)
0
Typ (mV)
1000
250
Max (mV)
1400
500
AD9974
SHA Mode—Differential Input Configuration
Referring to Figure 46 and Table 19, the CCDINM signal is a
constant dc voltage set at a level above ground potential. The
sensor signal is applied to the other input, and samples are taken
at the signal minimum and at a point of signal maximum. The
resulting differential signal is the difference between the signal
and the reference voltage.
This configuration uses a differential input sample/hold
amplifier (SHA) (see Figure 43).
AD9974
CCDINP
IMAGE
SENSOR
SHA/
CDS
(N + 1) SIGNAL SAMPLE
(N) SIGNAL SAMPLE
05955-043
CCDINM
Figure 43. SHA Mode—Differential Input Configuration
In this configuration, a signal is applied to the CCDINP input
and, simultaneously, an inverse signal is applied to the CCDINM
input. Sampling occurs on both signals at the same time. This
creates the differential output for amplification and the ADC
(see Figure 44 and Table 18).
PEAK SIGNAL
LEVEL (VFS)
INPUT_POS
BLACK SIGNAL LEVEL (VBLK)
05955-046
INPUT_NEG
MINIMUM SIGNAL LEVEL (VMIN)
GND
(N + 1) SIGNAL SAMPLE
Figure 46. SHA Mode—Single–Ended Input Signal (DC-Coupled)
(N) SIGNAL SAMPLE
Table 19. SHA Mode—Single-Ended Input Voltages
Signal Level
Black
Saturation
Minimum
INPUT_POS
BLACK SIGNAL LEVEL (VBLK)
PEAK SIGNAL
LEVEL (VFS)
INPUT_NEG
Figure 44. SHA Mode—Differential Input Signal
Table 18. SHA Mode—Differential Voltage Levels
Signal Level
Black
Saturation
Minimum
Symbol
VBLK
VFS
VMIN
Min (mV)
1000
0
Typ (mV)
0
VDD − 300
1800
Max (mV)
1400
0
Max (mV)
SHA Timing Control
1400
When SHA mode is selected, only the SHPLOC setting is used
to sample the input signal, but the SHDLOC signal should still
be programmed to an edge setting of SHPLOC + 32.
The SHA mode can also be used in a single-ended fashion, with
the signal from the image sensor applied to the CDS/SHA using
a single input, CCDINP. This is similar to the differential configuration, except in this case, the CCDINM line is held at a constant
dc voltage, establishing a reference level that matches the image
sensor reference voltage (see Figure 45).
AD9974
CCDINP
SHA/
CDS
05955-045
CCDINM
NOTES
1. DC VOLTAGE ABOVE GROUND MAYBE USED TO
MATCH THE SENSOR REFERENCE LEVEL.
Typ (mV)
0
1000
The timing shown in Figure 21 illustrates how the two internally
generated CDS clocks, SHP and SHD, are used to sample the
reference level and data level of the CCD signal, respectively. The
placement of the SHP and SHD sampling edges is determined by
the setting of the SHPLOC and SHDLOC register located at
Address 0x36. Placement of these two clock signals is critical in
achieving the best performance from the CCD.
SHA Mode—DC-Coupled, Single–Ended Input
IMAGE
SENSOR
Min (mV)
CDS Timing Control
05955-044
MINIMUM SIGNAL LEVEL (VMIN)
GND
Symbol
VBLK
VFS
VMIN
Figure 45. SHA Mode—Single–Ended Input Configuration, DC-Coupled
Rev. A | Page 31 of 52
AD9974
Variable Gain Amplifier
Optical Black Clamp
The VGA stage provides a gain range of approximately 6 dB to
42 dB, programmable with 10-bit resolution through the serial
digital interface. A gain of 6 dB is needed to match a 1 V input
signal with the ADC full-scale range of 2 V. When compared to
1 V full-scale systems, the equivalent gain range is 0 dB to 36 dB.
The optical black clamp loop is used to remove residual offsets
in the signal chain and track low frequency variations in the
CCD black level. During the optical black (shielded) pixel interval
on each line, the ADC output is compared with a fixed black
level reference, selected by the user in the clamp level register.
The value can be programmed between 0 LSB and 1023 LSB in
1023 steps.
The VGA gain curve follows a linear-in-dB characteristic. The
exact VGA gain is calculated for any gain register value by
The resulting error signal is filtered to reduce noise, and the
correction value is applied to the ADC input through a DAC.
Normally, the optical black clamp loop is turned on once per
horizontal line, but this loop can be updated more slowly to suit
a particular application. If external digital clamping is used during
postprocessing, the AD9974 optical black clamping can be disabled
using Bit 3 in AFE Register Address 0x00. When the loop is
disabled, the clamp level register can still be used to provide
fixed offset adjustment.
Gain (dB) = (0.0359 × Code) + 5.1 dB
where Code is the range of 0 to 1023.
42
VGA GAIN (dB)
36
30
24
Note that if the CLPOB loop is disabled, higher VGA gain
settings reduce the dynamic range because the uncorrected
offset in the signal path is gained up.
18
6
0
127
255
383
511
639
767
VGA GAIN REGISTER CODE
895
1023
05955-047
12
Figure 47. VGA Gain Curve
ADC
The AD9974 uses a high performance ADC architecture optimized for high speed and low power. Differential nonlinearity
(DNL) performance is typically better than 0.5 LSB. The ADC
uses a 2 V input range. See Figure 5, Figure 6, and Figure 7 for
typical noise performance and linearity plots for the AD9974.
The CLPOB pulse should be aligned with the optical black
pixels of the CCD. It is recommended that the CLPOB pulse
duration be at least 20 pixels wide. Shorter pulse widths can be
used, but the ability of the loop to track low frequency variations
in the black level is reduced. See the Horizontal Clamping and
Blanking section for more timing information.
Digital Data Outputs
The AD9974 digital output data is latched using the DOUTPHASE
register value, as shown in Figure 38. Output data timing is shown
in Figure 22. The switching of the data outputs can couple noise
back into the analog signal path. To minimize any switching
noise while using default SHPLOC and SHDLOC, it is
recommended that the DOUTPHASEP register be set to a value
between 36 and 47. Other settings can produce good results, but
experimentation is necessary.
Rev. A | Page 32 of 52
AD9974
APPLICATIONS INFORMATION
RECOMMENDED POWER-UP SEQUENCE
5.
When the AD9974 is powered up, the following sequence is
recommended (see Figure 48 for each step).
6.
1.
2.
3.
4.
Turn on the power supplies for the AD9974 and apply CLI
clock. There is no required sequence for turning on each
supply.
Although the AD9974 contains an on-chip power-on reset,
a software reset of the internal registers is recommended.
Write 1 to the SW_RST register (Address 0x10) to reset all
the internal registers to their default values. This bit is selfclearing and automatically resets to 0.
Write to the desired registers to configure high speed timing
and horizontal timing. Note that all TESTMODE registers
must be written as described in the Complete Register
Listing section.
To place the part into normal power operation, write 0 to the
STANDBY and REFBUF_PWRDN registers (Address 0x00).
The Precision Timing core must be reset by writing 1 to the
TGCORE_RST register (Address 0x14). This starts the
internal timing core operation.
Write 1 to the OUT_CONTROL register (Address 0x11).
The next VD/HD falling edge allows register updates to occur,
including OUT_CONTROL, which enables all clock outputs.
Additional Restrictions
When operating, note the following restrictions:
•
•
The HD falling edge should be located in the same CLI
clock cycle as the VD falling edge or after the VD falling
edge. The HD falling edge should not be located between
one and five cycles prior to the VD falling edge.
If possible, perform all start-up serial writes with VD and
HD disabled. This prevents unknown behavior caused by
partial updating of registers before all information is loaded.
The internal horizontal counter is reset 12 CLI cycles after the
falling edge of HD. See Figure 49 for details on how the internal
counter is reset.
AD9974 SUPPLIES
POWER
SUPPLIES
0V
1
CLI
(INPUT)
2
3
4
5
6
SERIAL
WRITES
1V
VD
(INPUT)
1ST FIELD
1H
HD
(INPUT)
CLOCKS ACTIVE WHEN OUTCONTROL
REGISTER IS UPDATED AT VD/HD EDGE
H-CLOCKS
H2, H4
H1, H3, RG
Figure 48. Recommended Power-Up Sequence
Rev. A | Page 33 of 52
05955-048
HI-Z BY
DEFAULT
AD9974
Example Register Settings for Power-Up
The following settings can be used for basic operation. A single CLPOB pulse is used with only H-pattern and one field. Additional
HPATS and FIELDS can be added, as needed, along with different CLPOB toggle positions.
010
028
800
801
802
803
804
805
806
807
808
809
80a
80b
80c
80d
80e
80f
810
811
812
813
814
815
816
817
818
819
81a
81b
81c
81d
81e
81f
02a
02b
02c
000
014
011
0000001
0000001
0064000
3ffffff
3ffffff
0064000
3ffffff
3ffffff
0000000
0000000
0000000
0000000
0000000
0000000
00dc05a
3ffffff
3ffffff
3ffffff
1000000
1000800
1000800
1000800
0000800
0000000
0000000
0000000
0000001
1000800
1000800
1000800
0000001
1000800
0000000
0000000
0000001
0000000
0000000
0000008
0000001
0000001
//software reset
//total number of H-Pattern groups = 1
//HPAT0 HBLKTOGO1, TOGO2 settings
//unused HBLK odd toggles set to zero or max value
//unused HBLK odd toggles set to zero or max value
//HPAT0 HBLKTOGE1, TOGE2 settings
//unused HBLK Even toggles set to zero or max value
//unused HBLK Even toggles set to zero or max value
//HBLK StartA, B are not used
//HBLK StartC is not used
//HBLK alternation patterns are not used
//HBLKLEN, HBLKREP not used, HBLK masking pol = 0
//HBLKSTART, end not used
//test, set to zero
//CLPOB pat 0 toggles
//CLPOB pat 1 toggles not used, set to max
//PBLK pat 0 toggles not used, set to max
//PBLK pat 1 toggles not used, set to max
//FIELD0 SCP0, SCP1
//SCP2, SCP3 set same as SCP1
//SCP4, SCP5 set same as SCP1
//SCP6, SCP7 set same as SCP1
//SCP8 set same as SCP1
//select HPAT0 for all regions
//select HPAT0 for all regions
//test, set to zero
//CLPOB start polarity = HIGH
//CLPOB masking set to highest SCP value (no mask)
//CLPOB masking set to highest SCP value (no mask)
//CLPOB masking set to highest SCP value (no mask)
//PBLK start polarity = HIGH
//PBLK masking set to highest SCP value (no mask)
//PBLK masking set to highest SCP value (no mask)
//PBLK masking set to highest SCP value (no mask)
//total number of fields = 1
//field select = FIELD0
//field select = FIELD0
//AFE settings
//reset TGCORE
//enable outputs
Rev. A | Page 34 of 52
AD9974
VD
tVDHD
HD
3ns MIN
CLI
3ns MIN
tCLIDLY
SHD
INTERNAL
HD
INTERNAL
H-COUNTER
RESET
11.5 CYCLES
X X X X X X X X X X X X X X 0 1 2
NOTES
1. EXTERNAL HD FALLING EDGE IS LATCHED BY CLI RISING EDGE, THEN LATCHED AGAIN BY SHD INTERNAL FALLING EDGE.
2. INTERNAL H-COUNTER IS ALWAYS RESET 11.5 CLOCK CYCLES AFTER THE INTERNAL HD FALLING EDGE.
3. DEPENDING ON THE VALUE OF SHDLOC, H-COUNTER RESET CAN OCCUR 12 OR 13 CLI CLOCK EDGES AFTER THE EXTERNAL HD FALLING EDGE.
4. SHPLOC = 0 IS SHOWN IN THE ABOVE EXAMPLE. IN THIS CASE, THE H-COUNTER RESET OCCURS 12 CLI RISING EDGES AFTER HD FALLING EDGE.
5. HD FALLING EDGE SHOULD OCCUR COINCIDENT WITH VD FALLING EDGE (WITHIN SAME CLI CYCLE) OR AFTER VD FALLING EDGE. HD FALLING
EDGE SHOULD NOT OCCUR WITHIN 1 AND 5 CLI CYCLES IMMEDIATELY BEFORE VD FALLING EDGE.
05955-049
H-COUNTER
(PIXEL COUNTER)
Figure 49. Horizontal Counter Pipeline Delay
VD
H-COUNTER
RESET
HD
NO TOGGLE POSITIONS ALLOWED IN THIS AREA
X
X
X
X
X
X
N – 11 N – 10 N – 9 N – 8 N – 7 N – 6 N – 5 N – 4 N – 3 N – 2 N – 1
NOTES
1. TOGGLE POSITIONS CANNOT BE PROGRAMMED WITHIN 12 PIXELS OF PIXEL 0 LOCATION.
N
0
1
2
05955-050
H-COUNTER
(PIXEL COUNTER)
Figure 50. No-Toggle Positions
Additional Restrictions
•
When operating, note the following restrictions:
•
The HD falling edge should be located in the same CLI
clock cycle as the VD falling edge or later than the VD
falling edge. The HD falling edge should not be located
within 1 cycle prior to the VD falling edge.
If possible, perform all start-up serial writes with VD and
HD disabled. This prevents unknown behavior caused by
partial updating of registers before all information is loaded.
The internal horizontal counter is reset 12 CLI cycles after the
falling edge of HD. See Figure 49 for details on how the internal
counter is reset.
Rev. A | Page 35 of 52
AD9974
STANDBY MODE OPERATION
The AD9974 contains two standby modes to optimize the
overall power dissipation in a particular application. Bit 1 and
Bit 0 of Address 0x00 control the power-down state of the device.
STANDBY[1:0] = 00 = normal operation (full power)
STANDBY[1:0] = 01 = reference standby mode
STANDBY[1:0] = 10 or 11 = total shutdown mode
(lowest power)
When returning from total shutdown mode to normal operation,
the timing core must be reset at least 100 μs after the STANDBY
register is written to.
There is an additional register to disable the internal voltage
reference buffer (Address 0x00[2]) independently. By default
the buffer is disabled, but it must be enabled for normal operation.
CLI FREQUENCY CHANGE
Table 20 summarizes the operation of each power-down mode.
The OUT_CONTROL register takes priority over the reference
standby mode in determining the digital output states, but total
shutdown mode takes priority over OUT_CONTROL. Total
shutdown mode has the lowest power consumption.
If the input clock, CLI, is interrupted or changes to a different
frequency, the timing core must be reset for proper operation.
After the CLI clock has settled to the new frequency, or the
previous frequency has resumed, write 0 and then 1 to the
TGCORE_RST register (Address 0x14). This guarantees proper
timing core operation.
Table 20. Standby Mode Operation
I/O Block
AFE
Timing Core
H1
H2
H3
H4
HL
RG
DOUT
Total Shutdown (Default) 1, 2
Off
Off
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
Low 3
OUT_CONTROL = Low2
No change
No change
Low
High
Low
High
Low
Low
Low
1
Reference Standby
Only REFT, REFB on
On
Low (4.3 mA)
High (4.3 mA)
Low (4.3 mA)
High (4.3 mA)
Low (4.3 mA)
Low (4.3 mA)
Low
To exit total shutdown, write 00 to STANDBY (Address 0x00, Bits[1:0]), then reset the timing core after 100 μs to guarantee proper settling.
Total shutdown mode takes priority over OUT_CONTROL for determining the output polarities.
3
The status of the DOUT pins is unknown at power-up. Low status is guaranteed in total shutdown mode after the power-up sequence is completed.
2
Rev. A | Page 36 of 52
AD9974
CIRCUIT CONFIGURATION
The AD9974 recommended circuit configuration is shown in
Figure 51. Achieving good image quality from the AD9974
requires careful attention to PCB layout. All signals should
be routed to maintain low noise performance. The CCD_A
and CCD_B output signals should be directly routed to Pin A1
and Pin A7, respectively, through a 0.1 μF capacitor. The master
clock, CLI_X, should be carefully routed to Pin A3 and Pin A9
to minimize interference with the CCDIN_X, REFT_X, and
REFB_X signals.
The digital outputs and clock inputs should be connected to the
digital ASIC away from the analog and CCD clock signals. Placing
series resistors close to the digital output pins may help reduce
digital code transition noise. If the digital outputs must drive
a load larger than 20 pF, buffering is recommended to minimize
additional noise. If the digital ASIC can accept gray code, the
outputs of the AD9974 can be selected to output data in gray
code format using Register 0x01[2]. Compared with binary
coding, gray coding helps reduce potential digital transition noise.
The H1_X to H4_X and RG_X traces should have low inductance
to avoid excessive distortion of the signals. Heavier traces are
recommended because of the large transient current demand
on H1_X to H4_X from the capacitive load of the CCD. If possible,
physically locating the AD9974 closer to the CCD reduces the
inductance on these lines. As always, the routing path should be
as direct as possible from the AD9974 to the CCD.
The CLI_X and CCDIN_X PCB traces should be carefully matched
in length and impedance to achieve optimal channel-to-channel
matching performance.
3 V System Compatibility
GROUNDING AND DECOUPLING
RECOMMENDATIONS
As shown in Figure 51, a single ground plane is recommended
for the AD9974. This ground plane needs to be as continuous as
possible, particularly around the P-type, AI-type, and A-type
pins to ensure that all analog decoupling capacitors provide the
lowest possible impedance path between the power and bypass
pins and their respective ground pins. All high frequency
decoupling capacitors need to be located as close as possible to
the package pins.
All the supply pins must be decoupled to ground with good
quality, high frequency chip capacitors. There also needs to be
a 4.7 μF or larger bypass capacitor for each main supply, that is,
AVDD, RGVDD, HVDD, and DRVDD, although this is not
necessary for each individual pin. In most applications, it is
easier to share the supply for RGVDD and HVDD, which can
be done as long as the individual supply pins are separately
bypassed. A separate 3 V supply can be used for DRVDD, but
this supply pin still needs to be decoupled to the same ground
plane as the rest of the chip. A separate ground for DRVSS is not
recommended.
The reference bypass pins (REFT, REFB) must be decoupled to
ground as close as possible to their respective pins. The bridge
capacitor between REFT and REFB is recommended for pixel
rates greater than 40 MHz. The analog input capacitor (CCDINM,
CCDINP) also needs to be located close to the pin.
The GND connections should be tied to the lowest impedance
ground plane on the PCB. Performance does not degrade if
several of these GND connections are left unconnected for
routing purposes.
The AD9974 typical circuit connections for a 3 V system are
shown in Figure 51. This application uses an external 3.3 V
supply connected to the IOVDD input of the AD0074, which
also serves as the LDO input. The LDO generates a 1.8 V output
for the AD9974 core supply voltages, AVDD and DVDD. The
LDOOUT pin can then be connected directly to the AVDD and
DVDD pins. In this configuration, the LDOEN pin is tied high
to enable the LDO.
Alternatively, a separate 1.8 V regulated supply voltage may be
used to power the AVDD and DVDD pins. In this case, the
LDOOUT pin needs to be left floating, and the LDOEN pin
needs to be grounded. A typical circuit configuration for a 1.8 V
system is shown in Figure 51.
Rev. A | Page 37 of 52
AD9974
3V IOVDD SUPPLY
1.8V LDO OUTPUT A
RG_A OUTPUT
RG_A DRIVER SUPPLY
A8
CCDINP_B
AVDD_B
A7
RGVDD_B
CCDINM_B
A6
C9
C10
RGVSS_B
0.1µF
0.1µF
RG_B
A10
B10
GND
GND
LDO_OUT_B
B9
B6
C6
GND
GND
GND
D6
E6
E5
GND
GND
D5
C5
IOVDD_B
0.1µF
0.1µF
0.1µF
IOVDD_A
GND
B5
A5
B3
B4
LDO_OUT_A
0.1µF
RG_A
RGVSS_A
RGVDD_A
C4
A1
C3
CCDINM_A
0.1µF
D9
F7
G1
F8
H1
G7
J1
H7
K1
J7
G2
K7
H2
G8
K2
H8
3V
DRIVER
3V
DRIVER
Figure 51. Recommended Circuit Configuration
Rev. A | Page 38 of 52
CLI_B
COMMON MASTER
CLOCK INPUT
REFB_B
REFT_B
0.1µF
0.1µF
0.1µF
SL_B
SDATA_B
SCK_B
HD_B
VD_B
3
HD COMMON INPUT
VD COMMON INPUT
HVDD_B
HVSS_B 0.1µF
H1B
4
H2B
SERIAL
INTERFACE
FOR CHN B
H1B–H4B
DRIVER
SUPPLY
H1B–H4B
OUTPUTS
H3B
H4B
DVDD_B
DVSS_B
1.8V ANALOG
0.1µF SUPPLY
D0_B (LSB)
D1_B
D2_B
D3_B
D4_B
D5_B
D6_B
D7_B
H9
J9
AVSS_B
D8_B
D9_B
K10
D10_B
J10
H10
D11_B
D12_B
G10
K9
D13_B (MSB)
DRVDD_B
J8
DRVSS_B
F6
G6
GND
GND
GND
GND
D10_A
H6
G9
J6
K8
H3
K6
G3
0.1µF
14
D10
F2
D9_A
CHN A DATA
OUTPUTS
CCDINP_A
NOT DRAWN TO SCALE
F9
F1
J3
D8_A
D3
GND
D7_A
AD9974
K5
D6_A
F10
D4
J5
D5_A
F3
GND
D4_A
E9
GND
D3_A
F4
H5
D2_A
E10
GND
D1_A
E8
E3
G5
D0_A (LSB)
E4
F5
DVSS_A
E7
J2
0.1µF
D8
E2
GND
DVDD_A
1.8V ANALOG
SUPPLY
E1
GND
H4A
C8
DRVSS_A
H3A
B8
D2
0.1µF
HVDD_A
0.1µF HVSS_A
H1A
H1A–H4A 4
OUTPUTS
H2A
4.7µF
C2
4.7µF +
VD_A
C7
K3
HD_A
B2
DRVDD_A
H1A–H4A
DRIVER
SUPPLY
HD COMMON INPUT
VD COMMON INPUT
C1
G4
SCK_A
D7
H4
SDATA_A
1.8V ANALOG
SUPPLY
0.1µF
A9
D12_A
SL_A
CCD SIGNAL_B PLUS
B7
D13_A (MSB)
0.1µF
SERIAL
INTERFACE
FOR CHN A
1.8V LDO OUTPUT B
RG_B OUTPUT
RG_B DRIVER
SUPPLY
D1
J4
0.1µF
REFT_A
A4
D11_A
0.1µF
A2
AVSS_A
REFB_A
B1
CLI_A
COMMON MASTER
CLOCK INPUT
AVDD_A
+
A3
4.7µF
K4
CCD SIGNAL_A PLUS
1.8V ANALOG SUPPLY
3V IOVDD SUPPLY
+
4.7µF
14
CHN B DATA
OUTPUTS
AD9974
3-WIRE SERIAL INTERFACE TIMING
All of the internal registers of the AD9974 are accessed through
a 3-wire serial interface. Each register consists of a 12-bit address
and a 28-bit data-word. Both the 12-bit address and 28-bit dataword are written starting with the LSB. To write to each register,
a 40-bit operation is required, as shown in Figure 52. Although
many registers are fewer than 28 bits wide, all 28 bits must be
written for each register. For example, if the register is only 20 bits
wide, the upper eight bits are don’t cares and must be filled with
0s during the serial write operation. If fewer than 28 data bits
are written, the register is not updated with new data.
Figure 53 shows a more efficient way to write to the registers,
using the AD9974 address auto-increment capability. Using this
method, the lowest desired address is written first, followed by
multiple 28-bit data-words. Each new 28-bit data-word is
automatically written to the next highest register address. By
eliminating the need to write each 12-bit address, faster register
loading is achieved. Continuous write operations can be used,
starting with any register location.
12-BIT ADDRESS
SDATA
A0
A1
A2
A3
A4
A5
A6
A7
tDS
SCK
1
2
3
4
5
A8
28-BIT DATA
A9
A10
A11
D0
D1
D2
D3
D25
D26
D27
tDH
6
7
8
9
10
11
12
13
14
15
16
38
tLS
39
40
tLH
SL
05955-052
NOTES
1. SDATA BITS ARE LATCHED ON SCK RISING EDGES. SCK CAN IDLE HIGH OR LOW BETWEEN WRITE OPERATIONS.
2. ALL 40 BITS MUST BE WRITTEN: 12 BITS FOR ADDRESS AND 28 BITS FOR DATA.
3. IF THE REGISTER LENGTH IS
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