ADAU1372BCPZ

Quad ADC, Dual DAC, Low Latency, Low Power Codec ADAU1372 Data Sheet FEATURES APPLICATIONS Low latency, 24-bit ADCs and DACs 102 dB SNR (through PGA and ADC with A-weighted filter) 107 dB dynamic range (through DAC and headphone with A-weighted filter) Serial port sample rates from 8 kHz to 192 kHz 4 single-ended analog inputs, configurable as microphone or line inputs Dual stereo digital microphone inputs Stereo analog audio output, single-ended or differential, configurable as either line output or headphone driver PLL supporting any input clock rate from 8 MHz to 27 MHz Full-duplex, asynchronous sample rate converters (ASRCs) Power supplies Analog and digital input/output of 1.8 V to 3.3 V Low power (15.5 mW) I2C and SPI control interfaces for flexibility 5 multipurpose pins supporting dual stereo digital microphone inputs, mute, push-button volume controls Handsets, headsets, and headphones Bluetooth® handsets, headsets, and headphones Personal navigation devices Digital still and video cameras GENERAL DESCRIPTION The ADAU1372 is a codec with four inputs and two outputs, which incorporates asynchronous sample rate converters. Optimized for low latency and low power, the ADAU1372 is ideal for headsets, handsets, and headphones. The ADAU1372 has built-in programmable gain amplifiers (PGAs); thus, with the addition of just a few passive components and a crystal, the ADAU1372 provides a solution for headset audio needs, microphone preamplifiers, ADCs, DACs, headphone amplifiers, and serial ports for connections to an external DSP. Note that throughout this data sheet, multifunction pins, such as SCL/SCLK, are referred to either by the entire pin name or by a single function of the pin, for example, SCLK, when only that function is relevant. MICBIAS1 MICROPHONE BIAS GENERATORS ADAU1372 POWER MANAGEMENT IOVDD AVDD AVDD AVDD DVDD PD MICBIAS0 REG_OUT FUNCTIONAL BLOCK DIAGRAM LDO REGULATOR ADC_SDATA1/CLKOUT/MP6 PLL AIN0REF PGA CLOCK OSCILLATOR XTALI/MCLKIN XTALO Σ-Δ ADC AIN0 DECIMATOR AIN1REF PGA AIN1 Σ-Δ ADC DECIMATOR DMIC0_1/MP4 DMIC2_3/MP5 HPOUTLP/LOUTLP Σ-Δ DACs HPOUTRP/LOUTRP HPOUTLN/LOUTLN INPUT/OUTPUT SIGNAL ROUTING DIGITAL MICROPHONE INPUTS AIN2REF Σ-Δ DACs HPOUTRN/LOUTRN DECIMATOR PGA Σ-Δ ADC AIN2 BIDIRECTIONAL ASRCS AIN3REF DECIMATOR PGA AIN3 SERIAL I/O PORT Σ-Δ ADC I2C/SPI CONTROL INTERFACE 12702-001 SDA/MISO SCL/SCLK ADDR0/SS ADDR1/MOSI DAC_SDATA/MP0 ADC_SDATA0/MP1 BCLK LRCLK AGND AGND AGND DGND DGND CM Figure 1. Rev. 0 Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADAU1372 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Push-Button Volume Controls ................................................. 35  Applications ....................................................................................... 1  Mute ............................................................................................. 35  General Description ......................................................................... 1  Talkthrough Mode ..................................................................... 35  Functional Block Diagram .............................................................. 1  Serial Data Input/Output Ports .................................................... 36  Revision History ............................................................................... 3  Serial Port Initialization ............................................................ 36  Specifications..................................................................................... 4  Tristating Unused Channels...................................................... 37  Analog Performance Specifications ........................................... 4  Applications Information .............................................................. 39  Crystal Amplifier Specifications................................................. 7  Power Supply Bypass Capacitors .............................................. 39  Digital Input/Output Specifications........................................... 8  Layout .......................................................................................... 39  Power Supply Specifications........................................................ 8  Grounding ................................................................................... 39  Typical Power Consumption....................................................... 9  Exposed Pad PCB Design ......................................................... 39  Digital Filters ................................................................................. 9  System Block Diagram............................................................... 40  Digital Timing Specifications ................................................... 10  Register Summary: Low Latency Codec ..................................... 41  Absolute Maximum Ratings.......................................................... 13  Register Details: Low Latency Codec .......................................... 43  Thermal Resistance .................................................................... 13  Clock Control Register .............................................................. 43  ESD Caution ................................................................................ 13  PLL Denominator MSB Register .............................................. 44  Pin Configuration and Function Descriptions ........................... 14  PLL Denominator LSB Register ............................................... 44  Typical Performance Characteristics ........................................... 17  PLL Numerator MSB Register .................................................. 44  Theory of Operation ...................................................................... 24  PLL Numerator LSB Register.................................................... 44  System Clocking and Power-Up ................................................... 25  PLL Integer Setting Register ..................................................... 45  Initialization ................................................................................ 25  PLL Lock Flag Register .............................................................. 46  Clock Initialization ..................................................................... 25  CLKOUT Setting Selection Register ........................................ 46  PLL ............................................................................................... 25  Regulator Control Register ....................................................... 47  Clock Output............................................................................... 26  DAC Input Select Register ........................................................ 47  Power Sequencing ...................................................................... 26  Serial Data Output 0/Serial Data Output 1 Input Select Register ........................................................................................ 48  Signal Routing ................................................................................. 27  Input Signal Paths ........................................................................... 28  Analog Inputs .............................................................................. 28  Digital Microphone Input ......................................................... 29  Analog-to-Digital Converters ................................................... 29  Serial Data Output 2/Serial Data Output 3 Input Select Register ........................................................................................ 49  Serial Data Output 4/Serial Data Output 5 Input Select Register ........................................................................................ 50  Output Signal Paths ........................................................................ 30  Serial Data Output 6/Serial Data Output 7 Input Select Register ........................................................................................ 51  Analog Outputs........................................................................... 30  ADC_SDATA0/ADC_SDATA1 Channel Select Register ..... 53  Digital-to-Analog Converters ................................................... 30  Output ASRC0/Output ASRC1 Source Register .................... 53  Asynchronous Sample Rate Converters .................................. 30  Output ASRC2/Output ASRC3 Source Register .................... 54  Control Port..................................................................................... 31  Input ASRC Channel Select Register ....................................... 56  Burst Mode Communication .................................................... 31  ADC Control 0 Register ............................................................ 56  I C Port ........................................................................................ 31  ADC Control 1 Register ............................................................ 57  SPI Port ........................................................................................ 34  ADC Control 2 Register ............................................................ 58  Burst Mode Communication .................................................... 34  ADC Control 3 Register ............................................................ 59  Multipurpose Pins .......................................................................... 35  ADC0 Volume Control Register .............................................. 60  2 Rev. 0 | Page 2 of 92 Data Sheet ADAU1372 ADC1 Volume Control Register ...............................................60  MP1 Function Setting Register ................................................. 75  ADC2 Volume Control Register ...............................................61  MP4 Function Setting Register ................................................. 76  ADC3 Volume Control Register ...............................................61  MP5 Function Setting Register ................................................. 77  PGA Control 0 Register..............................................................62  MP6 Function Setting Register ................................................. 78  PGA Control 1 Register..............................................................62  Push-Button Volume Settings Register .................................... 79  PGA Control 2 Register..............................................................63  Push-Button Volume Control Assignment Register .............. 80  PGA Control 3 Register..............................................................64  Debounce Modes Register ......................................................... 81  PGA Slew Control Register........................................................64  Headphone Line Output Select Register .................................. 81  PGA 10 dB Gain Boost Register................................................65  Decimator Power Control Register .......................................... 82  Input and Output Capacitor Charging Register .....................66  ADC to DAC Talkthrough Bypass Path Register....................67  ASRC Interpolator and DAC Modulator Power Control Register ......................................................................................... 83  Talkthrough Bypass Gain for ADC0 Register .........................67  Analog Bias Control 0 Register ................................................. 84  Talkthrough Bypass Gain for ADC1 Register .........................67  Analog Bias Control 1 Register ................................................. 85  MICBIAS Control Register ........................................................68  Digital Pin Pull-Up Control 0 Register .................................... 86  DAC Control 1 Register .............................................................69  Digital Pin Pull-Up Control 1 Register .................................... 87  DAC0 Volume Control Register................................................69  Digital Pin Pull-Down Control 2 Register .............................. 88  DAC1 Volume Control Register................................................70  Digital Pin Pull-Down Control 3 Register .............................. 89  Headphone Output Mutes Register ..........................................70  Digital Pin Drive Strength Control 4 Register ........................ 90  Serial Port Control 0 Register ....................................................71  Digital Pin Drive Strength Control 5 Register ........................ 91  Serial Port Control 1 Register ....................................................72  Outline Dimensions ........................................................................ 92  TDM Output Channel Disable Register ..................................73  Ordering Guide ........................................................................... 92  MP0 Function Setting Register .................................................74  REVISION HISTORY 12/14—Revision 0: Initial Version Rev. 0 | Page 3 of 92 ADAU1372 Data Sheet SPECIFICATIONS Master clock = 12.288 MHz, serial input sample rate = 48 kHz, measurement bandwidth = 20 Hz to 20 kHz, word width = 24 bits, ambient temperature = 25°C, outputs line loaded with 10 kΩ. ANALOG PERFORMANCE SPECIFICATIONS Supply voltages AVDD = IOVDD = 1.8 V, DVDD = 1.1 V, unless otherwise noted, PLL disabled, direct master clock. Table 1. Parameter ANALOG-TO-DIGITAL CONVERTERS (ADCs) ADC Resolution Digital Attenuation Step Digital Attenuation Range INPUT RESISTANCE Single-Ended Line Input PGA Inputs SINGLE-ENDED LINE INPUT Full-Scale Input Voltage Dynamic Range 1 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter Signal-to-Noise Ratio (SNR) 2 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter Interchannel Gain Mismatch Total Harmonic Distortion + Noise (THD + N) Offset Error Gain Error Interchannel Isolation Power Supply Rejection Ratio (PSRR) SINGLE-ENDED PGA INPUT Full-Scale Input Voltage Dynamic Range1 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter Test Conditions/Comments All ADCs Gain settings do not include 10 dB gain from PGA_x_BOOST settings; this additional gain does not affect input impedance; PGA_POP_DISx = 1 0 dB gain −12 dB gain 0 dB gain +35.25 dB gain PGA_ENx = 0, PGA_x_BOOST = 0, PGA_POP_DISx = 1 Scales linearly with AVDD AVDD = 1.8 V AVDD = 1.8 V AVDD = 3.3 V AVDD = 3.3 V 20 Hz to 20 kHz, −60 dB input AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V 20 Hz to 20 kHz, −1 dBFS input AVDD = 1.8 V AVDD = 3.3 V CM capacitor = 22 µF CM capacitor = 22 µF, 100 mV p-p at 1 kHz PGA_ENx = 1, PGA_x_BOOST = 0 Scales linearly with AVDD AVDD = 1.8 V AVDD = 1.8 V AVDD = 3.3 V AVDD = 3.3 V 20 Hz to 20 kHz, −60 dB input AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V Rev. 0 | Page 4 of 92 Min Typ Max Unit 24 0.375 95 Bits dB dB 14.3 32.0 20 0.68 kΩ kΩ kΩ kΩ AVDD/3.63 0.49 1.38 0.90 2.54 V rms V rms V p-p V rms V p-p 97 102 94 99 dB dB dB dB 98 103 96 100 40 dB dB dB dB mdB −90 −94 ±0.1 ±0.2 100 55 dB dB mV dB dB dB AVDD/3.63 0.49 1.38 0.90 2.54 V rms V rms V p-p V rms V p-p 96 102 94 99 dB dB dB dB Data Sheet Parameter THD + N SNR2 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter PGA Gain Variation With −12 dB Setting With +35.25 dB Setting PGA Boost PGA Mute Attenuation Interchannel Gain Mismatch Offset Error Gain Error Interchannel Isolation PSRR MICROPHONE BIAS Bias Voltage 0.65 × AVDD 0.90 × AVDD Bias Current Source Output Impedance MICBIASx Isolation Noise in the Signal Bandwidth 3 AVDD = 1.8 V ADAU1372 Test Conditions/Comments 20 Hz to 20 kHz, −1 dBFS input AVDD = 1.8 V AVDD = 3.3 V Min Typ Max Unit −88 −90 dB dB AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V 96 102 94 99 dB dB dB dB Standard deviation Standard deviation PGA_x_BOOST PGA_MUTEx 0.05 0.15 10 −65 0.005 0 ±0.2 83 63 dB dB dB dB dB mV dB dB dB 1.16 2.12 1.63 2.97 1 95 99 V V V V mA Ω dB dB MIC_GAINx = 0 MIC_GAINx = 1 27 16 nV/√Hz nV/√Hz MIC_GAINx = 0 MIC_GAINx = 1 35 19 nV/√Hz nV/√Hz All DACs 24 0.375 95 Bits dB dB AVDD/3.4 0.53 1.50 0.97 2.74 −72 V rms V rms V p-p V rms V p-p dB 100 104 97 101 dB dB dB dB 100 104 dB dB CM capacitor = 22 µF, 100 mV p-p at 1 kHz MIC_ENx = 1 AVDD = 1.8 V, MIC_GAINx = 1 AVDD = 3.3 V, MIC_GAINx = 1 AVDD = 1.8 V, MIC_GAINx = 0 AVDD = 3.3 V, MIC_GAINx = 0 3 MIC_GAINx = 0 MIC_GAINx = 1 20 Hz to 20 kHz AVDD = 3.3 V DIGITAL-TO-ANALOG CONVERTERS (DACs) DAC Resolution Digital Attenuation Step Digital Attenuation Range DAC SINGLE-ENDED OUTPUT Full-Scale Output Voltage Mute Attenuation Line Output Mode Dynamic Range1 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter SNR2 With A-Weighted Filter (RMS) Single-ended operation, HPOUTLP/LOUTLP and HPOUTRP/LOUTRP pins Scales linearly with AVDD AVDD = 1.8 V AVDD = 1.8 V, 0 dBFS AVDD = 3.3 V AVDD = 3.3 V, 0 dBFS 20 Hz to 20 kHz, −60 dB input AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V 20 Hz to 20 kHz AVDD = 1.8 V AVDD = 3.3 V Rev. 0 | Page 5 of 92 ADAU1372 Parameter With Flat 20 Hz to 20 kHz Filter Interchannel Gain Mismatch THD + N Gain Error Headphone Mode Dynamic Range1 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter SNR2 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter Interchannel Gain Mismatch THD + N 32 Ω Load 24 Ω Load 16 Ω Load Gain Error Headphone Output Power 32 Ω Load 24 Ω Load 16 Ω Load Offset Error Interchannel Isolation PSRR DAC DIFFERENTIAL OUTPUT Full-Scale Output Voltage Mute Attenuation Line Output Mode Dynamic Range1 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter SNR2 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter Data Sheet Test Conditions/Comments AVDD = 1.8 V AVDD = 3.3 V 20 Hz to 20 kHz, −1 dBFS input AVDD = 1.8 V AVDD = 3.3 V 20 Hz to 20 kHz, −60 dB input AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V 20 Hz to 20 kHz AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V 20 Hz to 20 kHz, −1 dBFS input AVDD = 1.8 V, output power = 6.7 mW AVDD = 3.3 V, output power = 22.4 mW AVDD = 1.8 V, output power = 8.9 mW AVDD = 3.3 V, output power = 30 mW AVDD = 1.8 V, output power = 13 mW AVDD = 3.3 V, output power = 44 mW AVDD = 1.8 V,