ADAU1772BCPZ-R7

Four ADC, Two DAC Low Power Codec with Audio Processor ADAU1772 Data Sheet FEATURES Low power (15 mW for typical noise cancelling solution) I2C and SPI control interfaces, self-boot from I2C EEPROM 7 MP pins supporting dual stereo digital microphone inputs, stereo PDM output, mute, DSP bypass, push-button volume controls, and parameter bank switching Programmable audio processing engine 192 kHz processing path Biquad filters, limiters, volume controls, mixing Low latency, 24-bit ADCs and DACs 102 dB SNR (signal through PGA and ADC with A-weighted filter) 107 dB combined SNR (signal through DAC and headphone with A-weighted filter) Serial port sample rates from 8 kHz to 192 kHz 38 μs analog-to-analog latency 4 single-ended analog inputs—configurable as microphone or line inputs Dual stereo digital microphone inputs Stereo analog audio output—single-ended or differential, configurable as either line output or headphone driver PLL supporting any input clock rate from 8 MHz to 27 MHz Full-duplex, asynchronous sample rate converters (ASRCs) Power supplies Analog and digital I/O of 1.8 V to 3.3 V Digital signal processing (DSP) core of 1.1 V to 1.8 V APPLICATIONS Noise cancelling handsets, headsets, and headphones Bluetooth ANC handsets, headsets, and headphones Personal navigation devices Digital still and video cameras GENERAL DESCRIPTION The ADAU1772 is a codec with four inputs and two outputs that incorporates a digital processing engine to perform filtering, level control, signal level monitoring, and mixing. The path from the analog input to the DSP core to the analog output is optimized for low latency and is ideal for noise cancelling headsets. With the addition of just a few passive components, a crystal, and an EEPROM for booting, the ADAU1772 provides a complete headset solution. MICROPHONE BIAS GENERATORS POWER MANAGEMENT IOVDD AVDD AVDD REG_OUT AVDD LDO REGULATOR ADAU1772 AIN0REF PGA AIN0 ADC_SDATA1/CLKOUT/MP6 ADC MODULATOR PLL ADC DECIMATOR CLOCK OSCILLATOR XTALO AIN1REF PGA AIN1 DMIC0_1/MP4 DMIC2_3/MP5 HPOUTLP/LOUTLP ADC MODULATOR DAC HPOUTLN/LOUTLN ADC DECIMATOR INPUT/OUTPUT SIGNAL ROUTING DIGITAL MICROPHONE INPUTS STEREO PDM MODULATOR HPOUTRP/LOUTRP DAC SERIAL INPUT/ OUTPUT PORT HPOUTRN/LOUTRN DAC_SDATA/MP0 ADC_SDATA0/PDMOUT/MP1 BCLK/MP2 LRCLK/MP3 SDA/MISO I2C/SPI CONTROL INTERFACE AND SELF-BOOT SCL/SCLK DSP CORE: BIQUAD FILTERS, LIMITERS, VOLUME CONTROLS, MIXING ADDR0/SS ADC DECIMATOR DGND CM ADC MODULATOR ADDR1/MOSI PGA AIN3 SELFBOOT AIN3REF BIDIRECTIONAL ASRCS AGND ADC MODULATOR AGND PGA ADC DECIMATOR AGND AIN2REF AIN2 XTALI/MCLKIN 10804-001 MICBIAS0 MICBIAS1 DVDD PD FUNCTIONAL BLOCK DIAGRAM Figure 1. Rev. C Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2012–2014 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADAU1772 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Control Port .................................................................................... 40  Applications ....................................................................................... 1  I2C Port ........................................................................................ 40  General Description ......................................................................... 1  SPI Port ........................................................................................ 43  Functional Block Diagram .............................................................. 1  Self-Boot ...................................................................................... 44  Revision History ............................................................................... 3  Multipurpose Pins .......................................................................... 45  Specifications..................................................................................... 4  Push-Button Volume Controls ................................................. 45  Analog Performance Specifications ........................................... 4  Limiter Compression Enable .................................................... 45  Crystal Amplifier Specifications................................................. 7  Parameter Bank Switching ........................................................ 45  Digital Input/Output Specifications........................................... 8  Mute ............................................................................................. 45  Power Supply Specifications........................................................ 8  DSP Bypass Mode ...................................................................... 46  Typical Power Consumption....................................................... 9  Serial Data Input/Output Ports .................................................... 47  Digital Filters ................................................................................. 9  Tristating Unused Channels...................................................... 47  Digital Timing Specifications ................................................... 10  Applications Information .............................................................. 50  Absolute Maximum Ratings.......................................................... 14  Power Supply Bypass Capacitors .............................................. 50  Thermal Resistance .................................................................... 14  Layout .......................................................................................... 50  ESD Caution ................................................................................ 14  Grounding ................................................................................... 50  Pin Configuration and Function Descriptions ........................... 15  Exposed Pad PCB Design ......................................................... 50  Typical Performance Characteristics ........................................... 17  Register Summary .......................................................................... 51  System Block Diagrams ................................................................. 28  Register Details ............................................................................... 53  Theory of Operation ...................................................................... 29  Clock Control Register .............................................................. 53  System Clocking and Power-Up ................................................... 30  PLL Denominator MSB Register .............................................. 54  Clock Initialization ..................................................................... 30  PLL Denominator LSB Register ............................................... 54  PLL ............................................................................................... 30  PLL Numerator MSB Register .................................................. 54  Clock Output............................................................................... 31  PLL Numerator LSB Register.................................................... 55  Power Sequencing ...................................................................... 31  PLL Integer Setting Register ..................................................... 55  Signal Routing ................................................................................. 32  PLL Lock Flag Register .............................................................. 56  Input Signal Paths ........................................................................... 33  CLKOUT Setting Selection Register ........................................ 56  Analog Inputs .............................................................................. 33  Regulator Control Register ....................................................... 57  Digital Microphone Input ......................................................... 34  Core Control Register ................................................................ 58  Analog-to-Digital Converters ................................................... 34  Filter Engine and Limiter Control Register ............................ 59  Output Signal Paths ........................................................................ 35  DB Value Register 0 Read.......................................................... 60  Analog Outputs........................................................................... 35  DB Value Register 1 Read.......................................................... 60  Digital-to-Analog Converters ................................................... 35  DB Value Register 2 Read.......................................................... 61  PDM Output ............................................................................... 35  Core Channel 0/Core Channel 1 Input Select Register......... 62  Asynchronous Sample Rate Converters .................................. 36  Core Channel 2/Core Channel 3 Input Select Register......... 63  Signal Levels ................................................................................ 36  DAC Input Select Register ........................................................ 64  Signal Processing ............................................................................ 37  PDM Modulator Input Select Register .................................... 65  Instructions ................................................................................. 37  Serial Data Output 0/Serial Data Output 1 Input Select Register ........................................................................................ 66  Data Memory .............................................................................. 37  Parameters ................................................................................... 37  Rev. C | Page 2 of 116 Data Sheet ADAU1772 Serial Data Output 2/Serial Data Output 3 Input Select Register .........................................................................................67 Headphone Output Mutes Register .......................................... 89 Serial Data Output 4/Serial Data Output 5 Input Select Register .........................................................................................68 Serial Port Control 1 Register.................................................... 91 Serial Data Output 6/Serial Data Output 7 Input Select Register .........................................................................................69 PDM Enable Register ................................................................. 93 ADC_SDATA0/ADC_SDATA1 Channel Select Register ......70 Output ASRC0/Output ASRC1 Source Register.....................71 Output ASRC2/Output ASRC3 Source Register.....................72 Input ASRC Channel Select Register ........................................73 ADC0/ADC1 Control 0 Register ..............................................74 ADC2/ADC3 Control 0 Register ..............................................75 ADC0/ADC1 Control 1 Register ..............................................76 ADC2/ADC3 Control 1 Register ..............................................77 ADC0 Volume Control Register ...............................................78 ADC1 Volume Control Register ...............................................78 ADC2 Volume Control Register ...............................................79 ADC3 Volume Control Register ...............................................79 PGA Control 0 Register..............................................................80 PGA Control 1 Register..............................................................80 PGA Control 2 Register..............................................................81 PGA Control 3 Register..............................................................82 PGA Slew Control Register........................................................83 PGA 10 dB Gain Boost Register................................................84 Input and Output Capacitor Charging Register .....................85 DSP Bypass Path Register ..........................................................86 DSP Bypass Gain for PGA0 Register ........................................86 DSP Bypass Gain for PGA1 Register ........................................86 MIC_BIAS0_1 Control Register ...............................................87 DAC Control Register ................................................................87 DAC0 Volume Control Register................................................88 Serial Port Control 0 Register.................................................... 90 TDM Output Channel Disable Register .................................. 92 PDM Pattern Setting Register ................................................... 94 MP0 Function Setting Register ................................................. 94 MP1 Function Setting Register ................................................. 95 MP2 Function Setting Register ................................................. 96 MP3 Function Setting Register ................................................. 97 MP4 Function Setting Register ................................................. 98 MP5 Function Setting Register ................................................. 99 MP6 Function Setting Register ...............................................100 Push-Button Volume Settings Register ..................................101 Push-Button Volume Control Assignment Register ............102 Debounce Modes Register .......................................................103 Headphone Line Output Select Register ................................103 Decimator Power Control Register ........................................105 ASRC Interpolator and DAC Modulator Power Control Register .......................................................................................106 Analog Bias Control 0 Register ...............................................106 Analog Bias Control 1 Register ...............................................107 Digital Pin Pull-Up Control 0 Register ..................................108 Digital Pin Pull-Up Control 1 Register ..................................109 Digital Pin Pull-Down Control 0 Register ............................110 Digital Pin Pull-Down Control 1 Register ............................111 Digital Pin Drive Strength Control 0 Register ......................112 Digital Pin Drive Strength Control 1 Register ......................113 Outline Dimensions ......................................................................114 Ordering Guide .........................................................................114 DAC1 Volume Control Register................................................88 REVISION HISTORY 3/14—Rev. B to Rev. C 8/12—Rev. 0 to Rev. A Changes to Figure 60 and Figure 62 Captions ............................ 25 Added Figure 64, Figure 65, Figure 66, Figure 67, Figure 68, and Figure 69, Renumbered Sequentially .................................... 26 Added Figure 70, and Figure 71 .................................................... 27 Changes to Figure 69 ...................................................................... 31 7/12—Revision 0: Initial Version 12/12—Rev. A to Rev. B Changes to Figure 90 ...................................................................... 47 Rev. C | Page 3 of 116 ADAU1772 Data Sheet SPECIFICATIONS Master clock = core clock = 12.288 MHz, serial input sample rate = 48 kHz, measurement bandwidth = 20 Hz to 20 kHz, word width = 24 bits, ambient temperature = 25°C, outputs line loaded with 10 kΩ. ANALOG PERFORMANCE SPECIFICATIONS Supply voltages AVDD = IOVDD = 1.8 V, DVDD = 1.1 V, unless otherwise noted. PLL disabled, direct master clock. Table 1. Parameter ANALOG-TO-DIGITAL CONVERTERS ADC Resolution Digital Attenuation Step Digital Attenuation Range INPUT RESISTANCE Single-Ended Line Input PGA Inputs SINGLE-ENDED LINE INPUT Full-Scale Input Voltage Dynamic Range 1 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter Signal-to-Noise Ratio (SNR) 2 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter Interchannel Gain Mismatch Total Harmonic Distortion + Noise (THD + N) Offset Error Gain Error Interchannel Isolation Power Supply Rejection Ratio SINGLE-ENDED PGA INPUT Full-Scale Input Voltage Dynamic Range1 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter Test Conditions/Comments All ADCs Gain settings do not include 10 dB gain from PGA_x_BOOST settings; this additional gain does not affect input impedance; PGA_POP_DISx = 1 0 dB gain −12 dB gain 0 dB gain +35.25 dB gain PGA_ENx = 0, PGA_x_BOOST = 0, PGA_POP_DISx = 1 Scales linearly with AVDD AVDD = 1.8 V AVDD = 1.8 V, 0 dBFS AVDD = 3.3 V AVDD = 3.3 V, 0 dBFS 20 Hz to 20 kHz, −60 dB input AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V 20 Hz to 20 kHz, −1 dBFS AVDD = 1.8 V AVDD = 3.3 V CM capacitor = 22 μF CM capacitor = 22 μF 100 mV p-p at 1 kHz PGA_ENx = 1, PGA_x_BOOST = 0 Scales linearly with AVDD AVDD = 1.8 V AVDD = 1.8 V, 0 dBFS AVDD = 3.3 V AVDD = 3.3 V, 0 dBFS 20 Hz to 20 kHz, −60 dB input AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V Rev. C | Page 4 of 116 Min Typ Max Unit 24 0.375 95 Bits dB dB 14.3 32.0 20 0.68 kΩ kΩ kΩ kΩ AVDD/3.63 0.49 1.38 0.90 2.54 V rms V rms V p-p V rms V p-p 97 102 94 99 dB dB dB dB 98 103 96 100 40 dB dB dB dB mdB −90 −94 ±0.1 ±0.2 100 dB dB mV dB dB 55 dB AVDD/3.63 0.49 1.38 0.90 2.54 V rms V rms V p-p V rms V p-p 96 102 94 99 dB dB dB dB Data Sheet Parameter Total Harmonic Distortion + Noise Signal-to-Noise Ratio2 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter PGA Gain Variation With −12 dB Setting With +35.25 dB Setting PGA Boost PGA Mute Attenuation Interchannel Gain Mismatch Offset Error Gain Error Interchannel Isolation Power Supply Rejection Ratio MICROPHONE BIAS Bias Voltage 0.65 × AVDD 0.90 × AVDD Bias Current Source Output Impedance MICBIASx Isolation Noise in the Signal Bandwidth 3 DIGITAL-TO-ANALOG CONVERTERS DAC Resolution Digital Attenuation Step Digital Attenuation Range DAC SINGLE-ENDED OUTPUT Full-Scale Output Voltage Mute Attenuation Dynamic Range1 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter Signal-to-Noise Ratio2 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter ADAU1772 Test Conditions/Comments 20 Hz to 20 kHz, −1 dBFS AVDD = 1.8 V AVDD = 3.3 V Min Typ Max Unit −88 −90 dB dB AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V 96 102 94 99 dB dB dB dB Standard deviation Standard deviation PGA_x_BOOST PGA_MUTEx 0.05 0.15 10 −65 0.005 0 ±0.2 83 63 dB dB dB dB dB mV dB dB dB 1.16 2.12 1.63 2.97 1 95 99 V V V V mA Ω dB dB 27 16 nV/√Hz nV/√Hz 35 19 nV/√Hz nV/√Hz 24 0.375 95 Bits dB dB AVDD/3.4 0.53 1.5 0.97 2.74 −72 V rms V rms V p-p V rms V p-p dB 100 104 97 101 dB dB dB dB 100 104 98 102 dB dB dB dB CM capacitor = 22 μF, 100 mV p-p at 1 kHz MIC_ENx = 1 AVDD = 1.8 V, MIC_GAINx = 1 AVDD = 3.3 V, MIC_GAINx = 1 AVDD = 1.8 V, MIC_GAINx = 0 AVDD = 3.3 V, MIC_GAINx = 0 3 MIC_GAINx = 0 MIC_GAINx = 1 AVDD = 1.8 V, 20 Hz to 20 kHz MIC_GAINx = 0 MIC_GAINx = 1 AVDD = 3.3 V, 20 Hz to 20 kHz MIC_GAINx = 0 MIC_GAINx = 1 All DACs Single-ended operation, HPOUTLP and HPOUTRP pins Scales linearly with AVDD AVDD = 1.8 V AVDD = 1.8 V, 0 dBFS AVDD = 3.3 V AVDD = 3.3 V, 0 dBFS Line output mode, 20 Hz to 20 kHz, −60 dB input AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V Line output mode, 20 Hz to 20 kHz AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V Rev. C | Page 5 of 116 ADAU1772 Parameter Interchannel Gain Mismatch Total Harmonic Distortion + Noise Gain Error Dynamic Range1 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter Signal-to-Noise Ratio2 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter Interchannel Gain Mismatch Total Harmonic Distortion + Noise 32 Ω load 24 Ω load 16 Ω load Headphone Output Power 32 Ω Load 24 Ω Load 16 Ω Load Gain Error Offset Error Interchannel Isolation Power Supply Rejection Ratio DAC DIFFERENTIAL OUTPUT Full-Scale Output Voltage Mute Attenuation Dynamic Range1 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter Signal-to-Noise Ratio2 With A-Weighted Filter (RMS) With Flat 20 Hz to 20 kHz Filter Interchannel Gain Mismatch Total Harmonic Distortion + Noise Gain Error Data Sheet Test Conditions/Comments Line output mode Line output mode, 20 Hz to 20 kHz, −1 dBFS AVDD = 1.8 V AVDD = 3.3 V Line output mode Headphone mode, 20 Hz to 20 kHz, −60 dB input AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V Headphone mode, 20 Hz to 20 kHz AVDD = 1.8 V AVDD = 3.3 V AVDD = 1.8 V AVDD = 3.3 V Headphone mode Headphone mode, 20 Hz to 20 kHz, −1 dBFS AVDD = 1.8 V, PO = 6.7 mW AVDD = 3.3 V, PO = 22.4 mW AVDD = 1.8 V, PO = 8.9 mW AVDD = 3.3 V, PO = 30 mW AVDD = 1.8 V, PO = 13 mW AVDD = 3.3 V, PO = 44 mW AVDD = 1.8 V,