ADF4106BCPZ-RL

PLL Frequency Synthesizer ADF4106 Data Sheet FEATURES GENERAL DESCRIPTION 6.0 GHz bandwidth 2.7 V to 3.3 V power supply Separate charge pump supply (VP) allows extended tuning voltage in 3 V systems Programmable dual-modulus prescaler 8/9, 16/17, 32/33, 64/65 Programmable charge pump currents Programmable antibacklash pulse width 3-wire serial interface Analog and digital lock detect Hardware and software power-down mode The ADF4106 frequency synthesizer can be used to implement local oscillators in the up-conversion and down-conversion sections of wireless receivers and transmitters. It consists of a low noise, digital phase frequency detector (PFD), a precision charge pump, a programmable reference divider, programmable A counter and B counter, and a dual-modulus prescaler (P/P + 1). The A (6-bit) counter and B (13-bit) counter, in conjunction with the dual-modulus prescaler (P/P + 1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter (R Counter) allows selectable REFIN frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). Its very high bandwidth means that frequency doublers can be eliminated in many high frequency systems, simplifying system architecture and reducing cost. APPLICATIONS Broadband wireless access Satellite systems Instrumentation Wireless LANS Base stations for wireless radios FUNCTIONAL BLOCK DIAGRAM AVDD DVDD VP RSET CPGND REFERENCE 14-BIT R COUNTER REFIN PHASE FREQUENCY DETECTOR CHARGE PUMP CP 14 R COUNTER LATCH CLK DATA LE 24-BIT INPUT REGISTER FUNCTION LATCH 22 FROM SDOUT FUNCTION LATCH A, B COUNTER LATCH CURRENT SETTING 1 CURRENT SETTING 2 CPI3 CPI2 CPI1 CPI6 CPI5 CPI4 HIGH Z 19 AVDD MUXOUT MUX 13 N = BP + A RFINA RFINB LOCK DETECT 13-BIT B COUNTER SDOUT LOAD PRESCALER P/P + 1 LOAD M3 M2 M1 6-BIT A COUNTER 02720-001 ADF4106 6 CE AGND DGND Figure 1. Rev. F Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. 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Technical Support www.analog.com ADF4106 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1 A Counter and B Counter ......................................................... 10 Applications ....................................................................................... 1 R Counter .................................................................................... 10 General Description ......................................................................... 1 Phase Frequency Detector (PFD) and Charge Pump............ 11 Functional Block Diagram .............................................................. 1 MUXOUT and Lock Detect...................................................... 11 Revision History ............................................................................... 2 Input Shift Register .................................................................... 11 Specifications..................................................................................... 3 The Function Latch .................................................................... 17 Timing Characterisitics ............................................................... 4 The Initialization Latch ............................................................. 18 Absolute Maximum Ratings............................................................ 6 Applications..................................................................................... 19 ESD Caution .................................................................................. 6 Local Oscillator for LMDS Base Station Transmitter ............ 19 Pin Configurations and Function Descriptions ........................... 7 Interfacing ................................................................................... 20 Typical Performance Characteristics ............................................. 8 PCB Design Guidelines for Chip Scale Package .................... 20 General Description ....................................................................... 10 Outline Dimensions ....................................................................... 21 Reference Input Section ............................................................. 10 Ordering Guide .......................................................................... 22 RF Input Stage ............................................................................. 10 Prescaler (P/P +1)....................................................................... 10 REVISION HISTORY 4/15—Rev. E to Rev. F Change to RFINA to RFINB Parameter, Table 3 .............................. 6 Updated Outline Dimensions ....................................................... 21 Changes to Ordering Guide .......................................................... 22 11/12—Rev. D to Rev. E Changed EVAL-ADF4106EBZ1 to EV-ADF4106SD1Z ...... Universal Added RFINA to RFINB Parameter, Table 3 .................................... 6 Updated Outline Dimensions ....................................................... 21 Changes to Ordering Guide .......................................................... 22 9/11—Rev. C to Rev. D Changes to Normalized Phase Noise Floor (PNSYNTH) Parameter, Table 1 ................................................................................................ 4 Added Normalized 1/f Noise (PN1_f) Parameter and Endnote 12, Table 1 ................................................................................................ 4 Changes to Ordering Guide .......................................................... 22 2/10—Rev. B to Rev. C Changes to Figure 4 and Table 4 ..................................................... 6 Changes to Figure 12 ........................................................................ 8 Updated Outline Dimensions ....................................................... 20 Changes to Ordering Guide .......................................................... 21 6/05—Rev. A to Rev. B Updated Format .................................................................. Universal Changes to Figure 1 ...........................................................................1 Changes to Table 1.............................................................................3 Changes to Table 2.............................................................................4 Changes to Table 3.............................................................................5 Changes to Figure 3 and Figure 4 ....................................................6 Changes to Figure 6 ...........................................................................7 Changes to Figure 10.........................................................................7 Deleted TPC 13 and TPC 14 ............................................................8 Changes to Figure 15.........................................................................8 Changes to Figure 20 Caption ...................................................... 10 Updated Outline Dimensions ....................................................... 20 Changes to Ordering Guide .......................................................... 21 5/03—Rev. 0 to Rev. A Edits to Specifications .......................................................................2 Edits to TPC 11 ..................................................................................7 Updated Outline Dimensions ....................................................... 19 10/01—Revision 0: Initial Revision Rev. F | Page 2 of 24 Data Sheet ADF4106 SPECIFICATIONS AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN, unless otherwise noted. Table 1. Parameter RF CHARACTERISTICS RF Input Frequency (RFIN) B Version1 B Chips2 (typ) Unit 0.5/6.0 0.5/6.0 GHz min/max –10/0 300 –10/0 300 dBm min/max MHz max P=8 325 325 MHz max P = 16 20/300 0.8/VDD 10 ±100 20/300 0.8/VDD 10 ±100 MHz min/max V p-p min/max pF max µA max For f < 20 MHz, ensure SR > 50 V/µs Biased at AVDD/2 (see Note 55) 104 104 MHz max ABP = 0, 0 (2.9 ns antibacklash pulse width) Programmable, see Table 9 5 625 2.5 3.0/11 2 2 5 625 2.5 3.0/11 2 2 mA typ µA typ % typ kΩ typ nA max % typ With RSET = 5.1 kΩ With RSET = 5.1 kΩ See Table 9 1 nA typical; TA = 25°C 0.5 V ≤ VCP ≤ VP − 0.5 V ICP vs. VCP ICP vs. Temperature LOGIC INPUTS VIH, Input High Voltage VIL, Input Low Voltage IINH, IINL, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage 1.5 2 1.5 2 % typ % typ 0.5 V ≤ VCP ≤ VP − 0.5 V VCP = VP/2 1.4 0.6 ±1 10 1.4 0.6 ±1 10 V min V max µA max pF max 1.4 1.4 V min VOH, Output High Voltage IOH VOL, Output Low Voltage POWER SUPPLIES AVDD DVDD VP IDD7 (AIDD + DIDD) IDD8 (AIDD + DIDD) IDD9 (AIDD + DIDD) IP Power-Down Mode10 (AIDD + DIDD) VDD − 0.4 100 0.4 VDD − 0.4 100 0.4 V min µA max V max 2.7/3.3 AVDD AVDD/5.5 11 11.5 13 0.4 10 2.7/3.3 AVDD AVDD/5.5 9.0 9.5 10.5 0.4 10 V min/V max RF Input Sensitivity Maximum Allowable Prescaler Output Frequency3 REFIN CHARACTERISTICS REFIN Input Frequency REFIN Input Sensitivity4 REFIN Input Capacitance REFIN Input Current PHASE DETECTOR Phase Detector Frequency6 CHARGE PUMP ICP Sink/Source High Value Low Value Absolute Accuracy RSET Range ICP Three-State Leakage Sink and Source Current Matching V min/V max mA max mA max mA max mA max µA typ Rev. F | Page 3 of 24 Test Conditions/Comments See Figure 18 for input circuit For lower frequencies, ensure slew rate (SR) > 320 V/µs Open-drain output chosen, 1 kΩ pull-up resistor to 1.8 V CMOS output chosen IOL = 500 µA AVDD ≤ VP ≤ 5.5V 9.0 mA typ 9.5 mA typ 10.5 mA typ TA = 25°C ADF4106 Parameter NOISE CHARACTERISTICS Normalized Phase Noise Floor (PNSYNTH)11 Normalized 1/f Noise (PN1_f)12 Phase Noise Performance13 900 MHz14 5800 MHz15 5800 MHz16 Spurious Signals 900 MHz14 5800 MHz15 5800 MHz16 Data Sheet B Version1 B Chips2 (typ) Unit Test Conditions/Comments –223 –223 dBc/Hz typ −122 −122 dBc/Hz typ –92.5 −76.5 −83.5 −92.5 −76.5 −83.5 dBc/Hz typ dBc/Hz typ dBc/Hz typ PLL loop B/W = 500 kHz, measured at 100 kHz offset 10 kHz offset; normalized to 1 GHz @ VCO output @ 1 kHz offset and 200 kHz PFD frequency @ 1 kHz offset and 200 kHz PFD frequency @ 1 kHz offset and 1 MHz PFD frequency –90/–92 –65/–70 –70/–75 –90/–92 –65/–70 –70/–75 dBc typ dBc typ dBc typ @ 200 kHz/400 kHz and 200 kHz PFD frequency @ 200 kHz/400 kHz and 200 kHz PFD frequency @ 1 MHz/2 MHz and 1 MHz PFD frequency Operating temperature range (B Version) is –40°C to +85°C. The B chip specifications are given as typical values. This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that is less than this value. 4 AVDD = DVDD = 3 V. 5 AC coupling ensures AVDD/2 bias. 6 Guaranteed by design. Sample tested to ensure compliance. 7 TA = 25°C; AVDD = DVDD = 3 V; P = 16; RFIN = 900 MHz. 8 TA = 25°C; AVDD = DVDD = 3 V; P = 16; RFIN = 2.0 GHz. 9 TA = 25°C; AVDD = DVDD = 3 V; P = 32; RFIN = 6.0 GHz. 10 TA = 25°C; AVDD = DVDD = 3.3 V; R = 16383; A = 63; B = 891; P = 32; RFIN = 6.0 GHz. 11 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider value) and 10 log FPFD. PNSYNTH = PNTOT − 10 log FPFD − 20 log N. 12 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, fRF, and at a frequency offset, f, is given by PN = PN1_f + 10 log(10 kHz/f) + 20 log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL. 13 The phase noise is measured with the EV-ADF4106SD1Z evaluation board and the Agilent E4440A Spectrum Analyzer. The spectrum analyzer provides the REFIN for the synthesizer (fREFOUT = 10 MHz @ 0 dBm). 14 fREFIN = 10 MHz; fPFD = 200 kHz; Offset Frequency = 1 kHz; fRF = 900 MHz; N = 4500; Loop B/W = 20 kHz. 15 fREFIN = 10 MHz; fPFD = 200 kHz; Offset Frequency = 1 kHz; fRF = 5800 MHz; N = 29000; Loop B/W = 20 kHz. 16 fREFIN = 10 MHz; fPFD = 1 MHz; Offset Frequency = 1 kHz; fRF = 5800 MHz; N = 5800; Loop B/W = 100 kHz. 1 2 3 TIMING CHARACTERISITICS AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN, unless otherwise noted. Table 2. Parameter t1 t2 t3 t4 t5 t6 1 Limit1 (B Version) 10 10 25 25 10 20 Unit ns min ns min ns min ns min ns min ns min Operating temperature range (B Version) is –40°C to +85°C. Rev. F | Page 4 of 24 Test Conditions/Comments DATA to CLOCK Setup Time DATA to CLOCK Hold Time CLOCK High Duration CLOCK Low Duration CLOCK to LE Setup Time LE Pulse Width Data Sheet ADF4106 t3 t4 CLOCK t1 DATA DB23 (MSB) t2 DB22 DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t6 LE 02720-002 t5 LE Figure 2. Timing Diagram Rev. F | Page 5 of 24 ADF4106 Data Sheet ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter AVDD to GND1 AVDD to DVDD VP to GND VP to AVDD Digital I/O Voltage to GND Analog I/O Voltage to GND REFIN, RFINA, RFINB to GND RFINA to RFINB Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature TSSOP θJA Thermal Impedance LFCSP θJA Thermal Impedance (Paddle Soldered) Reflow Soldering Peak Temperature Time at Peak Temperature Transistor Count CMOS Bipolar 1 Rating –0.3 V to + 3.6 V –0.3 V to + 0.3 V –0.3 V to + 5.8 V –0.3 V to + 5.8 V –0.3 V to VDD + 0.3 V –0.3 V to VP + 0.3 V –0.3 V to VDD + 0.3 V ±600 mV –40°C to +85°C –65°C to +125°C 150°C 112°C/W 30.4°C/W Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. This device is a high performance RF integrated circuit with an ESD rating of