ADF4106SCPZ-EP

PLL Frequency Synthesizer ADF4106-EP Enhanced Product FEATURES GENERAL DESCRIPTION 6.0 GHz bandwidth 2.7 V to 3.3 V power supply Separate charge pump supply (VP) allows extended tuning voltage in 3 V systems Programmable dual-modulus prescaler 8/9, 16/17, 32/33, 64/65 Programmable charge pump currents Programmable antibacklash pulse width 3-wire serial interface Analog and digital lock detect Hardware and software power-down mode Support defense and aerospace applications (AQEC) Military temperature range (−55°C to +125°C) Controlled manufacturing baseline One assembly/test site One fabrication site Product change notification Qualification data available upon request The ADF4106-EP frequency synthesizer can be used to implement local oscillators in the up-conversion and downconversion sections of wireless receivers and transmitters. It consists of a low noise, digital phase frequency detector (PFD), a precision charge pump, a programmable reference divider, programmable A counter and B counter, and a dual-modulus prescaler (P/P + 1). The A (6-bit) counter and B (13-bit) counter, in conjunction with the dual-modulus prescaler (P/P + 1), implement an N divider (N = BP + A). In addition, the 14-bit reference counter (R counter) allows selectable REFIN frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage controlled oscillator (VCO). Its very high bandwidth means that frequency doublers can be eliminated in many high frequency systems, simplifying system architecture and reducing cost. Additional application and technical information can be found in the ADF4106 data sheet. APPLICATIONS Broadband wireless access Satellite systems Instrumentation Wireless LANS Base stations for wireless radios AVDD FUNCTIONAL BLOCK DIAGRAM DVDD VP RSET CPGND REFERENCE 14-BIT R COUNTER REFIN PHASE FREQUENCY DETECTOR CHARGE PUMP CP 14 R COUNTER LATCH CLK DATA LE 24-BIT INPUT REGISTER SDOUT FUNCTION LATCH 22 FROM FUNCTION LATCH A, B COUNTER LATCH CURRENT SETTING 1 CURRENT SETTING 2 CPI3 CPI2 CPI1 CPI6 CPI5 CPI4 HIGH Z 19 AVDD MUXOUT MUX 13 N = BP + A RFINA RFINB LOCK DETECT 13-BIT B COUNTER SDOUT LOAD PRESCALER P/P + 1 LOAD M3 M2 M1 6-BIT A COUNTER 09272-001 ADF4106-EP 6 CE AGND DGND Figure 1. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2010–2018 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADF4106-EP Enhanced Product TABLE OF CONTENTS Features .............................................................................................. 1 ESD Caution...................................................................................5 Applications ....................................................................................... 1 Pin Configurations and Function Descriptions ............................6 General Description ......................................................................... 1 Typical Performance Characteristics ..............................................7 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Printed Circuit Board (PCB) Design Guidelines for Chip Scale Package................................................................................................9 Specifications..................................................................................... 3 Outline Dimensions ....................................................................... 10 Timing Characterisitics ............................................................... 4 Ordering Guide .......................................................................... 10 Absolute Maximum Ratings ............................................................ 5 REVISION HISTORY 10/2018—Rev. C to Rev. D Change to Features Section ............................................................. 1 Changes to Figure 6 .......................................................................... 7 Changes to Ordering Guide .......................................................... 10 11/2010—Rev. 0 to Rev. A Changes to Figure 6 ...........................................................................7 Changes to Figure 11.........................................................................8 Changes to Ordering Guide .......................................................... 10 11/2014—Rev. B to Rev. C Change to Table 1 ............................................................................. 3 Change to Table 2 ............................................................................. 4 Changes to Table 3 ............................................................................ 5 8/2010—Revision 0: Initial Version 8/2012—Rev. A to Rev. B Changes to Table 3 ............................................................................ 5 Updated Outline Dimensions ....................................................... 10 Changes to Ordering Guide .......................................................... 10 Rev. D | Page 2 of 10 Enhanced Product ADF4106-EP SPECIFICATIONS AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN, unless otherwise noted. Table 1. Parameter RF CHARACTERISTICS RF Input Frequency (RFIN) RF Input Sensitivity Maximum Allowable Prescaler Output Frequency 2 REFIN CHARACTERISTICS REFIN Input Frequency REFIN Input Sensitivity 3 REFIN Input Capacitance REFIN Input Current PHASE DETECTOR Phase Detector Frequency 5 CHARGE PUMP ICP Sink/Source High Value Low Value Absolute Accuracy RSET Range ICP Three-State Leakage Sink and Source Current Matching ICP vs. VCP ICP vs. Temperature LOGIC INPUTS VIH, Input High Voltage VIL, Input Low Voltage IINH, IINL, Input Current CIN, Input Capacitance LOGIC OUTPUTS VOH, Output High Voltage IOH VOL, Output Low Voltage POWER SUPPLIES AVDD DVDD VP IDD 6 (AIDD + DIDD) IDD 7 (AIDD + DIDD) IDD 8 (AIDD + DIDD) IP Power-Down Mode 9 (AIDD + DIDD) S Version 1 Unit Test Conditions/Comments 0.5/6.0 −10/0 300 325 GHz min/max dBm min/max MHz max MHz For lower frequencies, ensure slew rate (SR) > 320 V/µs 20/300 0.8/VDD 10 ±100 MHz min/max V p-p min/max pF max µA max For f < 20 MHz, ensure SR > 50 V/µs Biased at AVDD/2 4 104 MHz max ABP = 0, 0 (2.9 ns antibacklash pulse width) 5 625 2.5 3.0/11 2 2 1.5 2 mA typ µA typ % typ kΩ typ nA max % typ % typ % typ With RSET = 5.1 kΩ 1.4 0.6 ±1 10 V min V max µA max pF max 1.4 VDD − 0.4 100 0.4 V min V min µA max V max 2.7/3.3 AVDD AVDD/5.5 11 11.5 13 0.4 10 V min/V max V min/V max mA max mA max mA max mA max µA typ Rev. D | Page 3 of 10 P=8 P = 16 With RSET = 5.1 kΩ 1 nA typical; TA = 25°C 0.5 V ≤ VCP ≤ VP − 0.5 V 0.5 V ≤ VCP ≤ VP − 0.5 V VCP = VP/2 Open-drain output chosen, 1 kΩ pull-up resistor to 1.8 V CMOS output chosen IOL = 500 µA AVDD ≤ VP ≤ 5.5 V 9.0 mA typical 9.5 mA typical 10.5 mA typical TA = 25°C ADF4106-EP Enhanced Product Parameter NOISE CHARACTERISTICS Normalized Phase Noise Floor (PNSYNTH) 10 Normalized 1/f Noise (PN1_f) 11 Phase Noise Performance 12 900 MHz 13 5800 MHz 14 5800 MHz 15 Spurious Signals 900 MHz13 5800 MHz14 5800 MHz15 S Version 1 Unit Test Conditions/Comments −223 −122 dBc/Hz typ dBc/Hz typ −92.5 −76.5 −83.5 dBc/Hz typ dBc/Hz typ dBc/Hz typ PLL loop BW = 500 kHz Measured at 10 kHz offset; normalized to 1 GHz VCO output 1 kHz offset and 200 kHz PFD frequency 1 kHz offset and 200 kHz PFD frequency 1 kHz offset and 1 MHz PFD frequency −90/−92 −65/−70 −70/−75 dBc typ dBc typ dBc typ 200 kHz/400 kHz and 200 kHz PFD frequency 200 kHz/400 kHz and 200 kHz PFD frequency 1 MHz/2 MHz and 1 MHz PFD frequency Operating temperature range is −55°C to +125°C. This is the maximum operating frequency of the CMOS counters. The prescaler value should be chosen to ensure that the RF input is divided down to a frequency that is less than this value. 3 AVDD = DVDD = 3 V. 4 AC coupling ensures AVDD/2 bias. 5 Guaranteed by design. Sample tested to ensure compliance. 6 TA = 25°C; AVDD = DVDD = 3 V; P = 16; RFIN = 900 MHz. 7 TA = 25°C; AVDD = DVDD = 3 V; P = 16; RFIN = 2.0 GHz. 8 TA = 25°C; AVDD = DVDD = 3 V; P = 32; RFIN = 6.0 GHz. 9 TA = 25°C; AVDD = DVDD = 3.3 V; R = 16383; A = 63; B = 891; P = 32; RFIN = 6.0 GHz. 10 The synthesizer phase noise floor is estimated by measuring the in-band phase noise at the output of the VCO and subtracting 20 log N (where N is the N divider value) and 10 log FPFD. PNSYNTH = PNTOT − 10 log FPFD − 20 log N. 11 The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency, fRF, and at a frequency offset, f, is given by PN = P1_f + 10log(10 kHz/f) + 20log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in ADIsimPLL. 12 The phase noise is measured with the EVAL-ADF4106-EB1 evaluation board and the Agilent E4440A spectrum analyzer. The spectrum analyzer provides the REFIN for the synthesizer (fREFOUT = 10 MHz at 0 dBm). 13 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 900 MHz; N = 4500; loop B/W = 20 kHz. 14 fREFIN = 10 MHz; fPFD = 200 kHz; offset frequency = 1 kHz; fRF = 5800 MHz; N = 29,000; loop B/W = 20 kHz. 15 fREFIN = 10 MHz; fPFD = 1 MHz; offset frequency = 1 kHz; fRF = 5800 MHz; N = 5800; loop B/W = 100 kHz. 1 2 TIMING CHARACTERISITICS AVDD = DVDD = 3 V ± 10%, AVDD ≤ VP ≤ 5.5 V, AGND = DGND = CPGND = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMAX to TMIN, unless otherwise noted. Table 2. Parameter t1 t2 t3 t4 t5 t6 1 Limit 1 (B Version) 10 10 25 25 10 20 Unit ns min ns min ns min ns min ns min ns min Test Conditions/Comments DATA to CLOCK Setup Time DATA to CLOCK Hold Time CLOCK High Duration CLOCK Low Duration CLOCK to LE Setup Time LE Pulse Width Operating temperature range (S Version) is –55°C to +125°C. Timing Diagram t3 t4 CLOCK t1 DATA DB23 (MSB) t2 DB22 DB2 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t6 LE 09272-002 t5 LE Figure 2. Timing Diagram Rev. D | Page 4 of 10 Enhanced Product ADF4106-EP ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 3. Parameter AVDD to GND 1 AVDD to DVDD VP to GND VP to AVDD Digital I/O Voltage to GND Analog I/O Voltage to GND REFIN, RFINA, RFINB to GND RFINA to RFINB Operating Temperature Range Industrial (S Version) Storage Temperature Range Maximum Junction Temperature θJA Thermal Impedance 16-Lead TSSOP 20-Lead LFCSP (Paddle Soldered) Reflow Soldering Peak Temperature Time at Peak Temperature Transistor Count CMOS Bipolar Rating −0.3 V to + 3.6 V −0.3 V to + 0.3 V −0.3 V to + 5.8 V −0.3 V to + 5.8 V −0.3 V to VDD + 0.3 V −0.3 V to VP + 0.3 V −0.3 V to VDD + 0.3 V ±320 mV −55°C to +125°C −65°C to +125°C 150°C Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. This device is a high performance RF integrated circuit with an ESD rating of