Microwave Wideband Synthesizer
with Integrated VCO
ADF4355-3
Data Sheet
FEATURES
GENERAL DESCRIPTION
RF output frequency range: 51.5625 MHz to 6600 MHz
Fractional-N synthesizer and integer-N synthesizer
High resolution 38-bit modulus
Low phase noise, voltage controlled oscillator (VCO)
Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output
All power supplies: 3.3 V
Logic compatibility: 1.8 V
Programmable dual modulus prescaler of 4/5 or 8/9
Programmable output power level
RF output mute function
3-wire serial interface
Analog and digital lock detect
The ADF4355-3 allows the implementation of fractional-N or
integer-N phase-locked loop (PLL) frequency synthesizers when
used with an external loop filter and an external reference
frequency. A series of frequency dividers at the output provide
operation from 51.5625 MHz to 6600 MHz.
The ADF4355-3 has an integrated VCO with a fundamental
output frequency ranging from 3300 MHz to 6600 MHz. In
addition, the VCO frequency is connected to divide by 1, 2, 4, 8,
16, 32, or 64 circuits that allow the user to generate RF output
frequencies as low as 51.5625 MHz. For applications that require
isolation, the RF output stage can be muted. The mute function
is both pin- and software-controllable.
APPLICATIONS
Control of all on-chip registers is through a simple 3-wire interface.
The ADF4355-3 operates with analog, digital, charge pump, and
VCO power supplies ranging from 3.1515 V to 3.4485 V. The
ADF4355-3 also contains hardware and software power-down
modes.
Wireless infrastructure (W-CDMA, TD-SCDMA,
WiMAX, GSM, PCS, DCS, DECT)
Point to point/point to multipoint microwave links
Satellites/VSATs
Test equipment/instrumentation
Clock generation
FUNCTIONAL BLOCK DIAGRAM
REF IN A
REF IN B
CLK
DATA
LE
×2
DOUBLER
VVCO
VRF
AV DD
MULTIPLEXER
÷2
DIVIDER
10-BIT R
COUNTER
RSET
VP
DV DD
AV DD
CE
MUXOUT
LOCK
DETECT
CREG 1
CREG 2
DATA REGISTER
FUNCTION
LATCH
CHARGE
PUMP
CP OUT
PHASE
COMPARATOR
VTUNE
VREF
INTEGER
REG
FRACTION
REG
VBIAS
VCO
CORE
MODULUS
REG
VREGVCO
1/2/4/8
÷
16/32/64
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
OUTPUT
STAGE
RF OUTA+
RF OUTA–
PDB RF
OUTPUT
STAGE
MULTIPLEXER
AGND
CP GND
AGNDRF
SD GND
ADF4355-3
AGNDVCO
RF OUTB+
RF OUTB–
13345-001
N COUNTER
Figure 1.
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2015–2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADF4355-3
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Register 4 ..................................................................................... 22
Applications ....................................................................................... 1
Register 5 ..................................................................................... 23
General Description ......................................................................... 1
Register 6 ..................................................................................... 24
Functional Block Diagram .............................................................. 1
Register 7 ..................................................................................... 26
Revision History ............................................................................... 2
Register 8 ..................................................................................... 27
Specifications..................................................................................... 3
Register 9 ..................................................................................... 27
Timing Characteristics ................................................................ 5
Register 10 ................................................................................... 28
Absolute Maximum Ratings ............................................................ 6
Register 11 ................................................................................... 28
Transistor Count ........................................................................... 6
Register 12 ................................................................................... 29
ESD Caution .................................................................................. 6
Register Initialization Sequence ............................................... 29
Pin Configuration and Function Descriptions ............................. 7
Frequency Update Sequence ..................................................... 30
Typical Performance Characteristics ............................................. 9
RF Synthesizer—A Worked Example ...................................... 30
Theory of Operation ...................................................................... 12
Reference Doubler and Reference Divider ............................. 30
Reference Input Section ............................................................. 12
Spurious Optimization and Fast Lock ..................................... 31
RF N Divider ............................................................................... 12
Optimizing Jitter ......................................................................... 31
Phase Frequency Detector (PFD) and Charge Pump ............ 13
Spur Mechanisms ....................................................................... 31
MUXOUT and Lock Detect ...................................................... 13
Lock Time.................................................................................... 31
Input Shift Registers ................................................................... 13
Applications Information .............................................................. 32
Program Modes .......................................................................... 14
Direct Conversion Modulator .................................................. 32
VCO.............................................................................................. 14
Power Supplies ............................................................................ 33
Output Stage ................................................................................ 14
Loop Filter ................................................................................... 14
Printed Circuit Board (PCB) Design Guidelines for a ChipScale Package .............................................................................. 33
Register Maps .................................................................................. 16
Output Matching ........................................................................ 33
Register 0 ..................................................................................... 18
Outline Dimensions ....................................................................... 34
Register 1 ..................................................................................... 19
Ordering Guide .......................................................................... 34
Register 2 ..................................................................................... 20
Register 3 ..................................................................................... 21
REVISION HISTORY
8/2017—Rev. A to Rev. B
Changes to Frequency Update Sequence .................................... 30
Updated Outline Dimensions ....................................................... 34
Changes to Ordering Guide .......................................................... 34
1/2016—Rev. 0 to Rev. A
Change to Integrated RMS Jitter Parameter, Unit Column,
Table 1 ................................................................................................ 4
Changes to Reference Input Section ............................................ 12
Changes to Table 6 .......................................................................... 15
Changes to Figure 25...................................................................... 17
Changes to Reference Mode Section ........................................... 23
Changes to Negative Bleed Section .............................................. 24
Changes to Charge Pump Bleed Current Section ...................... 25
Changes to Figure 34, Figure 35, and Register 8 Section .......... 27
Changes to Figure 37 and Register 11 Section ........................... 28
7/2015—Revision 0: Initial Version
Rev. B | Page 2 of 34
Data Sheet
ADF4355-3
SPECIFICATIONS
AVDD = DVDD = VRF = VP = VVCO = VREGVCO = 3.3 V ± 4.5%, AGND = CPGND = AGNDVCO = SDGND = AGNDRF = 0 V, RSET = 5.1 kΩ, dBm referred
to 50 Ω, TA = TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
REFINA/REFINB CHARACTERISTICS
Input Frequency
Symbol
Min
Typ
Differential Mode
250
600
100
MHz
MHz
MHz
0.4
AVDD
V p-p
0.4
1.8
V p-p
±60
±250
125
pF
pF
µA
µA
MHz
Input Capacitance
Single-Ended Mode
Differential Mode
Input Current
Output Dividers
VCO Supply Current
RFOUTA±/RFOUTB± Supply Current
Low Power Sleep Mode
6.9
1.4
ICP
VINH
VINL
IINH/IINL
CIN
1.5
VOH
DVDD − 0.4
1.5
mA
mA
kΩ
%
%
%
DVDD
0.6
±1
3.0
REFINA biased at AVDD/2; ac coupling
ensures AVDD/2 bias
LVDS and LVPECL compatible, REFINA/
REFINB biased at 2.1 V; ac coupling ensures
2.1 V bias
Single-ended reference programmed
Differential reference programmed
3.1515
Fixed
0.5 V ≤ VCP 1 ≤ VP − 0.5 V
0.5 V ≤ VCP1 ≤ VP − 0.5 V
VCP1 = 2.5 V
1.8 V and 3.3 V compatible
V
V
µA
pF
0.4
500
V
V
V
µA
3.3 V output selected
1.8 V output selected
IOL 2 = 500 µA
3.3
AVDD
3.4485
V
3.3 V ± 4.5%
Voltages must equal AVDD
3.1
66
5
75
mA
mA
52
13/19/
25/31
1500
1950
70
20/27/
34/41
mA
mA
1.8
VOL
IOH
IVCO
IRFOUT x ±
Doubler is set in Register 4, Bit DB26
RSET = 5.1 kΩ
4.8
0.3
5.1
3
3
1.5
AVDD
DVDD, VRF,
VP, VVCO
IP
Test Conditions/Comments
For f < 10 MHz, ensure that the slew rate >
21 V/µs
10
10
Low
Output High Current
POWER SUPPLIES
Analog Power
Digital Power, RF Supply, Charge Pump,
and VCO Supply Voltage
Charge Pump Supply Current
DIDD + AIDD 3
Unit
REFIN
Single-Ended Mode
Differential Mode
Doubler Enabled
Input Sensitivity
Single-Ended Mode
Phase Detector Frequency
CHARGE PUMP (CP)
Charge Pump Current, Sink/Source
High
Low
RSET Range
Current Matching
ICP vs. VCP1
ICP vs. Temperature
LOGIC INPUTS
Input Voltage
High
Low
Input Current
Input Capacitance
LOGIC OUTPUTS
Output Voltage
High
Max
Rev. B | Page 3 of 34
µA
µA
Supply current drawn by DVDD plus supply
current drawn by AVDD
See Table 6
RF output stage is programmable;
RFOUTB+/RFOUTB− powered off
Hardware power-down
Software power-down
ADF4355-3
Parameter
RF OUTPUT CHARACTERISTICS
VCO Frequency Range
RF Output Frequency
VCO Sensitivity
Frequency Pushing (Open-Loop)
Frequency Pulling (Open-Loop)
Harmonic Content
Second
Data Sheet
Symbol
fRF
KV
Third
RF Output Power 4
RF Output Power Variation
Over Frequency
Level of Signal with Output Disabled
NOISE CHARACTERISTICS
Fundamental VCO Phase Noise
Performance
3.3 GHz Carrier
Typ
Max
Unit
Test Conditions/Comments
6600
6600
Fundamental VCO range
63
22
0.54
MHz
MHz
MHz/V
MHz/V
MHz
−27
−22
−20
−12
8
3
dBc
dBc
dBc
dBc
dBm
dBm
±1
±3
−60
−30
dB
dB
dBm
dBm
3300
51.5625
Voltage standing wave ratio (VSWR) = 2:1
Fundamental VCO output (RFOUTA+)
Divided VCO output (RFOUTA+)
Fundamental VCO output (RFOUTA+)
Divided VCO output (RFOUTA+)
RFOUTA+ = 1 GHz. 7.5 nH inductor to VRF
RFOUTA+/RFOUTA− = 4.4 GHz. 7.5 nH inductor
to VRF
RFOUTA+/RFOUTA− = 4.4 GHz
RFOUTA+/RFOUTA− = 1 GHz to 4.4 GHz
RFOUTA+/RFOUTA− = 1 GHz, VCO = 4 GHz
RFOUTA+/RFOUTA− = 4.4 GHz, VCO = 4.4 GHz
VCO noise in open-loop conditions
5.0 GHz Carrier
6.6 GHz Carrier
Normalized In-Band Phase Noise Floor
Fractional Channel 5
Integer Channel 6
Normalized 1/f Noise 7
Integrated RMS Jitter
Spurious Signals due to Phase Frequency
Detector (PFD) Frequency
Min
PN1_f
−113
−133
−135
−153
−110
−130
−132
−151
−107
−127
−129
−148
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
100 kHz offset from 3.3 GHz carrier
800 kHz offset from 3.3 GHz carrier
1 MHz offset from 3.3 GHz carrier
10 MHz offset from 3.3 GHz carrier
100 kHz offset from 5.0 GHz carrier
800 kHz offset from 5.0 GHz carrier
1 MHz offset from 5.0 GHz carrier
10 MHz offset from 5.0 GHz carrier
100 kHz offset from 6.6 GHz carrier
800 kHz offset from 6.6 GHz carrier
1 MHz offset from 6.6 GHz carrier
10 MHz offset from 6.6 GHz carrier
−221
−223
−116
200
−85
dBc/Hz
dBc/Hz
dBc/Hz
fs
dBc
10 kHz offset, normalized to 1 GHz
VCP is the voltage at the CPOUT pin.
IOL is the output low current.
3
TA = 25°C; AVDD = DVDD = VRF = VVCO = VP = 3.3 V; prescaler = 4/5; fREFIN = 122.88 MHz; fPFD = 61.44 MHz; and fRF = 1650 MHz.
4
RF output power using the EV-ADF4355-3SD1Z evaluation board measured into a spectrum analyzer, with board and cable losses de-embedded. Unused RF output
pins are terminated in 50 Ω.
5
Use this figure to calculate the phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output, use the following formula:
−221 + 10log(fPFD) + 20logN. The value given is the lowest noise mode for the fractional channel.
6
Use this figure to calculate the phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output, use the following formula:
−223 + 10log(fPFD) + 20logN. The value given is the lowest noise mode for the integer channel.
7
The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (fRF)
and at a frequency offset (f) is given by PN = P1_f + 10log(10 kHz/f) + 20log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in the
ADIsimPLL™ design tool.
1
2
Rev. B | Page 4 of 34
Data Sheet
ADF4355-3
TIMING CHARACTERISTICS
AVDD = DVDD =VRF = VP = VVCO = 3.3 V ± 4.5%, AGND = CPGND = AGNDVCO = SDGND = AGNDRF = 0 V, RSET = 5.1 kΩ, dBm referred to 50 Ω, TA = TMIN
to TMAX, unless otherwise noted.
Table 2. Write Timing
Parameter
fCLK
t1
t2
t3
t4
t5
t6
t7
Limit
50
10
5
5
10
10
5
20 or (2/fPFD), whichever is longer
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Description
SPI CLK frequency
LE setup time
DATA to CLK setup time
DATA to CLK hold time
CLK high duration
CLK low duration
CLK to LE setup time
LE pulse width
Write Timing Diagram
t4
t5
CLK
t2
DATA
DB31 (MSB)
t3
DB30
DB3
(CONTROL BIT C4)
DB2
(CONTROL BIT C3)
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
LE
t1
t6
Figure 2. Write Timing Diagram
Rev. B | Page 5 of 34
13345-002
t7
ADF4355-3
Data Sheet
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 3.
Parameter1
VRF, DVDD, AVDD to GND
AVDD to DVDD
VP, VVCO, VREGVCO to GND
CPOUT to GND1
Digital Input/Output Voltage to GND
Analog Input/Output Voltage to GND
REFINA, REFINB to GND
REFINA to REFINB
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
θJA, Thermal Impedance Pad Soldered
to GND
Reflow Soldering
Peak Temperature
Time at Peak Temperature
Electrostatic Discharge (ESD)
Charged Device Model
Human Body Model
1
Rating
−0.3 V to +3.6 V
−0.3 V to +0.3 V
−0.3 V to +3.6 V
−0.3 V to VP + 0.3 V
−0.3 V to DVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
±2.1 V
−40°C to +105°C
−65°C to +125°C
150°C
27.3°C/W
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
The ADF4355-3 is a high performance RF integrated circuit
with an ESD rating of 2500 V and is ESD sensitive. Take proper
precautions for handling and assembly.
TRANSISTOR COUNT
The transistor count for the ADF4355-3 is 103,665 (CMOS) and
3214 (bipolar).
ESD CAUTION
260°C
40 sec
500 V
2500 V
GND = AGND = SDGND = AGNDRF = AGNDVCO = CPGND = 0 V.
Rev. B | Page 6 of 34
Data Sheet
ADF4355-3
32
31
30
29
28
27
26
25
CREG 2
SDGND
MUXOUT
REFINA
REFINB
DVDD
PDBRF
CREG 1
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
CLK
DATA
LE
CE
AVDD
VP
CPOUT
ADF4355-3
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
VBIAS
VREF
RSET
AGNDVCO
VTUNE
VREGVCO
AGNDVCO
VVCO
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO AGND.
13345-003
AGND
VRF
RFOUTA+
RFOUTA−
AGNDRF
RFOUTB+
RFOUTB–
AVDD
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
CPGND 8
Figure 3. Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
Mnemonic
CLK
2
DATA
3
LE
4
CE
5, 16
AVDD
6
VP
7
CPOUT
8
9
10
CPGND
AGND
VRF
11
12
RFOUTA+
RFOUTA−
13
14
AGNDRF
RFOUTB+
15
RFOUTB−
17
VVCO
18, 21
19
AGNDVCO
VREGVCO
20
VTUNE
Description
Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high
impedance CMOS input.
Serial Data Input. The serial data is loaded most significant bit (MSB) first with the four least significant bits (LSBs)
as the control bits. This input is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register that
is selected by the four LSBs.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode. A
logic high on this pin powers up the device, depending on the status of the power-down bits.
Analog Power Supplies. These pins range from 3.1515 V to 3.4485 V. Connect decoupling capacitors to the analog
ground plane as close to these pins as possible. AVDD must have the same value as DVDD.
Charge Pump Power Supply. VP must have the same value as VVCO. Connect decoupling capacitors to the ground
plane as close to this pin as possible.
Charge Pump Output. When enabled, this output provides ±ICP to the external loop filter. The output of the loop
filter is connected to VTUNE to drive the internal VCO.
Charge Pump Ground. This output is the ground return pin for CPOUT.
Analog Ground. Ground return pin for AVDD.
Power Supply for the RF Output. Connect decoupling capacitors to the analog ground plane as close to this pin
as possible. VRF must have the same value as AVDD. For optimum spurious performance, VRF and DVDD must
originate from different regulators.
VCO Output. The output level is programmable. The VCO fundamental output or a divided down version is available.
Complementary VCO Output. The output level is programmable. The VCO fundamental output or a divided down
version is available.
RF Output Stage Ground. This pin is the ground return for the RF output stage.
Auxiliary VCO Output. The output level is programmable. The VCO fundamental output or a divided down version
is available.
Complementary Auxiliary VCO Output. The output level is programmable. The VCO fundamental output or a
divided down version is available.
Power Supply for the VCO. The voltage on this pin ranges from 3.1515 V to 3.4485 V. Connect decoupling
capacitors to the analog ground plane as close to this pin as possible.
VCO Ground. This pin is the ground return path for the VCO.
VCO Compensation Node. Connect decoupling capacitors to the ground plane as close to this pin as possible.
Connect this pin directly to VVCO.
Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CPOUT
output voltage. The capacitance at this pin (VTUNE input capacitance) is 7 pF.
Rev. B | Page 7 of 34
ADF4355-3
Pin No.
22
23
Mnemonic
RSET
VREF
24
VBIAS
25, 32
CREG1, CREG2
26
27
PDBRF
DVDD
28
29
30
REFINB
REFINA
MUXOUT
31
SDGND
EP
Data Sheet
Description
Bias Current Resistor. Connecting a resistor between this pin and ground sets the charge pump output current.
Internal Compensation Node. VREF is dc biased at half of the tuning range. Connect decoupling capacitors to the
ground plane as close to this pin as possible. The recommended capacitor values are 10 pF, 1 nF, and 4.7 µF.
Reference Voltage. Connect decoupling capacitors to the ground plane as close to this pin as possible. The
recommended capacitor values are 10 pF, 1 nF, and 1 µF.
Outputs from the LDO Regulator. Pin 25 and Pin 32 are the supply voltages to the digital circuits, and have a
nominal voltage of 1.8 V. Decoupling capacitors of 100 nF connected to AGND are required for these pins.
RF Power-Down. A logic low on this pin mutes the RF outputs. This mute function is also software-controllable.
Digital Power Supply. This pin must be at the same voltage as AVDD. Place decoupling capacitors to the ground
plane as close to this pin as possible. For optimum spurious performance, VRF and DVDD must originate from
different regulators.
Complementary Reference Input. If unused, ac-couple this pin to AGND.
Reference Input.
Multiplexer Output. The multiplexer output allows the digital lock detect, the analog lock detect, scaled RF, or the
scaled reference frequency to be externally accessible.
Digital Σ-Δ Modulator Ground. Pin 31 is the ground return path for the Σ-Δ modulator.
Exposed Pad. The exposed pad must be connected to AGND.
Rev. B | Page 8 of 34
Data Sheet
ADF4355-3
–50
–50
–70
–70
PHASE NOISE (dBc/Hz)
–90
–110
–130
–150
10k
100k
1M
OFFSET FREQUENCY (Hz)
10M
100M
–130
–170
1k
–50
–70
–70
–90
–110
–130
1M
10M
100M
÷1
÷2
÷4
÷8
÷16
÷32
÷64
–90
–110
–130
10k
100k
1M
OFFSET FREQUENCY (Hz)
10M
100M
–170
13345-005
1k
Figure 5. Open-Loop VCO Phase Noise, 5.0 GHz
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
13345-008
–150
–150
Figure 8. Closed-Loop Phase Noise, RFOUTA+, Fundamental VCO and Dividers,
VCO = 5.0 GHz, fPFD = 61.44 MHz, Loop Bandwidth = 35 kHz
–50
–70
–70
PHASE NOISE (dBc/Hz)
–50
–90
–110
–130
–150
÷1
÷2
÷4
÷8
÷16
÷32
÷64
–90
–110
–130
–150
1k
10k
100k
1M
OFFSET FREQUENCY (Hz)
10M
Figure 6. Open-Loop VCO Phase Noise, 6.6 GHz
100M
–170
13345-006
–170
100k
Figure 7. Closed-Loop Phase Noise, RFOUTA+, Fundamental VCO and Dividers,
VCO = 3.3 GHz, fPFD = 61.44 MHz, Loop Bandwidth = 35 kHz
–50
–170
10k
FREQUENCY (Hz)
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)
–110
13345-007
1k
Figure 4. Open-Loop VCO Phase Noise, 3.3 GHz
PHASE NOISE (dBc/Hz)
–90
–150
13345-004
–170
÷1
÷2
÷4
÷8
÷16
÷32
÷64
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
13345-009
PHASE NOISE (dBc/Hz)
TYPICAL PERFORMANCE CHARACTERISTICS
Figure 9. Closed-Loop Phase Noise, RFOUTA+, Fundamental VCO and Dividers,
VCO = 6.6 GHz, fPFD = 61.44 MHz, Loop Bandwidth = 35 kHz
Rev. B | Page 9 of 34
Data Sheet
–40
5
–50
WORST CASE PFD SPUR (dBc)
10
0
–5
–10
–15
–20
–40°C
+25°C
+105°C
–30
0
1
2
3
4
5
6
Figure 10. Output Power vs. Frequency, RFOUTA+/RFOUTA− (7.5 nH Inductors,
10 pF Bypass Capacitors, Board Losses De-Embedded)
–80
–90
0
1
2
3
4
5
6
FREQUENCY (GHz)
Figure 13. Worst Case PFD Spur vs. Frequency, fPFD = 15.36 MHz, 30.72 MHz,
and 61.44 MHz, Loop Filter = 35 kHz
–80
SECOND HARMONIC
THIRD HARMONIC
0
–90
PHASE NOISE (dBc/Hz)
–10
–20
–30
–40
–50
–100
–110
–120
–130
–140
0
1
2
3
4
FREQUENCY (GHz)
5
6
7
Figure 11. RFOUTA+/RFOUTA− Harmonics vs. Frequency (7.5 nH Inductors,
10 pF Bypass Capacitors, Board Losses De-Embedded)
1.2
–160
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
13345-018
–150
13345-049
RFOUTA+/RFOUTA− HARMONICS (dBc)
–70
–110
10
Figure 14. Spur Performance, GSM1800 Band, RFOUTA+ = 1550.2 MHz, REFIN =
122.88 MHz, fPFD = 61.44 MHz, Output Divide by 4 Selected, Loop Filter
Bandwidth = 35 kHz, Channel Spacing = 20 kHz
1kHz - 20MHz
12kHz - 20MHz
–80
1.0
–90
0.8
PHASE NOISE (dBc/Hz)
RMS JITTER (ps)
–60
–100
FREQUENCY (GHz)
–60
PFD = 61.44MHz
PFD = 30.72MHz
PFD = 15.36MHz
13345-051
–25
13345-048
OUTPUT POWER (dBm)
ADF4355-3
0.6
0.4
0.2
–100
–110
–120
–130
–140
1
2
3
4
5
OUTPUT FREQUENCY (GHz)
6
7
Figure 12. RMS Jitter vs. Output Frequency, fPFD = 61.44 MHz, Loop Filter = 35 kHz
–160
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
13345-019
0
13345-050
–150
0
Figure 15. Spur Performance, W-CDMA Band, RFOUTA+ = 2113.5 MHz, REFIN =
122.88 MHz, fPFD = 61.44 MHz, Output Divide by 2 Selected, Loop Filter
Bandwidth = 35 kHz, Channel Spacing = 20 kHz
Rev. B | Page 10 of 34
Data Sheet
ADF4355-3
–80
5
4
3
–100
FREQUENCY (MHz)
–110
–120
–130
–140
1
0
–1
–2
–3
–150
–4
10k
100k
1M
FREQUENCY (Hz)
10M
100M
Figure 16. Spur Performance, RFOUTA+ = 2.591 GHz,
REFIN = 122.88 MHz, fPFD = 61.44 MHz, Output Divide-by-2 Selected,
Loop Filter Bandwidth = 35 kHz, Channel Spacing = 20 kHz
–5
–150
13345-020
–160
1k
2
0
150
300
450
600 750
TIME (µs)
900
1050 1200 1350
13345-047
PHASE NOISE (dBc/Hz)
–90
Figure 17. Lock Time for 100 MHz Jump from 3300 MHz to 6600 MHz, Loop
Bandwidth = 3 kHz
Rev. B | Page 11 of 34
ADF4355-3
Data Sheet
THEORY OF OPERATION
REFERENCE INPUT SECTION
INT, FRACx, MODx, and R Counter Relationship
Figure 18 shows the reference input section of the ADF4355-3.
The reference input can accept both single-ended and differential
signals. Use the reference mode bit (Register 4, Bit DB9) to select
the signal. To use a differential signal on the reference input, program
this bit high. In this case, SW1 and SW2 are open, SW3 and SW4
are closed, and the current source that drives the differential pair
of transistors switches on. The differential signal is buffered, and
it is provided to an emitter coupled logic (ECL) to a CMOS
converter. When a single-ended signal is the reference, connect
the reference signal to REFINA and program Bit DB9 in Register 4
to 0. In this case, SW1 and SW2 are closed, SW3 and SW4 are
open, and the current source that drives the differential pair of
transistors switches off. Single-ended mode results in lower integer
boundary spurs.
The INT, FRAC1, FRAC2, MOD1, and MOD2 values, in
conjunction with the R counter, make it possible to generate
output frequencies that are spaced by fractions of the PFD
frequency (fPFD). For more information, see the RF Synthesizer—
A Worked Example section.
Calculate the RF VCO frequency (VCOOUT) by
VCOOUT = fPFD × N
where:
VCOOUT is the output frequency of the VCO (without using the
output divider).
fPFD is the frequency of the phase frequency detector.
N is the desired value of the feedback counter, N.
Calculate fPFD by
REFERENCE
INPUT MODE
fPFD = REFIN × ((1 + D)/(R × (1 + T)))
BUFFER
SW1
SW3
MULTIPLEXER
TO
R COUNTER
AVDD
N comprises
ECL TO CMOS
BUFFER
REFINA
N INT
REFINB
2.5kΩ
2.5kΩ
13345-022
SW4
BIAS
GENERATOR
Figure 18. Reference Input Stage
RF N DIVIDER
The RF N divider allows a division ratio in the PLL feedback path.
Determine the division ratio by the INT, FRAC1, FRAC2, and
MOD2 values that this divider comprises.
RF N COUNTER
FRAC1 +
N = INT +
MOD2
TO
PFD
MOD1
FRAC1
REG
FRAC2
VALUE
1.
2.
3.
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
INT
REG
(3)
Equation 3 results in a very fine frequency resolution with no residual frequency error. Apply this formula using the following steps:
FRAC2
N COUNTER
FRAC2
MOD2
MOD1
FRAC1
where:
INT is the 16-bit integer value (23 to 32,767 for the 4/5
prescaler, and 75 to 65,535 for the 8/9 prescaler).
FRAC1 is the numerator of the primary modulus (0 to 16,777,215).
FRAC2 is the numerator of the 14-bit auxiliary modulus
(0 to 16,383).
MOD2 is the programmable, 14-bit auxiliary fractional
modulus (2 to 16,383).
MOD1 is a 24-bit primary modulus with a fixed value of 224 =
16,777,216.
MOD2
VALUE
4.
13345-023
FROM
VCO OUTPUT/
OUTPUT DIVIDERS
(2)
where:
REFIN is the reference input frequency.
D is the REFIN doubler bit.
R is the preset divide ratio of the binary 10-bit programmable
reference counter (1 to 1023).
T is the REFIN divide by 2 bit (0 or 1).
85kΩ
SW2
(1)
Figure 19. RF N Divider
Rev. B | Page 12 of 34
Calculate N by dividing VCOOUT/fPFD. The integer value of
this number forms INT.
Subtract the INT value from the full N value.
Multiply the remainder by 224. The integer value of this
number forms FRAC1.
Calculate the MOD2 based on the channel spacing (fCHSP) by
MOD2 = fPFD /GCD(fPFD, fCHSP)
(4)
where:
fCHSP is the desired channel spacing.
GCD(fPFD, fCHSP) is the greatest common divider of the PFD
frequency and the channel spacing frequency.
Data Sheet
SDGND
Calculate FRAC2 by the following equation:
FRAC2 = ((N − INT) × 224 − FRAC1)) × MOD2
(5)
THREE-STATE OUTPUT
The FRAC2 and MOD2 fraction results in outputs with zero
frequency error for channel spacings when
SDGND
DGND
fPFD/GCD(fPFD/fCHSP) < 16,383
(6)
R DIVIDER OUTPUT
N DIVIDER OUTPUT
where:
fPFD is the frequency of the phase frequency detector.
GCD is a greatest common divider function.
fCHSP is the desired channel spacing.
RESERVED
INPUT SHIFT REGISTERS
R Counter
The 10-bit R counter allows the input reference frequency
(REFIN) to be divided down to produce the reference clock to
the PFD. Division ratios from 1 to 1023 are allowed.
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 20 is a simplified schematic of
the phase frequency detector. The PFD includes a fixed delay
element that sets the width of the antibacklash pulse. This pulse
ensures that there is no dead zone in the PFD transfer function
and provides a consistent reference spur level. Set the phase
detector polarity to positive on this device because of the
positive tuning of the VCO.
UP
U1
CLR1
DELAY
HIGH
U3
CHARGE
PUMP
CP
CLR2
DOWN
D2
Q2
U2
–IN
13345-024
+IN
DGND
Figure 21. MUXOUT Block Diagram
If negative bleed is enabled, lock detect is not reliable for low
PFD frequencies.
When FRAC1 and FRAC2 = 0, the synthesizer operates in
integer-N mode.
Q1
MUXOUT
SDGND to DVDD
INT N Mode
D1
CONTROL
DIGITAL LOCK DETECT
If zero frequency error is not required, the MOD1 and MOD2
denominators operate together to create a 38-bit resolution
modulus.
HIGH
MUX
13345-025
5.
ADF4355-3
The ADF4355-3 digital section includes a 10-bit R counter, a
16-bit RF integer-N counter, a 24-bit FRAC1 counter, a 14-bit
auxiliary fractional counter, and a 14-bit auxiliary modulus
counter. Data clocks into the 32-bit shift register on each rising
edge of CLK. The data clocks in MSB first. Data transfers from
the shift register to one of 13 latches on the rising edge of LE.
The state of the four control bits (C4, C3, C2, and C1) in the
shift register determines the destination latch. As shown in
Figure 2, the four least significant bits (LSBs) are DB3, DB2,
DB1, and DB0. The truth table for these bits is shown in Table 5.
Figure 24 and Figure 25 summarize the programing of the latches.
Table 5. Truth Table for the C4, C3, C2, and C1 Control Bits
C4
0
0
0
0
0
0
0
0
1
1
1
1
1
Figure 20. PFD Simplified Schematic
MUXOUT AND LOCK DETECT
The output multiplexer on the ADF4355-3 allows the user to access
various internal points on the chip. The M3, M2, and M1 bits in
Register 4 control the state of MUXOUT. Figure 21 shows the
MUXOUT section in block diagram form.
Rev. B | Page 13 of 34
C3
0
0
0
0
1
1
1
1
0
0
0
0
1
Control Bits
C2
0
0
1
1
0
0
1
1
0
0
1
1
0
C1
0
1
0
1
0
1
0
1
0
1
0
1
0
Register
Register 0
Register 1
Register 2
Register 3
Register 4
Register 5
Register 6
Register 7
Register 8
Register 9
Register 10
Register 11
Register 12
ADF4355-3
Data Sheet
130
PROGRAM MODES
120
Table 5 and Figure 24 through Figure 38 show the program
modes that must be set up in the ADF4355-3.
110
100
VCO
The VCO core in the ADF4355-3 consists of four separate VCOs,
each of which uses 256 overlapping bands, which allows covering
a wide frequency range without a large VCO sensitivity (KV) and
without resulting poor phase noise and spurious performance.
The correct VCO and band are chosen automatically by the VCO
and band select logic when Register 0 is updated and autocalibration is enabled. The VCO VTUNE is disconnected from the output of
the loop filter and is connected to an internal reference voltage.
The R counter output is the clock for the band select logic. After
band selection, normal PLL action resumes. The nominal value
of KV is 63 MHz/V when the N divider is driven from the VCO
output, or the KV value is divided by D. D is the output divider
value if the N divider is driven from the RF output divider
(chosen by programming Bits[D23:D21] in Register 6).
80
70
60
50
40
30
20
10
0
3.3
4.3
3.8
4.8
5.3
FREQUENCY (GHz)
5.8
6.3
13345-052
For example, to ensure that the modulus value loads correctly,
every time the modulus value updates, Register 0 must be
written to. The RF divider select in Register 6 is also double
buffered, but only when DB14 of Register 4 is high.
90
KV (MHz/V)
The following settings in the ADF4355-3 are double buffered:
main fractional value (FRAC1), auxiliary modulus value (MOD2),
auxiliary fractional value (FRAC2), reference doubler, reference
divide by 2 (RDIV2), phase value, R counter value, and charge
pump current setting. Two events must occur before the
ADF4355-3 uses a new value for any of the double buffered
settings. First, the new value must latch into the device by writing
to the appropriate register, and second, a new write to Register 0
must be performed.
Figure 22. KV vs. VCO Frequency
OUTPUT STAGE
The RFOUTA+ and RFOUTA− pins of the ADF4355-3 connect to
the collectors of an NPN differential pair driven by buffered
outputs of the VCO, as shown in Figure 23. In this scheme, the
ADF4355-3 contains internal 50 Ω resistors connected to the
VRF pin. To optimize the power dissipation vs. the output
power requirements, the tail current of the differential pair is
programmable using Bits[DB5:DB4] in Register 6. Four current
levels can be set. These levels give the approximate output power
levels of −4 dBm, −1 dBm, +2 dBm, and +5 dBm, respectively,
using a 50 Ω resistor to VRF and ac coupling into a 50 Ω load. For
accurate power levels, see the Typical Performance Characteristics
section. Add an external shunt inductor to provide higher power
levels; however, this is less wideband than the internal bias only.
Terminate the unused complementary output with a similar
circuit to the used output.
VRF
50Ω
The VCO shows the variation of KV as the tuning voltage, VTUNE,
varies within the band and from band to band. For wideband
applications covering a wide frequency range (and changing
output dividers), a value of 63 MHz/V provides the most accurate
KV, because this value is closest to the average value. Figure 22
shows how KV varies with fundamental VCO frequency along with
an average value for the frequency band. Users may prefer this
figure when using narrow-band designs.
RFOUTA+
50Ω
RFOUTA–
BUFFER/
DIVIDE BY
1/2/4/8/
16/32/64
13345-027
VCO
VRF
Figure 23. Output Stage
Another feature of the ADF4355-3 is that the supply current to
the output stages can shut down until the ADF4355-3 achieves
lock as measured by the digital lock detect circuitry. The mute until
lock detect (MTLD) bit (Bit DB11) in Register 6 enables this
function.
The RFOUTB+/RFOUTB− pins are duplicate outputs that can be
used independently or in addition to the RFOUTA+/RFOUTA− pins.
LOOP FILTER
Use only passive loop filters. For information on designing a
loop filter, use the ADIsimPLL design tool.
Rev. B | Page 14 of 34
Data Sheet
ADF4355-3
Table 6. Total IDD (RFOUTA± Refers to RFOUTA+/RFOUTA−)
Divide By
IVCO and IP
AIDD, DIDD, IRF
1
2
4
8
16
32
64
RFOUTA± Off
49.4 mA
RFOUTA± = −4 dBm
49.4 mA
RFOUTA± = −1 dBm
49.4 mA
RFOUTA± = +2 dBm
49.4 mA
RFOUTA± = +5 dBm
49.4 mA
91.8 mA
100.9 mA
110.8 mA
118.9 mA
124.0 mA
128.0 mA
130.4 mA
103.3 mA
113.6 mA
123.9 mA
132.1 mA
137.3 mA
141.4 mA
144.0 mA
106.5 mA
117.0 mA
127.5 mA
135.6 mA
140.8 mA
144.9 mA
147.4 mA
111.7 mA
122.8 mA
133.6 mA
141.8 mA
147.0 mA
151.1 mA
153.6 mA
116.9 mA
128.4 mA
139.8 mA
148.0 mA
153.3 mA
157.5 mA
160.0 mA
Rev. B | Page 15 of 34
ADF4355-3
Data Sheet
REGISTER MAPS
RESERVED
PRESCALER
AUTOCAL
REGISTER 0
CONTROL
BITS
16-BIT INTEGER VALUE (INT)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
0
0
0
0
0
0
0
0
0
0
AC1
PR1
N15
N16
N14
N13
N12
N11
N10
N8
N9
N7
DB8
DB7
DB6
DB5
DB4
N5
N4
N3
N2
N1
N6
DB3
DB2
C4(0) C3(0)
DB1
DB0
C2(0) C1(0)
REGISTER 1
CONTROL
BITS
DBR 1
24-BIT MAIN FRACTIONAL VALUE (FRAC1)
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
0
0
F24
0
F23
F22
F21
F19
F20
F18
F17
F16
F15
F14
F13
F12
F11
F10
F9
F8
F7
F6
DB7 DB6
F5
F4
F3
DB2
DB1
DB0
DB5 DB4
DB3
F2
C4(0) C3(0) C2(0) C1(1)
F1
REGISTER 2
14-BIT AUXILIARY FRACTIONAL VALUE (FRAC2)
DBR 1
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
F14
F13
F11
F12
F10
F9
F8
F7
F6
F5
CONTROL
BITS
14-BIT AUXILIARY MODULUS VALUE (MOD2) DBR 1
F4
F3
F2
M14
F1
M13
M12
M11
M10
M9
M8
M7
DB8
DB7
DB6
DB5
DB4
M5
M4
M3
M2
M1
M6
DB3
DB2
DB1
DB0
C4(0) C3(0) C2(1) C1(0)
PHASE
ADJUST
PHASE
RESYNC
SD LOAD
RESET
RESERVED
REGISTER 3
CONTROL
BITS
DBR 1
24-BIT PHASE VALUE (PHASE)
P22
P21
P20
P19
P18
P17
P16
P15
P14
P13
P12
P11
P10
P9
P8
P7
DB5 DB4
DB3
P6
P5
P4
P3
P2
P1
C4(0) C3(0) C2(1) C1(1)
COUNTER
RESET
P23
CP THREESTATE
P24
POWER-DOWN
PA1
PR1
PD
POLARIT Y
SD1
REF MODE
0
MUX LOGIC
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
DB7 DB6
CONTROL
BITS
DB2
DB1
DB0
DBR 1
DOUBLE BUFF
MUXOUT
RDIV2
RESERVED
REFERENCE
DOUBLER DBR 1
REGISTER 4
DBR 1
10-BIT R COUNTER
CURRENT
SETTING
DBR 1
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
0
M3
M2
M1
RD2
RD1
R10
R8
R9
R7
R6
R5
R4
R3
R2
CP4
D1
R1
CP3
CP2
CP1
U6
DB7 DB6
U5
U4
U3
DB5 DB4
DB3
U2
C4(0) C3(1) C2(0) C1(0)
U1
DB2
DB1
DB0
REGISTER 5
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26
0
0
0
0
0
DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
DB9
DB8
DB7
DB6
DB5
DB4
0
0
0
0
1
0
RF OUTPUT
ENABLE
RESERVED
RF
OUTPUT
POWER
0
DB3
DB2
DB1
DB0
C4(0) C3(1) C2(0) C1(1)
AUX RF
OUTPUT
POWER
CONTROL
BITS
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
1DBR
2DBB
BL10
BL9
1
0
1
0
D13
D12
D11
D10
BL8
BL7
BL6
BL5
BL4
BL3
BL2
BL1
0
D8
= DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.
= DOUBLE BUFFERED BITS—BUFFERED BY A WRITE TO REGISTER 0 WHEN BIT DB14 OF REGISTER 4 IS HIGH.
Figure 24. Register Summary (Register 0 to Register 6)
Rev. B | Page 16 of 34
0
D6
D5
D4
D3
D2
D1
DB2
DB1
DB0
C4(0) C3(1) C2(1) C1(0)
13345-028
RESERVED
CHARGE PUMP BLEED CURRENT
AUX RF OUTPUT
ENABLE
RF DIVIDER
SELECT2
MTLD
RESERVED
RESERVED
FEEDBACK
SELECT
NEGATIVE
BLEED
GATED
BLEED
RESERVED
REGISTER 6
Data Sheet
ADF4355-3
LDO MODE
LD
CYCLE
COUNT
RESERVED
FRAC-N LD
PRECISION
RESERVED
LOL MODE
LE SYNC
REGISTER 7
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4
0
0
0
1
0
0
LE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LD4
LD5
LOL LD3
CONTROL
BITS
DB3
DB2
DB1
DB0
LD2 LD1 C4(0) C3(1) C2(1) C1(1)
REGISTER 8
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
0
0
1
1
0
1
0
0
1
1
0
1
0
0
1
0
1
1
0
0
1
1
DB7 DB6
0
1
DB5 DB4
1
0
1
DB3
DB2
DB1
DB0
C4(1) C3(0) C2(0) C1(0)
REGISTER 9
VCO BAND DIVISION
SYNTHESIZER
LOCK TIMEOUT
RESERVED
TIMEOUT
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
VC8
VC7
VC6
VC5
VC4
VC3
VC2
VC1
TL10
TL9
TL8
TL7
TL6
TL5
TL4
TL3
TL2
TL1
1
1
1
1
1
SL5
CONTROL
BITS
DB7 DB6
DB5 DB4
SL4
SL2
SL3
DB3
DB2
DB1
DB0
SL1 C4(1) C3(0) C2(0) C1(1)
ADC
CLOCK DIVIDER
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AD8
AD7
AD6
AD5
AD4
DB7 DB6
AD3 AD2
AD1
ADC ENABLE
ADC
CONVERSION
REGISTER 10
DB5 DB4
CONTROL
BITS
DB3
DB2
DB1
DB0
AE2 AE1 C4(1) C3(0) C2(1) C1(0)
REGISTER 11
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
0
1
0
0
0
DB7 DB6
0
0
0
DB5 DB4
0
0
DB3
DB2
DB1
DB0
C4(1) C3(0) C2(1) C1(1)
REGISTER 12
P15
P14
P13
P12
P11
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
0
0
0
0
0
1
Figure 25. Register Summary (Register 7 to Register 12)
Rev. B | Page 17 of 34
DB9
DB8
DB7
DB6
DB5
DB4
0
1
0
0
0
0
DB3
DB2
DB1
DB0
C4(1) C3(1) C2(0) C1(0)
13345-029
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
P16
CONTROL
BITS
RESERVED
RESYNC CLOCK
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
0
0
0
0
0
0
0
0
0
0
AC1
PR1
CONTROL
BITS
16-BIT INTEGER VALUE (INT)
N16
N15
N14
N13
N12
N11
N10
N9
N8
N7
N6
DB8
DB7
DB6
DB5
DB4
N5
N4
N3
N2
N1
PR1
PRESCALER
N16
N15
...
N5
N4
N3
N2
N1
0
4/5
0
0
...
0
0
0
0
0
NOT ALLOWED
1
8/9
0
0
...
0
0
0
0
1
NOT ALLOWED
0
0
...
0
0
0
1
0
NOT ALLOWED
.
.
...
.
.
.
.
.
...
0
0
...
1
0
1
1
0
NOT ALLOWED
DB2
DB1
DB0
INTEGER VALUE (INT)
0
0
...
1
0
1
1
1
23
VCO
AUTOCAL
0
0
...
1
1
0
0
0
24
.
.
...
.
.
.
.
.
...
0
DISABLED
1
1
...
1
1
1
0
1
65533
1
ENABLED
1
1
...
1
1
1
1
0
65534
1
1
...
1
1
1
1
1
65535
AC1
DB3
C4(0) C3(0) C2(0) C1(0)
INTMIN = 75 WITH PRESCALER = 8/9
13345-030
RESERVED
PRESCALER
Data Sheet
AUTOCAL
ADF4355-3
Figure 26. Register 0
REGISTER 0
Prescaler Value
Control Bits
The dual modulus prescaler (P/P + 1), along with the INT,
FRACx, and MODx counters, determines the overall division
ratio from the VCO output to the PFD input. The PR1 bit
(Bit DB20) in Register 0 sets the prescaler value.
With Bits[C4:C1] set to 0000, Register 0 is programmed. Figure 26
shows the input data format for programming this register.
Reserved
Operating at CML levels, the prescaler takes the clock from the
VCO output and divides it down for the counters. It is based on
a synchronous 4/5 core. The prescaler limits the INT value;
therefore, if P is 4/5, INTMIN is 23, and if P is 8/9, INTMIN is 75.
Bits[DB31:DB22] are reserved and must be set to 0.
Automatic Calibration (Autocal)
Write to Register 0 to enact (by default) the VCO automatic
calibration, and to choose the appropriate VCO and VCO
subband. Write 1 to the AC1 bit (Bit DB21) to enable the
automatic calibration, which is the recommended mode of
operation.
16-Bit Integer Value
Set the AC1 bit to 0 to disable the automatic calibration, which
leaves the ADF4355-3 in the same band it is already in when
Register 0 is updated.
The 16 INT bits (Bits[DB19:DB4]) set the INT value, which
determines the integer part of the feedback division factor. The
INT value is used in Equation 3 (see the RF Synthesizer—A
Worked Example section). All integer values from 23 to 32,767
are allowed for the 4/5 prescaler. For the 8/9 prescaler, the
minimum integer value is 75, and the maximum value is 65,535.
Disable the automatic calibration only for fixed frequency
applications, phase adjust applications, or very small ( 100 MHz, disable bleed current using DB29.
where:
Floor() is a function to round down to the nearest integer value.
Bleed Value is the value programmed to Bits[DB20:DB13].
fPFD is the PFD frequency.
ICP is the value of charge pump current setting, Bits[DB13:DB10] of
Register 4.
Auxiliary RF Output Enable
Bit DB9 enables or disables the auxiliary frequency RF output
(RFOUTB+/RFOUTB−). When DB9 is set to 1, the auxiliary
frequency RF output is enabled. When DB9 is set to 0, the
auxiliary RF output is disabled.
Auxiliary RF Output Power
Bits[DB8:DB7] set the value of the auxiliary RF output power
level.
RF Output Enable
Bit DB6 enables or disables the primary RF output (RFOUTA+/
RFOUTA−). When DB6 is set to 0, the primary RF output is
disabled; when DB6 is set to 1, the primary RF output is
enabled.
Output Power
Bits[DB5:DB4] set the value of the primary RF output power level.
Reserved
Bit DB12 is reserved and must be set to 0.
Mute Till Lock Detect
When D8 (Bit DB11) is set to 1, the supply current to the RF
output stage is shut down until the device achieves lock, as
determined by the digital lock detect circuitry.
Rev. B | Page 25 of 34
LD MODE
LD
CYCLE
COUNT
RESERVED
LOL MODE
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4
0
0
0
1
0
0
LE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LD5
LD4
LE SYNCHRONIZ ATION
DB3
DB2
DB1
DB0
LD2 LD1 C4(0) C3(1) C2(1) C1(1)
LOL LD3
LD1
LE
CONTROL
BITS
LOCK DETECT MODE
0
FRACTIONAL-N
1
INTEGER-N (2.9ns)
LD3 LD2
FRACTIONAL-N LD PRECISION
0
0
5.0ns
0
1
6.0ns
1
0
8.0ns
1
1
12.0ns
LOL LOSS OF LOCK MODE
0
DISABLED
0
DISABLED
1
LE SYNCED TO REFIN
1
ENABLED
LD5 LD4
LOCK DETECT CYCLE COUNT
0
0
1024
0
1
2048
1
0
4096
1
1
8192
13345-037
RESERVED
FRAC-N LD
PRECISION
Data Sheet
LE SYNC
ADF4355-3
Figure 33. Register 7
REGISTER 7
Loss of Lock (LOL) Mode
Control Bits
Bits[DB31:DB29] and Bits[DB27:DB26] are reserved and must
be set to 0. Bit DB28 is reserved and must be set to 1.
Set LOL (Bit DB7) to 1 when the application is a fixed frequency
application in which the reference (REFIN) is likely to be removed,
such as a clocking application. The standard lock detect circuit
assumes that REFIN is always present; however, this may not be
the case with clocking applications. To enable this functionality,
set Bit DB7 to 1. Loss of lock mode does not function reliably
when using differential REFIN mode.
LE Sync
Fractional-N Lock Detect Precision (LDP)
When set to 1, Bit DB25 ensures that the load enable (LE) edge
is synchronized internally with the rising edge of the reference
input frequency. This synchronization prevents the rare event of
reference and RF dividers loading at the same time as a falling
edge of reference frequency, which can lead to longer lock times.
LD3 and LD2 (Bits[DB6:DB5]) set the precision of the lock detect
circuitry in fractional-N mode. LDP is available at 5.0 ns, 6.0 ns,
8.0 ns, or 12.0 ns. If bleed currents are used, use 12.0 ns.
With Bits[C4:C1] set to 0111, Register 7 is programmed. Figure 33
shows the input data format for programming this register.
Reserved
Reserved
Bits[DB24:DB10] are reserved and must be set to 0.
Fractional-N Lock Detect Count (LDC)
LD5 and LD4 (Bits[DB9:DB8]) set the number of consecutive
cycles counted by the lock detect circuitry before asserting lock
detect high. See Figure 33 for details.
Lock Detect Mode (LDM)
If LD1 (Bit DB4) is set to 0, each reference cycle is set by the
fractional-N lock detect precision as described in the
Fractional-N Lock Detect Count (LDC) section. If DB4 is
set to 1, each reference cycle is 2.9 ns long, which is more
appropriate for integer-N applications.
Rev. B | Page 26 of 34
Data Sheet
ADF4355-3
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
0
1
0
1
0
1
0
0
1
1
0
1
0
0
1
0
1
1
0
0
1
1
0
DB7 DB6
1
DB5 DB4
1
0
1
DB3
DB2
DB1
DB0
C4(1) C3(0) C2(0) C1(0)
13345-038
CONTROL
BITS
RESERVED
Figure 34. Register 8 (0x1A69A6B8)
TIMEOUT
VCO BAND DIVISION
SYNTHESIZER
LOCK TIMEOUT
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
VC8
VC7
VC5
VC6
VC4
VC3
VC2
VC1
TL10
TL9
TL8
TL7
TL6
TL5
TL4
TL3
TL2
TL1
1
1
1
1
..........
TL2
TL1
0
0
..........
0
1
1
0
0
..........
1
0
2
.
.
..........
.
.
.
.
.
..........
.
.
.
.
.
..........
.
.
.
1
1
..........
0
0
1020
1
1
..........
0
1
1021
1
1
..........
1
0
1022
1
1
..........
1
1
1023
..........
VC2
VC1
0
..........
0
1
1
0
0
..........
1
0
2
.
.
..........
.
.
.
.
.
..........
.
.
.
.
.
..........
.
.
.
1
1
..........
0
0
252
1
1
..........
0
1
253
1
1
..........
1
0
254
1
1
..........
1
1
255
DB7 DB6 DB5 DB4
SL4
SL3
SL2
DB3
DB2
DB1
DB0
SL1 C4(1) C3(0) C2(0) C1(1)
SL4
..........
SL2
SL1
0
..........
0
1
SLC WAIT
1
0
0
..........
1
0
2
.
.
..........
.
.
.
.
.
..........
.
.
.
.
.
..........
.
.
.
1
1
..........
0
0
28
1
1
..........
0
1
29
1
1
..........
1
0
30
1
1
..........
1
1
31
VCO BAND DIV
13345-039
VC7
0
VC8
TIMEOUT
SL5
0
SL5
TL9
TL10
1
CONTROL
BITS
Figure 35. Register 9
REGISTER 8
VCO Band Division
The bits in this register are reserved and must be programmed as
shown in Figure 34, using a hexadecimal word of 0x1A69A6B8.
VC8 to VC1 (Bits[DB31:DB24]) set the value of the VCO band
division clock. Determine the value of this clock by
VCO Band Div = ceiling(fPFD/2,400,000)
REGISTER 9
Timeout
For a worked example and more information, see the Lock
Time section.
TL10 to TL1 (Bits[DB23:DB14]) set the timeout value for the
VCO band selection.
Control Bits
With Bits[C4:C1] set to 1001, Register 9 is programmed. Figure 35
shows the input data format for programming this register.
Reserved Bits
Bits[DB13:DB9]) are reserved and must be set to 0b11111.
Synthesizer Lock Timeout
SL5 to SL1 (Bits[DB8:DB4]) set the synthesizer lock timeout
value. This value allows the VTUNE force to settle on the VTUNE pin.
The value must be 20 μs. Calculate the value using Equation 10:
Synthesizer Lock Timeout > (20 μs × fPFD)/Timeout
Rev. B | Page 27 of 34
(10)
Data Sheet
ADC
CLOCK DIVIDER
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
AD8
0
AD8
AD7
AD6
AD5
AD4
DB7 DB6
AD3 AD2
AD7
..........
AD2
0
0
..........
0
1
1
0
0
..........
1
0
2
.
.
..........
.
.
.
.
.
..........
.
.
.
.
.
..........
.
.
.
1
1
..........
0
0
252
1
1
..........
0
1
253
1
1
..........
1
0
254
1
1
..........
1
1
255
DB5 DB4
AD1
CONTROL
BITS
DB3
DB2
DB1
DB0
AE2 AE1 C4(1) C3(0) C2(1) C1(0)
AE1
ADC
0
DISABLED
1
ENABLED
AE2
ADC CONVERSION
0
DISABLED
1
ENABLED
AD1 ADC CLK DIV
13345-040
RESERVED
ADC ENABLE
ADC
CONVERSION
ADF4355-3
Figure 36. Register 10
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
1
0
0
0
0
0
DB7 DB6 DB5 DB4
0
0
0
0
DB3
DB2
DB1
DB0
C4(1) C3(0) C2(1) C1(1)
13345-041
CONTROL
BITS
RESERVED
Figure 37. Register 11 (0x0081200B)
Choose the ADC_CLK_DIV value such that
REGISTER 10
Control Bits
ADC_CLK_DIV = ceiling(((fPFD/100,000) − 2)/4)
With Bits[C4:C1] set to 1010, Register 10 is programmed.
Figure 36 shows the input data format for programming this
register.
(11)
where ceiling() is a function to round up to the nearest integer.
For example, for fPFD = 61.44 MHz, set ADC_CLK_DIV = 154
so that the ADC clock frequency is 99.417 kHz. If ADC_CLK_DIV
is greater than 255, set it to 255.
Reserved
Bits[DB31:DB14] are reserved. Bits[DB23:DB22] must be set to
11, and all other bits in this range must be set to 0.
ADC Conversion Clock (ADC_CLK_DIV)
An on-board analog-to-digital converter (ADC) is connected to
a temperature sensor. It determines the VTUNE setpoint relative
to the ambient temperature of the ADF4355-3 environment.
The ADC ensures that the initial tuning voltage in any application
is chosen correctly to avoid any temperature drift issues.
The ADC uses a clock that is equal to the output of the R
counter (or the PFD frequency) divided by ADC_CLK_DIV.
AD8 to AD1 (Bits[DB13:DB6]) set the value of this divider. On
power-up, the R counter is not programmed; however, in these
power-up cases, it defaults to R = 1.
ADC Conversion Enable
AE2 (Bit DB5) ensures that the ADC performs a conversion
when a write to Register 10 is performed. It is recommended to
enable this mode.
ADC Enable
AE1 (Bit DB4), when set to 1, powers up the ADC for the
temperature dependent VTUNE calibration. It is recommended to
always use this function.
REGISTER 11
The bits in this register are reserved and must be programmed
as described in Figure 37, using a hexadecimal word of
0x0081200B.
Rev. B | Page 28 of 34
Data Sheet
ADF4355-3
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
P15
P14
P13
P12
P11
P10
P9
P8
P7
P6
P5
P4
P3
P2
P16
P15
...
P5
P4
P3
P2
P1
RESYNC CLOCK
0
0
...
0
0
0
0
0
NOT ALLOWED
0
0
...
0
0
0
0
1
1
0
0
...
0
0
0
1
0
2
.
.
...
.
.
.
.
.
...
0
0
...
1
0
1
1
0
22
0
0
...
1
0
1
1
1
23
0
0
...
1
1
0
0
0
24
.
.
...
.
.
.
.
.
...
1
1
...
1
1
1
0
1
65533
1
1
...
1
1
1
1
0
65534
1
1
...
1
1
1
1
1
65535
P1
0
0
0
0
0
1
DB9
DB8
DB7
DB6
DB5
DB4
0
1
0
0
0
0
DB3
DB2
DB1
DB0
C4(1) C3(1) C2(0) C1(0)
13345-042
P16
CONTROL
BITS
RESERVED
RESYNC CLOCK
Figure 38. Register 12
REGISTER 12
14. Register 0.
Control Bits
For fPFD > 75 MHz (initially lock with halved fPFD), use the
following sequence:
With Bits[C4:C1] set to 1100, Register 12 is programmed. Figure 38
shows the input data format for programming this register.
Phase Resync Clock Divider Value
P16 to P1 (Bits[DB31:DB16]) set the timeout counter for
activation of phase resync. This value must be set such that a
the resync happens immediately after (and not before) the PLL
achieves lock after reprogramming.
Calculate the timeout value using the following equation:
Timeout Value = Phase Resync Clock/fPFD
(12)
Reserved
Bits[DB15:DB4] are reserved. Bit DB10 and Bit DB8 must be set
to 1, but all other bits in this range must be set to 0.
REGISTER INITIALIZATION SEQUENCE
At initial power-up, after the correct application of voltages to
the supply pins, the ADF4355-3 registers must be programmed
in sequence. For f ≤ 75 MHz, use the following sequence:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
Register 12.
Register 11.
Register 10.
Register 9.
Register 8.
Register 7.
Register 6.
Register 5.
Register 4.
Register 3.
Register 2.
Register 1.
Wait >16 ADC_CLK cycles. For example, if ADC_CLK =
99.417 kHz, wait 16/99,417 sec = 161 μs. See the Register 10
section for more information.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
Rev. B | Page 29 of 34
Register 12.
Register 11.
Register 10.
Register 4 (with the R divider doubled to halve fPFD).
Register 9.
Register 8.
Register 7.
Register 6.
Register 5.
Register 4 (with the R divider doubled to halve fPFD).
Register 3.
Register 2 (for halved fPFD).
Register 1 (for halved fPFD).
Wait >16 ADC_CLK cycles. For example, if ADC_CLK =
99.417 kHz, wait 16/99,417 sec = 161 μs. See the Register 10
section for more information.
Register 0 (for halved fPFD; autocalibration enabled).
Register 4 (with the R divider set for desired fPFD).
Register 2 (for desired fPFD).
Register 1 (for desired fPFD).
Register 0 (for desired fPFD; autocalibration disabled).
ADF4355-3
Data Sheet
Frequency updates require updating the auxiliary modulator
(MOD2) in Register 2, the fractional value (FRAC1) in Register 1,
and the integer value (INT) in Register 0. It is recommended to
perform a temperature dependent VTUNE calibration by updating
Register 10 first. Therefore, for fPFD ≤ 75 MHz, the sequence
must be as follows:
1.
2.
3.
4.
5.
Register 10.
Register 2.
Register 1.
Wait >16 ADC_CLK cycles. For example, if ADC_CLK =
99.417 kHz, wait 16/99,417 sec = 161 μs. See the Register 10
section for more information.
Register 0.
For example, in a universal mobile telecommunication system
(UMTS) where 2112.8 MHz RF frequency output (RFOUT) is
required, a 122.88 MHz reference frequency input (REFIN) is
available. Note that the ADF4355-3 VCO operates in the
frequency range of 3.3 GHz to 6.6 GHz. Therefore, RF divider
of 2 must be used (VCO frequency = 4225.6 MHz, RFOUT =
VCO frequency/RF divider = 4225.6 MHz/2 = 2112.8 MHz).
The feedback path is also important. In this example, the VCO
output is fed back before the output divider (see Figure 39).
In this example, the 122.88 MHz reference signal is divided by 2
to generate an fPFD value of 61.44 MHz. The desired channel
spacing is 200 kHz.
fPFD
PFD
For fPFD > 75 MHz (initially lock with halved fPFD), the sequence
must be as follows:
1.
2.
3.
4.
5.
Register 10.
Register 4 (RDivider doubled for halved fPFD).
Register 2 (for halved fPFD).
Register 1 (for halved fPFD).
Wait >16 ADC_CLK cycles. For example, if ADC_CLK =
99.417 kHz, wait 16/99,417 sec = 161 μs. See the Register 10
section for more information.
6. Register 0 (for halved fPFD; autocalibration enabled).
7. Register 4 (RDivider set for desired fPFD).
8. Register 2 (for desired fPFD).
9. Register 1 (for desired fPFD).
10. Register 0 (for desired fPFD; autocalibration disabled).
The worked example is as follows:
•
•
•
•
•
•
•
N = VCOOUT/fPFD = 4225.6 MHz/61.44 MHz =
68.7760416666666667
INT = int(VCO frequency/fPFD) = 68
FRAC = 0.7760416666666667
MOD1 = 16,777,216
FRAC1 = int(MOD1 × FRAC) = 13,019,817
Remainder = 0.6666666667 or 2/3
MOD2 = fPFD/GCD(fPFD/fCHSP) = 61.44 MHz/GCD(61.44 MHz/
200 kHz) = 1536
FRAC2 = remainder × 1536 = 1024
RF SYNTHESIZER—A WORKED EXAMPLE
From Equation 14,
Use the following equations to program the ADF4355-3
synthesizer:
where:
RFOUT is the RF frequency output.
INT is the integer division factor.
FRAC1 is the fractionality.
FRAC2 is the auxiliary fractionality.
MOD2 is the auxiliary modulus.
MOD1 is the fixed 24-bit modulus.
RF Divider is the output divider that divides down the VCO
frequency.
fPFD = REFIN × ((1 + D)/(R × (1 + T)))
where:
REFIN is the reference frequency input.
D is the RF REFIN doubler bit.
R is the RF reference division factor.
T is the reference divide by 2 bit (0 or 1).
RFOUT
Figure 39. Loop Closed Before Output Divider
•
(13)
÷2
N
DIVIDER
The frequency change occurs only when writing to Register 0.
FRAC2
FRAC1 +
MOD2 × (fPFD)/RF Divider
RFOUT = INT +
MOD1
VCO
13345-043
FREQUENCY UPDATE SEQUENCE
fPFD = (122.88 MHz × (1 + 0)/2) = 61.44 MHz
(15)
2112.8 MHz = 61.44 MHz × ((INT + (FRAC1 +
FRAC2/MOD2)/224))/2
(16)
where:
INT = 68
FRAC1 = 13,019,817
FRAC2 = 1024
MOD2 = 1536
REFERENCE DOUBLER AND REFERENCE DIVIDER
(14)
The on-chip reference doubler allows the input reference signal
to be doubled. The doubler is useful for increasing the PFD
comparison frequency. To improve the noise performance of
the system, increase the PFD frequency. Doubling the PFD
frequency typically improves noise performance by 3 dB.
The reference divide by 2 divides the reference signal by 2,
resulting in a 50% duty cycle PFD frequency.
Rev. B | Page 30 of 34
Data Sheet
ADF4355-3
SPURIOUS OPTIMIZATION AND FAST LOCK
LOCK TIME
Narrow loop bandwidths can filter unwanted spurious signals,
but these bandwidths usually have a long lock time. A wider
loop bandwidth achieves faster lock times but may lead to
increased spurious signals inside the loop bandwidth.
The PLL lock time divides into a number of settings. All of
these settings are modeled in the ADIsimPLL design tool.
OPTIMIZING JITTER
Synthesizer Lock Timeout
For lowest jitter applications, use the highest possible PFD
frequency to minimize the contribution of in-band noise from
the PLL. Set the PLL filter bandwidth such that the in-band noise
of the PLL intersects with the open-loop noise of the VCO,
minimizing the contribution of both to the overall noise.
The synthesizer lock timeout ensures that the VCO calibration
DAC, which forces VTUNE, settles to a steady value for the band
select circuitry.
Use the ADIsimPLL design tool for this task.
SPUR MECHANISMS
This section describes the two different spur mechanisms that
arise with a fractional-N synthesizer and how to minimize them
in the ADF4355-3.
Much faster lock times than those detailed in this data sheet are
possible; contact Analog Devices, Inc., for more information.
The timeout and synthesizer lock timeout variables programmed
in Register 9 select the length of time the DAC is allowed to
settle to the final voltage before the VCO calibration process
continues to the next phase, which is VCO band selection. The
PFD frequency is used as the clock for this logic, and the
duration is set by
(Timeout × Synthesizer Lock Timeout)/fPFD
Integer Boundary Spurs
The calculated time must be greater than or equal to 20 µs.
One mechanism for fractional spur creation is the interactions
between the RF VCO frequency and the reference frequency.
When these frequencies are not integer related (the purpose of a
fractional-N synthesizer), spur sidebands appear on the VCO
output spectrum at an offset frequency that corresponds to the
beat note or the difference in frequency between an integer
multiple of the reference and the VCO frequency. These spurs
are attenuated by the loop filter and are more noticeable on
channels close to integer multiples of the reference where the
difference frequency can be inside the loop bandwidth (thus
the name, integer boundary spurs).
VCO Band Selection
Reference Spurs
Reference spurs are generally not a problem in fractional-N
synthesizers because the reference offset is far outside the loop
bandwidth. However, any reference feedthrough mechanism
that bypasses the loop may cause a problem. Feedthrough of
low levels of on-chip reference switching noise, through the
prescaler back to the VCO, can result in reference spur levels
as high as −80 dBc.
(17)
Use the PFD frequency again as the clock for the band selection
process. Calculate this value by
fPFD/(VCO Band Selection × 16) < 150 kHz
(18)
The band selection takes 11 cycles of the previously calculated
value. Calculate the duration by
11 × (VCO Band Selection × 16)/fPFD
(19)
PLL Low-Pass Filter Settling Time
The time taken for the loop to settle is inversely proportional to
the low-pass filter bandwidth. The settling time is also modeled
in the ADIsimPLL design tool.
The total lock time for changing frequencies is the sum of the
three separate times (synthesizer lock, VCO band selection, and
PLL settling time), all of which are modeled in the ADIsimPLL
design tool.
Rev. B | Page 31 of 34
ADF4355-3
Data Sheet
APPLICATIONS INFORMATION
The LO ports of the ADL5375 can be driven differentially from
the complementary RFOUTA+/RFOUTA− outputs of the ADF4355-3.
A differential drive gives better second-order distortion performance than a single-ended LO driver and eliminates the use of
a balun to convert from a single-ended LO input to the more
desirable differential LO input for the ADL5375.
DIRECT CONVERSION MODULATOR
Direct conversion architectures are used to implement base station
transmitters. Figure 40 shows how to use Analog Devices devices to
implement such a system.
The circuit block diagram shows the AD9761 TxDAC® being
used with the ADL5375. The use of a dual integrated DAC, such
as the AD9761, ensures minimum error contribution (over
temperature) from this portion of the signal chain.
The ADL5375 accepts LO drive levels from −6 dBm to +6 dBm.
The optimum LO power can be software programmed on the
ADF4355-3, which allows levels from −4 dBm to +5 dBm from
each output.
The local oscillator (LO) is implemented using the ADF4355-3.
The low-pass filter was designed using the ADIsimPLL design
tool for a PFD of 61.44 MHz and a closed-loop bandwidth of
20 kHz.
51Ω
REFIO
MODULATED
DIGITAL
DATA
51Ω
IOUTA
LOW-PASS
FILTER
IOUTB
AD9761
The RF output is designed to drive a 50 Ω load; however, it
must be ac-coupled, as shown in Figure 40. If the I and Q inputs
are driven in quadrature by 2 V p-p signals, the resulting output
power from the ADL5375 modulator is approximately 2 dBm.
TxDAC
QOUTA
LOW-PASS
FILTER
QOUTB
FSADJ
51Ω
51Ω
2kΩ
VVCO
VDD
FREFIN
17
25
26 10
5
4
6
27
16
VVCO VP AV DD DVDD AV DD CE PDBRF VRF CREG1
100nF
LOCK
DETECT
32
30
CREG2 MUXOUT
RFOUTB+ 14
1nF 1nF
FREFIN
RFOUTB– 15
28 REFINB
7.5nH
7.5nH
1nF
2 DATA
SPI-COMPATIBLE SERIAL BUS
IBBN
VOUT
1 CLK
RFOUTA+ 11
ADF4355-3
3 LE
LOIP
LPF
LOIN
RFOUTA– 12
1nF
5.1kΩ
QBBP
33nF
1500pF
CPGND SDGND AGND A GNDRF A GNDVCO VREGVCO
31
9
13
18 21
10pF
19
VREF
VBIAS
23
24
0.1µF 10pF
RFOUT
DSOP
3.3kΩ
CPOUT 7
22 RSET
QUADRATURE
PHASE
SPLITTER
LPF
VTUNE 20
8
ADL5375
IBBP
29 REF A
IN
390pF
QBBN
1kΩ
0.1µF 10pF
0.1µF
Figure 40. Direct Conversion Modulator
Rev. B | Page 32 of 34
13345-044
1nF 1nF
100nF
Data Sheet
ADF4355-3
POWER SUPPLIES
Take care with the RF output traces to minimize discontinuities
and ensure the best signal integrity. Via placement and grounding
are critical.
The ADF4355-3 contains four multiband VCOs that together cover
an octave range of frequencies. To ensure best performance, it is
vital to connect a low noise regulator, such as the ADM7150, to
the VVCO pin. Connect the same regulator to VVCO, VREGVCO, VRF,
and VP.
OUTPUT MATCHING
The low frequency output can simply be ac-coupled to the next
circuit, if desired; however, if higher output power is required,
use a pull-up inductor to increase the output power level.
For the 3.3 V supply pins, use one or two ADM7150 regulators.
Figure 42 shows the recommended connections.
VRF
PRINTED CIRCUIT BOARD (PCB) DESIGN
GUIDELINES FOR A CHIP-SCALE PACKAGE
7.5nH
Figure 41. Optimum Output Stage
When differential outputs are not needed, terminate the unused
output or combine it with both outputs using a balun.
The bottom of the chip-scale package has a central exposed thermal
pad. The thermal pad on the PCB must be at least as large as the
exposed pad. On the PCB, there must be a minimum clearance of
0.25 mm between the thermal pad and the inner edges of the
pad pattern. This clearance ensures the avoidance of shorting.
For lower frequencies below 2 GHz, it is recommended to use a
100 nH inductor on the RFOUTA+/RFOUTA− pins.
The RFOUTA+/RFOUTA− pins are a differential circuit. Provide
each output with the same (or similar) components where
possible, such as the same shunt inductor value, bypass
capacitor, and termination.
To improve the thermal performance of the package, use thermal
vias on the PCB thermal pad. If vias are used, incorporate them
into the thermal pad at the 1.2 mm pitch grid. The via diameter
must be between 0.3 mm and 0.33 mm, and the via barrel must
be plated with 1 oz. of copper to plug the via.
The auxiliary frequency output, RFOUTB+/RFOUTB−, can be
treated the same as the RFOUTA+/RFOUTA− output. If unused,
leave both RFOUTB+/RFOUTB− pins open.
For a microwave PLL and VCO synthesizer, such as the ADF4355-3,
take care with the board stack-up and layout. Do not use FR4
material because it is too lossy above 3 GHz. Instead, Rogers 4350,
Rogers 4003, or Rogers 3003 dielectric material is suitable.
ON
OFF
EN
VOUT
ADM7150
COUT
1µF
100nF
REF
BYP
CBYP
1µF
VOUT = 3.3V
VREG
CREG
10µF
10
6
VVCO VP VRF
17
REF_SENSE
GND
FREF IN
FREF IN
1nF 1nF
LOCK
DETECT
100nF
25
30
CREG1 MUXOUT
5
26
4
27
32
16
AV DD DVDD AVDD CE PDB RF CREG2
29 REF INA
RFOUTB+ 14
1nF 1nF
RFOUTB– 15
28 REF INB
7.5nH
VIN
CIN
1µF
ON
OFF
CBYP
1µF
EN
VOUT
ADM7150
REF
BYP
VREG
CREG
10µF
REF_SENSE
GND
VOUT = 3.3V
COUT
1µF
SPI-COMPATIBLE SERIAL BUS
1 CLK
VIN = 6.0V
VOUT
7.5nH
1nF
2 DATA
RFOUTA+ 11
ADF4355-3
3 LE
RFOUTA– 12
1nF
VTUNE 20
1kΩ
CPOUT 7
22 RSET
5.1kΩ
2700pF
CPGND SDGND AGND AGNDRF AGNDVCO
8
31
9
13
18
VREGVCO
21
19
10pF
Figure 42. Power Supplies
Rev. B | Page 33 of 34
680pF
360kΩ
VREF VBIAS
23
47nF
24
0.1µF 10pF
0.1µF 10pF
0.1µF
13345-045
VIN
CIN
1µF
50Ω
13345-046
The lands on the 32-lead lead frame chip-scale package are rectangular. The PCB pad for these lands must be 0.1 mm longer than the
package land length and 0.05 mm wider than the package land
width. Center each land on the pad to maximize the solder joint size.
VIN = 6.0V
100pF
RFOUTA+
ADF4355-3
Data Sheet
OUTLINE DIMENSIONS
0.30
0.25
0.18
32
25
1
24
0.50
BSC
3.75
3.60 SQ
3.55
EXPOSED
PAD
17
TOP VIEW
0.80
0.75
0.70
TOP VIEW
PKG-004570
SEATING
PLANE
0.50
0.40
0.30
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
8
16
9
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
0.25 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5.
02-22-2017-B
PIN 1
INDICATOR
DETAIL A
(JEDEC 95)
5.10
5.00 SQ
4.90
Figure 43. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 0.75 mm Package Height
(CP-32-12)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADF4355-3BCPZ
ADF4355-3BCPZ-RL7
EV-ADF4355-3SD1Z
1
Temperature Range
−40°C to +105°C
−40°C to +105°C
Package Description
32-Lead Lead Frame Chip Scale Package [LFCSP]
32-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
Z = RoHS Compliant Part.
©2015–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D13345-0-8/17(B)
Rev. B | Page 34 of 34
Package Option
CP-32-12
CP-32-12
工商网监
湘ICP备2023018690号
