Data Sheet
6.8 GHz Wideband Synthesizer
with Integrated VCO
ADF4356
FEATURES
GENERAL DESCRIPTION
RF output frequency range: 53.125 MHz to 6800 MHz
Integer channel: −227 dBc/Hz
Fractional channel: −225 dBc/Hz
Integrated RMS jitter (1 kHz to 20 MHz): 97 fs for 6 GHz output
Fractional-N synthesizer and integer-N synthesizer
Pin compatible to the ADF4355
High resolution, 52-bit modulus
Phase frequency detector (PFD) operation to 125 MHz
Reference input frequency operation to 600 MHz
Maintains frequency lock over −40°C to +85°C
Low phase noise, voltage controlled oscillator (VCO)
Programmable divide by 1, 2, 4, 8, 16, 32, or 64 output
Analog and digital power supplies: 3.3 V
Charge pump and VCO power supplies: 5.0 V typical
Logic compatibility: 1.8 V
Programmable output power level
RF output mute function
Supported in the ADIsimPLL design tool
The ADF4356 allows implementation of fractional-N or integer-N
phase-locked loop (PLL) frequency synthesizers when used with
an external loop filter and an external reference frequency. A series
of frequency dividers at another frequency output permits
operation from 53.125 MHz to 6800 MHz.
The ADF4356 has an integrated VCO with a fundamental
output frequency ranging from 3400 MHz to 6800 MHz. In
addition, the VCO frequency is connected to divide by 1, 2, 4, 8,
16, 32, or 64 circuits that allow the user to generate RF output
frequencies as low as 53.125 MHz. For applications that require
isolation, the RF output stage can be muted. The mute function
is both pin- and software-controllable.
Control of all on-chip registers is through a simple 3-wire interface.
The ADF4356 operates with analog and digital power supplies
ranging from 3.15 V to 3.45 V, with charge pump and VCO
supplies from 4.75 V to 5.25 V. The ADF4356 also contains
hardware and software power-down modes.
APPLICATIONS
Wireless infrastructure (LTE, W-CDMA, TD-SCDMA,
WiMAX, GSM, PCS, DCS)
Point to point/point to multipoint microwave links
Satellites/VSATs
Test equipment/instrumentation
Clock generation
FUNCTIONAL BLOCK DIAGRAM
CE
REFINB
CLK
DATA
LE
10-BIT R
COUNTER
×2
DOUBLER
DVDD
VVCO
VP
VRF
MULTIPLEXER
÷2
DIVIDER
MUXOUT
LOCK
DETECT
CREG1
CREG2
DATA REGISTER
FUNCTION
LATCH
CHARGE
PUMP
CPOUT
PHASE
COMPARATOR
INTEGER
VALUE
FRACTION
VALUE
VTUNE
VREF
VBIAS
VCO
CORE
MODULUS
VALUE
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
VREGVCO
MULTIPLEXER
N COUNTER
MULTIPLEXER
AGND
OUTPUT
STAGE
÷1/2/4/8/16/
32/64
SDGND
CPGND
AGNDRF
RFOUTA–
PDBRF
OUTPUT
STAGE
ADF4356
AGNDVCO
RFOUTA+
RFOUTB+
RFOUTB–
15084-001
REFINA
AVDD
DVDD
Figure 1.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2016–2017 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
ADF4356
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Register 4 ..................................................................................... 21
Applications ....................................................................................... 1
Register 5 ..................................................................................... 22
General Description ......................................................................... 1
Register 6 ..................................................................................... 23
Functional Block Diagram .............................................................. 1
Register 7 ..................................................................................... 25
Revision History ............................................................................... 2
Register 8 ..................................................................................... 26
Specifications..................................................................................... 3
Register 9 ..................................................................................... 26
Timing Characteristics ................................................................ 5
Register 10 ................................................................................... 27
Absolute Maximum Ratings ............................................................ 6
Register 11 ................................................................................... 28
Transistor Count ........................................................................... 6
Register 12 ................................................................................... 28
ESD Caution .................................................................................. 6
Register 13 ................................................................................... 29
Pin Configuration and Function Descriptions ............................. 7
Register Initialization Sequence ............................................... 29
Typical Performance Characteristics ............................................. 9
Frequency Update Sequence ..................................................... 30
Theory of Operation ...................................................................... 12
RF Synthesizer—A Worked Example ...................................... 30
Reference Input Section ............................................................. 12
Reference Doubler and Reference Divider ............................. 31
RF N Divider ............................................................................... 12
Spurious Optimization and Fast Lock ..................................... 31
Phase Frequency Detector (PFD) and Charge Pump ............ 13
Optimizing Jitter ......................................................................... 31
MUXOUT and Lock Detect ...................................................... 13
Spur Mechanisms ....................................................................... 31
Input Shift Registers ................................................................... 13
Lock Time.................................................................................... 31
Program Modes .......................................................................... 14
Applications Information .............................................................. 33
VCO.............................................................................................. 14
Power Supplies ............................................................................ 33
Output Stage ................................................................................ 14
Register Maps .................................................................................. 16
Printed Circuit Board (PCB) Design Guidelines for a ChipScale Package .............................................................................. 33
Register 0 ..................................................................................... 18
Output Matching ........................................................................ 34
Register 1 ..................................................................................... 19
Outline Dimensions ....................................................................... 35
Register 2 ..................................................................................... 19
Ordering Guide .......................................................................... 35
Register 3 ..................................................................................... 20
REVISION HISTORY
6/2017—Rev. 0 to Rev. A
Changes to Frequency Update Sequence Section ...................... 30
10/2016—Revision 0—Initial Version
Rev. A | Page 2 of 35
Data Sheet
ADF4356
SPECIFICATIONS
AVDD = DVDD = VRF = 3.3 V ± 5%, 4.75 V ≤ VP = VVCO ≤ 5.25 V, AGND = CPGND = AGNDVCO = SDGND = AGNDRF = 0 V, RSET = 5.1 kΩ, dBm referred
to 50 Ω, TA = TMIN to TMAX, unless otherwise noted.
Table 1.
Parameter
REFINA/REFINB CHARACTERISTICS
Input Frequency Range
Symbol
Min
Typ
Max
Unit
For f < 10 MHz, ensure slew rate >
21 V/µs
Single-Ended Mode
Differential Mode
Input Sensitivity
Single-Ended Mode
10
10
250
600
MHz
MHz
0.4
AVDD
V p-p
Differential Mode
0.4
1.8
V p-p
±100
±250
125
pF
pF
µA
µA
MHz
Input Capacitance
Single-Ended Mode
Differential Mode
Input Current
Phase Frequency Detector
CHARGE PUMP (CP)
CP Current, Sink/Source
High Value
Low Value
RSET Range
Current Matching
ICP vs. VCP
ICP vs. Temperature
LOGIC INPUTS
Input Voltage
High
Low
Input Current
Input Capacitance
LOGIC OUTPUTS
Output High Voltage
Output High Current
Output Low Voltage
POWER SUPPLIES
Analog Power
Digital Power and RF Supply Voltage
CP and VCO Supply Voltage
CP Supply Power Current
DIDD + AIDD3
Output Dividers
Supply Current
Test Conditions/Comments
6.9
1.4
ICP
VINH
VINL
IINH/IINL
CIN
1.5
VOH
DVDD − 0.4
1.5
mA
mA
kΩ
%
%
%
DVDD
0.6
±1
3.0
3.15
4.75
3.3
AVDD
5.0
8
82
6 to
36
70
500
0.4
3.45
V
5.25
9
92
V
Rev. A | Page 3 of 35
90
Fixed
0.5 V ≤ VCP1 ≤ VP − 0.5 V
0.5 V ≤ VCP1 ≤ VP − 0.5 V
VCP1 = 2.5 V
V
V
µA
pF
V
V
µA
V
1.8
IOH
VOL
IVCO
Single-ended reference programmed
Differential reference programmed
RSET = 5.1 kΩ, this resistor is internal
in the ADF4356
4.8
0.3
5.1
3
3
1.5
AVDD
DVDD, VRF
VP, VVCO
IP
REFINA biased at AVDD/2; ac coupling
ensures AVDD/2 bias
LVDS and LVPECL compatible,
REFINA/ REFINB biased at 2.1 V; ac
coupling ensures 2.1 V bias
mA
mA
mA
1.8 V output selected
IOL2 = 500 µA
See Table 7 and Table 8
Voltages must equal AVDD
VP must equal VVCO
Each output divide by 2 consumes
6 mA
ADF4356
Parameter
RFOUTA+/RFOUTA−Supply Current
Data Sheet
Typ
Max
Unit
22
33
44
55
27
38
49
60
mA
mA
mA
mA
Test Conditions/Comments
RF Output A enabled/RF Output B
disabled
−4 dBm setting
−1 dBm setting
2 dBm setting
5 dBm setting
56
74
91
108
mA
mA
mA
mA
mA
mA
RF Output A enabled/RF Output B
enabled
−4 dBm setting
−1 dBm setting
2 dBm setting
5 dBm setting
Hardware power-down selected
Software power-down selected
6800
6800
25
12
0.5
MHz
MHz
MHz/V
MHz/V
MHz
−26
−29
−32
−14
7
−2
dBc
dBc
dBc
dBc
dBm
dBm
Power Variation
Power Variation over Frequency
RF Output B Power4
±1
±5
4
−2
dB
dB
dBm
dBm
Power Variation
Power Variation over Frequency
Level of Signal with RF Output Disabled
±1
±5
−53
−20
dB
RFOUTA+/RFOUTA− Plus RFOUTB+/RFOUTB−
Supply Current
Symbol
IRFOUTx±
Min
IRFOUTx±
48
65
82
99
5
20
Low Power Sleep Mode
RF OUTPUT CHARACTERISTICS
VCO Frequency Range
RF Output Frequency
VCO Sensitivity
Frequency Pushing (Open-Loop)
Frequency Pulling (Open-Loop)
Harmonic Content
Second
Third
RF Output A Power4
3400
53.125
KV
dBm
dBm
NOISE CHARACTERISTICS
Fundamental VCO Phase Noise
Performance
Fundamental VCO range
Voltage standing wave ratio (VSWR) =
2:1 RFOUTA+/RFOUTA−
Fundamental VCO output (RFOUTA+)
Divided VCO output (RFOUTA+)
Fundamental VCO output (RFOUTA+)
Divided VCO output (RFOUTA+)
RFOUTA+ = 1 GHz; 7.4 nH inductor to VRF
RFOUTA+ = 6.8 GHz; 7.4 nH inductor
to VRF
RFOUTA+ = 5 GHz
RFOUTA+ = 1 GHz to 6.8 GHz
RFOUTB+ = 1 GHz; 7.4 nH inductor to VRF
RFOUTB+ = 6.8 GHz; 7.4 nH inductor
to VRF
RFOUTB+ = 5 GHz
RFOUTB+ = 1 GHz to 6.8 GHz
RFOUTA+ = 1 GHz
RFOUTA+= 6.8 GHz
VCO noise in open-loop conditions
−115
−135
−137
−155
−113
−133
−135
−153
−110
−130
−132
−150
Rev. A | Page 4 of 35
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
100 kHz offset from 3.4 GHz carrier
800 kHz offset from 3.4 GHz carrier
1 MHz offset from 3.4 GHz carrier
10 MHz offset from 3.4 GHz carrier
100 kHz offset from 5.0 GHz carrier
800 kHz offset from 5.0 GHz carrier
1 MHz offset from 5.0 GHz carrier
10 MHz offset from 5.0 GHz carrier
100 kHz offset from 6.8 GHz carrier
800 kHz offset from 6.8 GHz carrier
1 MHz offset from 6.8 GHz carrier
10 MHz offset from 6.8 GHz carrier
Data Sheet
ADF4356
Parameter
Normalized In-Band Phase Noise Floor
Fractional Channel5
Integer Channel6
Normalized 1/f Noise, PN1_f7
Integrated RMS Jitter (1 kHz to 20 MHz)8
Spurious Signals Due to PFD Frequency
Symbol
Min
Typ
Max
−225
−227
−121
97
−85
Unit
Test Conditions/Comments
dBc/Hz
dBc/Hz
dBc/Hz
fs
dBc
10 kHz offset; normalized to 1 GHz
VCP is the voltage at the CPOUT pin.
IOL is the output low current.
TA = 25°C; AVDD = DVDD = VRF = 3.3 V; VVCO = VP = 5.0 V; prescaler = 4/5; fREFIN = 122.88 MHz; fPFD = 61.44 MHz; and fRF = 1650 MHz.
4
RF output power using the EV-ADF4356SD1Z evaluation board is measured into a spectrum analyzer. Unused RF output pins are terminated in 50 Ω.
5
Use this value to calculate the phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output, use the following formula:
−225 + 10log(fPFD) + 20logN. The value given is the lowest noise mode for the fractional channel.
6
Use this value to calculate the phase noise for any application. To calculate in-band phase noise performance as seen at the VCO output, use the following formula:
−227 + 10log(fPFD) + 20logN. The value given is the lowest noise mode for the integer channel.
7
The PLL phase noise is composed of 1/f (flicker) noise plus the normalized PLL noise floor. The formula for calculating the 1/f noise contribution at an RF frequency (fRF)
and at a frequency offset (f) is given by PN = P1_f + 10log(10 kHz/f) + 20log(fRF/1 GHz). Both the normalized phase noise floor and flicker noise are modeled in the
ADIsimPLL design tool.
8
Integrated RMS jitter using the EV-ADF4356SD1Z evaluation board is measured into a spectrum analyzer. The EV-ADF4356SD1Z evaluation board is configured to
accept a single ended REFIN (SMA 100) = 160 MHz, VCO frequency = 6 GHz, PFD frequency = 80 MHz, charge pump current = 0.9 mA, and bleed current is off. The loop
filter is configured for an 80 kHz loop filter bandwidth. Unused RF output pins are terminated in 50 Ω.
1
2
3
TIMING CHARACTERISTICS
AVDD = DVDD =VRF = 3.3 V ± 5%, 4.75 V ≤ VP = VVCO ≤ 5.25 V, AGND = CPGND = AGNDVCO = SDGND = AGNDRF = 0 V, RSET = 5.1 kΩ, dBm referred
to 50 Ω, TA = TMIN to TMAX, unless otherwise noted.
Table 2. Write Timing
Parameter
fCLK
t1
t2
t3
t4
t5
t6
t7
Limit
50
10
5
5
10
10
10
20 or (2/fPFD),
whichever is longer
Unit
MHz max
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Description
Serial peripheral interface CLK frequency
LE setup time
DATA to CLK setup time
DATA to CLK hold time
CLK high duration
CLK low duration
CLK to LE setup time
LE pulse width
Write Timing Diagram
t4
t5
CLK
t3
t2
DATA
DB31 (MSB)
DB30
DB3
(CONTROL BIT C4)
DB2
(CONTROL BIT C3)
DB1
(CONTROL BIT C2)
DB0 (LSB)
(CONTROL BIT C1)
t7
t1
t6
Figure 2. Write Timing Diagram
Rev. A | Page 5 of 35
15084-002
LE
ADF4356
Data Sheet
ABSOLUTE MAXIMUM RATINGS
The ADF4356 is a high performance RF integrated circuit with
an ESD rating of 2 kV and is ESD sensitive. Take proper
precautions for handling and assembly.
TA = 25°C, unless otherwise noted.
Table 3.
Parameter
VRF, DVDD, AVDD to GND1
AVDD to DVDD
VP, VVCO to GND1
CPOUT to GND1
Digital Input/Output Voltage to GND1
Analog Input/Output Voltage to GND1
REFINA, REFINB to GND1
REFINA to REFINB
Operating Temperature Range
Storage Temperature Range
Maximum Junction Temperature
Reflow Soldering
Peak Temperature
Time at Peak Temperature
Electrostatic Discharge (ESD)
Charged Device Model
Human Body Model
1
Rating
−0.3 V to +3.6 V
−0.3 V to +0.3 V
−0.3 V to +5.8 V
−0.3 V to VP + 0.3 V
−0.3 V to DVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
−0.3 V to AVDD + 0.3 V
±2.1 V
−40°C to +85°C
−65°C to +125°C
150°C
THERMAL RESISTANCE
Thermal performance is directly linked to printed circuit board
(PCB) design and operating environment. Careful attention to
PCB thermal design is required.
Table 4. Thermal Resistance
Package Type
CP-32-121
1
θJA
27.3
Unit
°C/W
Test Condition 1: thermal impedance simulated values are based on use of a
PCB with the thermal impedance paddle soldered to GND1.
TRANSISTOR COUNT
260°C
40 sec
The transistor count for the ADF4356 is 134,486 (CMOS) and
3874 (bipolar).
1000 V
2000 V
ESD CAUTION
GND = AGND = SDGND = AGNDRF = AGNDVCO = CPGND = 0 V.
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
Rev. A | Page 6 of 35
Data Sheet
ADF4356
32
31
30
29
28
27
26
25
CREG 2
SDGND
MUXOUT
REFINA
REFINB
DVDD
PDBRF
CREG 1
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
ADF4356
TOP VIEW
(Not to Scale)
24
23
22
21
20
19
18
17
VBIAS
VREF
NIC
AGNDVCO
VTUNE
VREGVCO
AGNDVDO
VVCO
NOTES
1. NIC = NOT INTERNALLY CONNECTED.
2. THE EXPOSED PAD MUST BE CONNECTED TO AGND.
15084-003
AGND
VRF
RFOUTA+
RFOUTA–
AGNDRF
RFOUTB+
RFOUTB–
AVDD
9
10
11
12
13
14
15
16
CLK
DATA
LE
CE
AVDD
VP
CPOUT
CPGND
Figure 3. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
1
Mnemonic
CLK
2
DATA
3
LE
4
CE
5, 16
AVDD
6
VP
7
CPOUT
8
9
10
CPGND
AGND
VRF
11
RFOUTA+
12
RFOUTA−
13
14
AGNDRF
RFOUTB+
15
RFOUTB−
17
VVCO
18, 21
19
AGNDVCO
VREGVCO
Description
Serial Clock Input. Data is clocked into the 32-bit shift register on the CLK rising edge. This input is a high
impedance CMOS input.
Serial Data Input. The serial data is loaded most significant bit (MSB) first with the four LSBs as the control bits.
This input is a high impedance CMOS input.
Load Enable, CMOS Input. When LE goes high, the data stored in the shift register is loaded into the register
that is selected by the four LSBs.
Chip Enable. A logic low on this pin powers down the device and puts the charge pump into three-state mode.
A logic high on this pin powers up the device, depending on the status of the power-down bits.
Analog Power Supplies. These pins range from 3.15 V to 3.45 V. Connect decoupling capacitors to the analog
ground plane as close to these pins as possible. AVDD must have the same value as DVDD.
Charge Pump Power Supply. VP must have the same value as VVCO. Connect decoupling capacitors to the
ground plane as close to this pin as possible.
Charge Pump Output. When enabled, this output provides ±ICP to the external loop filter. The output of the
loop filter is connected to VTUNE to drive the internal VCO.
Charge Pump Ground. This output is the ground return pin for CPOUT.
Analog Ground. This pin is the ground return pin for AVDD.
Power Supply for the RF Output. Connect decoupling capacitors to the analog ground plane as close to this
pin as possible. VRF must have the same value as AVDD.
VCO Output. The output level is programmable. The VCO fundamental output or a divided down version is
available.
Complementary VCO Output. The output level is programmable. The VCO fundamental output or a divided
down version is available.
RF Output Stage Ground. This pin is the ground return pin for the RF output stage.
Auxiliary VCO Output. The output level is programmable. The VCO fundamental output or a divided down
version is available.
Complementary Auxiliary VCO Output. The output level is programmable. The VCO fundamental output or a
divided down version is available.
Power Supply for the VCO. The voltage on this pin ranges from 4.75 V to 5.25 V. Place decoupling capacitors to
the analog ground plane as close to this pin as possible.
VCO Ground. This pin is the ground return path for the VCO.
VCO Compensation Node. Connect decoupling capacitors to the ground plane as close to this pin as possible.
Connect VREGVCO directly to VVCO.
Rev. A | Page 7 of 35
ADF4356
Pin No.
20
Mnemonic
VTUNE
22
NIC
23
VREF
24
25, 32
VBIAS
CREG1, CREG2
26
PDBRF
27
DVDD
28
29
30
REFINB
REFINA
MUXOUT
31
SDGND
EP
Data Sheet
Description
Control Input to the VCO. This voltage determines the output frequency and is derived from filtering the CPOUT
output voltage. The capacitance at this pin (VTUNE input capacitance) is 9 pF.
No Internal Connection. For existing designs that currently use the ADF4355, to upgrade to the ADF4356, the
RSET resistor can be left connected to this pin.
Internal Compensation Node. DC biased at half the tuning range. Connect decoupling capacitors to the
ground plane as close to this pin as possible.
Reference Voltage. Connect a 100 nF decoupling capacitor to the ground plane as close to this pin as possible.
Outputs from the LDO Regulator. CREG1 and CREG2 are the supply voltages to the digital circuits. Nominal
voltage of 1.8 V. Decoupling capacitors of 100 nF connected to AGND are required for these pins.
RF Power-Down. A logic low on this pin mutes the RF outputs. This mute function is also software-controllable.
Do not leave this pin floating.
Digital Power Supply. This pin must be at the same voltage as AVDD. Place decoupling capacitors to the ground
plane as close to this pin as possible.
Complementary Reference Input. If unused, ac couple this pin to AGND.
Reference Input.
Multiplexer Output. The multiplexer output allows the digital lock detect, the analog lock detect, scaled RF, or
the scaled reference frequency to be externally accessible.
Digital Σ-Δ Modulator Ground. SDGND is the ground return path for the Σ-Δ modulator.
Exposed Pad. The exposed pad must be connected to AGND.
Rev. A | Page 8 of 35
Data Sheet
ADF4356
TYPICAL PERFORMANCE CHARACTERISTICS
–50
–80
DIV1
DIV2
DIV4
DIV8
DIV16
DIV32
DIV64
–90
–70
PHASE NOISE (dBc/Hz)
PHASE NOISE (dBc/Hz)
–100
–90
–110
–130
–110
–120
–130
–140
–150
–150
1k
10k
100k
1M
10M
100M
FREQUENCY OFFSET FROM CARRIER (Hz)
–70
–70
PHASE NOISE (dBc/Hz)
–50
–90
–110
–130
–150
10M
100M
DIV1
DIV2
DIV4
DIV8
DIV16
DIV32
DIV64
–90
–110
–130
100k
1M
10M
100M
–170
1k
10k
100k
1M
10M
100M
FREQUENCY (Hz)
15084-008
10k
15084-005
1k
Figure 8. Closed-Loop Phase Noise, RFOUTB+ (100 nH Inductors),
Fundamental VCO and Dividers, VCO = 5.0 GHz, PFD = 61.44 MHz, Loop
Bandwidth = 40 kHz
Figure 5. Open-Loop VCO Phase Noise, 5.0 GHz
–50
–70
–70
PHASE NOISE (dBc/Hz)
–50
–90
–110
–130
–150
DIV1
DIV2
DIV4
DIV8
DIV16
DIV32
DIV64
–90
–110
–130
1k
10k
100k
1M
10M
FREQUENCY OFFSET FROM CARRIER (Hz)
Figure 6. Open-Loop VCO Phase Noise, 6.8 GHz
100M
–170
1k
10k
100k
1M
FREQUENCY (Hz)
10M
100M
15084-009
–150
15084-006
PHASE NOISE (dBc/Hz)
1M
–150
FREQUENCY OFFSET FROM CARRIER (Hz)
–170
100k
FREQUENCY (Hz)
–50
–170
10k
Figure 7. Closed-Loop Phase Noise, RFOUTB+ (100 nH Inductors),
Fundamental VCO and Dividers, VCO = 3.4 GHz, PFD = 61.44 MHz, Loop
Bandwidth = 40 kHz
Figure 4. Open-Loop VCO Phase Noise, 3.4 GHz
PHASE NOISE (dBc/Hz)
–170
1k
15084-004
–170
15084-007
–160
Figure 9. Closed-Loop Phase Noise, RFOUTB+ (100 nH Inductors),
Fundamental VCO and Dividers, VCO = 6.8 GHz, PFD = 61.44 MHz, Loop
Bandwidth = 40 kHz
Rev. A | Page 9 of 35
ADF4356
Data Sheet
10
10
+85°C
+25°C
–40°C
8
5
6
LEVEL (dBm)
2
0
–2
–4
–15
–20
RFOUTA+
RFOUTA–
RFOUTB+
RFOUTB–
–30
–8
3000
4000
5000
6000
7000
–35
15084-010
2000
TARGET FREQUENCY (MHz)
0
1000
2000
3000
4000
5000
6000
7000
FREQUENCY (MHz)
Figure 13. RFOUTA+/RFOUTA− Power vs. RFOUTB+/RFOUTB− Power (7.4 nH
Inductors, 10 pF AC Coupling Capacitors, Board Measurement)
Figure 10. Output Power vs. Frequency, RFOUTA+/RFOUTA− (7.4 nH
Inductors, 10 pF AC Coupling Capacitors, Board Measurement)
250
10
SECOND HARMONIC
THIRD HARMONIC
FOURTH HARMONIC
FIFTH HARMONIC
1kHz TO 20MHz
12kHz TO 20MHz
200
RMS JITTER/NOISE (fs)
0
LEVEL OF HARMONIC (dBm)
–10
–25
–6
–10
1000
–5
15084-013
OUTPUT POWER (dBm)
0
4
–10
–20
–30
–40
150
100
50
3000
4000
5000
6000
7000
TARGET FREQUENCY (MHz)
0
0
4
–50
WORST CASE PFD/REF SPUR (dBc)
–40
LEVEL (dBm)
2
0
–2
–4
–6
2000
3000
4000
FREQUENCY (MHz)
5000
6000
7000
4000
5000
6000
7000
PFD = 122.88MHz
PFD = 61.44MHz
PFD = 30.72MHz
–60
–70
–80
–90
–100
–110
15084-012
1000
3000
Figure 14. RMS Jitter/Noise vs. Output Frequency,
PFD Frequency = 61.44 MHz, Loop Filter = 40 kHz
6
0
2000
OUTPUT FREQUENCY (MHz)
Figure 11. RFOUTA+/RFOUTA− Harmonics vs. Frequency (7.4 nH Inductors,
10 pF AC Coupling Capacitors, Board Measurement)
–8
1000
0
1000
2000
3000
4000
5000
TARGET FREQUENCY (MHz)
Figure 12. RFOUTB+/RFOUTB− Power vs. Frequency (100 nH Inductors, 10 pF
AC Coupling Capacitors, Board Measurement)
6000
7000
15084-015
2000
15084-011
–60
1000
15084-014
–50
Figure 15. PFD Spur Amplitude vs. RFOUTA+/RFOUTA− Output Frequency,
PFD = 30.72 MHz, PFD = 61.44 MHz, PFD = 122.88 MHz, Loop Filter = 40 kHz
Rev. A | Page 10 of 35
Data Sheet
ADF4356
–60
–60
NOISE AND SPUR POWER (dBc/Hz)
NOISE AND SPUR POWER (dBc/Hz)
–70
–80
–100
–120
–140
–160
–80
–90
–100
–110
–120
–130
–140
10k
100k
1M
10M
100M
FREQUENCY (Hz)
–160
1k
15084-016
–180
1k
Figure 16. Fractional-N Spur Performance, GSM1800 Band, RFOUTA+ =
1550.2 MHz, REFIN = 122.88 MHz, PFD = 61.44 MHz, Output Divide by 4
Selected, Loop Filter Bandwidth = 40 kHz, Channel Spacing = 20 kHz
10k
100k
1M
15084-018
–150
10M
FREQUENCY (Hz)
Figure 18. Fractional-N Spur Performance, RFOUTA+ = 2.591 GHz,
REFIN = 122.88 MHz, PFD = 61.44 MHz, Output Divide by 2 Selected,
Loop Filter Bandwidth = 40 kHz, Channel Spacing = 20 kHz
–60
4650
4550
FREQUENCY (MHz)
NOISE AND SPUR POWER (dBc/Hz)
4600
–80
–100
–120
–140
4500
4450
1
4400
4350
4300
4250
–160
100k
1M
FREQUENCY (Hz)
10M
100M
4150
–1
15084-017
10k
Figure 17. Fractional-N Spur Performance, W-CDMA Band, RFOUTA+ =
2113.5 MHz, REFIN = 122.88 MHz, PFD = 61.44 MHz, Output Divide by 2
Selected, Loop Filter Bandwidth = 40 kHz, Channel Spacing = 20 kHz
0
1
2
TIME (ms)
3
4
15084-019
4200
–180
1k
Figure 19. Lock Time for 250 MHz Jump from 4150 MHz to 4400 MHz,
Loop Bandwidth = 23 kHz
Rev. A | Page 11 of 35
ADF4356
Data Sheet
THEORY OF OPERATION
REFERENCE INPUT SECTION
INT, FRACx, MODx, and R Counter Relationship
Figure 20 shows the reference input stage. The reference input
can accept both single-ended and differential signals. Use the
reference mode bit (Register 4, Bit DB9) to select the signal. To
use a differential signal on the reference input, program this bit
high. In this case, SW1 and SW2 are open, SW3 and SW4 are
closed, and the current source that drives the differential pair of
transistors switches on. The differential signal buffers and provides
an emitter-coupled logic (ECL) to the CMOS converter. When a
single-ended signal is used as the reference, program Bit DB9
in Register 4 to 0. Connect the single-ended reference signal to
REFINA. In this case, SW1 and SW2 are closed, SW3 and SW4
are open, and the current source that drives the differential pair
of transistors switches off.
The INT, FRAC1, FRAC2, MOD1, and MOD2 values, in
conjunction with the R counter, make it possible to generate
output frequencies spaced by fractions of the PFD frequency
(fPFD). For more information, see the RF Synthesizer—A Worked
Example section.
REFERENCE
INPUT MODE
85kΩ
SW2
BUFFER
SW1
SW3
MULTIPLEXER
TO
R COUNTER
AVDD
ECL TO CMOS
BUFFER
REFINA
REFINB
2.5kΩ
2.5kΩ
15084-020
SW4
BIAS
GENERATOR
Figure 20. Reference Input Stage, Differential Mode
RF N DIVIDER
The RF N divider allows a division ratio in the PLL feedback
path. Determine the division ratio by the INT, FRAC1, FRAC2,
and MOD2 values that this divider comprises.
RF N COUNTER
FRAC1 +
N = INT +
MOD2
MOD1
TO PFD
N COUNTER
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
INT
REG
FRAC1
REG
FRAC2
VALUE
MOD2
VALUE
15084-021
FROM
VCO OUTPUT/
OUTPUT DIVIDERS
FRAC2
Calculate the RF VCO frequency (VCOOUT) by
(1)
VCOOUT = fPFD × N
where:
VCOOUT is the output frequency of the VCO (without using the
output divider).
fPFD is the frequency of the phase frequency detector.
N is the desired value of the feedback counter, N.
Calculate fPFD by
(2)
fPFD = REFIN × ((1 + D)/(R × (1 + T)))
where:
REFIN is the reference input frequency.
D is the REFIN doubler bit.
R is the preset divide ratio of the binary 10-bit programmable
reference counter (1 to 1023).
T is the REFIN divide by 2 bit (0 or 1).
N comprises
FRAC2
FRAC1
MOD2
N INT
(3)
MOD1
where:
INT is the 16-bit integer value (23 to 32,767 for the 4/5
prescaler, and 75 to 65,535 for the 8/9 prescaler).
FRAC1 is the numerator of the primary modulus (0 to 16,777,215).
FRAC2 is the numerator of the 28-bit auxiliary modulus
(0 to 268,435,455).
MOD2 is the programmable, 28-bit auxiliary fractional
modulus (2 to 268,435,455).
MOD1 is a 24-bit primary modulus with a fixed value of 224 =
16,777,216.
Equation 3 results in a very fine frequency resolution with no
residual frequency error. To apply this formula, take the
following steps:
1. Calculate N by dividing VCOOUT/fPFD.
2. The integer value of this number forms INT.
3. Subtract the INT value from the full N value.
4. Multiply the remainder by 224.
5. The integer value of this number forms FRAC1.
6. Calculate MOD2 based on the channel spacing (fCHSP) by
(4)
MOD2 = fPFD/GCD(fPFD, fCHSP)
Figure 21. RF N Divider
7.
Rev. A | Page 12 of 35
where:
GCD(fPFD, fCHSP) is the greatest common divider of the PFD
frequency and the channel spacing frequency.
fCHSP is the desired channel spacing frequency.
Calculate FRAC2 by the following equation:
FRAC2 = ((N − INT) × 224 − FRAC1)) × MOD2
(5)
Data Sheet
ADF4356
The FRAC2 and MOD2 fraction results in outputs with zero
frequency error for channel spacings when
MUXOUT AND LOCK DETECT
fPFD/GCD(fPFD/fCHSP) < 268,435,455
(6)
where:
fPFD is the frequency of the phase frequency detector.
GCD is a greatest common denominator function.
fCHSP is the desired channel spacing frequency.
The output multiplexer on the ADF4356 allows the user to access
various internal points on the chip. The M3, M2, and M1 bits in
Register 4 control the state of MUXOUT. Figure 23 shows the
MUXOUT section in block diagram form.
DVDD
If zero frequency error is not required, the MOD1 and MOD2
denominators operate together to create a 52-bit resolution
modulus.
THREE-STATE OUTPUT
DVDD
SDGND
R DIVIDER OUTPUT
INT N Mode
N DIVIDER OUTPUT
When FRAC1 and FRAC2 are 0, the synthesizer operates in
integer-N mode.
CONTROL
MUXOUT
ANALOG LOCK DETECT
DIGITAL LOCK DETECT
The 10-bit R counter allows the input reference frequency
(REFIN) to be divided down to produce the reference clock to
the PFD. Division ratios from 1 to 1023 are allowed.
The PFD takes inputs from the R counter and N counter and
produces an output proportional to the phase and frequency
difference between them. Figure 22 is a simplified schematic of
the phase frequency detector. The PFD includes a fixed delay
element that sets the width of the antibacklash pulse. This pulse
ensures that there is no dead zone in the PFD transfer function
and provides a consistent reference spur level. Set the phase
detector polarity to positive on this device because of the
positive tuning of the VCO.
Q1
Figure 23. MUXOUT Schematic
INPUT SHIFT REGISTERS
PHASE FREQUENCY DETECTOR (PFD) AND
CHARGE PUMP
D1
SDGND
15084-023
RESERVED
R Counter
HIGH
MUX
UP
The ADF4356 digital section includes a 10-bit R counter, a
16-bit RF integer-N counter, a 24-bit FRAC1 counter, a 28-bit
auxiliary fractional counter, and a 28-bit auxiliary modulus
counter. Data clocks into the 32-bit shift register on each rising
edge of CLK. The data clocks in MSB first. Data transfers from
the shift register to one of 13 latches on the rising edge of LE.
The state of the four control bits (C4, C3, C2, and C1) in the
shift register determines the destination latch. As shown in
Figure 2, the four least significant bits (LSBs) are DB3, DB2,
DB1, and DB0. The truth table for these bits is shown in Table 6.
Figure 26 and Figure 27 summarize the programming of the
latches.
U1
Table 6. Truth Table for the C4, C3, C2, and C1 Control Bits
CLR1
DELAY
HIGH
U3
CHARGE
PUMP
CP
CLR2
DOWN
D2
Q2
U2
–IN
Figure 22. PFD Simplified Schematic
15084-022
+IN
C4
0
0
0
0
0
0
0
0
1
1
1
1
1
1
Rev. A | Page 13 of 35
Control Bits
C3
C2
0
0
0
0
0
1
0
1
1
0
1
0
1
1
1
1
0
0
0
0
0
1
0
1
1
0
1
0
C1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Register
Register 0
Register 1
Register 2
Register 3
Register 4
Register 5
Register 6
Register 7
Register 8
Register 9
Register 10
Register 11
Register 12
Register 13
ADF4356
Data Sheet
PROGRAM MODES
50
The following settings in the ADF4356 are double-buffered: main
fractional value (FRAC1), auxiliary modulus value (MOD2),
auxiliary fractional value (FRAC2), reference doubler, reference
divide by 2 (RDIV2), R counter value, and charge pump current
setting. Two events must occur before the ADF4356 uses a new
value for any of the double-buffered settings. First, the new value
must latch into the device by writing to the appropriate register,
and second, a new write to Register 0 must be performed.
VCO
The VCO core in the ADF4356 consists of four separate VCOs,
each of which uses 256 overlapping bands, which allows the
device to cover a wide frequency range without large VCO
sensitivity (KV) and without resulting poor phase noise and
spurious performance.
The correct VCO and band are chosen automatically by the
VCO and band select logic when Register 0 is updated and autocalibration is enabled.
The R counter output is used as the clock for the band select logic.
After band selection, normal PLL action resumes. The nominal
value of KV is 25 MHz/V when the N divider is driven from the
VCO output, or the KV value is divided by D. D is the output
divider value if the N divider is driven from the RF output divider
(chosen by programming Bits[DB23:DB21] in Register 6).
The VCO shows variation of KV as the tuning voltage, VTUNE,
varies within the band and from band to band. For wideband
applications covering a wide frequency range (and changing
output dividers), a value of 25 MHz/V provides the most accurate
KV, because this value is closest to the average value. Figure 24
shows how KV varies with fundamental VCO frequency along with
an average value for the frequency band. Users may prefer this
figure when using narrow-band designs.
LINEAR
TREND LINE
30
20
10
0
3.4
3.8
4.2
4.6
5.0
5.4
5.8
6.2
6.6
FREQUENCY (GHz)
Figure 24. VCO Sensitivity, KV vs. Frequency
OUTPUT STAGE
The RFOUTA+ and RFOUTA− pins of the ADF4356 connect to
the collectors of an NPN differential pair driven by buffered
outputs of the VCO, as shown in Figure 25. In this scheme,
the ADF4356 contains internal 50 Ω resistors connected to
the VRF pin. To optimize the power dissipation vs. the output
power requirements, the tail current of the differential pair is
programmable using Bits[DB2:DB1] in Register 6. Four current
levels can be set. These levels give approximate output power
levels of −4 dBm, −1 dBm, +2 dBm, and +5 dBm, respectively.
Levels of −4 dBm, −1 dBm, and +2 dBm can be achieved using
a 50 Ω resistor to VRF and ac coupling into a 50 Ω load. For
accurate power levels, refer to the Typical Performance
Characteristics section. An output power of 5 dBm requires an
external shunt inductor to provide higher power levels; however,
this addition results in less wideband performance using the
internal bias only. Terminate the unused complementary output
with a similar circuit to the used output.
VRF
50Ω
RFOUTA+
VCO
VRF
50Ω
RFOUTA–
BUFFER/
DIVIDE BY
1/2/4/8/
16/32/64
15084-025
For example, to ensure that the modulus value loads correctly,
every time that the modulus value updates, Register 0 must be
written to. The RF divider select in Register 6 is also double
buffered, but only if DB14 of Register 4 is high.
AVERAGE
VCO SENSITIVITY
40
15084-024
VCO SENSITIVITY, KV (MHz/V)
Table 6 and Figure 28 through Figure 41 show how the program
modes must be set up for the ADF4356.
Figure 25. Output Stage
Another feature of the ADF4356 is that the supply current to
the RFOUTA+/RFOUTA− output stage can shut down until the
ADF4356 achieves lock as measured by the digital lock detect
circuitry. The mute till lock detect (MTLD) bit (Bit DB11) in
Register 6 enables this function.
The RFOUTB+/RFOUTB− pins are duplicate outputs that can be
used independently or in addition to the RFOUTA+/RFOUTA− pins.
Rev. A | Page 14 of 35
Data Sheet
ADF4356
Table 7. Total IDD (RF Output A Enabled/RF Output B Disabled) 1
Divide By
5 V Supply (IVCO and IP)
3.3 V Supply (AIDD, DIDD, and IRF)
1
2
4
8
16
32
64
1
RFOUTA± Off
78 mA
RFOUTA± = −4 dBm
78 mA
RFOUTA± = −1 dBm
78 mA
RFOUTA± = 2 dBm
78 mA
RFOUTA± = 5 dBm
78 mA
84.8
94.1
103.9
111.9
116.9
120.9
123.3
106.2
114.9
124.9
132.9
138.0
142.0
144.4
117.3
125.7
136.2
144.3
149.5
153.6
156.0
128.2
136.4
147.3
155.6
160.7
164.8
167.3
138.9
146.5
158.0
166.8
171.8
176.1
178.4
RFOUTA± refers to RFOUTA+/RFOUTA−.
Table 8. Total IDD (RF Output A Enabled/RF Output B Enabled) 1
Divide By
5 V Supply (IVCO and IP)
3.3 V Supply (AIDD, DIDD, and IRF)
1
2
4
8
16
32
64
1
RFOUTA±/RFOUTB± Off
78 mA
RFOUTA±/RFOUTB± =
−4 dBm
78 mA
RFOUTA±/RFOUTB± =
−1 dBm
78 mA
RFOUTA±/RFOUTB± =
2 dBm
78 mA
RFOUTA±/RFOUTB± =
5 dBm
78 mA
84.9
94.2
104.0
112.0
117.0
121.0
123.4
133.5
142.4
151.9
159.7
164.5
168.4
170.8
150.0
159.8
169.5
177.3
182.2
186.1
188.6
166.3
177.2
187.0
194.7
199.5
203.5
205.8
182.1
193.6
204.0
211.6
216.5
220.4
222.8
RFOUTA± refers to RFOUTA+/RFOUTA− and RFOUTB± refers to RFOUTB+/RFOUTB−.
Rev. A | Page 15 of 35
ADF4356
Data Sheet
REGISTER MAPS
AUTOCAL
PRESCALER
REGISTER 0
RESERVED
CONTROL
BITS
16-BIT INTEGER VALUE (INT)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
0
0
0
0
0
0
0
0
0
0
AC1
N16
PR1
N15
N14
N13
N12
N11
N10
N9
N8
DB8
DB7
DB6
DB5
DB4
N5
N4
N3
N2
N1
N6
N7
DB3
DB2
DB1
DB0
C4(0) C3(0) C2(0) C1(0)
REGISTER 1
RESERVED
CONTROL
BITS
DBR 1
24-BIT MAIN FRACTIONAL VALUE (FRAC1)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12
0
0
0
0
F24
F23
F22
F21
F20
F19
F18
F16
F17
F14
F15
F13
F12
F11
F10
DB8 DB7
DB11 DB10 DB9
F9
F8
F7
F6
F5
F4
DB6 DB5
F3
F2
DB4 DB3
F1
DB2
DB1
DB0
C4(0) C3(0) C2(0) C1(1)
REGISTER 2
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
F14
F13
F10
F11
F12
F9
F8
F7
F6
F5
CONTROL
BITS
14-BIT AUXILIARY MODULUS MSB VALUE (MOD2_LSB)
14-BIT AUXILIARY FRACTIONAL LSB VALUE (FRAC2_LSB)
F4
F3
M14
F1
F2
M13
M12
M11
M10
M9
M7
M8
M6
DB8
DB7
DB6
DB5
M5
M4
M3
M2
DB4 DB3
DB2
DB1
DB0
M1 C4(0) C3(0) C2(1) C1(0)
PHASE
ADJUST
PHASE
RESYNC
SD LOAD
RESET
RESERVED
REGISTER 3
CONTROL
BITS
DBR 1
24-BIT PHASE VALUE (PHASE)
SD1
PR1
PA1
P24
P23
P22
P21
P20
P19
P18
P16
P17
P14
P15
P13
P12
P11
P10
P9
P7
P8
P5
P6
P4
P3
DB2
DB1
DB0
P2
P1
C4(0) C3(0) C2(1) C1(1)
COUNTER
RESET
0
CP THREESTATE
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
CONTROL
BITS
DBR 1
POWER-DOWN
MUX LOGIC
CURRENT
SETTING
PD
POLARITY
DBR 1
10-BIT R COUNTER
REF MODE
DBR1
DOUBLE BUFF
MUXOUT
RDIV2
RESERVED
REFERENCE
DOUBLER DBR 1
REGISTER 4
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3
0
0
M3
M2
M1
RD2
RD1
R10
R9
R8
R7
R6
R4
R5
R3
R1
R2
D1
CP4
CP3
CP2
CP1
U5
U6
U4
U3
U2
U1
DB2
DB1
DB0
C4(0) C3(1) C2(0) C1(0)
REGISTER 5
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
DB9
DB8
DB7
DB6
DB5
0
0
0
0
1
0
DB4 DB3
0
DB2
DB1
DB0
C4(0) C3(1) C2(0) C1(1)
BP1
1DBR
2DBB
BL10
BL9
1
0
1
D14
D13
D12
D11
D10
BL8
BL7
BL6
BL5
BL4
BL3
BL2
BL1
0
D8
= DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.
= DOUBLE BUFFERED BITS—BUFFERED BY A WRITE TO REGISTER 0 WHEN BIT DB14 OF REGISTER 4 IS HIGH.
Figure 26.
Rev. A | Page 16 of 35
0
D6
RF
OUTPUT A
POWER
CONTROL
BITS
DB8 DB7 DB6 DB5 DB4 DB3
D5
D4
D3
D2
D1
DB2
DB1
DB0
C4(0) C3(1) C2(1) C1(0)
15084-026
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
RF
OUTPUT B
POWER
RF OUTPUT A
ENABLE
RF OUTPUT B
ENABLE
RESERVED
CHARGE PUMP BLEED CURRENT
MTLD
RF
DIVIDER SELECT 2
RESERVED
RESERVED
FEEDBACK
SELECT
RF OUTPUT B
SELECT
NEGATIVE
BLEED
GATED
BLEED
BLEED
POLARITY
REGISTER 6
Data Sheet
ADF4356
LD MODE
LD
CYCLE
COUNT
RESERVED
FRAC-N LD
PRECISION
LOL MODE
LE SYNC
RESERVED
RESERVED
LE SEL
SYNC EDGE
REGISTER 7
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4
0
0
0
0
LE2
1
LE1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LD4
LD5
0
LOL LD3
CONTROL
BITS
DB3
DB2
DB1
DB0
LD2 LD1 C4(0) C3(1) C2(1) C1(1)
REGISTER 8
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
0
0
1
0
1
0
0
1
1
0
1
1
0
0
0
1
1
0
1
0
1
0
DB7 DB6
0
1
1
DB5 DB4
1
0
DB3
DB2
DB1
DB0
C4(1) C3(0) C2(0) C1(0)
REGISTER 9
VCO BAND DIVISION
AUTOMATIC
LEVEL CALIBRATION
TIMEOUT
TIMEOUT
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14
VC8
VC7
VC6
VC5
VC4
VC3
VC2
VC1
TL10
TL9
TL8
TL7
TL6
TL5
TL4
TL3
TL2
DB13 DB12 DB11 DB10
TL1
AL5
AL4
AL3
CONTROL
BITS
SYNTHESIZER
LOCK TIMEOUT
DB9
DB8 DB7 DB6 DB5 DB4
AL1
SL5
AL2
SL4
SL3
SL2
DB3
DB2
DB1
DB0
SL1 C4(1) C3(0) C2(0) C1(1)
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
ADC ENABLE
ADC
CLOCK DIVIDER
RESERVED
0
ADC
CONVERSION
REGISTER 10
CONTROL
BITS
DB13 DB12 DB11 DB10
DB9
DB8 DB7 DB6 DB5 DB4
AD8
AD4
AD3 AD2 AD1 AE2 AE1 C4(1) C3(0) C2(1) C1(0)
AD7
AD6
AD5
DB3
DB2
DB1
DB0
VCO BAND HOLD
REGISTER 11
RESERVED
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
0
0
0
0
0
0
VH
0
1
1
0
0
0
0
1
0
0
1
0
0
0
0
DB7 DB6
0
0
DB5 DB4
0
0
0
DB3
DB2
DB1
DB0
C4(1) C3(0) C2(1) C1(1)
REGISTER 12
PHASE RESYNC CLOCK VALUE
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
P20
P19
P18
P17
P16
P15
P14
P13
P12
P11
P10
P9
P8
CONTROL
BITS
RESERVED
P7
P6
P5
P4
P3
P2
P1
0
0
DB9
DB8
DB7
DB6
DB5
DB4
0
0
0
0
0
1
DB3
DB2
DB1
DB0
C4(1) C3(1) C2(0) C1(0)
REGISTER 13
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
F14
F13
F12
F11
F10
F9
F8
F7
F6
F5
F4
CONTROL
BITS
14-BIT AUXILIARY MODULUS MSB VALUE (MOD2_MSB) DBR 1
F3
F2
F1
M14
M13
M12
M11
M10
M9
M8
M7
Figure 27. Register Summary (Register 7 to Register 13)
Rev. A | Page 17 of 35
M6
DB8
DB7
DB6
DB5
M5
M4
M3
M2
DB4 DB3
DB2
DB1
DB0
M1 C4(1) C3(1) C2(0) C1(1)
15084-027
14-BIT AUXILIARY FRACTIONAL MSB VALUE (FRAC2_MSB) DBR 1
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
0
0
0
0
0
0
0
0
0
0
AC1
PR1
N16
PR1
PRESCALER
0
1
CONTROL
BITS
16-BIT INTEGER VALUE (INT)
N15
N14
4/5
8/9
AC1
VCO
AUTOCAL
0
1
DISABLED
DISABLED
N13
N12
N11
N10
N9
N8
DB8
DB7
DB6
DB5
DB4
N7
N6
N5
N4
N3
N2
N1
N16
N15
....
N5
N4
N3
N2
N1
0
0
0
.
0
0
0
.
1
1
1
0
0
0
.
0
0
0
.
1
1
1
....
....
....
....
....
....
....
....
....
....
....
0
0
0
.
1
1
1
.
1
1
1
0
0
0
.
0
0
1
.
1
1
1
0
0
0
.
1
1
0
.
1
1
1
0
0
1
.
1
1
0
.
0
1
1
0
1
0
.
0
1
0
.
1
0
1
DB3
DB2
DB1
DB0
C4(0) C3(0) C2(0) C1(0)
INTEGER VALUE (INT)
NOT ALLOWED
NOT ALLOWED
NOT ALLOWED
....
NOT ALLOWED
23
24
....
65533
65534
65535
INTMIN = 75 WITH PRESCALER = 8/9
15084-028
RESERVED
PRESCALER
Data Sheet
AUTOCAL
ADF4356
Figure 28. Register 0
REGISTER 0
Prescaler Value
Control Bits
The dual modulus prescaler (P/P + 1), along with the INT,
FRACx, and MODx counters, determines the overall division
ratio from the VCO output to the PFD input. The PR1 bit
(Bit DB20) in Register 0 sets the prescaler value.
With Bits[C4:C1] set to 0000, Register 0 is programmed. Figure 28
shows the input data format for programming this register.
Reserved
Bits[DB31:DB22] are reserved and must be set to 0.
Automatic Calibration (AUTOCAL)
Write to Register 0 to enact (by default) the VCO automatic
calibration, and to choose the appropriate VCO and VCO subband.
Write 1 to the AC1 bit (Bit DB21) to enable the automatic
calibration, which is the recommended mode of operation.
Set the AC1 bit (Bit DB21) to 0 to disable the automatic calibration,
which leaves the ADF4356 in the same band it was already in
when Register 0 is updated.
Disable the automatic calibration only for fixed frequency
applications, phase adjust applications, or very small ( (50 µs × fPFD)/Timeout
Synthesizer Lock Timeout
SL5 to SL1 (Bits[DB8:DB4]) set the synthesizer lock timeout
value. This value allows the VTUNE force to settle on the VTUNE pin.
The value must be 20 µs. Calculate the value using the following
equation:
Synthesizer Lock Timeout > (20 µs × fPFD)/Timeout
Rev. A | Page 26 of 35
ADF4356
ADC
CLOCK DIVIDER
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
0
0
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
AD8
AD8
AD7
AD6
AD5
AD4
DB7 DB6
AD3 AD2
AD7
..........
AD2
0
0
..........
0
1
1
0
0
..........
1
0
2
.
.
..........
.
.
.
.
.
..........
.
.
.
.
.
..........
.
.
.
1
1
..........
0
0
252
1
1
..........
0
1
253
1
1
..........
1
0
254
1
1
..........
1
1
255
DB5 DB4
AD1
CONTROL
BITS
DB3
DB2
DB1
DB0
AE2 AE1 C4(1) C3(0) C2(1) C1(0)
AE1
ADC
0
DISABLED
1
ENABLED
AE2
ADC CONVERSION
0
DISABLED
1
ENABLED
AD1 ADC CLK DIV
15084-038
RESERVED
ADC ENABLE
ADC
CONVERSION
Data Sheet
Figure 38. Register 10
REGISTER 10
For example, for fPFD = 61.44 MHz, set ALC_CLK_DIV = 154
so that the ADC clock frequency is 99.417 kHz.
Control Bits
With Bits[C4:C1] set to 1010, Register 10 is programmed.
Figure 38 shows the input data format for programming this
register.
Reserved
Bits[DB31:DB14] are reserved. Bits[DB23:DB22] must be set to
11, and all other bits in this range must be set to 0.
ADC Clock Divider (ADC_CLK_DIV)
An on-board analog-to-digital converter (ADC) determines the
VTUNE setpoint relative to the ambient temperature of the
ADF4356 environment. The ADC ensures that the initial tuning
voltage in any application is chosen correctly to avoid any
temperature drift issues.
If ADC_CLK_DIV is greater than 255, set it to 255.
ADC Conversion Enable
AE2 (Bit DB5) ensures that the ADC performs a conversion
when a write to Register 10 is performed. It is recommended to
enable this mode.
ADC Enable
AE1 (Bit DB4), when set to 1, powers up the ADC for the
temperature dependent VTUNE calibration. It is recommended to
always use this function.
The ADC uses a clock that is equal to the output of the R
counter (or the PFD frequency) divided by ADC_CLK_DIV.
AD8 to AD1 (Bits[DB13:DB6]) set the value of this divider. On
power-up, the R counter is not programmed; however, in these
power-up cases, it defaults to R = 1.
Choose the value such that
ADC_CLK_DIV = ceiling(((fPFD/100,000) − 2)/4)
where ceiling() is a function that rounds up to the nearest
integer.
Rev. A | Page 27 of 35
Data Sheet
VCO BAND HOLD
ADF4356
RESERVED
CONTROL
BITS
RESERVED
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8
0
0
0
0
VH
0
0
0
1
0
0
1
0
0
0
1
0
1
0
0
0
0
DB7 DB6
0
0
DB5 DB4
0
0
0
DB3
DB2
DB1
DB0
C4(1) C3(0) C2(1) C1(1)
VCO BAND HOLD
VH
0
1
15084-039
0
NORMAL OPERATION
VCO BAND HOLD
Figure 39. Register 11
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
P19
P18
P17
P16
P15
P14
P13
P12
P11
P10
P9
P8
P6
P7
P20
P19
...
P5
P4
P3
P2
P1
RESYNC CLOCK
0
0
...
0
0
0
0
0
NOT ALLOWED
0
0
...
0
0
0
0
1
1
0
0
...
0
0
0
1
0
2
.
.
...
.
.
.
.
.
...
0
0
...
1
0
1
1
0
22
0
0
...
1
0
1
1
1
23
0
0
...
1
1
0
0
0
24
.
.
...
.
.
.
.
.
...
1
1
...
1
1
1
0
1
65533
1
1
...
1
1
1
1
0
65534
1
1
...
1
1
1
1
1
1048575
P5
P4
P3
P2
P1
0
1
DB9
DB8
DB7
DB6
DB5
DB4
0
1
1
1
1
1
DB3
DB2
DB1
DB0
C4(1) C3(1) C2(0) C1(0)
15084-040
P20
CONTROL
BITS
RESERVED
PHASE RESYNC CLOCK VALUE
Figure 40. Register 12
REGISTER 11
REGISTER 12
Control Bits
Control Bits
With Bits[C4:C1] set to 1011, Register 11 is programmed. Figure 39
shows the input data format for programming this register.
With Bits[C4:C1] set to 1100, Register 12 is programmed. Figure 40
shows the input data format for programming this register.
Reserved
Phase Resync Clock Value
Bits[DB31:DB25] are reserved and must be set to 0. Bit DB22,
Bit DB21, Bit DB16, and Bit DB13 must be set to 1, and all other
bits in this range (Bits[DB23:DB4]) must be set to 0.
P20 to P1 (Bits[DB31:DB12]) set the timeout counter for
activation of phase resync. This value must be set such that
a resync happens immediately after (and not before) the PLL
has achieved lock after reprogramming.
VCO Band Hold
VH (Bit DB24), when set to 1, prevents a reset of the VCO core,
band, and bias during a counter reset. VCO band hold is
required for applications that use external PLLs.
Calculate the timeout value using the following equation:
Time Out Value = Phase Resync Clock Value/fPFD
When not using phase resync, set these bits to 1 for normal
operation.
Reserved
Bits [DB11:DB4] are reserved. Bit DB10 and Bits[DB8:DB4]
must be set to 1, and all other bits in this range must be set to 0.
Rev. A | Page 28 of 35
Data Sheet
ADF4356
DB31 DB30 DB29 DB28 DB27 DB26 DB25 DB24 DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10 DB9
F14
1DBR
F13
F12
F11
F10
F9
F8
F7
F6
F5
F4
CONTROL
BITS
14-BIT AUXILIARY MODULUS MSB VALUE (MOD2_MSB) DBR
F3
F2
M14
F1
M13
M12
M11
M10
M9
M8
M7
M6
DB8
DB7
DB6
DB5
DB4
M5
M4
M3
M2
M1
F14
F13
..........
F2
F1
FRAC2_MSB WORD
M14
M13
..........
M2
M1
MOD2_MSB VALUE
0
0
..........
0
0
0
0
0
..........
0
0
0
0
0
..........
0
1
1
0
0
..........
0
1
1
0
0
..........
1
0
2
0
0
..........
1
0
2
0
0
..........
1
1
3
0
0
..........
1
1
3
.
.
..........
.
.
.
.
.
..........
.
.
.
.
.
..........
.
.
.
.
.
..........
.
.
.
.
.
..........
.
.
.
.
.
..........
.
.
.
1
1
..........
0
0
16381
1
1
..........
0
0
16380
1
1
..........
0
1
16382
1
1
..........
0
1
16381
1
1
..........
1
0
16382
1
1
..........
1
0
16382
1
1
.........
1
1
16383
1
1
.........
1
1
16383
DB3
DB2
DB1
DB0
C4(1) C3(1) C2(0) C1(1)
= DOUBLE BUFFERED REGISTER—BUFFERED BY THE WRITE TO REGISTER 0.
15084-041
14-BIT AUXILIARY FRACTIONAL MSB VALUE (FRAC2_LSB) DBR
Figure 41. Register 13
REGISTER 13
Control Bits
With [C4:C1] set to 1101, Register 13 is programmed. Figure 41
shows the input data format for programming this register.
14-Bit Auxiliary Fractional MSB Value (FRAC2_MSB)
This value is used with the auxiliary fractional LSB value
(Register 2, Bits[DB31:DB18]) to generate the total auxiliary
fractional FRAC2 value.
For fPFD > 75 MHz (initially lock with halved fPFD), use the
following sequence:
FRAC2 = (FRAC2_MSB × 214) + FRAC2_LSB
These bits can be set to all zeros to ensure software
compatibility with the ADF4355.
14-Bit Auxiliary Modulus MSB Value (MOD2_MSB)
This value is used with the auxiliary fractional MSB value
(Register 2, Bits[DB17:DB4]) to generate the total auxiliary
modulus MOD2 value.
MOD2 = (MOD2_MSB × 214) + MOD2_LSB
REGISTER INITIALIZATION SEQUENCE
At initial power-up, after the correct application of voltages to
the supply pins, the ADF4356 registers must be programmed in
sequence. For f ≤ 75 MHz, use the following sequence:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
Register 13.
Register 12.
Register 11.
Register 10.
Register 9.
Register 8.
Register 7.
Register 6.
Register 5.
Register 4.
Register 3.
12. Register 2.
13. Register 1.
14. Ensure that >16 ADC_CLK cycles have elapsed between
the write of Register 10 and Register 0. For example, if
ADC_CLK = 99.417 kHz, wait 16/99,417 sec = 161 μs. See
the Register 10 section for more information.
15. Register 0.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
19.
20.
21.
Rev. A | Page 29 of 35
Register 13 (for halved fPFD).
Register 12.
Register 11.
Register 10.
Register 4 (with the R divider doubled to halve fPFD).
Register 9.
Register 8.
Register 7.
Register 6 (for the desired fPFD).
Register 5.
Register 4 (with the R divider doubled to halve fPFD).
Register 3.
Register 2 (for halved fPFD).
Register 1 (for halved fPFD).
Ensure that >16 ADC_CLK cycles have elapsed between
the write of Register 10 and Register 0. For example, if
ADC_CLK = 99.417 kHz, wait 16/99,417 sec = 161 μs. See the
Register 10 section for more information.
Register 0 (for halved fPFD; autocalibration enabled).
Register 13 (for the desired fPFD).
Register 4 (with the R divider set for the desired fPFD).
Register 2 (for the desired fPFD).
Register 1 (for the desired fPFD).
Register 0 (for the desired fPFD; autocalibration disabled).
ADF4356
Data Sheet
FREQUENCY UPDATE SEQUENCE
fPFD = REFIN × ((1 + D)/(R × (1 + T)))
1.
2.
3.
4.
5.
6.
Register 13.
Register 10.
Register 2.
Register 1.
Ensure that >16 ADC_CLK cycles have elapsed between
the write of Register 10 and Register 0. For example, if
ADC_CLK = 99.417 kHz, wait 16/99,417 sec = 161 μs. See the
Register 10 section for more information.
Register 0.
For fPFD > 75 MHz (initially lock with halved fPFD), the sequence
must be as follows:
1.
2.
3.
4.
5.
6.
Register 13 (for halved fPFD).
Register 10.
Register 4 (With the R divider doubled to halved fPFD).
Register 2 (for halved fPFD).
Register 1 (for halved fPFD).
Ensure that >16 ADC_CLK cycles have elapsed between
the write of Register 10 and Register 0. For example, if
ADC_CLK = 99.417 kHz, wait 16/99,417 sec = 161 μs. See the
Register 10 section for more information.
7. Register 0 (for halved fPFD; autocalibration enabled).
8. Register 13 (for the desired fPFD).
9. Register 4 (With the R divider set for the desired fPFD).
10. Register 2 (for the desired fPFD).
11. Register 1 (for the desired fPFD).
12. Register 0 (for desired fPFD; autocalibration disabled).
where:
REFIN is the reference frequency input.
D is the REFIN doubler bit.
R is the REFIN reference division factor.
T is the reference divide by 2 bit (0 or 1).
For example, in a universal mobile telecommunication system
(UMTS) where a 2112.8 MHz RF frequency output (RFOUT) is
required, a 122.88 MHz reference frequency input (REFIN)
is available. Note that the ADF4356 VCO operates in the
frequency range of 3400 MHz to 6800 MHz. Therefore, the RF
divider of 2 must be used (VCO frequency = 4225.6 MHz,
RFOUT = VCO frequency/RF divider = 4225.6 MHz/2 =
2112.8 MHz).
The feedback path is also important. In this example, the VCO
output is fed back before the output divider (see Figure 42). In
this example, the 122.88 MHz reference signal is divided by 2 to
generate fPFD of 61.44 MHz. The desired channel spacing is
200 kHz.
fPFD
The worked example is as follows:
N = VCOOUT/fPFD = 4225.6 MHz/61.44 MHz =
68.7760416666666667
INT = int(VCO frequency/fPFD) = 68
FRAC = 0.7760416666666667
MOD1 = 16,777,216
FRAC1 = int(MOD1 × FRAC) = 13,019,818
Remainder = 0.6666666667 or 2/3
MOD2 = fPFD/GCD(fPFD, fCHSP) =
61.44 MHz/GCD(61.44 MHz, 200 kHz) = 1536
Use the following equations to program the ADF4356 synthesizer:
RFOUT = INT +
RFOUT
Figure 42. Loop Closed Before Output Divider
RF SYNTHESIZER—A WORKED EXAMPLE
FRAC2
MOD2 × ( f )/ RF Divider
PFD
MOD1
÷2
N
DIVIDER
The frequency change occurs on the write to Register 0.
FRAC1 +
VCO
PFD
15084-042
Frequency updates require updating the auxiliary modulator
(MOD2) in Register 2, the fractional value (FRAC1) in Register 1,
and the integer value (INT) in Register 0. It is recommended to
perform a temperature dependent VTUNE calibration by updating
Register 10 first. Therefore, for fPFD ≤ 75 MHz, the sequence
must be as follows:
(8)
FRAC2 = Remainder × 1536 = 1024
(7)
where:
RFOUT is the RF output frequency.
INT is the integer division factor.
FRAC1 is the fractionality.
FRAC2 is the auxiliary fractionality (FRAC2 = (FRAC2_MSB ×
214) + FRAC2_LSB).
MOD2 is the auxiliary modulus (MOD2 = (MOD2_MSB × 214) +
MOD2_LSB).
MOD1 is the fixed 24-bit modulus.
RF Divider is the output divider that divides down the VCO
frequency.
From Equation 8,
fPFD = (122.88 MHz × (1 + 0)/2) = 61.44 MHz
2112.8 MHz = 61.44 MHz × ((INT + (FRAC1 +
FRAC2/MOD2)/224))/2
where:
INT = 68
FRAC1 = 13,019,818
FRAC2 = 1024
MOD2 = 1536
RF Divider = 2
Rev. A | Page 30 of 35
(9)
(10)
Data Sheet
ADF4356
REFERENCE DOUBLER AND REFERENCE DIVIDER
Lock Time—A Worked Example
The on-chip reference doubler allows the input reference signal
to be doubled. The doubler is useful for increasing the PFD
comparison frequency. To improve the noise performance of
the system, increase the PFD frequency. Doubling the PFD
frequency typically improves noise performance by 3 dB.
Assume that fPFD = 61.44 MHz,
The reference divide by 2 divides the reference signal by 2,
resulting in a 50% duty cycle PFD frequency.
VCO Band Div = ceiling(fPFD/1,600,000) = 39
where ceiling() is a function that rounds up to the nearest
integer.
By combining
ALC Wait > (50 µs × fPFD)/Timeout
Synthesizer Lock Timeout > (20 µs × fPFD)/Timeout
SPURIOUS OPTIMIZATION AND FAST LOCK
Narrow loop bandwidths can filter unwanted spurious signals;
however, these bandwidths typically have a long lock time. A
wider loop bandwidth achieves faster lock times but may lead
to increased spurious signals inside the loop bandwidth.
OPTIMIZING JITTER
For lowest jitter applications, use the highest possible PFD
frequency to minimize the contribution of in-band noise from
the PLL. Set the PLL filter bandwidth such that the in-band noise
of the PLL intersects with the open-loop noise of the VCO,
minimizing the contribution of both to the overall noise.
It is found that
ALC Wait = 2.5 × Synthesizer Lock Timeout
The ALC wait and synthesizer lock timeout values must be set
to fulfill this equation. Both values are 5 bits wide; therefore, the
maximum value for either is 31. There are several suitable values.
The following values meet the criteria:
ALC Wait = 30
Synthesizer Lock Timeout = 12
Finally, ALC wait > (50 µs × fPFD)/Timeout, is rearranged for
Use the ADIsimPLL design tool for this task.
Timeout = ceiling((fPFD × 50 µs)/ALC Wait)
SPUR MECHANISMS
Timeout = ceiling((61.44 MHz × 50 µs)/30) = 103
This section describes the two different spur mechanisms that
arise with a fractional-N synthesizer and how to minimize them
in the ADF4356.
Integer Boundary Spurs
One mechanism for fractional spur creation is the interactions
between the RF VCO frequency and the reference frequency.
When these frequencies are not integer related (the purpose of a
fractional-N synthesizer), spur sidebands appear on the VCO
output spectrum at an offset frequency that corresponds to the
beat note or the difference in frequency between an integer
multiple of the reference and the VCO frequency. These spurs
are attenuated by the loop filter and are more noticeable on
channels close to integer multiples of the reference where the
difference frequency can be inside the loop bandwidth (thus
the name, integer boundary spurs).
Reference Spurs
Reference spurs are generally not a problem in fractional-N
synthesizers because the reference offset is far outside the loop
bandwidth. However, any reference feedthrough mechanism
that bypasses the loop can cause a problem. Feedthrough of low
levels of on-chip reference switching noise, through the
prescaler back to the VCO, can result in reference spur levels
as high as −85 dBc.
LOCK TIME
The PLL lock time divides into a number of settings. All of
these settings are modeled in the ADIsimPLL design tool.
Synthesizer Lock Timeout
The synthesizer lock timeout ensures that the VCO calibration
DAC, which forces VTUNE, has settled to a steady value for the
band select circuitry.
The timeout and synthesizer lock timeout variables programmed
in Register 9 select the length of time the DAC is allowed to
settle to the final voltage, before the VCO calibration process
continues to the next phase, which is VCO band selection. The
PFD frequency is the clock for this logic, and the duration is set by
Timeout × Synthesizer Lock Timeout
f PFD
The calculated time must be equal to or greater than 20 µs.
VCO Band Selection
Use the PFD frequency again as the clock for the band selection
process. Calculate this value by
fPFD/(VCO Band Selection × 16) < 100 kHz
The band selection takes 11 cycles of the previously calculated
value. Calculate the duration by
11 × (VCO Band Selection × 16)/fPFD
Automatic Level Calibration Timeout
Use the automatic level calibration (ALC) function to choose
the correct bias current in the ADF4356 VCO core. Calculate
the time taken by
30 × ALC Wait × Timeout/fPFD
Much faster lock times than those detailed in this data sheet
are possible; contact Analog Devices for more information.
Rev. A | Page 31 of 35
ADF4356
Data Sheet
PLL Low-Pass Filter Settling Time
The time taken for the loop to settle is inversely proportional to
the low-pass filter bandwidth. The settling time is also modeled
in the ADIsimPLL design tool.
The total lock time for changing frequencies is the sum of the
four separate times (synthesizer lock, VCO band selection, ALC
timeout, and PLL settling time) and is all modeled in the
ADIsimPLL design tool.
Rev. A | Page 32 of 35
Data Sheet
ADF4356
APPLICATIONS INFORMATION
POWER SUPPLIES
On the PCB, there must be a minimum clearance of 0.25 mm
between the thermal pad and the inner edges of the pad pattern.
This clearance ensures the avoidance of shorting.
The ADF4356 contains four multiband VCOs that cover an
octave range of frequencies. To ensure the best performance, it is
vital to connect a low noise regulator, such as the ADM7150 or
the ADM7170 to the VVCO pin. Connect the same regulator to
package pins VVCO, VREGVCO, and VP.
To improve the thermal performance of the package, use thermal
vias on the PCB thermal pad. If vias are used, incorporate them
into the thermal pad at the 1.2 mm pitch grid. The via diameter
must be between 0.3 mm and 0.33 mm, and the via barrel must
be plated with 1 oz. of copper to plug the via.
For the 3.3 V supply pins, use two ADM7170 regulators, one for
the DVDD and AVDD supplies and one for VRF. Figure 43 shows
the recommended connections.
For a microwave PLL and VCO synthesizer, such as the ADF4356,
take care with the board stack-up and layout. Do not consider
using FR4 material because it is too lossy above 3 GHz. Instead,
Rogers 4350, Rogers 4003, or Rogers 3003 dielectric material is
suitable.
PRINTED CIRCUIT BOARD (PCB) DESIGN
GUIDELINES FOR A CHIP-SCALE PACKAGE
The lands on the 32-lead, lead frame chip scale package are
rectangular. The PCB pad for these lands must be 0.1 mm
longer than the package land length and 0.05 mm wider than
the package land width. Center each land on the pad to
maximize the solder joint size.
Take care with the RF output traces to minimize discontinuities
and ensure the best signal integrity. Via placement and grounding
are critical.
The bottom of the chip scale package has a central exposed
thermal pad. The thermal pad on the PCB must be at least as
large as the exposed pad.
VIN = 6.0V
VRF = 3.3V
VOUT
VIN
ADM7150
EN
OFF
100nF
REF
BYP
CBYP
1µF
COUT
1µF
VREG
CREG
10µF
100nF
REF_SENSE
LOCK DETECT
GND
VIN = 6.0V
VOUT = 3.3V
VOUT
VIN
CIN
1µF
ADM7150
ON
EN
OFF
CREG
10µF
VOUT
ADM7150
EN
VREG
7.5nH
7.5nH
1nF
COUT
1µF
REF OUTA+ 11
3 LE
ADF4356
1nF
REF OUTA– 12
VTUNE 20
430Ω
CPOUT 7
22 NIC
1µF
33nF
CPGND SDGND AGND
8
31
9
AGNDRF
19
13 18 21
23
6800pF
68Ω
VREGVCO VREF VBIAS
24
REF
BYP
CREG
10µF
VRF
1 CLK
VOUT = 5.0V
CBYP
1µF
1nF
2 DATA
VIN = 6.0V
OFF
REF OUTB– 15
28 REF INB
1nF
GND
ON
REF OUTB+ 14
100Ω
REF_SENSE
VIN
6
27
5
16
4
26
10
32
25
30
17
VVCO VP DVDD AVDD AVDD CE PDB RF VRF CREG 1 CREG 2 MUXOUT
29 REF INA
FREF IN
COUT
1µF
REF
VREG
CIN
1µF
1nF
FREF IN
BYP
CBYP
1µF
1nF
REF_SENSE
GND
10pF
Figure 43. Power Supplies
Rev. A | Page 33 of 35
0.1µF 10pF
0.1µF 10pF
0.1µF
15084-043
ON
SPI-COMPATIBLE SERIAL BUS
CIN
1µF
ADF4356
Data Sheet
OUTPUT MATCHING
The low frequency output can simply be ac-coupled to the next
circuit, if desired; however, if a higher output power is required,
use a pull-up inductor to increase the output power level.
VRF
7.5nH
100pF
50Ω
15084-044
RFOUTA+
For lower frequencies below 2 GHz, it is recommended to use a
100 nH inductor on the RFOUTA+/RFOUTA− pins and a 100 pF
ac coupling capacitor.
The RFOUTA+/RFOUTA− pins are a differential circuit. Provide
each output with the same (or similar) components where
possible, such as the same shunt inductor value, bypass
capacitor, and termination.
The RFOUTB+/RFOUTB− outputs can be treated the same as the
RFOUTA+/RFOUTA− outputs. If unused, leave both
RFOUTB+/RFOUTB− pins open.
Figure 44. Optimum Output Stage
When differential outputs are not required, terminate the
unused output or combine it with both outputs using a balun.
Rev. A | Page 34 of 35
Data Sheet
ADF4356
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
0.30
0.25
0.18
1
0.50
BSC
3.75
3.60 SQ
3.55
EXPOSED
PAD
17
TOP VIEW
0.80
0.75
0.70
TOP VIEW
PKG-004570
SEATING
PLANE
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
32
25
24
0.50
0.40
0.30
8
16
9
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.20 REF
0.25 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD-5.
02-22-2017-B
PIN 1
INDICATOR
5.10
5.00 SQ
4.90
Figure 45. 32-Lead Lead Frame Chip Scale Package [LFCSP]
5 mm × 5 mm Body and 0.75 mm Package Height
(CP-32-12)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADF4356BCPZ
ADF4356BCPZ-RL7
EV-ADF4356SD1Z
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
Package Description
32-Lead Lead Frame Chip Scale Package [LFCSP]
32-Lead Lead Frame Chip Scale Package [LFCSP]
Evaluation Board
Z = RoHS Compliant Part.
©2016–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D15084-0-6/17(A)
Rev. A | Page 35 of 35
Package Option
CP-32-12
CP-32-12
工商网监
湘ICP备2023018690号
