ADF7242BCPZ-RL

Low Power IEEE 802.15.4/Proprietary GFSK/FSK Zero-IF 2.4 GHz Transceiver IC ADF7242 FEATURES Frequency range (global ISM band) 2400 MHz to 2483.5 MHz Programmable data rates and modulation IEEE 802.15.4-2006-compatible (250 kbps) GFSK/FSK/GMSK/MSK modulation 50 kbps to 2000 kbps data rates Low power consumption 19 mA (typical) in receive mode 21.5 mA (typical) in transmit mode (PO = 3 dBm) 1.7 μA, 32 kHz crystal oscillator wake-up mode High sensitivity (IEEE 802.15.4-2006) −95 dBm at 250 kbps High sensitivity (0.1% BER) −96 dBm at 62.5 kbps (GFSK) −93 dBm at 500 kbps (GFSK) −90 dBm at 1 Mbps (GFSK) −87.5 dBm at 2 Mbps (GFSK) Programmable output power −20 dBm to +4.8 dBm in 2 dB steps Integrated voltage regulators 1.8 V to 3.6 V input voltage range Excellent receiver selectivity and blocking resilience Zero-IF architecture Complies with EN300 440 Class 2, EN300 328, FCC CFR47 Part 15, ARIB STD-T66 Digital RSSI measurement Fast automatic VCO calibration Automatic RF synthesizer bandwidth optimization On-chip low power processor performs Radio control Packet management Packet management support Insertion/detection of preamble/SWD/CRC/address IEEEE 802.15.4-2006 frame filtering IEEEE 802.15.4-2006 CSMA/CA unslotted modes Flexible 256-byte transmit/receive data buffer IEEEE 802.15.4-2006 and GFSK/FSK SPORT modes Fast settling automatic frequency control Flexible multiple RF port interface External PA/LNA support hardware Switched antenna diversity support Wake-up timer Very few external components Integrated PLL loop filter, receive/transmit switch, battery monitor, temperature sensor, 32 kHz RC and crystal oscillators Flexible SPI control interface with block read/write access Small form factor 5 mm × 5 mm 32-lead LFCSP package APPLICATIONS Wireless sensor networks Automatic meter reading/smart metering Industrial wireless control Healthcare Wireless audio/video Consumer electronics ZigBee FUNCTIONAL BLOCK DIAGRAM ADF7242 DAC LNA1 ADC DSSS DEMOD ADC AGC OCL AFC CDR RADIO CONTROLLER FSK DEMOD 8-BIT PROCESSOR 4kB PROGRAM ROM 2kB PROGRAM RAM 256-BYTE PACKET RAM 64-BYTE BBRAM 256-BYTE MCR PA FRACTIONAL-N RF SYNTHESIZER GAUSSIAN FILTER PRE-EMPHASIS FILTER WAKE-UP CTRL SPI GPIO SPORT IRQ LNA2 DAC PACKET MANAGER LDO × 4 BIAS Figure 1 Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved. 08912-001 BATTERY MONITOR TEMPERATURE SENSOR 26MHz OSC 32kHz RC OSC 32kHz XTAL OSC ADF7242 TABLE OF CONTENTS Features .............................................................................................. 1  Applications....................................................................................... 1  Functional Block Diagram .............................................................. 1  Revision History ............................................................................... 3  General Description ......................................................................... 4  Specifications..................................................................................... 6  General Specifications ................................................................. 6  RF Frequency Synthesizer Specifications.................................. 6  Transmitter Specifications........................................................... 7  Receiver Specifications ................................................................ 8  Auxiliary Specifications ............................................................. 11  Current Consumption Specifications ...................................... 12  Timing and Digital Specifications............................................ 13  Timing Diagrams........................................................................ 15  IEEE 802.15.4 TX SPORT Mode Timing Diagrams.............. 18  GFSK/FSK RX SPORT Mode Timing Diagrams ................... 18  Absolute Maximum Ratings.......................................................... 22  ESD Caution................................................................................ 22  Pin Configuration and Function Descriptions........................... 23  Typical Performance Characteristics ........................................... 25  Terminology .................................................................................... 34  Radio Controller ............................................................................. 35  Sleep Modes................................................................................. 37  RF Frequency Synthesizer ............................................................. 38  RF Frequency Synthesizer Calibration .................................... 38  RF Frequency Synthesizer Bandwidth..................................... 38  RF Channel Frequency Programming..................................... 39  Reference Crystal Oscillator ..................................................... 39  Transmitter ...................................................................................... 40  Transmit Operating Modes ....................................................... 40  Transmitter in IEEE 802.15.4-2006 Mode .............................. 40  IEEE 802.15.4 Automatic RX-To-TX Turnaround Mode..... 43  Transmitter in GFSK/FSK Mode.............................................. 43  Power Amplifier.......................................................................... 46  Receiver............................................................................................ 48  Receive Operating Modes ......................................................... 48  Receiver in IEEE 802.15.4-2006 Mode .................................... 48  Receiver Calibration................................................................... 49  IEEE 802.15.4-2006 Receive Timing and Control ..................... 50  Clear Channel Assessment (CCA)........................................... 51  Link Quality Indication (LQI).................................................. 52  IEEE 802.15.4 Automatic TX-to-RX Turnaround Mode...... 53  IEEE 802.15.4 Frame Filtering, Automatic Acknowledge, and Automatic CSMA/CA................................................................ 53  Receiver in GFSK/FSK Mode ................................................... 56  Receiver Radio Blocks ............................................................... 61  SPORT Interface ............................................................................. 63  GFSK/FSK SPORT Mode.......................................................... 63  IEEE 802.15.4-2006 SPORT Mode........................................... 65  Device Configuration .................................................................... 66  Configuration Values Common to IEEE 802.15.4 and GFSK/FSK Modes ...................................................................... 67  Configuration Values for GFSK/FSK Packet and SPORT Modes........................................................................................... 67  Configuration Values for IEEE 802.15.4-2006 Packet and SPORT Modes............................................................................. 68  RF Port Configurations/Antenna Diversity................................ 69  Auxillary Functions........................................................................ 70  Temperture Sensor ..................................................................... 70  Battery Monitor .......................................................................... 70  Wake-Up Controller (WUC).................................................... 70  Transmit Test Modes.................................................................. 71  Serial Peripheral interface (SPI) ................................................... 72  General Characteristics ............................................................. 72  Command Access....................................................................... 72  Status Word ................................................................................. 72  Memory Map .................................................................................. 74  BBRAM........................................................................................ 74  Modem Configuration RAM (MCR) ...................................... 74  Program ROM ............................................................................ 74  Program RAM ............................................................................ 74  Packet RAM ................................................................................ 74  Memory Access............................................................................... 76  Writing to the ADF7242............................................................ 77  Reading from the ADF7242...................................................... 77  Downloadable Firmware Modules............................................... 80  Interrupt Controller ....................................................................... 81  Rev. 0 | Page 2 of 108 ADF7242 Configuration ..............................................................................81  Description of Interrupt Sources ..............................................82  Applications Circuits ......................................................................83  Register Map ....................................................................................87  Outline Dimensions......................................................................105  Ordering Guide .........................................................................105  REVISION HISTORY 7/10—Revision 0: Initial Version Rev. 0 | Page 3 of 108 ADF7242 GENERAL DESCRIPTION The ADF7242 is a highly integrated, low power, and high performance transceiver for operation in the global 2.4 GHz ISM band. It is designed with emphasis on flexibility, robustness, ease of use, and low current consumption. The IC supports the IEEE 802.15.42006 2.4 GHz PHY requirements as well as proprietary GFSK/ FSK/GMSK/MSK modulation schemes in both packet and data streaming modes. With a minimum number of external components, it achieves compliance with the FCC CFR47 Part 15, ETSI EN 300 440 (Equipment Class 2), ETSI EN 300 328 (FHSS, DR > 250 kbps), and ARIB STD T-66 standards. The ADF7242 complies with the IEEE 802.15.4-2006 2.4 GHz PHY requirements with a fixed data rate of 250 kbps and DSSSOQPSK modulation. With its support of GFSK/FSK/GMSK/MSK modulation schemes, the IC can operate over a wide range of data rates from 50 kbps to 2 Mbps and is, therefore, equally suitable for proprietary applications in the areas of smart metering, industrial control, home and building automation, and consumer electronics. In addition, the agile frequency synthesizer of the ADF7242, together with short turnaround times, facilitates the implementation of FHSS systems. The transmitter path of the ADF7242 is based on a direct closed-loop VCO modulation scheme using a low noise fractional-N RF frequency synthesizer. The automatically calibrated VCO operates at twice the fundamental frequency to reduce spurious emissions and avoid PA pulling effects. The bandwidth of the RF frequency synthesizer is automatically optimized for transmit and receive operations to achieve optimum phase noise, modulation quality, and synthesizer settling time performance. The transmitter output power is programmable from −20 dBm to +4 dBm with automatic PA ramping to meet transient spurious specifications. An integrated biasing and control circuit is available in the IC to significantly simplify the interface to external PAs. The receive path is based on a zero-IF architecture enabling very high blocking resilience and selectivity performance, which are critical performance metrics in interference dominated environments such as the 2.4 GHz band. In addition, the architecture does not suffer from any degradation of blocker rejection in the image channel, which is typically found in low IF receivers. In GFSK/FSK modes, the receiver features a high speed automatic frequency control (AFC) loop, which allows the frequency synthesizer to find and correct any frequency errors in the received packet. The IC can operate with a supply voltage between 1.8 V and 3.6 V with very low power consumption in receive and transmit modes while maintaining its excellent RF performance, making it especially suitable for battery-powered systems. The ADF7242 features a flexible dual-port RF interface that can be used with an external LNA and/or PA in addition to supporting switched antenna diversity. The ADF7242 incorporates a very low power custom 8-bit processor that supports a number of transceiver management functions. These functions are handled by the two main modules of the processor; the radio controller and the packet manager. The radio controller manages the state of the IC in various operating modes and configurations. The host MCU can use single byte commands to interface to the radio controller. The packet manager is highly flexible and supports various packet formats. In transmit mode, the packet manager can be configured to add preamble, sync, and CRC words to the payload data stored in the on-chip packet RAM. In receive mode, the packet manager can detect and generate an interrupt to the MCU upon receiving valid sync or CRC words, and store the received data payload in the packet RAM. A total of 256 bytes of transmit and receive packet RAM space is provided to decouple the over-the-air data rate from the host MCU processing speed. Thus, the ADF7242 packet manager eases the processing burden on the host MCU and saves the overall system power consumption. In addition, for applications that require data streaming, a synchronous bidirectional serial port (SPORT) provides bitlevel input/output data, and has been designed to directly interface to a wide range of DSPs, such as ADSP-21xx, SHARC®, TigerSHARC®, and Blackfin®. The SPORT interface can optionally be used for GFSK/FSK as well as IEEE 802.15.4-2006 modes. The processor also permits the download and execution of a set of firmware modules, which include IEEE 802.15.4 automatic modes, such as node address filtering, as well as unslotted CSMA/CA. Execution code for these firmware modules is available from Analog Devices, Inc. To further optimize the system power consumption, the ADF7242 features an integrated low power 32 kHz RC wake-up oscillator, which is calibrated from the 26 MHz crystal oscillator while the transceiver is active. Alternatively, an integrated 32 kHz crystal oscillator can be used as a wake-up timer for applications requiring very accurate wake-up timing. A battery backed-up RAM (BBRAM) is available on the IC where IEEE 802.15.42006 network node addresses can be retained when the IC is in the sleep state. The ADF7242 also features a very flexible interrupt controller, which provides MAC-level and PHY-level interrupts to the host MCU. The IC is equipped with a SPI interface, which allows burst-mode data transfer for high data throughput efficiency. The IC also integrates a temperature sensor with digital readback and a battery monitor. Rev. 0 | Page 4 of 108 ADF7242 ADF7242 RFIO1P LNA1 RFIO1N RFIO2P LNA2 RFIO2N DAC ADC ADC DSSS DEMOD AGC OCL AFC CDR RADIO CONTROLLER DAC FSK DEMOD 8-BIT PROCESSOR 4kB PROGRAM ROM 2kB PROGRAM RAM 256- BYTE PACKET RAM 64-BYTE BBRAM 256-BYTE MCR PA DIV2 DIVIDER SDM PRE-EMPHASIS FILTER FSK MOD DSSS MOD SPI PABIAOP_ATB4 PAVSUP_ATB3 EXT PA INTERFACE CHARGEPUMP LOOP FILTER PFD GAUSSIAN Tx FILTER CS MOSI SCLK MISO RXEN_GP6 TXEN_GP5 PACKET MANAGER WAKE-UP CTRL EXT LNA/PA ENABLE GPIO PA RAMP BATTERY MONITOR TEMPERATURE SENSOR ANALOG TEST 26MHz OSC TIMER UNIT SPORT RC CAL 32kHz RC OSC 32kHz XTAL OSC TRCLK_CKO_GP3 DT_GP1 DR_GP0 IRQ1_GP4 IRQ2_TRFS_GP2 LDO1 LDO2 LDO3 LDO4 BIAS IRQ CREGRF1, CREGVCO CREGSYNTH CREGDIG1, RBIAS XOSC26P CREGRF2, CREGDIG2 CREGRF3 XOSC26N XOSC32KN_ATB2 XOSC32KP_GP7_ATB1 Figure 2. Detailed Functional Block Diagram Rev. 0 | Page 5 of 108 08912-011 ADF7242 SPECIFICATIONS VDD_BAT = 1.8 V to 3.6 V, GND = 0 V, TA = TMIN to TMAX, unless otherwise noted. Typical specifications are at VDD_BAT = 3.6 V, TA = 25°C, fCHANNEL = 2450 MHz. All measurements are performed using the ADF7242 reference design, RFIO2 port, unless otherwise noted. GENERAL SPECIFICATIONS Table 1. Parameter GENERAL PARAMETERS Voltage Supply Range VDD_BAT Input Frequency Range Operating Temperature Range Data Rate GFSK/FSK Mode IEEE 802.15.4-2006 Mode Resolution Min Typ Max Unit Test Conditions 1.8 2400 −40 50 250 100 3.6 2483.5 +85 2000 V MHz °C kbps kbps bps Applies to FSK modes only RF FREQUENCY SYNTHESIZER SPECIFICATIONS Table 2. Parameter CHANNEL FREQUENCY RESOLUTION PHASE ERROR Min Typ 10 3 Max Unit kHz Degrees Test Conditions Applies to GFSK/FSK modes Receive mode; any data rate, IEEE 802.15.4-2006 or GFSK/FSK mode; integration bandwidth from 10 kHz to 400 kHz Transmit mode; IEEE 802.15.4-2006, 2 Mbps to 290 kbps, GFSK/FSK/GMSK/MSK mode; integration bandwidth from 10 kHz to 1800 kHz Transmit mode; 289.9 kbps to 184 kbps GFSK/FSK/GMSK/MSK mode; integration bandwidth from 10 kHz to 800 kHz Transmit mode; 183.9 kbps to 50 kbps GFSK/FSK/GMSK/MSK mode; integration bandwidth from 10 kHz to 500 kHz Applies to all modes Frequency synthesizer settled to 3.5 MHz Gaussian filter available for 2000 kbps, 1000 kbps, 500 kbps, 250 kbps, 125 kbps and 62.5 kbps only Rev. 0 | Page 7 of 108 ADF7242 Parameter Transmit Modulation Phase Error Min Typ 7 6.5 4.5 6 4 Transmit Modulation Error Rate (MER) 24 Max Unit Degrees Degrees Degrees Degrees Degrees dB Test Conditions 2 Mbps (fDEV = ±500 kHz) GFSK SPORT mode, transmitter output power = 3 dBm 1 Mbps (fDEV = ±250 kHz) GFSK SPORT mode, transmitter output power = 3 dBm 500 kbps (fDEV = ±250 kHz) GFSK SPORT mode, transmitter output power = 3 dBm 250 kbps (fDEV = ±130 kHz) GFSK SPORT mode, transmitter output power = 3 dBm 125 kbps (fDEV = ±60 kHz) FSK SPORT mode, transmitter output power = 3 dBm 2 Mbps GFSK SPORT mode, transmitter output power = 3dBm; measured as the standard deviation from ±500 kHz frequency deviation 1 Mbps GFSK SPORT mode, transmitter output power = 3 dBm; measured as the standard deviation from ±250 kHz frequency deviation 500 kbps GFSK SPORT mode, transmitter output power = 3dBm; measured as the standard deviation from ±250 kHz frequency deviation 250 kbps GFSK SPORT mode, transmitter output power = 3 dBm; measured as the standard deviation from ±130 kHz frequency deviation 125 kbps FSK SPORT mode, transmitter output power = 3 dBm; measured as the standard deviation from ±60 kHz frequency deviation 2 Mbps (fDEV = ±500 kHz) GFSK SPORT mode 1 Mbps (fDEV = ±250 kHz) GFSK SPORT mode 500 kbps (fDEV = ±250 kHz) GFSK SPORT mode 250 kbps (fDEV = ±130 kHz) GFSK SPORT mode 125 kbps (fDEV = ±60 kHz) FSK SPORT mode 62.5 kbps (fDEV = ±60 kHz) FSK SPORT mode 2 Mbps GFSK SPORT mode, 5 MHz channel spacing 2.2 MHz channel bandwidth, transmitter output power = 3 dBm 250 kbps FSK SPORT mode, 300 kHz channel spacing 250 kHz channel bandwidth, transmitter output power = 3 dBm 24 dB 24 dB 24 dB 22 dB Transmit 20 dB Bandwidth 2 Mbps GFSK SPORT Mode 1 Mbps GFSK SPORT Mode 500 kbps GFSK SPORT Mode 250 kbps GFSK SPORT Mode 125 kbps GFSK SPORT Mode 62.5 kbps FSK SPORT Mode Transmit Adjacent Channel Power ±First Channel ±Second Channel ±First Channel ±Second Channel 1 2520 1250 985 520 302 226 −53.5 −54.5 −27 −51.5 kHz kHz kHz kHz kHz kHz dBm dBm dBm dBm RBW = resolution bandwidth. RECEIVER SPECIFICATIONS Table 4. Parameter GENERAL RECEIVER SPECIFICATIONS RF Front-End LNA and Mixer IIP3 Min Typ −13.6 −12.6 Max Unit dBm dBm Test Conditions At maximum gain, fBLOCKER1 = 5 MHz, fBLOCKER2 = 10.1 MHz, PRF,IN = −35 dBm At maximum gain, fBLOCKER1 = 20 MHz, fBLOCKER2 = 40.1 MHz, PRF,IN = −35 dBm At maximum gain, fBLOCKER1 = 40 MHz, fBLOCKER2 = 80.1 MHz, PRF,IN = −35 dBm −10.5 dBm Rev. 0 | Page 8 of 108 ADF7242 Parameter RF Front-End LNA and Mixer IIP2 RF Front-End LNA and Mixer 1 dB Compression Point Receiver LO Level at RFIO2 Port LNA Input Impedance at RFIO1 Port LNA Input Impedance at RFIO2 Port Receive Spurious Emissions Compliant with EN 300 440 30 MHz to 1000 MHz 1 GHz to 12.75 GHz RECEIVE PATH IEEE 802.15.4-2006 MODE Sensitivity (Prf,in,min, 802154) Saturation Level CW Blocker Rejection ±5 MHz ±10 MHz ±20 MHz ±30 MHz Modulated Blocker Rejection ±5 MHz ±10 MHz ±15 MHz ±20 MHz ±30 MHz Co-Channel Rejection Out-of Band Blocker Rejection −5 MHz −10 MHz −20 MHz −30 MHz −60 MHz +5 MHz +10 MHz +20 MHz +30 MHz +60 MHz Min Typ 24.7 −20.5 −100 50.2 − 52.2j 74.3 − 10.7j Max Unit dBm dBm dBm Ω Ω Test Conditions At maximum gain, fBLOCKER1 = 5 MHz, fBLOCKER2 = 5.5 MHz, PRF,IN = −50 dBm At maximum gain IEEE 802.15.4 packet mode Measured in RX state Measured in RX state −57 −47 −95 −15 55 60 63 64 48 61 62.5 65 65 −6 −34.2 −30.7 −29.7 −25.7 −24.2 −33.4 −29.9 −28.2 −23.7 −29.9 dBm dBm dBm dBm dB dB dB dB dB dB dB dB dB dB dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm 1% PER with PSDU length of 20 bytes according to the IEEE 802.15.4-2006 standard 1% PER with PSDU length of 20 bytes PRF,IN = PRF,IN,MIN, 802154 + 3 dB PRF,IN = PRF,IN,MIN, 802154 + 3 dB PRF,IN = PRF,IN,MIN, 802154 + 3 dB PRF,IN = PRF,IN,MIN, 802154 + 3 dB PRF,IN = PRF,IN,MIN, 802154 + 3 dB PRF,IN = PRF,IN,MIN, 802154 + 3 dB PRF,IN = PRF,IN,MIN, 802154 + 3 dB PRF,IN = PRF,IN,MIN, 802154 + 3 dB PRF,IN = PRF,IN,MIN, 802154 + 3 dB Prf,IN = Prf,IN,MIN + 10 dB Modulated Blocker PRF,IN = PRF,IN,MIN, 802154 + 3 dB, measured at fCHANNEL = 2405 MHz PRF,IN = PRF,IN,MIN, 802154 + 3 dB, measured at fCHANNEL = 2405 MHz PRF,IN = PRF,IN,MIN, 802154 + 3 dB, measured at fCHANNEL = 2405 MHz PRF,IN = PRF,IN,MIN, 802154 + 3 dB, measured at fCHANNEL = 2405 MHz PRF,IN = PRF,IN,MIN, 802154 + 3 dB, measured at fCHANNEL = 2405 MHz PRF,IN = PRF,IN,MIN, 802154 + 3 dB, measured at fCHANNEL = 2480 MHz PRF,IN = PRF,IN,MIN, 802154 + 3 dB, measured at fCHANNEL = 2480 MHz PRF,IN = PRF,IN,MIN, 802154 + 3 dB, measured at fCHANNEL = 2480 MHz PRF,IN = PRF,IN,MIN, 802154 + 3 dB, measured at fCHANNEL = 2480 MHz PRF,IN = PRF,IN,MIN, 802154 + 3 dB, measured at fCHANNEL = 2480 MHz Two-sided bandwidth; cascaded analog and digital channel filtering PRF,IN = PRF,IN,MIN + 3 dB Receiver Channel Bandwidth 2252 kHz Frequency Error Tolerance −80 +80 ppm Rev. 0 | Page 9 of 108 ADF7242 Parameter RSSI Dynamic range Accuracy Averaging Time Minimum Sensitivity RECEIVE PATH GFSK MODE Sensitivity 1 % PER PRF,IN,MIN 2 Mbps PRF,IN,MIN 1 Mbps PRF,IN,MIN 500 kbps PRF,IN,MIN 250 kbps PRF,IN,MIN 125 kbps PRF,IN,MIN 100 kbps PRF,IN,MIN 62.5 kbps PRF,IN,MIN 50 kbps Sensitivity 0.1% BER PRF,IN,MIN 2 Mbps PRF,IN,MIN 1 Mbps PRF,IN,MIN 500 kbps PRF,IN,MIN 250 kbps PRF,IN,MIN 125 kbps PRF,IN,MIN 62.5 kbps PRF,IN,MIN 50 kbps Minimum Preamble Length Min Typ 85 ±3 128 −95 Max Unit dB dB μs dBm Test Conditions Measured using IEEE 802.15.4-2006 packet mode −84.5 −87.5 −92 −92 −94 −95 −96 −96 −87.5 −90 −93 −93 −93 −96 −96 11 9 7 7 7 7 6 6 −15 dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm dBm Bytes Bytes Bytes Bytes Bytes Bytes Bytes Bytes dBm 2000 kbps (fDEV = ±500 kHz) GFSK packet mode 1000 kbps (fDEV = ±250 kHz) GFSK packet mode 500 kbps (fDEV = ±250 kHz) GFSK packet mode 250 kbps (fDEV = ±130 kHz) GFSK packet mode 125 kbps (fDEV = ±60 kHz) FSK packet mode 100 kbps (fDEV = ±30 kHz) FSK packet mode 62.5 kbps (fDEV = ±60 kHz) FSK packet mode 50 kbps (fDEV = ±30 kHz) FSK packet mode 2000 kbps (fDEV = ±500 kHz) GFSK SPORT mode 1000 kbps (fDEV = ±250 kHz) GFSK SPORT mode 500 kbps (fDEV = ±250 kHz) GFSK SPORT mode 250 kbps (fDEV = ±130 kHz) GFSK SPORT mode 125 kbps (fDEV = ±60 kHz) FSK SPORT mode 62.5 kbps (fDEV = ±6 0kHz) FSK SPORT mode 50 kbps (fDEV = ±30 kHz) FSK SPORT mode 2000 kbps (fDEV = ±50 0kHz) GFSK packet mode 1000 kbps (fDEV = ±-250 kHz) GFSK packet mode 500 kbps (fDEV = ±250 kHz) GFSK packet mode 250 kbps (fDEV = ±-130 kHz) GFSK packet mode 125 kbps (fDEV = ±60 kHz) FSK packet mode 100 kbps (fDEV = ±-30 kHz) FSK packet mode 62.5 kbps (fDEV = ±-60 kHz) FSK packet mode 50 kbps (fDEV = ±30 kHz) FSK packet mode All GFSK/FSK modes, packet and SPORT modes, 1% PER and 0.1% BER PRF,IN = PRF,IN,MIN, 2 Mbps + 3 dB Saturation Level CW Blocking Rejection (2000 kbps (fDEV = ±500 kHz) GFSK Packet Mode) ±5 MHz ±10 MHz ±20 MHz ±30 MHz Modulated Blocking Rejection (2000 kbps (fDEV = ±500 kHz) GFSK Packet Mode) ±5 MHz ±10 MHz ±20 MHz ±30 MHz CW Blocker Rejection (125 kbps (fDEV = ±60 kHz) FSK Packet Mode) ±2 MHz ±5 MHz ±12 MHz ±20 MHz ±32 MHz 51 56 56.5 60.5 dB dB dB dB PRF,IN = PRF,IN,MIN, 2 Mbps + 3 dB 48 53 58 60 dB dB dB dB PRF,IN = PRF,IN,MIN, 125 kbps + 3 dB 54.5 62 64 69 70.5 dB dB dB dB dB Rev. 0 | Page 10 of 108 ADF7242 Parameter Modulated Blocking Rejection (2000 kbps (fDEV = ±500 kHz) GFSK Packet Mode) ±2 MHz ±5 MHz ±12 MHz ±20 MHz ±32 MHz Co-Channel Rejection Min Typ Max Unit Test Conditions PRF,IN = PRF,IN,MIN, 125 kbps + 3 dB 52.5 60 64.5 68.5 71 −13 −9 dB dB dB dB dB dB dB 2000 kbps (fDEV = ±500 kHz) GFSK packet mode, PRF,IN = PRF,IN,MIN, 2 Mbps + 10 dB, modulated blocker 250 kbps (fDEV = ±130 kHz) GFSK packet mode, PRF,IN = PRF,IN,MIN, 250 kbps + 10 dB, modulated blocker Receiver Channel Bandwidth Minimum Channel 3 dB Bandwidth Analog Filter Analog and Digital Filter Cascade Maximum Channel 3 dB Bandwidth Frequency Error Tolerance, 2000 kbps (fDEV = ±500 kHz) GFSK Packet Mode AFC Off AFC On Frequency Error Tolerance, 500 kbps (fDEV = ±250 kHz) FSK Packet Mode AFC Off AFC On RSSI, 2000 kbps (fDEV = ±500 kHz) GFSK Mode Accuracy Minimum Sensitivity, Packet Mode Minimum Sensitivity, SPORT Mode RSSI, 500 kbps (fDEV = ±250 kHz) GFSK Mode Accuracy Minimum Sensitivity, Packet Mode Minimum Sensitivity, SPORT Mode 1110 520 2252 kHz kHz kHz Two-sided bandwidth Two-sided bandwidth Two-sided bandwidth ±55 ±165 kHz kHz AFC pull-in range = ±80 kHz ±90 ±190 kHz kHz AFC pull-in range = ±80 kHz ±3 −84.5 −87.5 ±3 −92 −93 dBm dBm dBm dBm dBm dBm SPORT mode with no preamble or SWD detection SPORT mode with no preamble or SWD detection AUXILIARY SPECIFICATIONS Table 5. Parameter 32 kHz RC OSCILLATOR Frequency Frequency Accuracy Frequency Drift Temperature Coefficient Voltage Coefficient Calibration Time 32 kHz CRYSTAL OSCILLATOR Frequency Maximum ESR Start-Up Time WAKE-UP TIMER Prescaler Tick Period Wake-Up Period Min Typ 32.768 1 0.14 4 1 32.768 319.8 2000 Max Unit kHz % %/°C %/V ms kHz kΩ ms Test Conditions After calibration After calibration at 25°C 10 pF on XOSC32KP and XOSC32KN 12.5pF load capacitors on XOSC32KP and XOSC32KN 0.0305 61 × 10−6 20,000 1.31 × 105 Rev. 0 | Page 11 of 108 ms sec ADF7242 Parameter TEMPERATURE SENSOR Range Resolution Accuracy Min −40 4.7 ±6.4 Typ Max +85 Unit °C °C °C Test Conditions Average of 1000 ADC readbacks, after using linear fitting, with correction at known temperature BATTERY MONITOR Trigger Voltage Trigger Voltage Step Size Start-Up Time Current Consumption EXTERNAL PA INTERFACE RON, PAVSUP_ATB3 to VDD_BAT ROFF, PAVSUP_ATB3 to GND ROFF, PABIASOP_ATB4 to GND PABIASOP_ATB4 Source Current, Maximum PABIASOP_ATB4 Sink Current, Minimum PABIASOP_ATB4 Current Control Resolution PABIASOP_ATB4 Compliance Voltage PABIASOP_ATB4 Compliance Voltage Servo Loop Bias Current Servo Loop Bias Current Control Step 1.7 62 5 30 5 10 10 80 −80 6 150 3.45 22 0.349 3.6 V mV μs μA Ω MΩ MΩ μA μA Bits mV V mA mA extpa_bias_mode = 0, 1, 2, 5, 6 extpa_bias_mode = 3, 4, power-down extpa_bias_mode = 0, power-down expta_bias_mode = 1, 3 extpa_bias_mode = 2, 4 extpa_bias_mode = 1, 2, 3, 4, 5 extpa_bias_mode = 2, 4 extpa_bias_mode = 1, 3 extpa_bias_mode = 5, 6 extpa_bias_mode = 5, 6 CURRENT CONSUMPTION SPECIFICATIONS Table 6. Parameter CURRENT CONSUMPTION TX Mode Current Consumption −20 dBm −10 dBm 0 dBm +3 dBm +4 dBm Idle Mode PHY_RDY Mode RX Mode Current Consumption MEAS State SLEEP_BBRAM SLEEP_BBRAM_RCO SLEEP_BBRAM_XTO Min Typ Max Unit Test Conditions 16.5 17.4 19.6 21.5 25 1.8 10 19 3 0.3 1 1.7 mA mA mA mA mA mA mA mA mA μA μA μA IEEE 802.15.4-2006 continuous packet transmission mode IEEE 802.15.4-2006 continuous packet transmission mode IEEE 802.15.4-2006 continuous packet transmission mode IEEE 802.15.4-2006 continuous packet transmission mode IEEE 802.15.4-2006 continuous packet transmission mode XTO26M + digital active IEEE 802.15.4-2006 packet mode BBRAM contents retained 32 kHz RC oscillator running, some BBRAM contents retained, wake-up time enabled 32 kHz crystal oscillator running, some BBRAM contents retained, wake-up time enabled Rev. 0 | Page 12 of 108 ADF7242 TIMING AND DIGITAL SPECIFICATIONS Table 7. Logic Levels Parameter LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINH/IINL Input Capacitance, CIN LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL Output Rise/Fall Output Load Min 0.7 × VDD_BAT 0.2 × VDD ±1 10 VDD_BAT − 0.4 0.4 5 7 Typ Max Unit V V μA pF V V ns pF IOH = 500 μA IOL = 500 μA Test Conditions Table 8. GPIOs Parameter GPIO OUTPUTS Output Drive Level Output Drive Level Min Typ 5 5 Max Unit mA mA Test Conditions All GPIOs in logic high state All GPIOs in logic low state Table 9. SPI Interface Timing Parameter t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15, t16 Min 40 40 40 80 10 5 5 40 10 270 300 400 20 20 Typ Max 15 Unit ns ns ns ns ns ns ns ns ns ns ns μs ns ns ms Description CS falling edge to MISO setup time (TRX active) CS to SCLK setup time SCLK high time SCLK low time SCLK period SCLK falling edge to MISO delay MOSI to SCLK rising edge setup time MOSI to SCLK rising edge hold time SCLK to CS hold time CS high to SCLK wait time CS high time CS low to MISO high wake-up time, 26 MHz crystal with 10 pF load capacitance, TA = 25°C SCLK rise time SCLK fall time CS high time on wake-up after RC_RESET or RC_SLEEP command (see Figure 5 and Figure 70) 26 MHz crystal with 10 pF load 2 Rev. 0 | Page 13 of 108 ADF7242 Table 10. IEEE 802.15.4 State Transition Timing Parameter Idle to PHY_RDY State PHY_RDY to Idle State PHY_RDY or TX to RX State (Different Channel) PHY_RDY or RX to TX State (Different Channel) PHY_RDY or TX to RX State (Same Channel) RX or PHY_RDY to TX State (Same Channel) RX Channel Change TX Channel Change TX to PHY_RDY State PHY_RDY to CCA State CCA to PHY_RDY State RX to Idle State TX to Idle State Idle to MEAS State MEAS to Idle State CCA to Idle State RX to CCA State CCA to RX State Min Typ 142 13.5 192 192 140 140 192 192 23 192 14.5 5.5 30.5 19 6 14.5 18 205 Max Unit μs μs μs μs μs μs μs μs μs μs μs μs μs μs μs μs μs μs Test Conditions VCO calibration performed VCO calibration performed VCO calibration skipped VCO calibration skipped VCO calibration performed VCO calibration performed Table 11. GFSK/FSK State Transition Timing Parameter Idle to PHY_RDY State PHY_RDY to Idle State PHY_RDY or TX to RX State (Different Channel) PHY_RDY or RX to TX State (Different Channel) PHY_RDY or RX to TX State (Different Channel) PHY_RDY or TX to RX State (Same Channel) RX or PHY_RDY to TX State (Same Channel) RX or PHY_RDY to TX State (Same Channel) RX Channel Change TX Channel Change TX Channel Change TX to PHY_RDY State PHY_RDY to CCA State CCA to PHY_RDY State RX to Idle State TX to Idle State Idle to MEAS State MEAS to Idle State CCA to Idle State RX to CCA State CCA to RX State 1 Min Typ 180 13.5 192 664 612 140 664 664 192 664 23 192 14.5 18.5 30.5 19 6 14.5 18 205 Max 664 Unit μs μs μs μs μs μs μs μs μs μs μs μs μs μs μs μs μs μs μs μs μs Test Conditions VCO calibration performed VCO calibration performed VCO calibration performed, mac_delay_ext1= 472 μs VCO calibration skipped VCO calibration skipped VCO calibration performed, mac_delay_ext 1 = 472 μs VCO calibration performed VCO calibration performed VCO calibration performed, mac_delay_ext1 = 472 μs mac_delay_ext setting applies to both RX and TX states. The default setting is 0 μs. Rev. 0 | Page 14 of 108 ADF7242 Table 12. Timing IEEE 802.15.4-2006 SPORT Mode Parameter t21 t22 t23 t24 Min 18 0.51 16 Typ 2 Max Unit μs μs μs μs Test Conditions/Comments SFD detect to TRCLK_CLKO_GP3 (data bit clock) active delay TRCLK_CKO_GP3 bit period DR_GP0 to TRCLK_CKO_GP3 falling edge setup time TRCLK_CKO_GP3 symbol burst period Table 13. MAC Timing Parameter t26 t27 t28 tRX_MAC_DELAY 664 192 Min Typ 38 Max 150 150 Unit μs μs μs μs μs Test Conditions/Comments Time from frame received to rx_pkt_rcvd interrupt generation Time allowed, from issuing a RC_TX command, to update Register delaycfg2, Bit mac_delay_ext (0x10B[7:0]) Time allowed, from issuing a RC_TX command, to cancel the RC_TX command IEEE 802.15.4 mode as defined by the standard GFSK/FSK mode as required by state transition timing Table 14. Timing GFSK SPORT Mode Parameter t29 t30 t31 t32 t33 t34 t35 t36 t37 t38 t39 t40 t41 t42 Min tSYM/2 − 30 tSYM/2 − 30 tSYM 20 20 1.3 14 10 tSYM/2 − 60 Sync_word_length × tSYM 5 × tSYM Sync_word_length × tSYM 105 tSYM/2 ns ns μs μs μs ns μs μs us μs Typ 14 Max Unit μs ns ns Test Conditions/Comments RC_PHY_RDY to TRCLK_CKO_GP3 (data clock) off DR_GP0 to TRCLK_CKO_GP3 active edge hold time DR_GP0 to TRCLK_CKO_GP3 active edge setup time TRCLK_CLKO_GP3 clock period DT_GP1 to TRCLK_CKO_GP3 sampling edge setup time DT_GP1 to TRCLK_CKO_GP3 sampling edge hold time PA nominal power to TRCLK_CKO_GP3 activity/entry into TX state RC_PHY_RDY to TRCLK_CLKO_GP3 off RC_PHY_RDY to PA power shutdown IRQ2_TRFS_GP2 rising edge to TRCLK_CKO_GP3 active edge delay DR_GP0 activity to end of sync word delay Sync word detect to IRQ2_TRFS_GP2 high TRCLK_CKO_GP3 active to valid data RC_RX command to TRCLK_CKO_GP3 activity delay (calibrations performed) 6.2 TIMING DIAGRAMS SPI Interface Timing Diagram CS t11 t2 SCLK t3 t4 t5 t9 t10 t1 MISO BIT 7 t6 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 BIT 7 BIT 0 X BIT 7 t7 MOSI 7 t8 08912-002 6 5 4 3 2 1 0 7 7 Figure 3. SPI Interface Timing Additional description and timing diagrams are available in the Serial Peripheral interface section. Rev. 0 | Page 15 of 108 ADF7242 Sleep-to-Idle SPI Timing CS t9 SCLK 7 6 5 4 3 2 1 0 t12 MISO X Figure 4. Sleep-to-Idle State Timing t16 CS SPI COMMAND TO ADF7242 RC_RESET OR RC_SLEEP DEVICE STATUS IDLE, PHY_RDY, RX SLEEP IDLE Figure 5. Wake-Up After an RC_RESET or RC_SLEEP Command MAC Delay Timing Diagram PACKET TRANSMITTED PACKET RECEIVED FRAME IN TX_BUFFER VALID IEEE802.15.4-2006 FRAME 08912-064 08912-003 t1 t6 RC_STATUS RX tx_mac_delay + mac_delay_ext TX PHY_RDY t26 REGISTER irq_src0, FIELD rc_ready REGISTER irq_src1, FIELD rx_pkt_rcvd REGISTER irq_src1, FIELD tx_pkt_sent t27,t28 Figure 6. IEEE 802.15.4 MAC Timing Rev. 0 | Page 16 of 108 08912-016 ADF7242 IEEE 802.15.4 RX SPORT Mode Timing Diagrams Table 15. IEEE 802.15.4 RX SPORT Modes Configurations Register rc_cfg, Field rc_mode (0x13E[7:0]) 2 0 Register gp_cfg, Field gpio_config (0x32C[7:0]) 1 7 Functionality Bit clock and data available (see Figure 7) Symbol clock and data available (see Figure 8) COMMAND RC_STATUS RC_RX PREVIOUS STATE RC_PHY_RDY RX PHY_RDY tRX_MAC_DELAY PREAMBLE SFD PHR PSDU t29 t21 TRCLK_CKO_GP3 t21 t24 DR_GP0 ..... DATA INVALID TRCLK_CKO_GP3 ..... ..... ..... DR_GP0 ..... t22 Figure 7. IEEE 802.15.4 RX SPORT Mode: Bit Clock and Data Available COMMAND RC_STATUS RC_RX PREVIOUS STATE RC_PHY_RDY RX PHY_RDY tRX_MAC_DELAY PREAMBLE SFD PHR PSDU t29 t21 TRCLK_CKO_GP3 t26 t21 GP6, GP5, GP1, GP01 1GP6 SYMBOL [3:0] [3:0] [3:0] [3:0] [3:0] [3:0] [3:0] [3:0] Figure 8. IEEE 802.15.4 RX SPORT Mode: Symbol Clock Output Rev. 0 | Page 17 of 108 08912-009 = RXEN_GP6 GP5 = TXEN_GP5 GP1 = DT_GP1 GP0 = DR_GP0 08912-004 t23 ADF7242 IEEE 802.15.4 TX SPORT MODE TIMING DIAGRAMS Table 16. IEE 802.15.4 TX SPORT Mode Configurations Register rc_cfg, Field rc_mode (0x13E[7:0]) 3 Register gp_cfg, Field gpio_config (0x32C[7:0]) 1 or 4 Functionality Transmission starts after PA ramp up (see Figure 9) gpio_config = 1: data clocked in on rising edge of clock gpio_config = 4: data clocked in on falling edge of clock RC_TX RC_PHY_RDY RC STATE PHY_RDY TX PHY_RDY PA POWER t37 t35 PACKET COMPONENT PREAMBLE SFD PHR PSDU t36 TRCLK_CKO_GP3 ..... PACKET DATA DT_GP1 ..... REGISTER gp_cfg, FIELD gpio_config = 1 DATA CLOCKED IN ON RISING EDGE REGISTER gp_cfg, FIELD gpio_config = 4 DATA CLOCKED IN ON FALLING EDGE t32 TRCLK_CKO_GP3 DT_GP1 SAMPLE TRCLK_CKO_GP3 DT_GP1 SAMPLE t32 DT_GP1 DT_GP1 t33 t34 t33 t34 Figure 9. IEEE 802.15.4-2006 TX SPORT Mode Refer to the SPORT Interface section for further details. GFSK/FSK RX SPORT MODE TIMING DIAGRAMS Table 17. GFSK/FSK RX SPORT Mode Configurations Register rc_cfg, Field rc_mode (0x13E[7:0]) 3 Register gp_cfg, Field gpio_config (0x32C[7:0]) 1 or 4 Functionality TRCLK and data pins active in RX, without gating by frame detection (see Figure 10) gpio_config = 1: data clocked out on falling edge/rising edge gpio_config = 4: data clocked out on rising edge/rising edge TRCLK and Data pins activity gated by preamble detection (see Figure 11) gpio_config = 2: data clocked out on falling edge/rising edge gpio_config = 5: data clocked out on rising edge/rising edge TRCLK and data pins activity gated by synchronization word detection (see Figure 12) gpio_config = 3: data clocked out on falling edge/rising edge gpio_config = 6: data clocked out on rising edge/rising edge 3 2 or 5 3 3 or 6 Rev. 0 | Page 18 of 108 08912-122 ADF7242 COMMAND RC_STATUS RC_RX RC_PHY_RDY PREVIOUS STATE RX PHY_RDY tRX_MAC_DELAY PACKET COMPONENT t29 PREAMBLE SYNC WORD PAYLOAD POSTAMBLE t42 IRQ2_TRFS_GP2 TRCLK_CKO_GP3 ..... PACKET DATA DR_GP0 ..... DATA INVALID REGISTER gp_cfg, FIELD gpio_config = 1 DATA CLOCKED OUT ON FALLING EDGE REGISTER gp_cfg, FIELD gpio_config = 4 DATA CLOCKED OUT ON RISING EDGE IRQ2_TRFS_GP2 IRQ2_TRFS_GP2 t32 TRCLK_CKO_GP3 TRCLK_CKO_GP3 t32 t31 DR_GP0 t31 t30 08912-005 DR_GP0 t30 Figure 10. GFSK/FSK RX SPORT Mode: CLK and Data Pins Active in RX, Without Gating by Frame Detection COMMAND RC_STATUS RC_RX RC_PHY_RDY PREVIOUS STATE RX PHY_RDY tRX_MAC_DELAY PACKET COMPONENT IRQ2_TRFS_GP2 PREAMBLE SYNC WORD PAYLOAD POSTAMBLE t29 t40 t41 TRCLK_CKO_GP3 ..... t39 DR_GP0 PACKET DATA ..... DATA INVALID REGISTER gp_cfg, FIELD gpio_config = 2 DATA CLOCKED OUT ON FALLING EDGE REGISTER gp_cfg, FIELD gpio_config = 5 DATA CLOCKED OUT ON RISING EDGE IRQ2_TRFS_GP2 IRQ2_TRFS_GP2 t38 TRCLK_CKO_GP3 t32 TRCLK_CKO_GP3 t38 t32 t31 DR_GP0 t31 t30 DR_GP0 t30 08912-006 Figure 11. GFSK/FSK RX SPORT Mode: SCLK and Data Pin Activity Gated By Preamble Detection Rev. 0 | Page 19 of 108 ADF7242 COMMAND RC_STATUS RC_RX RC_PHY_RDY PREVIOUS STATE RX PHY_RDY tRX_MAC_DELAY PACKET COMPONENT IRQ2_TRFS_GP2 TRCLK_CKO_GP3 PREAMBLE SYNC WORD PAYLOAD POSTAMBLE t29 t40 ..... t39 DR_GP0 PACKET DATA ..... DATA INVALID REGISTER gp_cfg, FIELD gpio_config = 3 DATA CLOCKED OUT ON FALLING EDGE REGISTER gp_cfg, FIELD gpio_config = 6 DATA CLOCKED OUT ON RISING EDGE IRQ2_TRFS_GP2 IRQ2_TRFS_GP2 t38 TRCLK_CKO_GP3 t32 TRCLK_CKO_GP3 t38 t32 t31 DR_GP0 t31 DR_GP0 08912-007 t30 t30 Figure 12. GFSK/FSK RX SPORT Mode: SCLK and Data Pins Activity Gated By Synchronization Word Detection GFSK/FSK TX SPORT Mode Timing Diagrams Table 18. GFSK/FSK TX SPORT Mode Configurations Register rc_cfg, Field rc_mode (0x13E[7:0]) 3 Register gp_cfg, Field gpio_config (0x32C[7:0]) 1 or 4 Functionality Transmission starts after PA ramp up (see Figure 13) gpio_config = 1: data clocked in on rising edge of clock gpio_config = 4: data clocked in on falling edge of clock Rev. 0 | Page 20 of 108 ADF7242 RC_TX RC_PHY_RDY RC STATE PHY_RDY TX PHY_RDY PA POWER t37 t35 SYNC WORD POSTAMBLE PACKET COMPONENT PREAMBLE PSDU t36 TRCLK_CKO_GP3 ..... PACKET DATA DT_GP1 ..... REGISTER gp_cfg, FIELD gpio_config = 1 DATA CLOCKED IN ON RISING EDGE REGISTER gp_cfg, FIELD gpio_config = 4 DATA CLOCKED IN ON FALLING EDGE t32 TRCLK_CKO_GP3 DT_GP1 SAMPLE TRCLK_CKO_GP3 DT_GP1 SAMPLE t32 DT_GP1 DT_GP1 t33 t34 t33 t34 Figure 13. GFSK/FSK TX SPORT Mode Refer to the SPORT Interface section for further details. Rev. 0 | Page 21 of 108 08912-123 ADF7242 ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 19. Parameter VDD_BAT to GND Operating Temperature Range Industrial Storage Temperature Range Maximum Junction Temperature LFCSP θJA Thermal Impedance Reflow Soldering Peak Temperature Time at Peak Temperature Rating −0.3 V to +3.9 V −40°C to +85°C −65°C to +125°C 150°C 26°C/W 260°C 40 sec The exposed paddle of the LFCSP package should be connected to ground. This device is a high performance RF integrated circuit with an ESD rating of 1%