ADIS16490BMLZ

Tactical Grade, Six Degrees of Freedom Inertial Sensor ADIS16490 Data Sheet FEATURES GENERAL DESCRIPTION Triaxial, digital gyroscope, ±100°/sec dynamic range ±0.05° axis to axis misalignment error ±0.25° axis to package misalignment error 1.8°/hr in run bias stability 0.09°/√hr angular random walk Triaxial, digital accelerometer, ±8 g 3.6 μg in run bias stability Triaxial, delta angle and delta velocity outputs Factory calibrated sensitivity, bias, and axial alignment Calibration temperature range: −40°C to +85°C Serial peripheral interface (SPI) compatible Programmable operation and control Automatic and manual bias correction controls 4 finite impulse response (FIR) filter banks, 120 configurable taps Digital input/output (I/O): data ready, external clock Sample clock options: internal, external, or scaled On demand self test of inertial sensors Single-supply operation: 3.0 V to 3.6 V 2000 g shock survivability Operating temperature range: −40°C to +105°C The ADIS16490 is a complete inertial system that includes a triaxis gyroscope and a triaxis accelerometer. Each inertial sensor in the ADIS16490 combines industry leading iMEMS® technology with signal conditioning that optimizes dynamic performance. The factory calibration characterizes each sensor for sensitivity, bias, alignment, and linear acceleration (gyroscope bias). As a result, each sensor has its own dynamic compensation formulas that provide accurate sensor measurements. The ADIS16490 provides a simple, cost effective method for integrating accurate, multiaxis inertial sensing into industrial systems, especially when compared with the complexity and investment associated with discrete designs. All necessary motion testing and calibration are part of the production process at the factory, greatly reducing system integration time. Tight orthogonal alignment simplifies inertial frame alignment in navigation systems. The SPI and register structure provide a simple interface for data collection and configuration control. The ADIS16490 uses the same footprint and connector system as the ADIS16375, ADIS16480, ADIS16485, and ADIS16488A, which greatly simplifies the upgrade process. The ADIS16490 is packaged in a module that is approximately 47 mm × 44 mm × 14 mm and includes a standard connector interface. APPLICATIONS Precision instrumentation, stabilization Guidance, navigation, control Avionics, unmanned vehicles Precision autonomous machines, robotics FUNCTIONAL BLOCK DIAGRAM DIO1 DIO2 DIO3 DIO4 RST SELF TEST VDD POWER MANAGEMENT I/O OUTPUT DATA REGISTERS TRIAXIAL GYRO TRIAXIAL ACCEL CONTROLLER CALIBRATION AND FILTERS TEMP GND CS SCLK SPI USER CONTROL REGISTERS DIN DOUT ADIS16490 15029-001 CLOCK Figure 1. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2016–2020 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADIS16490 Data Sheet TABLE OF CONTENTS Features .............................................................................................. 1  Device Configuration ................................................................ 15  Applications ...................................................................................... 1  User Register Memory Map.......................................................... 16  General Description ......................................................................... 1  User Register Defintions ............................................................... 19  Functional Block Diagram .............................................................. 1  Gyroscope Data .......................................................................... 20  Revision History ............................................................................... 2  Acceleration Data ....................................................................... 21  Specifications .................................................................................... 3  Delta Angles ................................................................................ 22  Timing Specifications .................................................................. 5  Delta Velocity ............................................................................. 23  Absolute Maximum Ratings ........................................................... 7  Calibration .................................................................................. 25  Thermal Resistance ...................................................................... 7  FIR Filters .................................................................................... 34  ESD Caution.................................................................................. 7  Applications Information ............................................................. 36  Pin Configuration and Function Descriptions ............................ 8  Mounting Best Practices ........................................................... 36  Typical Performance Characteristics ............................................. 9  Preventing Misinsertion ............................................................ 36  Theory of Operation ...................................................................... 12  Evaluation Tools......................................................................... 36  Inertial Sensor Signal Chain ..................................................... 12  Power Supply Considerations .................................................. 36  Register Structure ....................................................................... 13  Packaging and Ordering Information ......................................... 37  Serial Peripheral Interface ......................................................... 14  Outline Dimensions ................................................................... 37  Data Ready .................................................................................. 14  Ordering Guide .......................................................................... 37  Reading Sensor Data .................................................................. 15  REVISION HISTORY 9/2020—Rev. C to Rev. D Changes to Table 1 ........................................................................... 3 Changes tSTALL Parameter and Endnote 2, Table 2 ....................... 5 Changes to Flash Memory Update Section, On Demand Self Test (ODST) Section, and Data Ready Indicator Section......... 29 Changes to Scaling the Input Clock (PPS Mode), SYNC_SCALE Section ................................................................... 31 Changes to Figure 50 ..................................................................... 35 5/2019—Rev. B to Rev. C Changes to Table 1 ........................................................................... 3 Changes to Table 6 ........................................................................... 8 Changes to Theory of Operation Section, Inertial Sensor Signal Chain Section, and Gyroscope Data Sampling Section ............ 12 Changes to Data Ready Section .................................................... 14 Added Figure 31 and Figure 32; Renumbered Sequentially ..... 14 Added Figure 33 ............................................................................. 15 Changes to Table 10 ....................................................................... 16 Changes to Delta Velocity Section ............................................... 24 Change to Flash Memory Endurance Counter, FLSHCNT_LOW, FLSHCNT_HIGH Section .............................................................. 28 Changes to Data Ready Indicator Section .................................. 29 Changes to Continuous Bias Estimation (CBE), NULL_CNFG Section .............................................................................................. 31 Updated Outline Dimensions ...................................................... 37 3/2018—Rev. A to Rev. B Changes to Table 137 ..................................................................... 31 4/2017—Rev. 0 to Rev. A Changes to Nonlinearity Parameter, Table 1 ................................3 Changes to Gyroscope Factory Calibration Section.................. 12 Changes to Accelerometer Factory Calibration Section ........... 13 Updated Outline Dimensions ...................................................... 37 10/2016—Revision 0: Initial Version Rev. D | Page 2 of 37 Data Sheet ADIS16490 SPECIFICATIONS TC = 25°C, VDD = 3.3 V, angular rate = 0°/sec, dynamic range = ±100°/sec ± 1 g, unless otherwise noted. Table 1. Parameter GYROSCOPES Dynamic Range Sensitivity Repeatability 1 Sensitivity Temperature Coefficient Misalignment Nonlinearity Bias Repeatability1, 3 In Run Bas Stability Angular Random Walk Temperature Coefficient Linear Acceleration Effect Vibration Rectification Error Noise Output Noise Rate Noise Density −3 dB Bandwidth Sensor Resonant Frequency ACCELEROMETERS 4 Dynamic Range Sensitivity Repeatability1 Sensitivity Temperature Coefficient Misalignment Nonlinearity Bias Repeatability1, 3 In Run Stability Velocity Random Walk Temperature Coefficient Repeatability Noise Output Noise Noise Density −3 dB Bandwidth Sensor Resonant Frequency TEMPERATURE SENSOR Scale Factor Test Conditions/Comments Min Typ Max ±100 Unit x_GYRO_OUT and x_GYRO_LOW (32-bit) −40°C ≤ TC ≤ +85°C −40°C ≤ TC ≤ +85°C, 1 σ ±24 °/sec °/sec/LSB % ppm/°C Axis to axis 2 Axis to frame (package) Best fit straight line, full scale (FS) = 100°/sec ±0.05 ±0.25 0.3 Degrees Degrees % FS −40°C ≤ TC ≤ +85°C, 1 σ 1σ 1σ −40°C ≤ TC ≤ +85°C, 1 σ Any axis, 1 σ (CONFIG[7] = 1) Any axis, 1 σ (CONFIG[7] = 0) 0.05 1.8 0.09 0.0005 0.005 0.015 0.0003 °/sec °/hr °/√hr °/sec/°C °/sec/g °/sec/g °/sec/g2 No filtering f = 10 Hz to 40 Hz, no filtering 0.05 0.002 480 65 °/sec rms °/sec/√Hz rms Hz kHz x_ACCL_OUT and x_ACCL_LOW (32-bit) −40°C ≤ TC ≤ +85°C −40°C ≤ TC ≤ +85°C, 1 σ 7.6294 × 10−9 0.05 ±16 g g/LSB % ppm/°C Axis to axis Axis to frame (package) Best fit straight line, ±2 g Best fit straight line, ±4 g Best fit straight line, ±8 g ±0.035 ±0.25 0.1 0.15 1.6 Degrees Degrees % FS % FS % FS −40°C ≤ TC ≤ +85°C, 1 σ 1σ 1σ −40°C ≤ TC ≤ +85°C, 1 σ −40°C ≤ TC ≤ +85°C, 1 σ ±3.5 3.6 0.008 ±0.008 1 mg μg m/sec/√hr mg/°C mg No filtering f = 10 Hz to 40 Hz, no filtering 0.5 16 750 2.5 mg rms μg/√Hz rms Hz kHz Output = 0x0000 at 25°C (±5°C) 0.01429 °C/LSB 7.6294 × 10−8 0.5 Each axis ±8 Rev. D | Page 3 of 37 0.2 ADIS16490 Parameter LOGIC INPUTS 5 Input Voltage High, VIH Low, VIL RST Pulse Width Input Current Logic 1, IIH Logic 0, IIL All Pins Except RST RST Pin Input Capacitance, CIN DIGITAL OUTPUTS5 Output Voltage High, VOH Low, VOL FLASH MEMORY Data Retention 7 FUNCTIONAL TIMES 8 Power-On Start-Up Time Reset Recovery Time Flash Memory Update Time Self Test Time CONVERSION RATE Initial Clock Accuracy Temperature Coefficient Sync Input Clock POWER SUPPLY, VDD Power Supply Current 10 Data Sheet Test Conditions/Comments Min Typ Max Unit 0.8 V V µs 10 µA 10 µA mA pF 2.0 1 VIH = 3.3 V VIL = 0 V 0.33 10 ISOURCE = 0.5 mA ISINK = 2.0 mA Endurance 6 TJ = 85°C Time until data is available 2.4 0.4 100,000 20 GLOB_CMD register, Bit 7 = 1 (see Table 142) RST pulled low 9, then restored to high GLOB_CMD[1] = 1 (see Table 129) Operating voltage range Normal mode, VDD = 3.3 V, µ + σ V V Cycles Years 230 190 230 ms ms ms 1237 40 4.25 0.02 40 ms ms kSPS % ppm/°C kHz V mA 3.0 3.0 4.5 3.6 89 The repeatability specifications represent a projection for long-term aging, which is derived from the drift behaviors that a sample of units exhibited throughout their 1000-hour, 110°C high temperature operating life (HTOL). Cross axis sensitivity is the sine of this number. 3 Bias repeatability describes a long-term behavior over a variety of conditions. Short-term repeatability relates to the in run bias stability and noise density specifications. 4 All specifications associated with the accelerometers relate to the full-scale range of ±8 g. 5 The digital I/O signals use a 3.3 V system. 6 Endurance is qualified as per JEDEC Standard 22, Method A117, measured at −40°C, +25°C, +85°C, and +125°C. 7 The data retention specification assumes a junction temperature (TJ) of 85°C per JEDEC Standard 22, Method A117. Data retention lifetime decreases with TJ. 8 These times do not include thermal settling and internal filter response times, which may affect overall accuracy. 9 The RST line must be in a low state for at least 10 μs to ensure a proper reset initiation and recovery. 10 Supply current transients can reach 250 mA during initial startup or reset recovery. 1 2 Rev. D | Page 4 of 37 Data Sheet ADIS16490 TIMING SPECIFICATIONS TC = 25°C, VDD = 3.3 V, unless otherwise noted. Table 2. Parameter fSCLK tSTALL 2 tCLS tCHS tCS Description Serial clock Stall period between data Serial clock low period Serial clock high period Chip select to clock edge tDAV tDSU tDHD tDR, tDF tDSOE tHD tSFS tDSHI tNV t1 t2 t3 DOUT valid after SCLK edge DIN setup time before SCLK rising edge DIN hold time after SCLK rising edge DOUT rise/fall times, ≤100 pF loading CS assertion to data out active SCLK edge to data out invalid Last SCLK edge to CS deassertion CS deassertion to data out high impedance Data invalid time Input sync pulse width Input sync to data invalid Input sync period 3 1 2 3 Min 1 0.01 5 31 31 32 Typ Max1 15 Unit MHz µs ns ns ns 10 ns ns ns ns ns ns ns ns µs µs µs µs 2 2 3 0 0 32 0 11 8 11 9 15 5 233 222.2 Guaranteed by design and characterization, but not tested in production. See Table 3 for exceptions to the stall time rating. Note that an insufficient stall time results in reading all 0s for the register attempting to be read. This measurement represents the inverse of the maximum frequency for the input sample clock: 4500 Hz. Register Specific Stall Times Table 3. Parameter STALL TIME FNCTIO_CTRL FILTR_BNK_0 FILTR_BNK_1 NULL_CNFG SYNC_SCALE DEC_RATE GPIO_CTRL CONFIG GLOB_CMD[1] GLOB_CMD[3] GLOB_CMD[6] GLOB_CMD[7] 1 Description Min 1 Configure DIOx functions Enable/select FIR filter banks Enable/select FIR filter banks Configure autonull bias function Configure input clock scale factor Configure decimation rate Configure general-purpose I/O lines Configure miscellaneous functions On demand self test Flash memory update Factory calibration restore Software reset 340 65 65 71 340 340 45 45 40 1.24 350 130 Typ Max Monitoring the data ready signal (see Table 131 for FNCTIO_CTRL configuration) for the return of regular pulsing can help minimize system wait times. Rev. D | Page 5 of 37 Unit μs μs μs μs μs μs μs μs ms sec μs ms ADIS16490 Data Sheet Timing Diagrams CS tCHS tCS 1 2 3 tCLS 4 5 tSFS 6 15 16 SCLK tDAV MSB DOUT DB14 tHD DB13 R/W A6 DB11 DB10 DB2 tDSHI DB1 tDHD tDSU DIN DB12 tDR A5 LSB tDF A4 A3 A2 D2 D1 15029-002 tDSOE LSB Figure 2. SPI Timing and Sequence tSTALL 15029-003 CS SCLK Figure 3. Stall Time and Data Rate t2 t3 t1 DIO4 (SYNC CLOCK) DATA READY DATA VALID DATA VALID Figure 4. Input Clock Timing Diagram, FNCTIO_CTRL[7:4] = 0xFD Rev. D | Page 6 of 37 15029-004 OUTPUT REGISTERS tNV Data Sheet ADIS16490 ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE Table 4. Parameter Acceleration Any Axis, Unpowered Any Axis, Powered VDD to GND Digital Input Voltage to GND Digital Output Voltage to GND Operating Temperature Range Storage Temperature Range1 Barometric Pressure 1 Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. Rating 1500 g 1500 g −0.3 V to +3.6 V −0.3 V to VDD + 0.2 V −0.3 V to VDD + 0.2 V −40°C to +105°C −55°C to +150°C 2 bar θJA is the natural convection junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. θJC is the junction to case thermal resistance. Extended exposure to temperatures that are lower than −40°C or higher than +105°C can adversely affect the accuracy of the factory calibration. Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. The ADIS16490 is a multichip module, which includes many active components. The values in Table 5 identify the thermal response of the hottest component inside of the ADIS16490, with respect to the overall power dissipation of the module. This approach enables a simple method for predicting the temperature of the hottest junction, based on either ambient or case temperature. For example, when the ambient temperature is 70°C, the hottest junction inside of the ADIS16490 is 76.7°C. TJ = θJA × VDD × IDD + 70°C TJ = 22.8°C/W × 3.3 V × 0.089 A + 70°C TJ = 76.7°C Table 5. Package Characteristics Package Type ML-24-91 1 θJA 30.7°C/W θJC 20.9°C/W Device Weight 42 g Thermal impedance simulated values come from a case when 4 M2 × 0.4 mm machine screws (torque = 20 inch-ounces) secure the ADIS16490 to the printed circuit board. ESD CAUTION Rev. D | Page 7 of 37 ADIS16490 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADIS16490 DNC DNC DNC DNC DNC GND NO PIN VDD RST CS DOUT DIO4 TOP VIEW (Not to Scale) 24 22 20 18 16 14 12 10 8 6 4 2 PIN 23 19 17 15 13 11 9 7 5 3 1 DNC DNC DNC NO PIN GND VDD DIO2 DIO1 DIN SCLK DIO3 NOTES 1. THIS REPRESENTATION DISPLAYS THE TOP VIEW PINOUT FOR THE MATING SOCKET CONNECTOR. 2. THE ACTUAL CONNECTOR PINS ARE NOT VISIBLE FROM THE TOP VIEW. 3. MATING CONNECTOR: SAMTEC CLM-112-02 OR EQUIVALENT. 4. DNC = DO NOT CONNECT. 5. PIN 12 AND PIN 15 ARE NOT PHYSICALLY PRESENT. PIN 1 PIN 2 15029-006 21 15029-005 23 DNC PIN 1 Figure 6. Axial Orientation (Top Side Facing Up) Figure 5. Pin Configuration Table 6. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10, 11 12, 15 13, 14 16 to 22, 24 23 Mnemonic DIO3 DIO4 SCLK DOUT DIN CS DIO1 RST DIO2 VDD NO PIN GND DNC Type Input/output Input/output Input Output Input Input Input/output Input Input/output Supply Not applicable Supply Not applicable Description Configurable Digital Input/Output 3. Configurable Digital Input/Output 4. SPI Serial Clock. SPI Data Output. Clocks output on the SCLK falling edge. SPI Data Input. Clocks input on the SCLK rising edge. SPI Chip Select. Configurable Digital Input/Output 1. Reset. Configurable Digital Input/Output 2. Power Supply. These pins are not physically present. Power Ground. Do Not Connect. Do not connect to these pins. DNC Not applicable Do Not Connect. Do not connect to this pin. This pin can tolerate connection to 3.3 V. Rev. D | Page 8 of 37 Data Sheet ADIS16490 TYPICAL PERFORMANCE CHARACTERISTICS 0.4 ROOT ALLAN VARIANCE (Degrees/Hour) 100 BIAS ERROR (°/sec) 0.2 10 AVERAGE µ + 1σ µ – 1σ 1 µ + 3σ µ 0 µ – 3σ 100 10 1 10000 1000 Tau (Seconds) –0.4 –45 –35 –25 –15 –5 Figure 7. Gyroscope Root Allan Variance 25 35 45 55 65 75 85 0.1 µ + 3σ µ 0 µ – 3σ –0.2 –0.4 –45 –35 –25 –15 –5 5 15 25 35 45 55 65 75 85 CASE TEMPERATURE (°C) Figure 8. Gyroscope Sensitivity Error, −40°C to +85°C, 1°C/min 0.1 µ + 3σ µ 0 µ – 3σ –0.1 –0.1 –45 –35 –25 –15 –5 5 15 25 35 45 55 65 75 85 CASE TEMPERATURE (°C) 15029-313 MISALIGNMENT ERROR (Degrees) 0.2 15029-308 SENSITIVITY ERROR (%) 15 Figure 10. Gyroscope Bias Error, −40°C to +85°C, 1°C/min 0.4 Figure 11. Gyroscope Axis to Axis Misalignment Error, −40°C to +85°C 0.4 GYROSCOPE NOISE DENSITY (°/s/√Hz) 100 0.2 µ + 3σ 0 µ –0.2 µ – 3σ –0.4 –45 –35 –25 –15 –5 5 15 25 35 45 55 65 75 85 CASE TEMPERATURE (°C) 15029-309 SENSITIVITY ERROR (%) 5 CASE TEMPERATURE (°C) 10 1 0.1 0.01 0.1 1 10 100 1k FREQUENCY (Hz) Figure 9. Gyroscope Sensitivity Error, +85°C to −40°C, 1°C/min Figure 12. Gyroscope Noise Density, TC = 25°C Rev. D | Page 9 of 37 10k 15029-314 0.1 15029-307 0.1 0.01 15029-310 –0.2 ADIS16490 Data Sheet 0.20 3σ X Y Z 0.15 0.5 SENSITIVITY ERROR (%) NONLINEARITY (% FS) 1.0 0 –0.5 0.10 µ + 3σ 0.05 0 µ –0.05 µ – 3σ –0.10 –80 –60 –40 –20 0 20 40 60 80 100 RATE (°/sec) –0.20 –45 –35 –25 –15 –5 15029-315 –1.5 –100 5 15 25 35 45 55 65 75 85 CASE TEMPERATURE (°C) Figure 13. Gyrscope Nonlinearity 15029-318 –0.15 Figure 16. Accelerometer Sensitivity Error, +85°C to −40°C, 1°C/min 1k 4 2 100 BIAS ERROR (mg) ROOT ALLAN VARIANCE (µg) 3 10 µ + 1σ µ 1 µ + 3σ 0 µ –1 µ – 3σ –2 –3 1 10 100 1k 10k Tau (Seconds) –4 –45 –35 –25 –15 –5 0.20 0.20 0.15 0.15 0.10 µ + 3σ 0 µ –0.05 µ – 3σ –0.10 15 25 35 45 55 65 75 85 Figure 17. Accelerometer Bias Error, −40°C to +85°C, 1°C/min MISALIGNMENT ERROR (Degrees) SENSITIVITY ERROR (%) Figure 14. Accelerometer Root Allan Variance, 25°C 0.05 5 CASE TEMPERATURE (°C) 15029-319 0.1 –0.15 0.10 µ + 3σ 0.05 0 µ –0.05 µ – 3σ –0.10 –0.20 –45 –35 –25 –15 –5 5 15 25 35 45 55 65 75 85 CASE TEMPERATURE (°C) Figure 15. Accelerometer Sensitivity Error, −40°C to +85°C, 1°C/min 15029-317 –0.15 –0.20 –45 –35 –25 –15 –5 5 15 25 35 45 CASE TEMPERATURE (°C) 55 65 75 85 15029-321 1 0.01 15029-316 µ – 1σ Figure 18. Accelerometer Axis to Axis Misalignment Error, −40°C to +85°C Rev. D | Page 10 of 37 Data Sheet ADIS16490 400 20 X Y Z 300 GYROSCOPE BIAS (°/Hour) 0 –40 –60 –80 –100 +3σ 100 0 –100 –3σ –200 200 15029-322 –300 –120 20 2000 FREQUENCY (Hz) Figure 19. Accelerometer Vibration Response (Swept Sine, 2 g peak) 2 1 0 –1 –2 2g FIT 4g FIT 8g FIT –6 –4 –2 0 2 4 6 LINEAR FORCE (g) 8 15029-323 –3 –8 –400 0 0.5 1.0 1.2 2.0 2.5 3.0 3.5 4.0 4.5 TIME FROM INITIAL TURN-ON (Minutes) Figure 21. Gyroscope Bias vs. Time from Initial Turn-On 3 NONLINEARITY (% FS) 200 Figure 20. Accelerometer Nonlinearity (FIT Is Curve Fit) Rev. D | Page 11 of 37 5.0 15029-311 MAGNITUDE (dB) –20 ADIS16490 Data Sheet The ADIS16490 is an autonomous sensor system. A power-on self test begins automatically after the voltage on the power supply pins reaches a minimum safe level as defined by Table 1. After the automatic power-on self test, the ADIS16490 begins sampling, processing, and loading calibrated sensor data into the output registers, which are accessible using the SPI port. INERTIAL SENSOR SIGNAL CHAIN MEMS SENSORS CALIBRATION FILTERING OUTPUT DATA REGISTERS The ADIS16490 offers two modes of operation to control data production with an external clock: sync mode and pulse per second (PPS) mode. In sync mode, the external clock directly controls the data sampling and production clock (fSM in Figure 23 and Figure 24). In PPS mode, users can provide a lower input clock rate (1 Hz to 128 Hz) and use a scale factor (SYNC_SCALE register, see Table 141) to establish a data collection and processing rate that is between 3000 Hz and 4250 Hz for best performance. Inertial Sensor Calibration The calibration function for the gyroscopes and the accelerometers has two components: factory calibration and user calibration (see Figure 25). 15029-211 Figure 22 provides the basic signal chain for the inertial sensors in the ADIS16490, which processes data at a rate of 4250 SPS when using the internal sample clock. Using one of the external clock options in FNCTIO_CTRL[7:4] (see Table 131) can provide flexibility in selecting this rate. External Clock Options FROM SENSORS Figure 22. Signal Processing Diagram, Inertial Sensors FACTORY CALIBRATION USER CALIBRATION TO FILTERING 15029-214 THEORY OF OPERATION Figure 25. Gyroscope Calibration Processing Gyroscope Data Sampling Gyroscope Factory Calibration The ADIS16490 produces angular rate measurements around three orthogonal axes (x, y, and z). Figure 23 shows the basic signal flow for the production of x-axis gyroscope data (same as y-axis and z-axis). This signal chain contains two digital MEMS gyroscopes (XG1 and XG2), which have their own ADC and sample clocks (fSGX1 and fSGX2 = 4100 Hz that produce data independently from each other. The sensor to sensor tolerance on this sample rate is ±200 SPS. Processing these data starts with combining (summation and rescale) the most recent sample from each gyroscope together by using an independent sample master frequency (fSM) clock (fSM = 4250 Hz, see Figure 23), which drives the rest of the digital signal processing (calibration, alignment, and filtering) for the gyroscopes and accelerometers. Gyroscope factory calibration applies the following correction formula to the data of each gyroscope: ADC X-AXIS RATE DATA SAMPLE 1 X-AXIS ANGULAR RATE DATA PROCESSING fSGX1 = 4100Hz MEMS GYROSCOPE XG2 ADC X-AXIS RATE DATA SAMPLE 2 fSGX2 = 4100Hz 15029-212 MEMS GYROSCOPE XG1 fSM = 4250Hz Figure 23. Gyroscope Data Sampling Accelerometer Data Sampling The ADIS16490 produces linear acceleration measurements along the same orthogonal axes (x, y, and z) as the gyroscopes, using the same clock (fSM, see Figure 23 and Figure 24) that triggers data acquisition and subsequent processing of the gyroscope data. ADC X-AXIS ACCELERATION DATA PROCESSING fSM = 4250SPS (1) where: ωXC, ωYC, and ωZC are the postcalibration gyroscope data. m11, m12, m13, m21, m22, m23, m31, m32, and m33 are the scale and alignment correction factors. ωX, ωY, and ωZ are the precalibration gyroscope data. bX, bY, and bZ are the bias correction factors. g11, g12, g13, g21, g22, g23, g31, g32, and g33 are the linear g correction factors. a'X, a'Y, and a'Z are the postcalibration accelerometer data. All the correction factors in each matrix/array are derived from direct observation of the response of each gyroscope to a variety of rotation rates at multiple temperatures across the calibration temperature range (−40°C ≤ TC ≤ +85°C). These correction factors are stored in the flash memory bank, but they are not available for observation. CONFIG[7] provides an on/off control for the linear g compensation (see Table 135). See Figure 46 for more details on the user calibration options that are available for the gyroscopes. 15029-213 X-AXIS MEMS ACCELEROMETER ω  bX   m11 m12 m13   ω   XC       X   ω YC  = m21 m22 m23  ×  ω Y  + bY   + ω  b   m31 m32 m33   ω      Z   Z    ZC   g 11 g 12 g 13  a' X       g 21 g 22 g 23  × a'Y   g 31 g 32 g 33  a'     Z Figure 24. Accelerometer Data Sampling Rev. D | Page 12 of 37 Data Sheet ADIS16490 Accelerometer Factory Calibration The decimation filter averages multiple samples together to produce each register update. In this type of filter structure, the number of samples in the average is equal to the reduction in the update rate for the output data registers. See the DEC_RATE register for the user controls for this filter (see Table 137). The accelerometer factory calibration applies the following correction formulas to the data of each accelerometer: m13   a X  bX         m23  ×  aY  + bY   + m33   aZ  bZ   p13  ω2XC    2  p23  ×  ωYC  0   ω2ZC  a' X  m11 m12    a'Y  = m21 m22 a' Z  m31 m32    0 p32 where: aX, aY, and aZ are the precalibration accelerometer data. a'X, a'Y, and a'Z are the postcalibration accelerometer data. m11, m12, m13, m21, m22, m23, m31, m32, and m33 are the scale and alignment correction factors. bX, bY, and bZ are the bias correction factors. 0, p12, p13, p21, 0, p23, p31, p32, and 0 are the point of percussion correction factors ω2XC, ω2YC, and ω2ZC are the postcalibration gyroscope data (squared). All the correction factors in each matrix/array are derived from direct observation of the response of each accelerometer to a variety of inertial test conditions at multiple temperatures across the calibration temperature range (−40°C ≤ TC ≤ +85°C). These correction factors are stored in the flash memory bank, but they are not available for observation. CONFIG[6] provides an on/off control for the point of percussion alignment (see Table 135). See Figure 47 for more details on the user calibration options that are available for the accelerometers. Filtering FROM CALIBRATION FIR FILTER DECIMATION FILTER TO DATA REGISTERS 15029-215 After calibration, the data of each inertial sensor passes through two digital filters, both of which have user configurable attributes: FIR and decimation (see Figure 26). Figure 26. Inertial Sensor Filtering The FIR filter includes four banks of coefficients that have 120 taps each. FILTR_BNK_0 (see Table 143) and FILTR_BNK_1 (see Table 145) provide the configuration options for the use of the FIR filters of each inertial sensor. Each FIR filter bank includes a preconfigured filter, but users can design their own filters and write over these values using the register of each coefficient. For example, Table 174 provides the details for FIR_COEF_A071, which contains Coefficient 71 in FIR Bank A. Refer to Figure 50 for the frequency response of the factory default filters. These filters do not represent any specific application environment; they are only examples. All communication with the ADIS16490 involves accessing its user registers. The register structure contains both output data and control registers. The output data registers include the latest sensor data, error flags, and identification data. The control registers include sample rate, filtering, input/output, calibration, and diagnostic configuration options. All communication between the ADIS16490 and an external processor involves either reading or writing to one of the user registers. TRIAXIS GYRO ADC DSP OUTPUT REGISTERS TRIAXIS ACCEL TEMP SENSOR CONTROLLER CONTROL REGISTERS 15029-012 p12 SPI 0   p21  p31  REGISTER STRUCTURE (2) Figure 27. Basic Operation The register structure uses a paged addressing scheme that contains 13 pages, with each page containing 64 register locations. Each register is 16 bits wide, with each byte having its own unique address within the memory map of that page. The SPI port has access to one page at a time, using the bit sequence in Figure 28. Select the page to activate for SPI access by writing its code to the PAGE_ID register. Read the PAGE_ID register to determine which page is currently active. Table 7 displays the PAGE_ID contents for each page and their basic functions. The PAGE_ID register is located at Address 0x00 on every page. Table 7. User Register Page Assignments Page 0 1 2 3 4 5 6 7 8 9 10 11 12 Rev. D | Page 13 of 37 PAGE_ID 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0B 0x0C Function Output data, clock, identification Reserved Calibration Control: sample rate, filtering, I/O Serial number, CRC values FIR Filter Bank A, Coefficient 0 to Coefficient 59 FIR Filter Bank A, Coefficient 60 to Coefficient 119 FIR Filter Bank B, Coefficient 0 to Coefficient 59 FIR Filter Bank B, Coefficient 60 to Coefficient 119 FIR Filter Bank C, Coefficient 0 to Coefficient 59 FIR Filter Bank C, Coefficient 60 to Coefficient 119 FIR Filter Bank D, Coefficient 0 to Coefficient 59 FIR Filter Bank D, Coefficient 60 to Coefficient 119 ADIS16490 Data Sheet CS DIN R/W DOUT D15 A6 A5 A4 A3 A2 A1 A0 D14 D13 D12 D11 D10 D9 D8 DC7 DC6 D7 D6 DC5 DC4 DC3 DC2 DC1 DC0 D5 D4 D3 D2 D1 D0 R/W D15 A6 A5 D14 D13 NOTES 1. DOUT BITS ARE PRODUCED ONLY WHEN THE PREVIOUS 16-BIT DIN SEQUENCE STARTS WITH R/W = 0. 2. WHEN CS IS HIGH, DOUT IS IN A THREE-STATE, HIGH IMPEDANCE MODE, WHICH ALLOWS MULTIFUNCTIONAL USE OF THE LINE FOR OTHER DEVICES. 15029-013 SCLK Figure 28. SPI Communication Bit Sequence DATA READY The serial peripheral interface (SPI) provides access to the user register structures and typically connects to a compatible port on an embedded processor, using the connection diagram shown in Figure 29. The four SPI signals facilitate synchronous, serial data communication. The factory default configuration provides users with a data ready (DR) signal on the DIO2 pin, which pulses low when the output data registers are updating (see Figure 30). In this configuration, connect DIO2 to a pin on the embedded processor, which triggers data collection, when this signal pulses high. Register FNCTIO_ CTRL[3:0] (see Table 131) provides user configuration options for this function. I/O LINES ARE COMPATIBLE WITH 3.3V LOGIC LEVELS 3.3V VDD 11 10 6 CS SCLK 3 SCLK MOSI 5 DIN MISO 4 DOUT IRQ 9 DIO2 DIO2 ACTIVE ADIS16490 Figure 30. Data Ready, When FNCTIO_CTRL[3:0] = 1101 (default) 14 15029-011 13 During the start-up and reset recovery processes, the DR signal can exhibit transient behavior before data production begins. Figure 31 provides an example of the DR behavior during startup, and Figure 32 and Figure 33 provide examples of the DR behavior during recovery from reset commands. TIME THAT VDD > 3V Figure 29. Electrical Connection Diagram Table 8. Generic Master Processor Pin Names and Functions Mnemonic SS IRQ MOSI MISO SCLK VDD PULSING INDICATES DATA PRODUCTION Function Slave select Interrupt request Master output, slave input Master input, slave output Serial clock DR START-UP TIME Figure 31. Data Ready Response During Startup Embedded processors typically use control registers to configure their serial ports for communicating with SPI slave devices such as the ADIS16490. Table 9 provides a list of settings that describe the SPI protocol of the ADIS16490. The initialization routine of the master processor typically establishes these settings using firmware commands to write them into its serial control registers. SOFTWARE RESET COMMAND GLOB_CMD[7] = 1 DR PULSING RESUMES DR RESET RECOVERY TIME Figure 32. Data Ready Response During Reset (Register GLOB_CMD, Bit 7 = 1) Recovery Table 9. Generic Master Processor SPI Settings Processor Setting Master SCLK ≤ 15 MHz SPI Mode 3 MSB First Mode 16-Bit Mode INACTIVE 15029-122 SS Description ADIS16490 operates as slave Maximum serial clock rate CPOL = 1 (polarity), CPHA = 1 (phase) Bit sequence, see Figure 28 for coding Shift register/data length Rev. D | Page 14 of 37 15029-123 SYSTEM PROCESSOR SPI MASTER 15029-129 SERIAL PERIPHERAL INTERFACE Data Sheet ADIS16490 Each byte has its own unique address in the user register map (see Table 10). Updating the contents of a register requires writing to its low byte first and its high byte second. There are three parts to coding a SPI command (see Figure 28), which writes a new byte of data to a register: the write bit (R/W = 1), the address of the byte, [A6:A0], and the new data for that location, [DC7:DC0]. Figure 36 provides a coding example for writing 0xFEDC to the XG_BIAS_LOW register (see Table 93), assuming that PAGE_ID already equals 0x0002. RST PIN RELEASED DR PULSING RESUMES 15029-124 DR RESET RECOVERY TIME Figure 33. Data Ready Response During Reset (RST = 0) Recovery CS READING SENSOR DATA DIN DOUT 0x1A00 0x1800 NEXT ADDRESS Z_GYRO_OUT Z_GYRO_LOW 15029-016 Reading a single register requires two 16-bit cycles on the SPI: one to request the contents of a register and another to receive those contents. The 16-bit command code (see Figure 28) for a read request on the SPI has three parts: the read bit (R/W = 0), either address of the register, [A6:A0], and eight don’t care bits, [DC7:DC0]. Figure 34 provides an example that includes two register reads in succession. This example starts with DIN = 0x1A00, to request the contents of the Z_GYRO_OUT register, and follows with 0x1800, to request the contents of the Z_GYRO_LOW register (assuming PAGE_ID already equals 0x0000). The sequence in Figure 34 also illustrates full duplex mode of operation, which means that the ADIS16490 can receive requests on DIN while also transmitting data out on DOUT within the same 16-bit SPI cycle. Figure 34. SPI Read Example Figure 35 provides an example of the four SPI signals when reading the PROD_ID register (see Table 79) in a repeating pattern. This pattern can be helpful when troubleshooting the SPI interface setup and communications. CS SCLK DIN 0x90DC 0x91FE Figure 36. SPI Sequence for Writing 0xFEDC to XG_BIAS_LOW Dual Memory Structure The ADIS16490 uses a dual memory structure (see Figure 37), with SRAM supporting real-time operation and flash memory storing operational code, calibration coefficients, and user configurable register settings. The manual flash update command (GLOB_CMD[3], see Table 129) provides a single-command method for storing user configuration settings into flash memory, for automatic recall during the next power-on or reset recovery process. This portion of the flash memory bank has two independent banks that operate in a ping pong manner, alternating with every flash update. During power-on or reset recovery, the ADIS16490 performs a cyclic redundancy check (CRC) on the SRAM and compares it to a CRC computation from the same memory locations in flash memory. If this fails, the ADIS16490 resets and boots up from the other flash memory location. SYS_E_FLAG[2] (see Table 16) provides an error flag for detecting when the back-up flash memory supported the last power-on or reset recovery. Table 10 provides a memory map for the user registers in the ADIS16490, which includes flash backup support (indicated by yes or no in the flash column). 15029-017 DIN = 0111 1110 0000 0000 = 0x7E00 DOUT DOUT = 0100 0000 0110 1010 = 0x406A = 16,490 (PROD_ID) NONVOLATILE FLASH MEMORY VOLATILE SRAM (NO SPI ACCESS) SPI ACCESS START-UP RESET Figure 35. SPI Read Example, Second 16-Bit Sequence DEVICE CONFIGURATION Each register contains 16 bits (two bytes). Bits[7:0] contain the low byte and Bits[15:8] contain the high byte of each register. Rev. D | Page 15 of 37 Figure 37. SRAM and Flash Memory Diagram 15029-015 MANUAL FLASH BACKUP SCLK DIN 15029-014 RST ADIS16490 Data Sheet USER REGISTER MEMORY MAP Table 10. User Register Memory Map (N/A Means Not Applicable) Name PAGE_ID Reserved DATA_CNT Reserved SYS_E_FLAG DIAG_STS Reserved TEMP_OUT X_GYRO_LOW X_GYRO_OUT Y_GYRO_LOW Y_GYRO_OUT Z_GYRO_LOW Z_GYRO_OUT X_ACCL_LOW X_ACCL_OUT Y_ACCL_LOW Y_ACCL_OUT Z_ACCL_LOW Z_ACCL_OUT TIME_STAMP Reserved X_DELTANG_LOW X_DELTANG_OUT Y_DELTANG_LOW Y_DELTANG_OUT Z_DELTANG_LOW Z_DELTANG_OUT X_DELTVEL_LOW X_DELTVEL_OUT Y_DELTVEL_LOW Y_DELTVEL_OUT Z_DELTVEL_LOW Z_DELTVEL_OUT Reserved PROD_ID Reserved PAGE_ID Reserved X_GYRO_SCALE Y_GYRO_SCALE Z_GYRO_SCALE X_ACCL_SCALE Y_ACCL_SCALE Z_ACCL_SCALE XG_BIAS_LOW XG_BIAS_HIGH YG_BIAS_LOW YG_BIAS_HIGH ZG_BIAS_LOW R/W R/W N/A R N/A R R N/A R R R R R R R R R R R R R R N/A R R R R R R R R R R R R N/A R N/A R/W N/A R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Flash Backup No N/A No N/A No No N/A No No No No No No No No No No No No No No N/A No No No No No No No No No No No No N/A Yes N/A No N/A Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes PAGE_ID 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x01 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 Address 0x00, 0x01 0x02, 0x03 0x04, 0x05 0x06, 0x07 0x08, 0x09 0x0A, 0x0B 0x0C, 0x0D 0x0E, 0x0F 0x10, 0x11 0x12, 0x13 0x14, 0x15 0x16, 0x17 0x18, 0x19 0x1A, 0x1B 0x1C, 0x1D 0x1E, 0x1F 0x20, 0x21 0x22, 0x23 0x24, 0x25 0x26, 0x27 0x28, 0x29 0x2A to 0x3F 0x40, 0x41 0x42, 0x43 0x44, 0x45 0x46, 0x47 0x48, 0x49 0x4A, 0x4B 0x4C, 0x4D 0x4E, 0x4F 0x50, 0x51 0x52, 0x53 0x54, 0x55 0x56, 0x57 0x58 to 0x7D 0x7E, 0x7F 0x00 to 0x7F 0x00, 0x01 0x02, 0x03 0x04, 0x05 0x06, 0x07 0x08, 0x09 0x0A, 0x0B 0x0C, 0x0D 0x0E, 0x0F 0x10, 0x11 0x12, 0x13 0x14, 0x15 0x16, 0x17 0x18, 0x19 Default 0x0000 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 0x406A N/A 0x0000 N/A 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 Rev. D | Page 16 of 37 Register Description Page identifier Reserved Data counter Reserved Output, system error flags (0x0000 if no errors) Output, self test error flags (0x0000 if no errors) Reserved Output, temperature Output, x-axis gyroscope, low word Output, x-axis gyroscope, high word Output, y-axis gyroscope, low word Output, y-axis gyroscope, high word Output, z-axis gyroscope, low word Output, z-axis gyroscope, high word Output, x-axis accelerometer, low word Output, x-axis accelerometer, high word Output, y-axis accelerometer, low word Output, y-axis accelerometer, high word Output, z-axis accelerometer, low word Output, z-axis accelerometer, high word Output, time stamp Reserved Output, x-axis delta angle, low word Output, x-axis delta angle, high word Output, y-axis delta angle, low word Output, y-axis delta angle, high word Output, z-axis delta angle, low word Output, z-axis delta angle, high word Output, x-axis delta velocity, low word Output, x-axis delta velocity, high word Output, y-axis delta velocity, low word Output, y-axis delta velocity, high word Output, z-axis delta velocity, low word Output, z-axis delta velocity, high word Reserved Output, product identification (16490d) Reserved Page identifier Reserved Calibration, scale, x-axis gyroscope Calibration, scale, y-axis gyroscope Calibration, scale, z-axis gyroscope Calibration, scale, x-axis accelerometer Calibration, scale, y-axis accelerometer Calibration, scale, z-axis accelerometer Calibration, bias, gyroscope, x-axis, low word Calibration, bias, gyroscope, x-axis, high word Calibration, bias, gyroscope, y-axis, low word Calibration, bias, gyroscope, y-axis, high word Calibration, bias, gyroscope, z-axis, low word Data Sheet Name ZG_BIAS_HIGH XA_BIAS_LOW XA_BIAS_HIGH YA_BIAS_LOW YA_BIAS_HIGH ZA_BIAS_LOW ZA_BIAS_HIGH Reserved USER_SCR_1 USER_SCR_2 USER_SCR_3 USER_SCR_4 FLSHCNT_LOW FLSHCNT_HIGH PAGE_ID GLOB_CMD Reserved FNCTIO_CTRL GPIO_CTRL CONFIG DEC_RATE NULL_CNFG SYNC_SCALE Reserved FILTR_BNK_0 FILTR_BNK_1 Reserved FIRM_REV FIRM_DM FIRM_Y BOOT_REV PAGE_ID Reserved CAL_SIGTR_LWR CAL_SIGTR_UPR CAL_DRVTN_LWR CAL_DRVTN_UPR CODE_SIGTR_LWR CODE_SIGTR_UPR CODE_DRVTN_LWR CODE_DRVTN_UPR Reserved SERIAL_NUM Reserved PAGE_ID Reserved FIR_COEF_Axxx 2 PAGE_ID Reserved FIR_COEF_Axxx2 PAGE_ID Reserved FIR_COEF_Bxxx 3 ADIS16490 R/W R/W R/W R/W R/W R/W R/W R/W N/A R/W R/W R/W R/W R R R/W W N/A R/W R/W R/W R/W R/W R/W N/A R/W R/W N/A R R R R R/W N/A R R R R R R R R N/A R N/A R/W N/A R/W R/W N/A R/W R/W N/A R/W Flash Backup Yes Yes Yes Yes Yes Yes Yes N/A Yes Yes Yes Yes Yes Yes No No N/A Yes Yes Yes Yes Yes Yes N/A Yes Yes N/A Yes Yes Yes Yes No N/A Yes Yes No No Yes Yes No No N/A Yes N/A No N/A Yes No N/A Yes No N/A Yes PAGE_ID 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x02 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x03 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x04 0x05 0x05 0x05 0x06 0x06 0x06 0x07 0x07 0x07 Address 0x1A, 0x1B 0x1C, 0x1D 0x1E, 0x1F 0x20, 0x21 0x22, 0x23 0x24, 0x25 0x26, 0x27 0x28 to 0x73 0x74, 0x75 0x76, 0x77 0x78, 0x79 0x7A, 0x7B 0x7C, 0x7D 0x7E, 07F 0x00, 0x01 0x02, 0x03 0x04, 0x05 0x06, 0x07 0x08, 0x09 0x0A, 0x0B 0x0C, 0x0D 0x0E, 0x0F 0x10, 0x11 0x12 to 0x15 0x16, 0x17 0x18, 0x19 0x1A to 0x77 0x78, 0x79 0x7A, 0x7B 0x7C, 0x7D 0x7E, 0x7F 0x00, 0x01 0x02, 0x03 0x04, 0x05 0x06, 0x07 0x08, 0x09 0x0A, 0x0B 0x0C, 0x0D 0x0E, 0x0F 0x10, 0x11 0x12, 0x13 0x1C to 0x1F 0x20, 0x21 0x22 to 0x7F 0x00, 0x01 0x02 to 0x07 0x08 to 0x7F 0x00 0x02 to 0x07 0x08 to 0x7F 0x00, 0x01 0x02 to 0x07 0x08 to 0x7F Default 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 0x0000 N/A N/A 0x0000 N/A N/A 0x000D 0x00X0 1 0x00C0 0x0000 0x070A 0x109A N/A 0x0000 0x0000 N/A N/A N/A N/A N/A 0x0000 N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A N/A 0x0000 N/A N/A 0x0000 N/A N/A 0x0000 N/A N/A Rev. D | Page 17 of 37 Register Description Calibration, bias, gyroscope, z-axis, high word Calibration, bias, accelerometer, x-axis, low word Calibration, bias, accelerometer, x-axis, high word Calibration, bias, accelerometer, y-axis, low word Calibration, bias, accelerometer, y-axis, high word Calibration, bias, accelerometer, z-axis, low word Calibration, bias, accelerometer, z-axis, high word Reserved User Scratch Register 1 User Scratch Register 2 User Scratch Register 3 User Scratch Register 4 Diagnostic, flash memory count, low word Diagnostic, flash memory count, high word Page identifier Control, global commands Reserved Control, I/O pins, functional definitions Control, I/O pins, general purpose Control, clock, and miscellaneous correction Control, output sample rate decimation Control, automatic bias correction configuration Input clock scaling (PPS mode) Reserved Filter selection Filter selection Reserved Firmware revision Firmware programming date: day/month Firmware programming date: year Boot loader revision Page identifier Reserved Signature CRC, calibration coefficients, low word Signature CRC, calibration coefficients, high word Real-time CRC, calibration coefficients, low word Real-time CRC, calibration coefficients, high word Signature CRC, program code, low word Signature CRC, program code, high word Real-time CRC, program code, low word Real-time CRC, program code, high word Reserved Serial number Reserved Page identifier Reserved FIR Filter Bank A: Coefficient 0 through Coefficient 59 Page identifier Reserved FIR Filter Bank A: Coefficient 60 through Coefficient 119 Page identifier Reserved FIR Filter Bank B: Coefficient 0 through Coefficient 59 ADIS16490 Name PAGE_ID Reserved FIR_COEF_Bxxx3 PAGE_ID Reserved FIR_COEF_Cxxx 4 PAGE_ID Reserved FIR_COEF_Cxxx4 PAGE_ID Reserved FIR_COEF_Dxxx 5 PAGE_ID Reserved FIR_COEF_Dxxx5 Data Sheet R/W R/W N/A R/W R/W N/A R/W R/W N/A R/W R/W N/A R/W R/W N/A R/W Flash Backup No N/A Yes No N/A Yes No N/A Yes No N/A Yes No N/A Yes PAGE_ID 0x08 0x08 0x08 0x09 0x09 0x09 0x0A 0x0A 0x0A 0x0B 0x0B 0x0B 0x0C 0x0C 0x0C Address 0x00, 0x01 0x02 to 0x07 0x08 to 0x7F 0x00, 0x01 0x02 to 0x07 0x08 to 0x7F 0x00, 0x01 0x02 to 0x07 0x08 to 0x7F 0x00, 0x01 0x02 to 0x07 0x08 to 0x7F 0x00, 0x01 0x02 to 0x07 0x08 to 0x7F Default 0x0000 N/A N/A 0x0000 N/A N/A 0x0000 N/A N/A 0x0000 N/A N/A 0x0000 N/A N/A The GPIO_CTRL[7:4] bits reflect the logic levels on the DIOx lines and do not have a default setting. See the FIR Filter Bank A, FIR_COEF_A000 to FIR_COEF_A119 section for additional information. 3 See the FIR Filter Bank B, FIR_COEF_B000 to FIR_COEF_B119 section for additional information. 4 See the FIR Filter Bank C, FIR_COEF_C000 to FIR_COEF_C119 section for additional information. 5 See the FIR Filter Bank D, FIR_COEF_D000 to FIR_COEF_D119 section for additional information. 1 2 Rev. D | Page 18 of 37 Register Description Page identifier Reserved FIR Filter Bank B: Coefficient 60 through Coefficient 119 Page identifier Reserved FIR Filter Bank C: Coefficient 0 through Coefficient 59 Page identifier Reserved FIR Filter Bank C: Coefficient 60 through Coefficient 119 Page identifier Reserved FIR Filter Bank D: Coefficient 0 through Coefficient 59 Page identifier Reserved FIR Filter Bank D: Coefficient 60 through Coefficient 119 Data Sheet ADIS16490 USER REGISTER DEFINTIONS Page Number (PAGE_ID) Table 16. SYS_E_FLAG Bit Assignments Table 11. PAGE_ID Register Definition Page 0x00 Addresses 0x00, 0x01 Default 0x0000 Access R/W Bits 15 Flash Backup No [14:9] 8 Table 12. PAGE_ID Bit Assignments Bits [15:0] Description Page number, binary numerical format The contents in the PAGE_ID register (see Table 11 and Table 12) contain the current page setting, and provide a control for selecting another page for SPI access. For example, set DIN = 0x8002 to select Page 2 for SPI-based user access. See Table 10 for the page assignments associated with each user accessible register. Data/Sample Counter (DATA_CNT) 7 6 Table 13. DATA_CNT Register Definition Page 0x00 Addresses 0x04, 0x05 Default Not applicable Access R Flash Backup No 5 Table 14. DATA_CNT Bit Assignments Bits [15:0] 4 3 Description Data counter, binary format. The DATA_CNT register (see Table 13 and Table 14) is a continuous, real-time, sample counter. It starts at 0x0000, increments every time that the output data registers update, and wraps around from 0xFFFF (65,535 decimal) to 0x0000 (0 decimal). 2 Status/Error Flag Indicators (SYS_E_FLAG) Table 15. SYS_E_FLAG Register Definition Page 0x00 Addresses 0x08, 0x09 Default 0x0000 Access R Flash Backup No 1 0 Description Watch dog timer flag. A 1 indicates that the ADIS16490 automatically resets itself to clear an issue. Not used. Sync error. A 1 indicates that the sample timing is not scaling correctly, when operating in PPS mode (FNCTIO_CTRL[8] = 1, see Table 131). When this error occurs, verify that the input sync frequency is correct and that SYNC_SCALE (see Table 141) has the correct value. Processing overrun. A 1 indicates occurrence of a processing overrun. Initiate a reset to recover. Replace the ADIS16490 if this error persists. Flash memory update failure. A 1 indicates that the most recent flash memory update failed (GLOB_CMD[3], see Table 129). Repeat the test and replace the ADIS16490 if this error persists. Sensor failure. A 1 indicates failure of the self test processes (GLOB_CMD[1], see Table 129), when the device is not in motion. Replace the ADIS16490 if the error persists. Not used. SPI communication error. A 1 indicates that the total number of SCLK cycles is not equal to an integer multiple of 16. Repeat the previous communication sequence to recover. Persistence in this error may indicate a weakness in the SPI service from the master processor. SRAM error condition. A 1 indicates a failure in the CRC (period = 20 ms) between the SRAM and flash memory. Initiate a reset to recover and replace the ADIS16490 if this error persists. Boot memory failure. A 1 indicates that the CRC on the primary flash memory bank did not match the reference CRC value and that the device automatically rebooted using the backup memory bank in flash. Replace the ADIS16490 if this error persists. Not used. The SYS_E_FLAG register (see Table 15 and Table 16) provides various error flags. Reading this register causes all of its bits to return to 0, with the exception of Bit 7. If an error condition persists, its flag (bit) automatically returns to an alarm value of 1. Rev. D | Page 19 of 37 ADIS16490 Data Sheet Self Test Error Flags (DIAG_STS) Z-AXIS Table 17. DIAG_STS Register Definition Page 0x00 Addresses 0x0A, 0x0B Default 0x0000 Access R ωZ Flash Backup No X-AXIS Y-AXIS Table 18. DIAG_STS Bit Definitions ωY 15029-018 ωX Description (Default = 0x0000) Not used Self test failure, z-axis accelerometer (1 = failure) Self test failure, y-axis accelerometer (1 = failure) Self test failure, x-axis accelerometer (1 = failure) Self test failure, z-axis gyroscope (1 = failure) Self test failure, y-axis gyroscope (1 = failure) Self test failure, x-axis gyroscope (1 = failure) PIN 23 PIN 1 Figure 38. Gyroscope Axis and Polarity Assignments Each gyroscope has two output data registers. Figure 39 illustrates how these two registers combine to support a 32-bit, twos complement data format for the x-axis gyroscope measurements. This format also applies to the y-axis and z-axis as well. SYS_E_FLAG[5] (see Table 16) contains the pass/fail result (0 = pass) for the on demand self test (ODST) operations, whereas the DIAG_STS register (see Table 17 and Table 18) contains pass/fail flags (0 = pass) for each inertial sensor. Reading the DIAG_STS register causes all of its bits to restore to 0. The bits in DIAG_STS return to 1 if the error conditions persists. X-Axis Gyroscope (X_GYRO_LOW, X_GYRO_OUT) Internal Temperature (TEMP_OUT) Table 22. X_GYRO_LOW Register Definition Table 19. TEMP_OUT Register Definition Page 0x00 Page 0x00 Addresses 0x0E, 0x0F Default Not applicable Access R Flash Backup No Table 20. TEMP_OUT Bit Definitions Bits [15:0] Description Temperature data; twos complement, 1°C per 70 LSB, 25°C = 0x0000 The TEMP_OUT register (see Table 19 and Table 20) provides a coarse measurement of the temperature inside of the ADIS16490 and is useful for monitoring relative changes in the thermal environment. Table 21. TEMP_OUT Data Format Examples Temperature (°C) +85 +25 + 2/70 +25 + 1/70 +25 +25 – 1/70 +25 – 2/70 −40 Decimal +4200 +2 +1 0 −1 −2 −4550 Hex 0x1068 0x0002 0x0001 0x0000 0xFFFF 0xFFFE 0xEE3A Binary 0001 0000 0110 1000 0000 0000 0000 0010 0000 0000 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1110 1110 1110 0011 1010 X_GYRO_OUT X_GYRO_LOW 0 15 15 0 X-AXIS GYROSCOPE DATA 15029-019 Bits [15:6] 5 4 3 2 1 0 Figure 39. Gyroscope Output Data Structure Addresses 0x10, 0x11 Default Not applicable Access R Flash Backup No Table 23. X_GYRO_LOW Bit Definitions Bits [15:0] Description X-axis gyroscope data; low word Table 24. X_GYRO_OUT Register Definition Page 0x00 Addresses 0x12, 0x13 Default Not applicable Access R Flash Backup No Table 25. X_GYRO_OUT Bit Definitions Bits [15:0] Description X-axis gyroscope data; high word; twos complement, ±100°/sec range; 0°/sec = 0x0000, 1 LSB = 0.005°/sec The X_GYRO_LOW (see Table 22 and Table 23) and X_GYRO_ OUT (see Table 24 and Table 25) registers contain the gyroscope data for the x-axis. Y-Axis Gyroscope (Y_GYRO_LOW, Y_GYRO_OUT) Table 26. Y_GYRO_LOW Register Definition Page 0x00 Addresses 0x14, 0x15 Default Not applicable Access R GYROSCOPE DATA Table 27. Y_GYRO_LOW Bit Definitions The gyroscopes in the ADIS16490 measure the angular rate of rotation around three orthogonal axes (x, y, and z). Figure 38 illustrates the orientation of each gyroscope axis, along with the direction of rotation that produces a positive response in each of their measurements. Bits [15:0] Flash Backup No Description Y-axis gyroscope data; low word Table 28. Y_GYRO_OUT Register Definition Page 0x00 Rev. D | Page 20 of 37 Addresses 0x16, 0x17 Default Not applicable Access R Flash Backup No Data Sheet ADIS16490 Table 29. Y_GYRO_OUT Bit Definitions ACCELERATION DATA Bits [15:0] The accelerometers in the ADIS16490 measure both dynamic and static (response to gravity) acceleration along three orthogonal axes (x, y, and z). Figure 40 illustrates the orientation of each accelerometer axis, along with the direction of acceleration that produces a positive response in each of their measurements. Description Y-axis gyroscope data; high word; twos complement, ±100°/sec range; 0°/sec = 0x0000, 1 LSB = 0.005°/sec The Y_GYRO_LOW (see Table 26 and Table 27) and Y_GYRO_ OUT (see Table 28 and Table 29) registers contain the gyroscope data for the y-axis. Z-Axis Gyroscope (Z_GYRO_LOW, Z_GYRO_OUT) Z-AXIS aZ Table 30. Z_GYRO_LOW Register Definition Page 0x00 Addresses 0x18, 0x19 Default Not applicable Access R Flash Backup No X-AXIS Y-AXIS Table 31. Z_GYRO_LOW Bit Definitions PIN 23 PIN 1 Figure 40. Accelerometer Axis and Polarity Assignments Table 32. Z_GYRO_OUT Register Definition Page 0x00 Addresses 0x1A, 0x1B Default Not applicable Access R Flash Backup No Table 33. Z_GYRO_OUT Bit Definitions Bits [15:0] 15029-020 Description Z-axis gyroscope data; additional resolution bits Each accelerometer has two output data registers. Figure 41 illustrates how these two registers combine to support a 32-bit, twos complement data format for the x-axis accelerometer measurements. This format also applies to the y- and z-axes. Description Z-axis gyroscope data; high word; twos complement, ±100°/sec range; 0°/sec = 0x0000, 1 LSB = 0.005°/sec X_ACCL_OUT 15 X_ACCL_LOW 0 0 15 X-AXIS ACCELEROMETER DATA 15029-021 Bits [15:0] aX aY The Z_GYRO_LOW (see Table 30 and Table 31) and Z_GYRO_ OUT (see Table 32 and Table 33) registers contain the gyroscope data for the z-axis. X-Axis Accelerometer (X_ACCL_LOW, X_ACCL_OUT) Gyroscope Resolution Table 36. X_ACCL_LOW Register Definition Table 34 and Table 35 offer various numerical examples that demonstrate the format of the angular rate (gyroscopes) data in both 16-bit and 32-bit formats. Page 0x00 Table 34. 16-Bit Gyroscope Data Format Examples Bits [15:0] Rotation Rate (°/sec) +100 +0.01 +0.005 0 −0.005 −0.01 −100 Decimal +20,000 +2 +1 0 −1 −2 −20,000 Hex 0x4E20 0x0002 0x0001 0x0000 0xFFFF 0xFFFE 0xB1E0 Binary 0100 1110 0010 0000 0000 0000 0000 0010 0000 0000 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1110 1011 0001 1110 0000 Table 35. 32-Bit Gyroscope Data Format Examples Rotation Rate (°/sec) +100 +0.005/215 +0.005/216 0 −0.005/216 −0.005/215 −100 Decimal +1,310,720,000 +2 +1 0 −1 −2 −1,310,720,000 Hex 0x4E200000 0x00000002 0x00000001 0x0000000 0xFFFFFFFF 0xFFFFFFFE 0xB1E00000 Figure 41. Accelerometer Output Data Structure Addresses 0x1C, 0x1D Default Not applicable Access R Flash Backup No Table 37. X_ACCL_LOW Bit Definitions Description X-axis accelerometer data; low word Table 38. X_ACCL_OUT Register Definition Page 0x00 Addresses 0x1E, 0x1F Default Not applicable Access R Flash Backup No Table 39. X_ACCL_OUT Definitions Bits [15:0] Description X-axis accelerometer data, high word; twos complement, ±8 g range; 0 g = 0x0000, 1 LSB = 0.5 mg The X_ACCL_LOW (see Table 36 and Table 37) and X_ACCL_ OUT (see Table 38 and Table 39) registers contain the accelerometer data for the x-axis. Y-Axis Accelerometer (Y_ACCL_LOW, Y_ACCL_OUT) Table 40. Y_ACCL_LOW Register Definition Page 0x00 Rev. D | Page 21 of 37 Addresses 0x20, 0x21 Default Not applicable Access R Flash Backup No ADIS16490 Data Sheet Table 41. Y_ACCL_LOW Bit Definitions Table 49. 32-Bit Accelerometer Data Format Examples Bits [15:0] Acceleration +8 g +0.1/215 mg +0.5/216 mg 0 mg −0.5/216 mg −0.1/215 mg −8 g Description Y-axis accelerometer data; low word Table 42. Y_ACCL_OUT Register Definition Page 0x00 Addresses 0x22, 0x23 Default Not applicable Access R Flash Backup No Table 43. Y_ACCL_OUT Bit Definitions Bits [15:0] Description Y-axis accelerometer data, high word; twos complement, ±8 g range, 0 g = 0x0000, 1 LSB = 0.5 mg The Y_ACCL_LOW (see Table 40 and Table 41) and Y_ACCL_OUT (see Table 42 and Table 43) registers contain the accelerometer data for the y-axis. Z-Axis Accelerometer (Z_ACCL_LOW, Z_ACCL_OUT) Decimal +1,048,576,000 +2 +1 0 −1 −2 −1,048,576,000 DELTA ANGLES In addition to the angular rate of rotation (gyroscope) measurements around each axis (x, y, and z), the ADIS16490 also provides delta angle measurements that represent a computation of angular displacement between each sample update. Z-AXIS Table 44. Z_ACCL_LOW Register Definition Page 0x00 Addresses 0x24, 0x25 Default Not applicable Access R Hex 0x3E800000 0x00000002 0x00000001 0x00000000 0xFFFFFFFF 0xFFFFFFFE 0xC1800000 ΔθZ Flash Backup No X-AXIS Table 45. Z_ACCL_LOW Bit Definitions Description Z-axis accelerometer data; low word ΔθX ΔθY 15029-022 Bits [15:0] Y-AXIS PIN 23 PIN 1 Table 46. Z_ACCL_OUT Register Definition Page 0x00 Addresses 0x26, 0x27 Default Not applicable Access R Figure 42. Delta Angle Axis and Polarity Assignments Flash Backup No Table 47. Z_ACCL_OUT Bit Definitions Bits [15:0] Description Z-axis accelerometer data, high word; twos complement, ±8 g range; 0 g = 0x0000, 1 LSB = 0.5 mg The Z_ACCL_LOW (see Table 44 and Table 45) and Z_ACCL_ OUT (see Table 46 and Table 47) registers contain the accelerometer data for the z-axis. Accelerometer Resolution Table 48 and Table 49 offer various numerical examples that demonstrate the format of the linear acceleration data in both 16-bit and 32-bit formats. Table 48. 16-Bit Accelerometer Data Format Examples Acceleration +8 g +1.0 mg +0.5 mg 0 mg −0.5 mg −1.0 mg −8 g Decimal +16,000 +2 +1 0 −1 −2 −16,000 Hex 0x3E80 0x0002 0x0001 0x0000 0xFFFF 0xFFFE 0xC180 Binary 0011 1110 1000 0000 0000 0000 0000 0010 0000 0000 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1110 1100 0001 1000 0000 The delta angle outputs represent an integration of the gyroscope measurements and use the following formula for all three axes (x-axis displayed): ∆θ x ,n D = ( 1 D −1 × ∑ ω x ,n D + d + ω x ,n D + d − 1 2 fS d =0 ) where: D is the decimation rate = DEC_RATE + 1 (see Table 137). fS is the sample rate. d is the incremental variable in the summation formula. ωx is the x-axis rate of rotation (gyroscope). n is the sample time, prior to the decimation filter. When using the internal sample clock, fS is equal to 4250 SPS. When using the external clock option, fS is equal to the frequency of the external clock. The range in the delta angle registers accommodates the maximum rate of rotation (100°/sec), the nominal sample rate (4250 SPS) and an update rate of 1 Hz (DEC_RATE = 0x1099; divide by 4249 plus 1, see Table 137), all at the same time. When using an external clock that is higher than 4250 SPS, reduce the DEC_RATE setting to avoid overranging the delta angle registers. Each axis of the delta angle measurements has two output data registers. Figure 43 illustrates how these two registers combine to support a 32-bit, twos complement data format for the x-axis delta angle measurements. This format also applies to the yand z-axes. Rev. D | Page 22 of 37 Data Sheet ADIS16490 0 15 0 X-AXIS DELTA ANGLE DATA Bits [15:0] Table 60. Z_DELTANG_OUT Register Definitions Figure 43. Delta Angle Output Data Structure X-Axis Delta Angle (X_DELTANG_LOW, X_DELTANG_OUT) The X_DELTANG_LOW (see Table 50 and Table 51) and X_DELTANG_OUT (see Table 52 and Table 53) registers contain the delta angle data for the x-axis. Addresses 0x40, 0x41 Default Not applicable Access R Bits [15:0] Flash Backup No Description X-axis delta angle data; low word Addresses 0x42, 0x43 Default Not applicable Access R Flash Backup No Table 53. X_DELTANG_OUT Bit Definitions Bits [15:0] Description X-axis delta angle data, high word; twos complement, ±720° range, 0° = 0x0000, 1 LSB = 720°/215 = ~0.022° Y-Axis Delta Angle (Y_DELTANG_LOW, Y_DELTANG_OUT) Table 54. Y_DELTANG_LOW Register Definitions Addresses 0x44, 0x45 Default Not applicable Access R Flash Backup No Table 55. Y_DELTANG_LOW Bit Definitions Bits [15:0] Description Y-axis delta angle data; low word Addresses 0x46, 0x47 Default Not applicable Access R Description Z-axis delta angle data, high word; twos complement, ±720° range, 0° = 0x0000, 1 LSB = 720°/215 = ~0.022° Delta Angle Resolution Delta Angle (°) +720 × (215 − 1)/215 +720/214 +720/215 0 −720/215 −720/214 −720 Decimal +32,767 +2 +1 0 −1 −2 −32,768 Delta Angle (°) +720 × (231 − 1)/231 +720/230 +720/231 0 −720/231 −720/230 −720 Hex 0x7FFF 0x0002 0x0001 0x0000 0xFFFF 0xFFFE 0x8000 Binary 0111 1111 1110 1111 0000 0000 0000 0010 0000 0000 0000 0001 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111 1111 1110 1000 0000 0000 0000 Decimal +2,147,483,647 +2 +1 0 −1 −2 −2,147,483,647 Hex 0x7FFFFFFF 0x00000002 0x00000001 0x00000000 0xFFFFFFFF 0xFFFFFFFE 0x80000000 Flash Backup No In addition to the linear acceleration measurements along each axis (x, y, and z), the ADIS16490 also provides delta velocity measurements that represent a computation of linear velocity change between each sample update. Table 57. Y_DELTANG_OUT Bit Definitions Bits [15:0] Flash Backup No DELTA VELOCITY Table 56. Y_DELTANG_OUT Register Definitions Page 0x00 Access R Table 63. 32-Bit Delta Angle Data Format Examples The Y_DELTANG_LOW (see Table 54 and Table 55) and Y_DELTANG_OUT (see Table 56 and Table 57) registers contain the delta angle data for the y-axis. Page 0x00 Default Not applicable Table 62. 16-Bit Delta Angle Data Format Examples Table 52. X_DELTANG_OUT Register Definitions Page 0x00 Addresses 0x4A, 0x4B Table 62 and Table 63 offer various numerical examples that demonstrate the format of the delta angle data in both 16-bit and 32-bit formats. Table 51. X_DELTANG_LOW Bit Definitions Bits [15:0] Page 0x00 Table 61. Z_DELTANG_OUT Bit Definitions Table 50. X_DELTANG_LOW Register Definitions Page 0x00 Description Z-axis delta angle data; low word Z-AXIS Description Y-axis delta angle data, high word; twos complement, ±720° range, 0° = 0x0000, 1 LSB = 720°/215 = ~0.022° ΔV Z Z-Axis Delta Angle (Z_DELTANG_LOW, Z_DELTANG_OUT) X-AXIS Y-AXIS The Z_DELTANG_LOW (see Table 58 and Table 59) and Z_DELTANG_OUT (see Table 60 and Table 61) registers contain the delta angle data for the z-axis. ΔV X ΔVY PIN 23 PIN 1 Figure 44. Delta Velocity Axis and Polarity Assignments Table 58. Z_DELTANG_LOW Register Definitions Page 0x00 Addresses 0x48, 0x49 Default Not applicable Access R Flash Backup No Rev. D | Page 23 of 37 15029-024 15 Table 59. Z_DELTANG_LOW Bit Definitions X_DELTANG_LOW 15029-025 X_DELTANG_OUT ADIS16490 Data Sheet The delta velocity outputs represent an integration of the acceleration measurements and use the following formula for all three axes (x-axis displayed): ∆Vx ,n D ( 1 D −1 = × ∑ a x ,n D + d + a x ,n D + d − 1 2 f S d =0 ) Page 0x00 X_ DELTVEL_LOW X-AXIS DELTA VELOCITY DATA X-Axis Delta Velocity (X_DELTVEL_LOW, X_DELTVEL_OUT) Table 64. X_DELTVEL_LOW Register Definitions Addresses 0x4C, 0x4D Default Not applicable Access R Bits [15:0] Flash Backup No Description X-axis delta angle data; low word Table 66. X_DELTVEL_OUT Register Definitions Page 0x00 Addresses 0x4E, 0x4F Default Not applicable Access R Flash Backup No Table 67. X_DELTVEL_OUT Bit Definitions Bits [15:0] Description X-axis delta velocity data; twos complement, ±200 m/sec range, 0 m/sec = 0x0000; 1 LSB = 200 m/sec ÷ 215 = ~6.104 mm/sec The X_DELTVEL_LOW (see Table 64 and Table 65) and X_DELTVEL_OUT (see Table 66 and Table 67) registers contain the delta velocity data for the x-axis. Flash Backup No Description Y-axis delta angle data; low word Addresses 0x52, 0x53 Default Not applicable Access R Flash Backup No Description Y-axis delta velocity data, high word; twos complement, ±200 m/sec range, 0 m/sec = 0x0000; 1 LSB = 200 m/sec ÷ 215 = ~6.104 mm/sec The Y_DELTVEL_LOW (see Table 68 and Table 69) and Y_DELTVEL_OUT (see Table 70 and Table 71) registers contain the delta velocity data for the y-axis. Z-Axis Delta Velocity (Z_DELTVEL_LOW, Z_DELTVEL_OUT) Table 72. Z_DELTVEL_LOW Register Definitions Page 0x00 Addresses 0x54, 0x55 Default Not applicable Access R Flash Backup No Table 73. Z_DELTVEL_LOW Bit Definitions Page 0x00 Description Z-axis delta angle data; low word Addresses 0x56, 0x57 Default Not applicable Access R Flash Backup No Table 75. Z_DELTVEL_OUT Bit Definitions Bits [15:0] Table 65. X_DELTVEL_LOW Bit Definitions Bits [15:0] Access R Table 74. Z_DELTVEL_OUT Register Definitions Figure 45. Delta Angle Output Data Structure Page 0x00 Default Not applicable Table 71. Y_DELTVEL_OUT Bit Definitions Bits [15:0] 15029-025 0 Addresses 0x50, 0x51 Table 70. Y_DELTVEL_OUT Register Definitions Each axis of the delta velocity measurements has two output data registers. Figure 45 illustrates how these two registers combine to support 32-bit, twos complement data format for the delta velocity measurements along the x-axis. This format also applies to the y- and x-axes. 0 15 Page 0x00 Bits [15:0] When using the internal sample clock, fS is equal to 4250 SPS. When using the external clock option, fS is equal to the frequency of the external clock. The range in the delta velocity registers accommodates the maximum linear acceleration (8 g), the nominal sample rate (4250 SPS) and an update rate of 1 Hz (DEC_RATE = 0x1099; divide by 4249 plus 1, see Table 137), all at the same time. When using an external clock that is higher than 4250 SPS, reduce the DEC_RATE setting to avoid overranging the delta velocity registers. 15 Table 68. Y_DELTVEL_LOW Register Definitions Table 69. Y_DELTVEL_LOW Bit Definitions where: D is the decimation rate = DEC_RATE + 1 (see Table 137). fS is the sample rate. d is the incremental variable in the summation formula. ax is the x-axis rate of acceleration (accelerometer). n is the sample time, prior to the decimation filter. X_ DELTVEL_OUT Y-Axis Delta Velocity (Y_DELTVEL_LOW, Y_DELTVEL_OUT) Description Z-axis delta velocity data, high word; twos complement, ±200 m/sec range, 0 m/sec = 0x0000; 1 LSB = 200 m/sec ÷ 215 = ~6.104 mm/sec The Z_DELTVEL_LOW (see Table 72 and Table 73) and Z_DELTVEL_OUT (see Table 74 and Table 75) registers contain the delta velocity data for the z-axis. Delta Velocity Resolution Table 76 and Table 77 offer various numerical examples that demonstrate the format of the delta angle data in both 16-bit and 32-bit formats. Table 76. 16-Bit Delta Velocity Data Format Examples Velocity (m/sec) +200 × (215 − 1)/215 +200/214 +200/215 0 Rev. D | Page 24 of 37 Decimal +32,767 +2 +1 0 Hex 0x7FFF 0x0002 0x0001 0x0000 Binary 0111 1111 1110 1111 0000 0000 0000 0010 0000 0000 0000 0001 0000 0000 0000 0000 Data Sheet Decimal −1 −2 −32,768 Hex 0xFFFF 0xFFFE 0x8000 Binary 1111 1111 1111 1111 1111 1111 1111 1110 1000 0000 0000 0000 1 + X_GYRO_SCALE X-AXIS GYRO Decimal +2,147,483,647 +2 +1 0 −1 −2 −2,147,483,648 Hex 0x7FFFFFFF 0x00000002 0x00000001 0x00000000 0xFFFFFFFF 0xFFFFFFFE 0x80000000 Product Identification, PROD_ID Table 78. PROD_ID Register Definitions Page 0x00 Addresses 0x7E, 0x7F Default 0x406A Access R Description Product identification = 0x406A XG_BIAS_LOW Figure 46. User Calibration Signal Path, Gyroscopes Calibration, Gyroscope Scale, Y_GYRO_SCALE Table 82. Y_GYRO_SCALE Register Definitions Page 0x02 Addresses 0x06, 0x07 Default 0x0000 Access R/W Table 83. Y_GYRO_SCALE Bit Definitions Bits [15:0] Description Y-axis gyroscope scale correction; twos complement, 0x0000 = unity gain, 1 LSB = 1 ÷ 215 = ~0.003052% Table 84. Z_GYRO_SCALE Register Definitions Page 0x02 Addresses 0x08, 0x09 Default 0x0000 Access R/W CALIBRATION Table 85. Z_GYRO_SCALE Bit Definitions The signal chain of each inertial sensor (accelerometers, gyroscopes) includes application of unique correction formulas that come from extensive characterization of bias, sensitivity, alignment, and response to linear acceleration (gyroscopes) over a temperature range of −40°C to +85°C for the ADIS16490. These correction formulas are not accessible, but users do have the opportunity to adjust the bias and the scale factor, for each sensor individually, through user accessible registers. These correction factors follow immediately after the factory derived correction formulas in the signal chain, which processes at a rate of 4250 Hz when using the internal sample clock (see fSM in Figure 23 and Figure 24). Bits [15:0] The Z_GYRO_SCALE register (see Table 84 and Table 85) allows users to adjust the scale factor for the z-axis gyroscopes. This register influences the z-axis gyroscope measurements in the same manner that X_GYRO_SCALE influences the x-axis gyroscope measurements (see Figure 46). Calibration, Accelerometer Scale, X_ACCL_SCALE Table 86. X_ACCL_SCALE Register Definitions Calibration, Gyroscope Scale, X_GYRO_SCALE Table 80. X_GYRO_SCALE Register Definitions Table 87. X_ACCL_SCALE Bit Definitions Default 0x0000 Access R/W Bits [15:0] Flash Backup Yes Table 81. X_GYRO_SCALE Bit Definitions Bits [15:0] Description X-axis gyroscope scale correction; twos complement, 0x0000 = unity gain, 1 LSB = 1 ÷ 215 = ~0.003052% Flash Backup Yes Description Z-axis gyroscope scale correction; twos complement, 0x0000 = unity gain, 1 LSB = 1 ÷ 215 = ~0.003052% Page 0x02 Addresses 0x04, 0x05 Flash Backup Yes Calibration, Gyroscope Scale, Z_GYRO_SCALE The PROD_ID register (see Table 78 and Table 79) contains the numerical portion of the part number (16490). See Figure 35 for an example of how to use a looping read of this register to validate the integrity of the communication. Page 0x02 X_GYRO_LOW The Y_GYRO_SCALE register (see Table 82 and Table 83) allows users to adjust the scale factor for the y-axis gyroscopes. This register influences the y-axis gyroscope measurements in the same manner that X_GYRO_SCALE influences the x-axis gyroscope measurements (see Figure 46). Flash Backup Yes Table 79. PROD_ID Bit Definitions Bits [15:0] X_GYRO_OUT XG_BIAS_HIGH Table 77. 32-Bit Delta Angle Data Format Examples Velocity (m/sec) +200 × (231 − 1)/231 +200/230 +200/231 0 −200/231 −200/230 −200 FACTORY CALIBRATION AND FILTERING 15029-026 Velocity (m/sec) −200/215 −200/214 −200 ADIS16490 Addresses 0x0A, 0x0B Default 0x0000 Access R/W Flash Backup Yes Description X-axis accelerometer scale correction; twos complement, 0x0000 = unity gain, 1 LSB = 1 ÷ 215 = ~0.003052% The X_ACCL_SCALE register (see Table 86 and Table 87) allows users to adjust the scale factor for the x-axis accelerometers. See Figure 47 for an illustration of how this scale factor influences the x-axis accelerometer data. The X_GYRO_SCALE register (see Table 80 and Table 81) provides users with the opportunity to adjust the scale factor for the x-axis gyroscopes. See Figure 46 for an illustration of how this scale factor influences the x-axis gyroscope data. Rev. D | Page 25 of 37 ADIS16490 Data Sheet 1 + X_ACCL_SCALE Table 95. XG_BIAS_HIGH Bit Definitions X_ACCL_OUT XA_BIAS_HIGH Bits [15:0] X_ACCL_LOW 15029-027 X-AXIS ACCL FACTORY CALIBRATION AND FILTERING XA_BIAS_LOW Figure 47. User Calibration Signal Path, Accelerometers Calibration, Accelerometer Scale, Y_ACCL_SCALE Table 88. Y_ACCL_SCALE Register Definitions Page 0x02 Addresses 0x0C, 0x0D Default 0x0000 Access R/W Flash Backup Yes Table 89. Y_ACCL_SCALE Bit Definitions Bits [15:0] Description Y-axis accelerometer scale correction; twos complement, 0x0000 = unity gain, 1 LSB = 1 ÷ 215 = ~0.003052% Description X-axis gyroscope offset correction, high word; twos complement, 0°/sec = 0x0000, 1 LSB = 0.005°/sec The XG_BIAS_LOW (see Table 92 and Table 93) and XG_ BIAS_HIGH (see Table 94 and Table 95) registers combine to allow users to adjust the bias of the x-axis gyroscopes. The digital format examples in Table 34 also apply to the XG_BIAS_HIGH register, and the digital format examples in Table 35 apply to the number that comes from combining the XG_BIAS_LOW and XG_BIAS_HIGH registers. See Figure 46 for an illustration of how these two registers combine and influence the x-axis gyroscope measurements. Calibration, Gyroscope Bias, YG_BIAS_LOW, YG_BIAS_HIGH The Y_ACCL_SCALE register (see Table 88 and Table 89) allows users to adjust the scale factor for the y-axis accelerometers. This register influences the y-axis accelerometer measurements in the same manner that X_ACCL_SCALE influences the x-axis accelerometer measurements (see Figure 47). Table 96. YG_BIAS_LOW Register Definitions Calibration, Accelerometer Scale, Z_ACCL_SCALE Bits [15:0] Page 0x02 Addresses 0x0E, 0x0F Default 0x0000 Access R/W Flash Backup Yes Page 0x02 Description Z-axis accelerometer scale correction; twos complement, 0x0000 = unity gain, 1 LSB = 1 ÷ 215 = ~0.003052% The Z_ACCL_SCALE register (see Table 90 and Table 91) allows users to adjust the scale factor for the z-axis accelerometers. This register influences the z-axis accelerometer measurements in the same manner that X_ACCL_SCALE influences the x-axis accelerometer measurements (see Figure 47). Calibration, Gyroscope Bias, XG_BIAS_LOW, XG_BIAS_HIGH Table 92. XG_BIAS_LOW Register Definitions Page 0x02 Addresses 0x10, 0x11 Default 0x0000 Access R/W Flash Backup Yes Table 93. XG_BIAS_LOW Bit Definitions Bits [15:0] Description X-axis gyroscope offset correction, low word; twos complement, 0°/sec = 0x0000, 1 LSB = 0.005°/sec ÷ 216 Table 94. XG_BIAS_HIGH Register Definitions Page 0x02 Addresses 0x12, 0x13 Default 0x0000 Access R/W Flash Backup Yes Access R/W Flash Backup Yes Description Y-axis gyroscope offset correction, low word; twos complement, 0°/sec = 0x0000, 1 LSB = 0.005°/sec ÷ 216 Table 98. YG_BIAS_HIGH Register Definitions Table 91. Z_ACCL_SCALE Bit Definitions Bits [15:0] Default 0x0000 Table 97. YG_BIAS_LOW Bit Definitions Table 90. Z_ACCL_SCALE Register Definitions Page 0x02 Addresses 0x14, 0x15 Addresses 0x16, 0x17 Default 0x0000 Access R/W Flash Backup Yes Table 99. YG_BIAS_HIGH Bit Definitions Bits [15:0] Description Y-axis gyroscope offset correction, high word; twos complement, 0°/sec = 0x0000, 1 LSB = 0.005°/sec The YG_BIAS_LOW (see Table 96 and Table 97) and YG_ BIAS_HIGH (see Table 98 and Table 99) registers combine to allow users to adjust the bias of the y-axis gyroscopes. The digital format examples in Table 34 also apply to the YG_BIAS_HIGH register, and the digital format examples in Table 35 apply to the number that comes from combining the YG_BIAS_LOW and YG_BIAS_HIGH registers. These registers influences the y-axis gyroscope measurements in the same manner that the XG_BIAS_ LOW and XG_BIAS_HIGH registers influence the x-axis gyroscope measurements (see Figure 46). Calibration, Gyroscope Bias, ZG_BIAS_LOW, ZG_BIAS_HIGH Table 100. ZG_BIAS_LOW Register Definitions Page 0x02 Addresses 0x18, 0x19 Default 0x0000 Access R/W Flash Backup Yes Table 101. ZG_BIAS_LOW Bit Definitions Bits [15:0] Rev. D | Page 26 of 37 Description Z-axis gyroscope offset correction, low word; twos complement, 0°/sec = 0x0000, 1 LSB = 0.005°/sec ÷ 216 Data Sheet ADIS16490 Table 102. ZG_BIAS_HIGH Register Definitions Table 109. YA_BIAS_LOW Bit Definitions Page 0x02 Bits [15:0] Addresses 0x1A, 0x1B Default 0x0000 Access R/W Flash Backup Yes Table 103. ZG_BIAS_HIGH Bit Definitions Bits [15:0] Table 110. YA_BIAS_HIGH Register Definitions Description Z-axis gyroscope offset correction, high word twos complement, 0°/sec = 0x0000, 1 LSB = 0.005°/sec Page 0x02 The ZG_BIAS_LOW (see Table 100 and Table 101) and ZG_ BIAS_HIGH (see Table 102 and Table 103) registers combine to allow users to adjust the bias of the z-axis gyroscopes. The digital format examples in Table 34 also apply to the ZG_BIAS_ HIGH register, and the digital format examples in Table 35 apply to the number that comes from combining the ZG_BIAS_LOW and ZG_BIAS_HIGH registers. These registers influence the z-axis gyroscope measurements in the same manner that the XG_BIAS_LOW and XG_BIAS_HIGH registers influence the x-axis gyroscope measurements (see Figure 46). Calibration, Accelerometer Bias, XA_BIAS_LOW, XA_BIAS_HIGH Table 104. XA_BIAS_LOW Register Definitions Page 0x02 Addresses 0x1C, 0x1D Default 0x0000 Access R/W Flash Backup Yes Addresses 0x22, 0x23 Default 0x0000 Access R/W Description X-axis accelerometer offset correction, low word, twos complement, 0 g = 0x0000, 1 LSB = 0.5 mg ÷ 216 Table 111. YA_BIAS_HIGH Bit Definitions Bits [15:0] Description Y-axis accelerometer offset correction, high word, twos complement, 0 g = 0x0000, 1 LSB = 0.5 mg The YA_BIAS_LOW (see Table 108 and Table 109) and YA_ BIAS_HIGH (see Table 110 and Table 111) registers combine to allow users to adjust the bias of the y-axis accelerometers. The digital format examples in Table 48 also apply to the YA_BIAS_ HIGH register, and the digital format examples in Table 49 apply to the number that comes from combining the YA_BIAS_LOW and YA_BIAS_HIGH registers. These registers influence the y-axis accelerometer measurements in the same manner that the XA_BIAS_LOW and XA_BIAS_HIGH registers influence the x-axis accelerometer measurements (see Figure 47). Table 112. ZA_BIAS_LOW Register Definitions Page 0x02 Addresses 0x24, 0x25 Default 0x0000 Access R/W Table 106. XA_BIAS_HIGH Register Definitions Table 113. ZA_BIAS_LOW Bit Definitions Page 0x02 Bits [15:0] Addresses 0x1E, 0x1F Default 0x0000 Access R/W Flash Backup Yes Table 107. XA_BIAS_HIGH Bit Definitions Bits [15:0] Page 0x02 The XA_BIAS_LOW (see Table 104 and Table 105) and XA_ BIAS_HIGH (see Table 106 and Table 107) registers combine to allow users to adjust the bias of the x-axis accelerometers. The digital format examples in Table 48 also apply to the XA_BIAS_ HIGH register and the digital format examples in Table 49 apply to the number that comes from combining the XA_ BIAS_LOW and XA_BIAS_HIGH registers. See Figure 47 for an illustration of how these two registers combine and influence the x-axis gyroscope measurements. Table 108. YA_BIAS_LOW Register Definitions Page 0x02 Addresses 0x20, 0x21 Default 0x0000 Access R/W Flash Backup Yes Flash Backup Yes Description Z-axis accelerometer offset correction, low word, twos complement, 0 g = 0x0000, 1 LSB = 0.5 mg ÷ 216 Table 114. ZA_BIAS_HIGH Register Definitions Description X-axis accelerometer offset correction, high word, twos complement, 0 g = 0x0000, 1 LSB = 0.5 mg Calibration, Accelerometer Bias, YA_BIAS_LOW, YA_BIAS_HIGH Flash Backup Yes Calibration, Accelerometer Bias, ZA_BIAS_LOW, ZA_BIAS_HIGH Table 105. XA_BIAS_LOW Bit Definitions Bits [15:0] Description Y-axis accelerometer offset correction, low word, twos complement, 0 g = 0x0000, 1 LSB = 0.5 mg ÷ 216 Addresses 0x26, 0x27 Default 0x0000 Access R/W Flash Backup Yes Table 115. ZA_BIAS_HIGH Bit Definitions Bits [15:0] Description Z-axis accelerometer offset correction, high word, twos complement, 0 g = 0x0000, 1 LSB = 0.5 mg The ZA_BIAS_LOW (see Table 112 and Table 113) and ZA_ BIAS_HIGH (see Table 114 and Table 115) registers combine to allow users to adjust the bias of the z-axis accelerometers. The digital format examples in Table 48 also apply to the ZA_BIAS_ HIGH register and the digital format examples in Table 49 apply to the number that comes from combining the ZA_BIAS_LOW and ZA_BIAS_HIGH registers. These registers influence the z-axis accelerometer measurements in the same manner that the XA_BIAS_LOW and XA_BIAS_HIGH registers influence the x-axis accelerometer measurements (see Figure 47). Rev. D | Page 27 of 37 ADIS16490 Data Sheet Scratch Registers, USER_SCR_x The FLSHCNT_LOW (see Table 124 and Table 125) and FLSHCNT_HIGH (see Table 126 and Table 127) registers combine to provide a 32-bit, binary counter that tracks the number of flash memory write cycles. In addition to the number of write cycles, the flash memory has a finite service lifetime, which depends on the junction temperature. Figure 48 provides guidance for estimating the retention life for the flash memory at specific junction temperatures. The junction temperature is approximately 7°C above the case temperature. Table 116. USER_SCR_1 Register Definitions Page 0x02 Addresses 0x74, 0x75 Default 0x0000 Access R/W Flash Backup Yes Table 117. USER_SCR_1 Bit Definitions Bits [15:0] Description User defined Table 118. USER_SCR_2 Register Definitions Addresses 0x76, 0x77 Default 0x0000 Access R/W Flash Backup Yes 600 Bits [15:0] RETENTION (Years) Table 119. USER_SCR_2 Bit Definitions Description User defined Table 120. USER_SCR_3 Register Definitions Page 0x02 Addresses 0x78, 0x79 Default 0x0000 Access R/W Flash Backup Yes 300 150 Table 121. USER_SCR_3 Bit Definitions Bits [15:0] 450 0 Description User defined 30 55 70 85 100 125 JUNCTION TEMPERATURE (°C) 40 Global Commands, GLOB_CMD Page 0x02 Table 128. GLOB_CMD Register Definitions Default 0x0000 Access R/W Flash Backup Yes Table 123. USER_SCR_4 Bit Definitions Page 0x03 Bits [15:0] Table 129. GLOB_CMD Bit Definitions Description User defined The USER_SCR_1 (see Table 116 and Table 117), USER_SCR_2 (see Table 118 and Table 119), USER_SCR_3 (see Table 120 and Table 121), USER_SCR_4 (see Table 122 and Table 123) registers provide four locations for users to store information. Flash Memory Endurance Counter, FLSHCNT_LOW, FLSHCNT_HIGH Table 124. FLSHCNT_LOW Register Definitions Page 0x02 Addresses 0x7C, 0x7D Default Not applicable Access R Flash Backup Yes Table 125. FLSHCNT_LOW Bit Definitions Bits [15:0] Description Flash memory write counter, low word Addresses 0x7E, 0x7F Default Not applicable Access R Table 127. FLSHCNT_HIGH Bit Definitions Bits [15:0] Description Flash memory write counter, high word Bits [15:8] 7 6 [5:4] 3 2 1 0 Addresses 0x02, 0x03 Default Not applicable Access W Flash Backup No Description Not used Software reset Factory calibration restore Not used Flash memory update Not used Self test Bias correction update The GLOB_CMD register (see Table 128 and Table 129) provides trigger bits for several operations. Write a 1 to the appropriate bit in GLOB_CMD to start a particular function. Software Reset Table 126. FLSHCNT_HIGH Register Definitions Page 0x02 150 Figure 48. Flash Memory Retention Table 122. USER_SCR_4 Register Definitions Addresses 0x7A, 0x7B 135 15029-028 Page 0x02 Flash Backup Yes Select Page 3 (DIN = 0x8003) and then set GLOB_CMD[7] = 1 (DIN = 0x8280, DIN = 0x8300) to initiate a reset in the operation of the ADIS16490. This reset removes all data, initializes all registers from their flash settings, and restarts data sampling and processing. This function provides a firmware alternative to providing a low pulse on the RST pin (see Table 6, Pin 8). Rev. D | Page 28 of 37 Data Sheet ADIS16490 Factory Calibration Restore Auxiliary I/O Line Configuration, FNCTIO_CTRL Select Page 3 (DIN = 0x8003) and then set GLOB_CMD[6] = 1 (DIN = 0x8240, DIN = 0x8300) to initiate restoration of the factory calibration. This restoration writes 0x0000 to the following registers: X_GYRO_SCALE, Y_GYRO_SCALE, Z_GYRO_SCALE, X_ACCL_SCALE, Y_ACCL_SCALE, Z_ACCL_SCALE, XG_BIAS_LOW, XG_BIAS_HIGH, YG_BIAS_LOW, YG_BIAS_HIGH, ZG_BIAS_LOW, ZG_BIAS_HIGH, XA_BIAS_LOW, XA_BIAS_HIGH, YA_BIAS_LOW, YA_BIAS_HIGH, ZA_BIAS_LOW, and ZA_BIAS_HIGH. Table 130. FNCTIO_CTRL Register Definitions Page 0x03 Note that the user must not poll the status registers while waiting for the update to complete because the serial port is disabled. Rather, the user must either wait the prescribed amount of time found in Table 3 or wait for the data ready indicator pin to begin toggling. On Demand Self Test (ODST) Select Page 3 (DIN = 0x8003) and then set GLOB_CMD[1] = 1 (DIN = 0x8202, then DIN = 0x8300) to run the ODST routine, which executes the following steps: 1. 2. 3. 4. 5. 6. 7. Measure the output on each sensor. Activate an internal force on the mechanical elements of each sensor, which simulates the force associated with actual inertial motion. Measure the output response on each sensor. Deactivate the internal force on each sensor. Calculate the difference between the force on and normal operating conditions (force off). Compare the difference with internal pass/fail criteria. Report the pass/fail results for each sensor in DIAG_STS (see Table 18) and the overall pass/fail flag in SYS_E_FLAG[5] (see Table 16). False positive results are possible when executing the ODST while the device is in motion. Note that the user must not poll the status registers while waiting for the test to complete. Rather, the user must either wait the prescribed amount of time found in Table 3 or wait for the data ready indicator pin to begin toggling. Bias Correction Update Select Page 3 (DIN = 0x8003) and set GLOB_CMD[0] = 1 (DIN = 0x8201, then DIN = 0x8300) to update the user offset registers with the correction factors of the CBE (see Table 139). Ensure that the inertial platform is stable during the entire average time for optimal bias estimates. Default 0x000D Access R/W Flash Backup Yes Table 131. FNCTIO_CTRL Bit Definitions Bits [15:9] 8 7 6 Flash Memory Update Select Page 3 (DIN = 0x8003) and then set GLOB_CMD[3] = 1 (DIN = 0x8208, DIN = 0x8300) to initiate a manual flash update. SYS_E_FLAG[6] (see Table 16) identifies success (0) or failure (1) in completing this process. Addresses 0x06, 0x07 [5:4] 3 2 [1:0] Description Not used Sync clock mode: 1 = PPS, 0 = sync Sync clock input enable: 1 = enabled, 0 = disabled Sync clock input polarity: 1 = rising edge, 0 = falling edge Sync clock input line selection: 00 = DIO1, 01 = DIO2, 10 = DIO3, 11 = DIO4 Data ready enable: 1 = enabled, 0 = disabled Data ready polarity: 1 = positive, 0 = negative Data ready line selection: 00 = DIO1, 01 = DIO2, 10 = DIO3, 11 = DIO4 The FNCTIO_CTRL register (see Table 130 and Table 131) provides configuration control for each I/O pin (DIO1, DIO2, DIO3, and DIO4). Each DIOx pin supports only one function at a time. When a single pin has two assignments, the enable bit for the lower priority function automatically resets to zero (disabling the lower priority function). The order of priority is as follows, from highest priority to lowest priority: data ready, sync clock input, and general-purpose. The ADIS16490 can take up to 20 ms to execute a write command to the FNCTIO_CTRL register. During this time, the operational state and the contents of the register remain unchanged, but the SPI interface supports normal communication (for accessing other registers). Data Ready Indicator The FNCTIO_CTRL[3:0] bits provide three configuration options for the data ready function: on/off, polarity, and DIOx line. The primary purpose this signal is to drive the interrupt control line of an embedded processor, which can help synchronize data collection and minimize latency. The data ready indicator is useful to determine if the controller inside the ADIS16490 is busy with a task (for example, a flash memory update) because data ready stops togging while these tasks are performed and resumes on completion. The factory default assigns DIO2 as a positive polarity, data ready signal, which means that the data in the output registers is valid when the DIO2 line is high (see Figure 30). This configuration works well when DIO2 drives an interrupt service pin that activates on a low to high pulse. Use the following sequence to change this assignment to DIO3 with negative polarity: 1. 2. Select Page 3 (DIN = 0x8003). Set FNCTIO_CTRL[3:0] = 1000 (DIN = 0x860A, then DIN = 0x8700). The timing jitter on the data ready signal is typically within ±1.4 µs. When using DIO1 to support the data ready function, this signal can experience premature data ready pulses during the ADIS16490 start-up. However, these pulses do not indicate Rev. D | Page 29 of 37 ADIS16490 Data Sheet that data production has started. If it is necessary to use DIO1 for this function, use it in conjunction with a delay or other control mechanism to prevent premature data acquisition activity during the start-up process. Input Sync/Clock Control The FNCTIO_CTRL[8:4] bits provide several configuration options for using one of the DIOx lines as an external clock signal and for controlling inertial sensor data collection and processing. For example, use the following sequence to establish DIO4 as a positive polarity, input clock pin that operates in sync mode and preserves the factory default setting for the data ready function: 1. 2. 3. Select Page 3 (DIN = 0x8003). Set FNCTIO_CTRL[7:0] = 0xFD (DIN = 0x86FD). Set FNCTIO_CTRL[15:8] = 0x00 (DIN = 0x8700). In sync mode, the ADIS16490 disables its internal sample clock, and the frequency of the external clock signal establishes the rate of data collection and processing (fSM in Figure 23 and Figure 24). When using the PPS mode (FNCTIO_CTRL[8] = 1) the rate of data collection and production (fSM) is equal to the product of the external clock frequency and scale factor (KECSF) in the SYNC_SCALE register (see Table 141). General-Purpose I/O Control, GPIO_CTRL Table 132. GPIO_CTRL Register Definitions1 Page 0x03 1 Addresses 0x08, 0x09 Default 0x00X0 Access R/W Flash Backup Yes set their level by writing to GPIO_CTRL[7:4]. For example, use the following sequence to set DIO1 and DIO3 as high and low output lines, respectively, and set DIO2 and DIO4 as input lines. Select Page 3 (DIN = 0x8003) and set GPIO_ CTRL[7:0] = 0x15 (DIN = 0x8815, then DIN = 0x8900). Miscellaneous Configuration, CONFIG Table 134. CONFIG Register Definitions Page 0x03 Addresses 0x0A, 0x0B Default 0x00C0 Access R/W Flash Backup Yes Table 135. CONFIG Bit Definitions Bits [15:8] 7 6 [5:0] Description Not used Linear g compensation for gyroscopes (1 = enabled) Point of percussion alignment (1 = enabled) Not used The CONFIG register (see Table 134 and Table 135) provides configuration options for the linear g compensation in the gyroscopes (on/off) and the point of percussion alignment for the accelerometers (on/off). Point of Percussion CONFIG[6] offers a point of percussion alignment function that maps the accelerometer sensors to the corner of the package identified in Figure 49. To activate this feature, select Page 3 (DIN = 0x8003), then set CONFIG[6] = 1 (DIN = 0x8A40, DIN = 0x8B00). The GPIO_CTRL[7:4] bits reflect the logic levels on the DIOx lines and do not have a default setting. Table 133. GPIO_CTRL Bit Definitions1 2 1 0 1 Description Don’t care General-Purpose I/O Line 4 (DIO4) data level General-Purpose I/O Line 3 (DIO3) data level General-Purpose I/O Line 2 (DIO2) data level General-Purpose I/O Line 1 (DIO1) data level General-Purpose I/O Line 4 (DIO4) direction control (1 = output, 0 = input) General-Purpose I/O Line 3 (DIO3) direction control (1 = output, 0 = input) General-Purpose I/O Line 2 (DIO2) direction control (1 = output, 0 = input) General-Purpose I/O Line 1 (DIO1) direction control (1 = output, 0 = input) PIN 23 PIN 1 POINT OF PERCUSSION ALIGNMENT REFERENCE POINT. SEE CONFIG[6]. 15029-029 Bits [15:8] 7 6 5 4 3 Figure 49. Point of Percussion Reference Point Linear Acceleration on Effect on Gyroscope Bias The ADIS16490 includes first-order compensation for the linear g effect in the gyroscopes, which uses the following model:  ω  LG11 LG12 LG13   A X  ω  XC       XPC  + × = A LG LG LG ω ω  YPC   YC   21 22 23   Y   ω  LG   A  ω LG LG 31 32 33 Z     ZPC   ZC   The GPIO_CTRL[7:4] bits reflect the logic levels on the DIOx lines and do not have a default setting. When FNCTIO_CTRL does not configure a DIOx pin, the GPIO_ CTRL register (see Table 132 and Table 133) provides user controls for general-purpose use of the DIOx pins. GPIO_CTRL[3:0] provide input/output assignment controls for each line. When the DIOx lines are inputs, monitor their level by reading GPIO_CTRL[7:4]. When the DIOx lines are used as outputs, The linear g correction factors, LGXY, apply correction for linear acceleration in all three directions to the data path of each gyroscope (ωXPC, ωYPC, and ωZPC) at the rate of the data samples (4250 SPS when using the internal clock). CONFIG[7] provides an on/off control for this compensation. The factory default value for this bit activates this compensation. To turn it off, select Page 3 (DIN = 0x8003) and set CONFIG[7] = 0 (DIN = 0x8A40, DIN = Rev. D | Page 30 of 37 Data Sheet ADIS16490 0x8B00). Note that this command sequence also preserves the default setting for the point of percussion alignment function (on). Decimation Filter, DEC_RATE NULL_CNFG enables the bias null command for the gyroscopes, disables the bias null command for the accelerometers, and sets the average time to ~15.42 seconds. tB = 2TBC/4250 = 210/4250 = ~0.241 seconds Table 136. DEC_RATE Register Definitions Page 0x03 Addresses 0x0C, 0x0D Default 0x0000 Access R/W tA = 64 × tB = 64 × 0.241 = 15.42 seconds Flash Backup Yes where: tB is the time base. tA is the averaging time. Table 137. DEC_RATE Bit Definitions Bits [15:0] Description Decimation rate, binary format, maximum = 4249 The DEC_RATE register (see Table 136 and Table 137) provides user control for the final filter stage (see Figure 26), which averages and decimates the accelerometers and gyroscopes data, while also extending the time that the delta angle and delta velocity track between each update. The output sample rate is equal to 4250/(DEC_RATE + 1). For example, select Page 3 (DIN = 0x8003), and set DEC_RATE = 0x2A (DIN = 0x8C2A, then DIN = 0x8D00) to reduce the output sample rate to ~98.8 SPS (4250 ÷ 43). Data Update Rate in External Sync Modes When using the input sync option, in direct mode (FNCTIO_ CTRL[8:7] = 01, see Table 131), replace the 4250 number in this relationship with the input clock frequency. When using the input sync option, in PPS mode (FNCTIO_CTRL[8:7] = 11, see Table 131), replace the 4250 number in this relationship with the product of the input sync frequency and the scale value in the SYNC_SCALE register (see Table 141). Continuous Bias Estimation (CBE), NULL_CNFG Table 138. NULL_CNFG Register Definitions Page 0x03 Addresses 0x0E, 0x0F Default 0x070A Access R/W Flash Backup Yes Table 139. NULL_CNFG Bit Definitions Bits [15:14] 13 12 11 10 9 8 [7:4] [3:0] Description Not used Z-axis acceleration bias correction enable (1 = enabled) Y-axis acceleration bias correction enable (1 = enabled) X-axis acceleration bias correction enable (1 = enabled) Z-axis gyroscope bias correction enable (1 = enabled) Y-axis gyroscope bias correction enable (1 = enabled) X-axis gyroscope bias correction enable (1 = enabled) Not used Time base control (TBC), range: 0 to 13 (default = 10); tB = 2TBC/4250, time base; tA = 64 × tB, average time When a sensor bit in NULL_CNFG is active (equal to 1), setting GLOB_CMD[0] = 1 (DIN sequence: 0x8003, 0x8201, 0x8300) causes its bias correction register to automatically update with a value that corrects for its present bias error (from the CBE). For example, setting NULL_CNFG[8] equal to 1 causes an update in the XG_BIAS_LOW (see Table 93) and XG_BIAS_HIGH (see Table 95) registers. Scaling the Input Clock (PPS Mode), SYNC_SCALE Table 140. SYNC_SCALE Register Definitions Page 0x03 Addresses 0x10, 0x11 Default 0x109A Access R/W Flash Backup Yes Table 141. SYNC_SCALE Bit Definitions Bits [15:0] Description External clock scale factor (KECSF), binary format The PPS mode (FNCTIO_CTRL[8] = 1, see Table 131) supports the use of an input sync frequency that is slower than the data sample rates of the inertial sensors. This mode supports a frequency range of 1 Hz to 128 Hz for the input sync mode. In this mode, the data sample rate is equal to the product of the value in the SYNC_SCALE register (see Table 140 and Table 141) and the input sync frequency. For example, the following command sequence sets the data collection and processing rate (fSM in Figure 23 and Figure 24) to 4000 Hz (SYNC_SCALE = 0x0FA0) when using a 1 Hz signal on the DIO3 line as the external clock input, while also preserving the factory default configuration for the data ready signal: 1. 2. 3. 4. 5. Select Page 3 (DIN = 0x8003). Set SYNC_SCALE[7:0] = 0xA0 (DIN = 0x90A0). Set SYNC_SCALE[15:8] = 0x0F (DIN = 0x910F). Set FNCTIO_CTRL[7:0] = 0xFD (DIN = 0x86ED). Set FNCTIO_CTRL[15:8] = 0x00 (DIN = 0x8701). Note that the data ready indicator pin does not begin to toggle until at least two external clock edges (with valid time period between them) are detected by the ADIS16495. The NULL_CNFG register (see Table 138 and Table 139) provides the configuration controls for the continuous bias estimator (CBE), which associates with the bias correction update command in GLOB_CMD[0] (see Table 129). NULL_CNFG[3:0] establishes the total average time (tA) for the bias estimates and NULL_CNFG[13:8] provide on/off controls for each sensor. The factory default configuration for Rev. D | Page 31 of 37 ADIS16490 Data Sheet FIR Filter Control, FILTR_BNK_0, FILTR_BNK_1 Table 147. FIRM_REV Bit Definitions Table 142. FILTR_BNK_0 Register Definitions Bits [15:12] Page 0x03 Addresses 0x16, 0x17 Default 0x0000 Access R/W Flash Backup Yes [11:8] Table 143. FILTR_BNK_0 Bit Definitions Bits 15 14 [13:12] 11 [10:9] 8 [7:6] 5 [4:3] 2 [1:0] Description (Default = 0x0000) Don’t care Y-axis accelerometer filter enable (1 = enabled) Y-axis accelerometer filter bank selection: 00 = Bank A, 01 = Bank B, 10 = Bank C, 11 = Bank D X-axis accelerometer filter enable (1 = enabled) X-axis accelerometer filter bank selection: 00 = Bank A, 01 = Bank B, 10 = Bank C, 11 = Bank D Z-axis gyroscope filter enable (1 = enabled) Z-axis gyroscope filter bank selection: 00 = Bank A, 01 = Bank B, 10 = Bank C, 11 = Bank D Y-axis gyroscope filter enable (1 = enabled) Y-axis gyroscope filter bank selection: 00 = Bank A, 01 = Bank B, 10 = Bank C, 11 = Bank D X-axis gyroscope filter enable (1 = enabled) X-axis gyroscope filter bank selection: 00 = Bank A, 01 = Bank B, 10 = Bank C, 11 = Bank D [7:4] [3:0] The FIRM_REV register (see Table 146 and Table 147) provides the firmware revision for the internal firmware. This register uses a BCD format, where each nibble represents a digit. For example, if FIRM_REV = 0x1234, the firmware revision is 12.34. Firmware Revision Day and Month, FIRM_DM Table 148. FIRM_DM Register Definitions Page 0x03 Bits [15:12] [11:8] Page 0x03 [7:4] Default 0x0000 Access R/W Flash Backup Yes Table 145. FILTR_BNK_1 Bit Definitions Bits [15:3] 2 [1:0] [3:0] Description Don’t care Z-axis accelerometer filter enable (1 = enabled) Z-axis accelerometer filter bank selection: 00 = Bank A, 01 = Bank B, 10 = Bank C, 11 = Bank D The FILTR_BNK_0 (see Table 142 and Table 143) and FILTR_ BNK_1 (see Table 144 and Table 145) registers provide the configuration controls for the FIR filter bank in the signal chain of each sensor (see Figure 26). These registers provide on/off control for the FIR bank for each inertial sensor, along with the FIR bank (A, B, C, or D) that each sensor uses. Table 146. FIRM_REV Register Definitions Addresses 0x78, 0x79 Default Not applicable Access R Default Not applicable Access R Flash Backup Yes Description Factory configuration month BCD code, tens digit, numerical format = 4-bit binary, range = 0 to 2 Factory configuration month BCD code, ones digit, numerical format = 4-bit binary, range = 0 to 9 Factory configuration day BCD code, tens digit, numerical format = 4-bit binary, range = 0 to 3 Factory configuration day BCD code, ones digit, numerical format = 4-bit binary, range = 0 to 9 The FIRM_DM register (see Table 148 and Table 149) contains the month and day of the factory configuration date. FIRM_ DM[15:12] and FIRM_DM[11:8] contain digits that represent the month of the factory configuration in a BCD format. For example, November is the 11th month in a year and is represented by FIRM_DM[15:8] = 0x11. FIRM_DM[7:4] and FIRM_DM[3:0] contain digits that represent the day of factory configuration in a BCD format. For example, the 27th day of the month is represented by FIRM_DM[7:0] = 0x27. Firmware Revision, FIRM_REV Page 0x03 Addresses 0x7A, 0x7B Table 149. FIRM_DM Bit Definitions Table 144. FILTR_BNK_1 Register Definitions Addresses 0x18, 0x19 Description Firmware revision binary coded decimal (BCD) code, tens digit, numerical format = 4-bit binary, range = 0 to 9 Firmware revision BCD code, ones digit, numerical format = 4-bit binary, range = 0 to 9 Firmware revision BCD code, tenths digit, numerical format = 4-bit binary, range = 0 to 9 Firmware revision BCD code, hundredths digit, numerical format = 4-bit binary, range = 0 to 9 Flash Backup Yes Rev. D | Page 32 of 37 Data Sheet ADIS16490 Firmware Revision Year, FIRM_Y Signature CRC, Calibration Values, CAL_SIGTR_LWR Table 150. FIRM_Y Register Definitions Table 154. CAL_SIGTR_LWR Register Definitions Page 0x03 Addresses 0x7C, 0x7D Default Not applicable Access R Flash Backup Yes Page 0x04 Addresses 0x04, 0x05 Default Not applicable Access R Table 151. FIRM_Y Bit Definitions Table 155. CAL_SIGTR_LWR Bit Definitions Bits [15:12] Bits [15:0] [11:8] [7:4] [3:0] Description Factory configuration year BCD code, thousands digit, numerical format = 4-bit binary, range = 0 to 9 Factory configuration year BCD code, hundreds digit, numerical format = 4-bit binary, range = 0 to 9 Factory configuration year BCD code, tens digit, numerical format = 4-bit binary, range = 0 to 3 Factory configuration year BCD code, ones digit, numerical format = 4-bit binary, range = 0 to 9 The FIRM_Y register (see Table 150 and Table 151) contains the year of the factory configuration date. For example, the year 2013 is represented by FIRM_Y = 0x2013. Table 156. CAL_SIGTR_UPR Register Definitions Page 0x04 Default Not applicable Access R Flash Backup Yes Table 153. BOOT_REV Bit Definitions Bits [15:8] [7:0] Addresses 0x06, 0x07 Default Not applicable Access R Flash Backup Yes Table 157. CAL_SIGTR_UPR Bit Definitions Bits [15:0] Description Factory programmed CRC value for the program code, high word Derived CRC, Calibration Values, CAL_DRVTN_LWR Table 152. BOOT_REV Register Definitions Addresses 0x7E, 0x7F Description Factory programmed CRC value for the program code, low word Signature CRC, Calibration Values, CAL_SIGTR_UPR Boot Revision Number, BOOT_REV Page 0x03 Flash Backup Yes Table 158. CAL_DRVTN_LWR Register Definitions Page 0x04 Addresses 0x08, 0x09 Default Not applicable Access R Flash Backup No Table 159. CAL_DRVTN_LWR Bit Definitions Description Binary, major revision number Binary, minor revision number Bits [15:0] Description Calculated CRC value for the program code, low word Continuous SRAM Testing Derived CRC, Calibration Values, CAL_DRVTN_UPR This device employs a CRC function on the SRAM memory blocks that contain the program code (CODE_SIGTR_xxx) and the calibration coefficients (CAL_DRVTN_xxx). This process operates in the background and generates real-time, 32-bit CRC values for the program code and calibration coefficients, respectively. At the conclusion of each cycle, the processor writes these calculated values in the CAL_DRVTN_xxx and CODE_DRVTN_xxx registers (see Table 159, Table 161, Table 167, and Table 169) and compares them with the signature values, which reflect the state of these memory locations at the time of factory configuration. When the calculation results do not match the signature values, SYS_E_ FLAG[2] increases to a 1. The respective signature values are available for user access through the CAL_SIGTR_xxx and CODE_SIGTR_xxx registers (see Table 155, Table 157, Table 163, and Table 165). The following conditions must be met for SYS_E_FLAG[2] to remain at the zero level: Table 160. CAL_DRVTN_UPR Register Definitions • • • • Signature CRC, Program Code, CODE_SIGTR_UPR CAL_SIGTR_LWR = CAL_DRVTN_LWR CAL_SIGTR_UPR = CAL_DRVTN_UPR CODE_SIGTR_LWR = CODE_DRVTN_LWR CODE_SIGTR_UPR = CODE_DRVTN_UPR Page 0x04 Addresses 0x0A, 0x0B Default Not applicable Access R Flash Backup No Table 161. CAL_DRVTN_UPR Bit Definitions Bits [15:0] Description Calculated CRC value for the program code, high word Signature CRC, Program Code, CODE_SIGTR_LWR Table 162. CODE_SIGTR_LWR Register Definitions Page 0x04 Addresses 0x0C, 0x0D Default Not applicable Access R Flash Backup Yes Table 163. CODE_SIGTR_LWR Bit Definitions Bits [15:0] Description Factory programmed CRC value for the calibration coefficients, low word Table 164. CODE_SIGTR_UPR Register Definitions Page 0x04 Rev. D | Page 33 of 37 Addresses 0x0E, 0x0F Default Not applicable Access R Flash Backup Yes ADIS16490 Data Sheet Table 165. CODE_SIGTR_UPR Bit Definitions FIR Filter Bank A, FIR_COEF_A000 to FIR_COEF_A119 Bits [15:0] Table 172. FIR Filter Bank A Memory Map Description Factory programmed CRC value for the calibration coefficients, high word Derived CRC, Program Code, CODE_DRVTN_LWR Table 166. CODE_DRVTN_LWR Register Definitions Page 0x04 Addresses 0x10, 0x11 Default Not applicable Access R Flash Backup No Table 167. CODE_DRVTN_LWR Bit Definitions Bits [15:0] Description Calculated CRC value for the calibration coefficients, low word Derived CRC, Program Code, CODE_DRVTN_UPR Table 168. CODE_DRVTN_LWR Register Definitions Page 0x04 Addresses 0x12, 0x13 Default Not applicable Access R Flash Backup No Table 169. CODE_DRVTN_UPR Bit Definitions Bits [15:0] Description Calculated CRC value for the calibration coefficients, high word Default Not applicable Access R Flash Backup Yes Table 171. SERIAL_NUM Bit Definitions Bits [15:0] Addresses 0x00, 0x01 0x02 to 0x07 0x08, 0x09 0x0A, 0x0B 0x0C to 0x7D 5 6 6 6 6 6 0x05 0x06 0x06 0x06 0x06 0x06 0x7E, 0x07F 0x00, 0x01 0x02 to 0x07 0x08, 0x09 0x0A, 0x0B 0x0C to 0x7D 6 0x06 0x7E, 0x7F Register PAGE_ID Not used FIR_COEF_A000 FIR_COEF_A001 FIR_COEF_A002 to FIR_COEF_A058 FIR_COEF_A059 PAGE_ID Not used FIR_COEF_A060 FIR_COEF_A061 FIR_COEF_A062 to FIR_COEF_A118 FIR_COEF_A119 Table 173 and Table 174 provide detailed register and bit definitions for one of the FIR coefficient registers in Bank A, FIR_COEF_A071. Table 175 provides a configuration example, which sets this register to a decimal value of −169 (0xFF57). Page 0x06 Table 170. SERIAL_NUM Register Definitions Addresses 0x20, 0x21 PAGE_ID 0x05 0x05 0x05 0x05 0x05 Table 173. FIR_COEF_A071 Register Definitions Lot Specific Serial Number, SERIAL_NUM Page 0x04 Page 5 5 5 5 5 Addresses 0x1E, 0x1F Default Not applicable Access R/W Flash Backup Yes Table 174. FIR_COEF_A071 Bit Definitions Bits [15:0] Description FIR Bank A, Coefficient 71, twos complement Table 175. Configuration Example, FIR Coefficient Description Lot specific serial number FIR FILTERS The ADIS16490 provides four FIR filter banks to configure and select for each individual inertial sensor using the FILTR_BNK_0 (see Table 143) and FILTR_BNK_1 (see Table 145) registers. Each FIR filter bank (A, B, C, and D) has 120 taps that consume two pages of memory. The coefficient associated with each tap, in each filter bank, has its own dedicated register that uses a 16bit, twos complement format. The FIR filter has unity gain when the sum of all of the coefficients is equal to 32,768. For filter designs that require less than 120 taps, write 0x0000 to all unused registers to eliminate the latency associated with that particular tap. DIN 0x8006 0x9E57 0x9FFF Description Select Page 6 FIR_COEF_A071[7:0] = 0x57 FIR_COEF_A071[15:8] = 0xFF FIR Filter Bank B, FIR_COEF_B000 to FIR_COEF_B119 Table 176. Filter Bank B Memory Map Page 7 7 7 7 7 PAGE_ID 0x07 0x07 0x07 0x07 0x07 Addresses 0x00, 0x01 0x02 to 0x07 0x08, 0x09 0x0A, 0x0B 0x0C to 0x7D 7 8 8 8 8 8 0x07 0x08 0x08 0x08 0x08 0x08 0x7E, 0x07F 0x00, 0x01 0x02 to 0x07 0x08, 0x09 0x0A, 0x0B 0x0C to 0x7D 8 0x08 0x7E, 0x7F Rev. D | Page 34 of 37 Register PAGE_ID Not used FIR_COEF_B000 FIR_COEF_B001 FIR_COEF_B002 to FIR_COEF_B058 FIR_COEF_B059 PAGE_ID Not used FIR_COEF_B060 FIR_COEF_B061 FIR_COEF_B062 to FIR_COEF_B118 FIR_COEF_B119 Data Sheet ADIS16490 FIR Filter Bank C, FIR_COEF_C000 to FIR_COEF_C119 Default Filter Performance Table 177. Filter Bank C Memory Map The FIR filter banks have factory programmed filter designs. They are all low-pass filters that have unity dc gain. Table 179 provides a summary of each filter design, and Figure 50 shows the frequency response characteristics. The phase delay is equal to ½ of the total number of taps. Addresses 0x00, 0x01 0x02 to 0x07 0x08, 0x09 0x0A, 0x0B 0x0C to 0x7D 9 10 10 10 10 10 0x09 0x0A 0x0A 0x0A 0x0A 0x0A 0x7E, 0x07F 0x00, 0x01 0x02 to 0x07 0x08, 0x09 0x0A, 0x0B 0x0C to 0x7D 10 0x0A 0x7E, 0x7F Register PAGE_ID Not used FIR_COEF_C000 FIR_COEF_C001 FIR_COEF_C002 to FIR_COEF_C058 FIR_COEF_C059 PAGE_ID Not used FIR_COEF_C060 FIR_COEF_C061 FIR_COEF_C062 to FIR_COEF_C118 FIR_COEF_C119 Table 179. FIR Filter Descriptions, Default Configuration FIR Filter Bank A B C D 0 –3dB –20 Table 178. Filter Bank D Memory Map PAGE_ID 0x0B 0x0B 0x0B 0x0B 0x0B Addresses 0x00, 0x01 0x02 to 0x07 0x08, 0x09 0x0A, 0x0B 0x0C to 0x7D 11 12 12 12 12 12 0x0B 0x0C 0x0C 0x0C 0x0C 0x0C 0x7E, 0x07F 0x00, 0x01 0x02 to 0x07 0x08, 0x09 0x0A, 0x0B 0x0C to 0x7D 12 0x0C 0x7E, 0x7F −3 dB Frequency (Hz) 300 100 300 100 –10 FIR Filter Bank D, FIR_COEF_D000 to FIR_COEF_D119 Page 11 11 11 11 11 Taps 120 120 32 32 Register PAGE_ID Not used FIR_COEF_D000 FIR_COEF_D001 FIR_COEF_D002 to FIR_COEF_D058 FIR_COEF_D059 PAGE_ID Not used FIR_COEF_D060 FIR_COEF_D061 FIR_COEF_D062 to FIR_COEF_D118 FIR_COEF_D119 –30 –40 –50 –60 –70 NO FIR ACCELEROMETER NO FIR GYROSCOPE BANK A BANK B BANK C BANK D –80 –90 –100 10 100 FREQUENCY (Hz) 1k Figure 50. FIR Filter Frequency Response Curves Rev. D | Page 35 of 37 15029-031 PAGE_ID 0x09 0x09 0x09 0x09 0x09 MAGNITUDE (dB) Page 9 9 9 9 9 ADIS16490 Data Sheet APPLICATIONS INFORMATION MOUNTING BEST PRACTICES PREVENTING MISINSERTION For the best performance, follow these simple rules when installing the ADIS16490 into a system: The ADIS16490 connector uses the same pattern as the ADIS16485, but with Pin 12 and Pin 15 missing. This pin configuration enables a mating connector to plug these holes, which makes inserting the ADIS16490 incorrectly very difficult. Samtec has a custom part number that provides this type of mating socket: ASP-193371-04. • Eliminate opportunity for translational force (x- and y-axis direction, per Figure 40) application on the electrical connector. Use uniform mounting forces on all four corners. The suggested torque setting is 40 inch ounces (0.285 Nm). When the IMU rests on the PCB, which contains the mating connector (see Figure 51), use a diameter of at least 2.85 mm for the passthrough holes. • • These rules help prevent irregular force profiles, which can warp the package and introduce bias errors in the sensors. Figure 51 and Figure 52 provide details for mounting hole and connector alignment pin drill locations. PASSTHROUGH HOLE FOR MOUNTING SCREWS POWER SUPPLY CONSIDERATIONS DIAMETER OF THE HOLE MUST ACCOMODATE DIMENSIONAL TOLERANCE BETWEEN THE CONNECTOR AND HOLES. The VDD power supply must charge 46 µF of capacitance (inside of the ADIS16490, across the VDD and GND pins) during its initial ramp and settling process. When VDD reaches 2.85 V, the ADIS16490 begins its internal start-up process, which generates additional transient current demand. See Figure 53 for a typical current profile during the start-up process. The first peak in Figure 53 relates to charging the 46 µF capacitor bank, whereas the other transient activity relates to numerous functions turning on during the initialization process of the ADIS16490. 42.600 DEVICE OUTLINE 21.300 BSC 1.642 BSC The ADIS16IMU1/PCBZ (sold separately) provides a breakout board function for the ADIS16490, which means that it provides access to the ADIS16490 through larger connectors that support standard 1 mm ribbon cabling. It also provides four mounting holes for attachment of the ADIS16490 to the breakout board. Use the EVAL-ADIS2 and ADIS16IMU1/PCBZ to evaluate the ADIS16490 on a PC-based platform. 19.800 BSC 0.560 BSC 2× ALIGNMENT HOLES FOR MATING SOCKET 5 BSC Breakout Board, ADIS16IMU1/PCBZ PC-Based Evaluation, EVAL-ADIS2 39.600 BSC 5 BSC 15029-033 NOTES 1. ALL DIMENSIONS IN mm UNITS. 2. IN THIS CONFIGURATION, THE CONNECTOR IS FACING DOWN AND ITS PINS ARE NOT VISIBLE. EVALUATION TOOLS T a b a 1.608ms 92.00mA b 159.8ms 152.0mA Δ158.2ms Δ60.00mA Figure 51. Suggested PCB Layout Pattern, Connector Down 0.4334 [11.0] 0.019685 [0.5000] (TYP) 0.0240 [0.610] 3 VDD 0.054 [1.37] DR 0.1800 [4.57] 2 0.022± DIA (TYP) NONPLATED 0.022 DIA THRU HOLE (TYP) THRU HOLE 2× NONPLATED THRU HOLE 15029-034 4 0.0394 [1.00] Figure 52. Suggested Layout and Mechanical Design When Using Samtec CLM-112-02-G-D-A for the Mating Connector CURRENT CH2 2.0V BW CH3 2.0V BW CH4 100mA BW M40.0ms T 20.10% A CH3 3.00V 12.5MS/s 5M pts 15029-350 0.0394 [1.00] Figure 53. Transient Current Demand, Startup (DR Means Data Ready) Rev. D | Page 36 of 37 Data Sheet ADIS16490 PACKAGING AND ORDERING INFORMATION OUTLINE DIMENSIONS 39.70 39.60 39.50 44.15 44.00 43.85 2.50 Ø 2.40 2.30 2.115 2.040 1.965 2.075 2.000 1.925 47.15 47.00 46.85 37.67 37.57 37.47 42.70 42.60 42.50 20.10 20.00 19.90 1.76 1.66 1.56 TOP VIEW BOTTOM VIEW 2.115 Ø 2.040 1.965 34.68 34.58 34.48 DETAIL A Mating Connector: SAMTECH CLM-112-02-G-D-A DETAIL A 0.250 BSC FRONT VIEW 2.94 2.84 2.74 14.15 14.00 13.85 0.250 BSC 0.40 0.30 SQ 0.20 07-26-2019-B 1.00 BSC PITCH Figure 54. 24-Lead Module with Connector Interface [MODULE] (ML-24-9) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADIS16490BMLZ 1 Temperature Range −40°C to +105°C Description 24-Lead Module with Connector Interface [MODULE] Z = RoHS Compliant Part. ©2016–2020 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D15029-9/20(D) Rev. D | Page 37 of 37 Package Option ML-24-9