High Efficiency Dual
Power Supply Controller
ADP3026
FEATURES
GENERAL DESCRIPTION
Wide input voltage range: 5.5 V to 25 V
High conversion efficiency > 96%
Integrated current sense—no external resistor required
Low shutdown current: 19 µA (typical)
Voltage mode PWM with input feed-forward for fast line
transient response
Dual synchronous buck controllers
Built-in gate drive boost circuit for driving external
N-channel MOSFETs
2 fixed output voltages: 3.3 V and 5 V
PWM frequency: 200 kHz
Extensive circuit protection functions
The ADP3026 is a highly efficient dual synchronous buck
switching regulator controller optimized for converting a
battery or adapter input into multiple supply voltages. The
ADP3026 provides accurate and reliable short-circuit protection
using an internal current sense circuit, which reduces cost and
increases overall efficiency. Other protection features include
programmable soft start, UVLO, and integrated output
undervoltage/overvoltage protection.
The ADP3026 is specified over the 0°C to 70°C commercial
temperature range and is available in a 28-lead TSSOP package.
APPLICATIONS
Portable instruments
General-purpose dc-to-dc converters
FUNCTIONAL BLOCK DIAGRAM
VIN
5.5V TO 25V
5V LINEAR
REF
Q1
Q3
L2
L1
5V
3.3V
3.3V
SMPS
5V
SMPS
Q2
Q4
PWRGD
POWER-ON
RESET
ADP3026
02950-001
SS3
SS5
Figure 1.
Rev. 0
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Tel: 781.329.4700
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Fax: 781.326.8703
© 2004 Analog Devices, Inc. All rights reserved.
ADP3026
TABLE OF CONTENTS
Specifications..................................................................................... 3
Circuit Description .................................................................... 10
Absolute Maximum Ratings............................................................ 5
Application Information ........................................................... 11
ESD Caution.................................................................................. 5
Layout Considerations............................................................... 16
Pin Configuration and Function Descriptions............................. 6
Outline Dimensions ....................................................................... 18
Typical Performance Characteristics ............................................. 8
Ordering Guide .......................................................................... 18
Theory of Operation ...................................................................... 10
REVISION HISTORY
10/04—Revision 0: Initial Version
Rev. 0 | Page 2 of 20
ADP3026
SPECIFICATIONS
@ TA = 0°C to 70°C, VIN = 12 V, SS5 = SS3 = INTVCC, INTVCC Load = 0 mA, REF Load = 0 mA, SD = 5 V, unless otherwise noted.
All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC) methods.
Table 1.
Parameter
INTERNAL 5 V REGULATOR
Input Voltage Range
5 V Voltage
Line Regulation
Total Variation
Undervoltage Lockout
Threshold Voltage
Symbol
INTVCC
Conditions
TA = 25°C
5.5 V ≤ VIN ≤ 25 V
Line, temperature
INTVCC falling
Undervoltage Lockout
Hysteresis
REFERENCE
Output Voltage1
SUPPLY CURRENT
Shutdown Current
Standby Current
Min
5.5
4.95
4.8
4.05
Typ
5.02
1.0
4.25
Max
Unit
25
5.15
V
V
mV/V
V
V
5.2
4.5
270
REF
IQ
5.5 V ≤ VIN ≤ 25 V
784
SD = 0 V
SS3 = SS5 = 0 V
SD = 5 V
No loads
SS3 = SS5 = 5 V
FB5 = 5.05 V, FB3 = 3.33 V
Quiescent Current
OSCILLATOR
Frequency
POWER GOOD
Output Voltage in Regulation
Output Voltage out of Regulation
PWRGD Trip Threshold
PWRGD Hysteresis
CPOR Pull-Up Current
ERROR AMPLIFIER
DC Gain2
Gain-Bandwidth Product
MAIN SMPS CONTROLLERS
Fixed 5 V Output Voltage
Fixed 3.3 V Output Voltage
Current Limit Threshold
CLSET5 = CLSET3 = Floating
CLSET5 = CLSET3 = 0 V
Soft-Start Current
Soft-Start Turn-On Threshold
Transition Time (DRVL)
Rise
Fall
Transition Time (DRVH)
Rise
Fall
Logic Input Low Voltage
Logic Input High Voltage
2
fOSC
PWRGD
5.5 V ≤ VIN ≤ 25 V
165
10 kΩ pull-up to 5 V
10 kΩ pull-up to 5 V
FB5 < 90% of nominal output value
FB5 rising
FB5 falling
CPOR = 1.2 V
4.8
−6
−3
800
816
V
19
120
50
200
µA
µA
1.3
1.9
mA
200
235
kHz
0.4
V
V
−3.7
4
−1
−1.5
−0.3
47
10
GBW
FB5
FB3
mV
%
%
µA
dB
MHz
5.5 V ≤ VIN ≤25 V
5.5 V ≤ VIN ≤25 V
4.90
3.234
5.0
3.3
5.10
3.366
V
V
5.5 V ≤ VIN ≤ 25 V, TA = 25°C
5.5 V ≤ VIN ≤ 25 V, TA = 25°C
SS3 = SS5 = 3 V
54
240
0.7
0.4
72
300
2.1
0.6
90
360
3.8
0.8
mV
mV
µA
V
SS5, SS3
tR(DRVL)
tF(DRVL)
CLOAD = 3000 pF, 10% to 90%
CLOAD = 3000 pF, 90% to 10%
40
45
70
70
ns
ns
tR(DRVH)
tF(DRVH)
CLOAD = 3000 pF, 10% to 90%
CLOAD = 3000 pF, 90% to 10%
SD
SD
50
50
100
100
0.6
ns
ns
V
V
Rev. 0 | Page 3 of 20
2.9
ADP3026
Parameter
FAULT PROTECTION
Output Overvoltage Trip Threshold
Output Undervoltage Lockout Threshold
1
2
Symbol
Conditions
Min
Typ
Max
Unit
With respect to nominal output
With respect to nominal output
115
70
120
80
125
90
%
%
The reference’s line regulation error is insignificant. The reference cannot be used for external load.
Guaranteed by design, not tested in production.
Rev. 0 | Page 4 of 20
ADP3026
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
VIN to AGND
AGND to PGND
INTVCC
BST5, BST3 to PGND
BST5 to SW5
BST3 to SW3
CS5, CS3
SW3, SW5 to PGND
SD
DRVL5/3 to PGND
DRVH5/3 to SW5/3
All Other Inputs and Outputs
θJA
Operating Ambient
Temperature Range
Junction Temperature Range
Storage Temperature Range
Lead Temperature Range
(Soldering 10 s)
Rating
−0.3 V to +27 V
±0.3 V
AGND − 0.3 V to +6 V
−0.3 V to +32 V
−0.3 V to +6 V
−0.3 V to +6 V
AGND − 0.3 V to VIN
−2 V to VIN + 0.3 V
AGND − 0.3 V to +27 V
−0.3 V to INTVCC + 0.3 V
−0.3 V to INTVCC + 0.3 V
AGND − 0.3 V to INTVCC + 0.3 V
98°C/W
0°C to 70°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those listed in the operational sections
of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability. Absolute maximum ratings apply individually
only, not in combination. Unless otherwise specified, all other
voltages are referenced to GND.
0°C to 150°C
−65°C to +150°C
300°C
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on
the human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. 0 | Page 5 of 20
ADP3026
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
CS5 1
28 BST5
FB5 2
27 DRVH5
EAN5 3
EAO5 4
ADP3026
25 DRVL5
24 PGND
TOP VIEW
CLSET5 6 (Not to Scale) 23 SD
REF 7
22 INTVCC
AGND 8
CLSET3 9
SS3 10
21 VIN
20 DRVL3
19 SW3
EAO3 11
18 DRVH3
EAN3 12
17 BST3
FB3 13
16 CPOR
CS3 14
15 PWRGD
02950-002
SS5 5
26 SW5
Figure 2. 28-Lead TSSOP Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1
Mnemonic
CS5
2
3
4
5
6
FB5
EAN5
EAO5
SS5
CLSET5
7
REF
8
9
AGND
CLSET3
10
11
12
13
14
SS3
EAO3
EAN3
FB3
CS3
15
PWRGD
16
CPOR
17
18
19
20
21
22
23
BST3
DRVH3
SW3
DRVL3
VIN
INTVCC
SD
24
25
26
27
28
PGND
DRVL5
SW5
DRVH5
BST5
Function
Current Sense Input for the Top N-Channel MOSFET of the 5 V Buck Converter. Connect to the drain of the top
N-channel MOSFET.
Feedback Input for the 5 V Buck Converter. Connect to the output sense point in fixed output mode.
Inverting Input of the Error Amplifier of the 5 V Buck Converter. Use for external loop compensation.
Error Amplifier Output for the 5 V Buck Converter.
Soft Start for the 5 V Buck Converter. Also used as an on/off pin.
Current Limit Setting. A resistor can be connected from AGND to CLSET5. A minimum current limit is obtained
by leaving it unconnected. A maximum current limit is obtained by connecting it to AGND.
800 mV Band Gap Reference. Bypass it with a capacitor (22 nF typical) to AGND. REF cannot be used directly
with an external load.
Analog Signal Ground.
Current Limit Setting. A resistor can be connected from AGND to CLSET3. A minimum current limit is obtained
by leaving it unconnected. A max current limit is obtained by connecting it to AGND.
Soft Start for the 3.3 V Buck Converter. Also used as an on/off pin.
Error Amplifier Output for the 3.3 V Buck Converter.
Error Amplifier Inverting Input of the 3.3 V Buck Converter. Use for external loop compensation.
Feedback Input for the 3.3 V Buck Converter. Connect to output sense point.
Current Sense Input for the Top N-Channel MOSFET of the 3.3 V Buck Converter. It should be connected to the
drain of the N-channel MOSFET.
Power Good Output. PWRGD goes low with no delay whenever the 5 V output drops 7% below its nominal
value. When the 5 V output is within −3% of its nominal value, PWRGD will be released after a time delay
determined by the timing capacitor on the CPOR pin.
Connect a capacitor between CPOR and AGND to set the delay time for the PWRGD pin. A 1 µA pull-up current
is used to charge the capacitor. A manual reset (MR) function can also be implemented by grounding this pin.
Boost Capacitor Connection for High-Side Gate Driver of the 3.3 V Buck Converter.
High-Side Gate Driver for the 3.3 V Buck Converter.
Switching Node (Inductor) Connection of the 3.3 V Buck Converter.
Low-Side Gate Driver of the 3.3 V Buck Converter.
Main Supply Input (5.5 V to 25 V).
Linear Regulator Bypass for the internal 5 V LDO. Bypass this pin with a 4.7 µF capacitor to AGND.
Shutdown Control Input, Active Low. If SD = 0 V, the chip is in shutdown with very low quiescent current. For
automatic startup, connect SD to VIN directly.
Power Ground.
Low-Side Driver for the 5 V Buck Converter.
Switching Node (Inductor) Connection for the 5 V Buck Converter.
High-Side Gate Driver for the 5 V Buck Converter.
Boost Capacitor Connection for the High-Side Gate Driver of the 5 V Buck Converter.
Rev. 0 | Page 6 of 20
ADP3026
INPUT
VIN
21
ADP3026
72mV
– +
+
CS5
1
–
SD 23
INTVCC
22
5V
LINEAR REG
14mV
– +
+
–
REF
AGND
7
CLSET5
6
800mV
REF
UVLO
8
28
27
26
BST5
DRVH5
SW5
INTVCC
200kHz
OSC
CONTROL
LOGIC
25
24
PWRGD 15
VOUT5
5V
DRVL5
PGND
FB5
+
–
–3mV
1µA
16
2
FB5
+
+2% 816mV
–
+
0% 800mV
–
+
–2% 784mV
–
–
EA
3
800mV
4
SHUTDOWN
EAN5
EAO5
+
+20% 960mV
–
+
–20% 640mV
–
S
OC
Q
R
–
+
1.8V
2.5µA
SS5
5
+
ON5
–
0.6V
02950-003
CPOR
POWERON
RESET
+
5V
DUPLICATE FOR SECOND CONTROLLER
Figure 3. Detailed Block Diagram
Rev. 0 | Page 7 of 20
ADP3026
TYPICAL PERFORMANCE CHARACTERISTICS
100
190
VIN = 7V
90
170
VIN = 15V
80
CURRENT (µA)
60
50
130
70°C
110
25°C
90
40
0°C
70
30
0
1
2
3
4
5
6
7
OUTPUT CURRENT (A)
50
02950-004
20
5
15
20
25
INPUT VOLTAGE (V)
Figure 4. Efficiency vs. 5 V Output Current
100
10
02950-007
EFFICIENCY (%)
150
70
Figure 7. Input Shutdown Current vs. Input Voltage
210
VIN = 7V
VIN = 12V
90
OSCILLATOR FREQUENCY (kHz)
VIN = 15V
EFFICIENCY (%)
80
70
60
50
40
205
200
195
190
185
30
1
2
3
4
5
6
OUTPUT CURRENT (A)
180
0
25
50
02950-008
0
02950-005
20
75
AMBIENT TEMPERATURE (°C)
Figure 5. Efficiency vs. 3.3 V Output Current
Figure 8. Oscillator Frequency vs. Temperature
1800
350
70°C
1400
25°C
0°C
1200
1000
5
10
15
INPUT VOLTAGE (V)
20
25
02950-006
CURRENT (µA)
1600
300
250
200
0
10
20
30
40
50
60
AMBIENT TEMPERATURE (°C)
Figure 9. Current Limit Threshold vs. Temperature
Figure 6. Input Standby Current vs. Input Voltage
Rev. 0 | Page 8 of 20
70
02950-009
CURRENT LIMIT THRESHHOLD (mV)
CLSET = GND, VIN = 12V
ADP3026
805
CHANNEL 1 = IOUT 1A/DIV
CHANNEL 2 = VOUT 100nV/DIV
804
802
2
801
800
798
797
796
0
10
20
30
40
50
60
70
AMBIENT TEMPERATURE (°C)
02950-010
1
795
M40µs
A CH1
18.4mV
Figure 13. Load Transient Response - 1A to 3A
Figure 10. Reference Output vs. Temperature
VIN = 12V
CSS5 = 22nF
CSS3 = 83nF
CH1 10mVΩ CH2 100mV
02950-012
IN = 15V
OUT = 5V
L = 10µH
COUT = 220µF
R_INT = 130kΩ
R1 = 6.2kΩ
C1 = 220pF
C3 = 27pF
R2 = 175kΩ
C2 = 330pF
IOUT = 1A – 3A
799
CHANNEL 1 = 5V OUTPUT
CHANNEL 2 = 3.3V OUTPUT
CH1 = VIN
CHANNEL 3 = SS5
CH2 2V
CH3 5V
CH4 5V
M40ms
A CH1
3.2V
02950-011
CH1 2V
Figure 11. Soft Start Sequencing
Figure 14. VIN = 7.5 V to 22 V Transient, 5 V Output,
CH1—Input Voltage, CH2—Output Voltage
CHANNEL 1 = IOUT 1A/DIV
CHANNEL 2 = VOUT 100nV/DIV
2
1
IN = 15V
OUT = 5V
L = 10µH
COUT = 220µF
R_INT = 130kΩ
R1 = 6.2kΩ
C1 = 220pF
C3 = 27pF
R2 = 175kΩ
C2 = 330pF
IOUT = 1A – 3A
CH1 10mVΩ CH2 100mV
M40µs
A CH1
02950-014
CH2 = VOUT
CHANNEL 4 = SS3
18.4mV
02950-013
REFERENCE OUTPUT (mV)
803
Figure 12. Load Transient Response - 3A to 1A
Rev. 0 | Page 9 of 20
ADP3026
THEORY OF OPERATION
The ADP3026 is a step-down power supply controller for
battery-powered applications. The ADP3026 contains the
control circuit for two synchronous step-down converter. for
fixed 3.3 V and 5 V outputs.
MOSFET falls to zero when in discontinuous conduction mode
(DCM). In continuous conduction mode (CCM), the current
flowing through the low-side MOSFET never reaches zero, so
the synchronous rectifier is turned off by the next clock cycle.
Shutdown (SD)
CIRCUIT DESCRIPTION
Internal 5 V Supply (INTVCC)
An internal low dropout regulator (LDO) generates a 5 V
supply (INTVCC) to power all of the functional blocks within
the IC. The total current rating of this LDO is 50 mA. However,
this current is used for supplying gate-drive power, and it is
recommended that current is not drawn from this pin for other
purposes. Bypass INTVCC to AGND with a 4.7 µF capacitor. A
UVLO circuit is also included in the regulator. When INTVCC
< 4.1 V, the two switching regulators and the linear regulator
controller are shut down. The UVLO hysteresis voltage is about
270 mV. The internal LDO has a built-in foldback current limit
so that it will be protected if a short circuit is applied to the 5 V
output.
Holding SD low puts the ADP3026 into ultralow current
shutdown mode. For automatic startup, tie SD to VIN through a
resistor.
Soft Start and Power-Up Sequencing (SS)
SS3 and SS5 are soft start pins for the two controllers. A 2.1 µA
pull-up current charges an external soft start capacitor. Powerup sequencing is easily done by choosing different capacitance.
When SS3/SS5 < 0.6 V, the two switching regulators are turned
off. When 0.6 V < SS5/SS3 < 1.8 V, the regulators start working
in soft start mode. When SS3/SS5 > 1.8 V, the regulators are in
normal operating mode. The minimum soft start time (~20 µs)
is set by an internal capacitor. Table 4 shows the ADP3026’s
operating modes.
Reference (REF)
Current Limiting (CLSET)
The ADP3026 contains a precision 800 mV band gap reference.
Bypass REF to AGND with a 22 nF ceramic capacitor. The
reference is for internal use only; do not draw current from REF.
A cycle-by-cycle current limiting scheme is used by monitoring
current through the top N-channel MOSFET when it is turned
on. By measuring the voltage drop across the high-side
MOSFET VDS(ON), the external sense resistor is not required. The
current limit value is controlled by CLSET. When CLSET is
floating, the maximum VDS(ON) = 72 mV at room temperature;
when CLSET = 0 V, the maximum VDS(ON) = 300 mV at room
temperature. An external resistor (REXT) between CLSET and
AGND sets a current limit value between 72 mV and 300 mV.
The relationship between the external resistance and the
maximum VDS(ON) is
Boosted High-Side Gate Drive Supply (BST)
The gate drive voltage for the high-side N-channel MOSFET is
generated by a flying capacitor boost circuit. The boost
capacitor connected between BST and SW is charged from the
INTVCC supply. Use only small-signal diodes for the boost
circuit.
Synchronous Rectifier (DRVL)
Synchronous rectification is used to improve efficiency, reduce
conduction losses, and ensure proper start-up of the boost gate
driver circuit. Antishoot-through protection is included to
prevent cross conduction during switch transitions. The lowside driver must be turned off before the high-side driver is
turned on. For typical N-channel MOSFETs, the dead time is
about 50 ns. On the other edge, a dead time of about 50 ns is
achieved by an internal delay circuit. The synchronous rectifier
is turned off when the current flowing through the low-side
V DS(ON ) MAX = 72 mV
(110 kΩ + R EXT )
(26 kΩ + R EXT )
(1)
The temperature coefficient of R DS(ON) of the N-channel
MOSFET is canceled by the internal current limit circuitry so
that the current limit value is accurate over a wide temperature
range.
Table 4. Operating Modes
SD
SS5
SS3
Description
Low
High
High
High
High
High
X
SS5 < 0.6 V
0.6 V < SS5 < 1.8 V
1.8 V < SS5
X
X
X
SS3 < 0.6 V
X
X
0.6 V < SS3 < 1.8 V
1.8 V < SS3
All Circuits Turned Off
5 V and 3.3 V Off; INTVCC = 5 V, REF = 0.8 V
5 V in Soft Start
5 V in Normal Operation
3.3 V in Soft Start
3.3 V in Normal Operation
Rev. 0 | Page 10 of 20
ADP3026
Output Undervoltage Protection
Each switching controller has an undervoltage protection
circuit. When the current flowing through the high-side
MOSFET reaches the current limit continuously for eight clock
cycles, and the output voltage is below 20% of the nominal
output voltage, both controllers are latched off and do not
restart until SD or SS3/SS5 is toggled, or until VIN is cycled
below 4.1 V. This feature is disabled during soft start.
Output Overvoltage and Reverse Voltage Protection
Both converter outputs are continuously monitored for
overvoltage. If either output voltage is higher than the nominal
output voltage by more than 20%, both converters’ high-side
gate drivers (DRVH5/3) are latched off; the low-side gate
drivers are latched on and neither restart until SD or SS5/SS3 is
toggled, or until VIN is cycled below 4 V. The low-side gate driver
(DRVL) is kept high when the controller is in off-state and the
output voltage is less than 93% of the nominal output voltage.
Discharging the output capacitors through the main inductor
and low-side N-channel MOSFET causes the output voltage to
ring. This makes the output momentarily go below GND. To
prevent damage to the circuit, use a reverse-biased 1 A Schottky
diode in parallel with the output capacitors to clamp the
negative surge.
Power Good Output (PWRGD)
The ADP3026 provides a PWRGD signal that is used to indicate
to a microprocessor that the ADP3026 output voltages are in
regulation. During startup, the PWRGD pin is held low until the
5 V output is within –3% of its preset voltage. Then, after a time
delay determined by an external timing capacitor connected
from CPOR to GND, PWRGD is actively pulled up to INTVCC
by an external pull-up resistor. The delay is calculated by
Td =
1.2 V × CCPOR
(2)
1 μA
referred to as low power, basic, and extended power. Table 5
shows the input/output specifications for these three levels.
Input Voltage Range
The input voltage range of the ADP3026 is 5.5 V to 25 V. The
converter design is optimized to deliver the best performance
within a 7.5 V to 18 V range, which is the nominal voltage for
three to four cell Li-Ion battery stacks. Voltages above 18 V may
occur under light loads and when the system is powered from
an ac adapter with no battery installed.
Maximum Output Current and MOSFET Selection
The maximum output current for each switching regulator is
limited by sensing the voltage drop between the drain and
source of the high-side MOSFET when it is turned on. A
current sense comparator senses voltage drop between CS5 and
SW5 for the 5 V converter, and between CS3 and SW3 for the
3.3 V converter. The sense comparator threshold is 72 mV when
the programming pin, CLSET, is floating, and 300 mV when
CLSET is connected to ground. Current-limiting is based on
sensing the peak current. Peak current varies with input voltage
and depends on the inductor value. The higher the inductor
ripple current or input voltage, the lower the converter’s
maximum output current at the set current sense amplifier
threshold. The relation between peak inductor and dc output
current is given by
⎛ VIN ( MAX ) − VOUT ⎞
⎟
IPEAK = IOUT + VOUT × ⎜⎜
⎟
⎝ 2 × f × L × VIN ( MAX ) ⎠
At a given current comparator threshold, VTH, and MOSFET
RDS(ON), the maximum inductor peak current is
I PEAK =
A typical application circuit using the ADP3026 is shown in
Figure 15. Although the component values given in Figure 16
are based on a 5 V @ 4 A/3.3 V @ 4 A design, the ADP3026’s
output drivers are capable of handling output currents
anywhere from less than 1 A to more than 10 A. Throughout
this section, design examples and component values are given
for three different power levels. For simplicity, these levels are
V TH
RDS(ON )
(4)
Rearranging Equation 2 to solve for IOUT(MAX) gives
CPOR can also be used as a manual reset (MR) function. When
the 5 V output is lower than the preset voltage by more than 7%,
PWRGD is immediately pulled low.
APPLICATION INFORMATION
I (OUT ) MAX =
⎛ V IN ( MAX ) − V OUT ⎞
V TH
⎟⎟
− V OUT × ⎜⎜
RDS(ON )
⎝ 2 × f × L × V IN ( MAX ) ⎠
Input Voltage Range
Switching Output 1
Switching Output 2
(5)
Thus, VTH can be chosen to design the required maximum
output current. It is important to remember that this current
limit circuit is designed to protect against high current or shortcircuit conditions only. This protects the IC and MOSFETs long
enough to allow the output undervoltage protection circuitry to
latch off the supply.
Table 5. Typical Power Level Examples
Low Power
5.5 V to 25 V
3.3 V/2 A
5 V/2 A
(3)
Basic
5.5 V to 25 V
3.3 V/4 A
5 V/4 A
Rev. 0 | Page 11 of 20
Extended Power
5.5 V to 25 V
3.3 V/10 A
5 V/10 A
ADP3026
VIN
5.5V–25V
R8
4.7Ω
C12
4.7µF
U1
C15C
10µF
ADP3026
C1
330pF
R1
3.3kΩ
C2
R2
C3
33pF
510pF 175kΩ
R3
200kΩ
C4
33nF
BST5 28
2 FB5
DRVH5 27
3 EAN5
SW5 26
4 EAO5
DRVL5 25
5 SS5
C6
47nF
9 CLSET3
C7
33pF
L2
10µH
Q5
SI4410
D6
10BQ040
D4
10BQ040
VOUT5
C17B 5V, 4A
100µF
C17
100µF
Q4
SI4410
R10
10kΩ
INTVCC 22
VIN 21
DRVL3 20
C13
4.7µF
R9
10Ω
C15
10µF
SW3 19
10 SS3
R5
1000pF 91kΩ
D2
1N4148
SD 23
8 AGND
R4
200kΩ
C14
100nF
PGND 24
6 CLSET5
7 REF
C5
22nF
C8
1 CS5
C15D
10µF
11 EAO3
DRVH3 18
12 EAN3
BST3 17
D1
1N4148
C15B
10µF
Q2
C11 SI4410
L1
10µH
100nF
R6
1.8kΩ
C9
680pF
13 FB3
CPOR 16
14 CS3
PWRGD 15
C10
47nF
Q3
SI4410
D5
10BQ040
D3
10BQ040
C16
100µF
C16B
100µF
02950-015
R7
10kΩ
VOUT3
3.3V, 4A
Figure 15. 33 W, Dual-Output DC-DC Converter
Nominal Inductor Value
The inductor guidelines in this data sheet are based on the
assumption that the inductor ripple current is 30% of the
maximum output dc current at the nominal 12 V input voltage.
The inductor ripple current and inductance value are not
critical, but this choice is important in analyzing the trade-offs
between cost, size, efficiency, and volume. The higher the ripple
current, the lower the inductor size and volume. However, this
leads to higher ac losses in the windings. Conversely, a higher
inductance means lower ripple current and smaller output filter
capacitors, but slower transient response.
V OUT
V IN ( NOM ) × I OUT × f
Table 6. Standard Inductor Values (200 kHz Frequency)
3.3 V/2A
3.3 V/2A
3.3 V/10A
5 V/2A
5 V/4A
5 V/10A
20 µH
8.2 µH
3.3 µH
22 µH
10 µH
4.7 µH
Inductor Selection
Once the value for the inductor is known, there are two ways to
proceed: design the inductor in-house or buy the closest
inductor that meets the overall design goals.
Standard Inductors
The inductance should be based on the maximum output
current plus 15% (½ of the 30% ripple allowance) at the
nominal input voltage
L ≥ 3 × (V IN ( NOM ) − V OUT ) ×
Optimum standard inductor values for the three power levels
are shown in Table 6.
Buying a standard inductor provides the fastest, easiest solution,
and many companies offer suitable power inductor solutions. A
list of power inductor manufacturers is given in Table 7.
(6)
Rev. 0 | Page 12 of 20
ADP3026
Table 7. Recommended Inductor Manufacturers
Coilcraft
Phone: 847/639-6400
Fax: 847/639-1469
Web: www.coilcraft.com
SMT Power Inductors
Series 1608, 3308, 3316, 5022, 5022HC,
DO3340
Low Cost Solution
SMT Shielded Power Inductors
Series DS5022, DS3316, DT3316
Best for Low EMI/RFI
Power Inductors and Chokes,
Series DC1012, PCV-0, PCV-1, PCV-2, PCH-27,
PCH-45
Low Cost
Coiltronics
Phone: 561/241-7876
Fax: 561/241-9339
Web: www.coiltronics.com
SMT Power Inductors
Series UNI-PAC2, UNI-PAC3 and UNI-PAC4
Low Cost Solution
SMT Power Inductors
Series, ECONO-PAC, VERSA-PAC
Best for Low Profile or Flexible Design
Power Inductors CTX Series
Low EMI/RFI
Low Cost Toroidal Inductors but Not
Miniature
CIN and COUT Selection
Chip Inductors
LQN6C, LQS66C
The value of COUT is determined by
In continuous conduction mode, the source current of the
upper MOSFET is approximately a square wave of duty cycle
VOUT/VIN. To prevent large voltage transients use a low ESR
input capacitor sized for the maximum rms current. The
maximum rms capacitor current is given by
I RMS = V OUT × (V IN − V OUT ) ×
Murata Electronics
North America Inc.
Phone: 770/436-1300
Fax: 770/436-3030
Web: www.murata.com
SMT Power Inductors
Series LQT2535
Best for Low EMI/RFI
I OUT ( MAX )
V IN
COUT =
The selection of the output capacitor, COUT, is driven by the
required effective series resistance (ESR) and the desired output
ripple. A good guideline is to limit the ripple voltage to 1% of
the nominal output voltage. It is assumed that the total ripple is
caused by two factors: 25% comes from the COUT bulk
capacitance value, and 75% comes from the capacitor ESR.
(8)
where IRIPPLE = 0.3 × IOUT and VRIPPLE = 0.01 × VOUT. The
maximum acceptable ESR of COUT is found using
(7)
This formula has a maximum at VIN = 2 × VOUT, where IRMS =
IOUT(MAX)/2. Note that the capacitor manufacturer’s ripple current
ratings are often based on only 2000 hours of life. It is therefore
advisable to further derate the capacitor, or to choose a
capacitor rated at a higher temperature than required. Several
capacitors may also be connected in parallel to meet size or
height requirements in the design. If electrolytic or tantalum
capacitors are used, place an additional 0.1 µF to 1 µF ceramic
bypass capacitor in parallel with CIN.
I RIPPLE
2 × f × V RIPPLE
ESR ≤ 0.75 ×
V RIPPLE
I RIPPLE
(9)
Manufacturers such as Vishay, AVX, Elna, WIMA, and Sanyo
provide good high performance capacitors. Sanyo’s OSCON
semiconductor dielectric capacitors have lower ESR for a given
size, at a somewhat higher price. Choosing sufficient capacitors
to meet the ESR requirement for COUT normally exceeds the
amount of capacitance needed to meet the ripple current
requirement.
In surface-mount applications, multiple capacitors may have to
be paralleled to meet the capacitance, ESR, or rms current
handling requirements. Aluminum electrolytic and dry
tantalum capacitors are available in surface-mount
configurations. In the case of tantalum, it is critical that
capacitors are surge tested for use in switching power supplies.
Recommendations for output capacitors are shown in Table 8.
Rev. 0 | Page 13 of 20
ADP3026
Table 8. Recommended Capacitor Manufacturers
Maximum Output Current
Input Capacitor
2A
TOKIN Multilayer
Ceramic Cap, 22 µF/25 V
P/N:C55Y5U1E226Z
TAIYO YUDEN INC.
Ceramic Caps, Y5V Series 10 µF/25 V
P/N: TMK432BJ106KM
SANYO POSCAP TPC
Series, 68 µF/10 V
SANYO POSCAP TPC
Series, 68 µF/10 V
Output Capacitor
3.3 V Output
Output Capacitor
5 V Output
Power MOSFET Selection
N-channel power MOSFETs are used for both the main and
synchronous switches. The important selection parameters for
the power MOSFETs are threshold voltage (VGS(TH)) and on
resistance (RDS(ON)). An internal LDO regulator generates a 5 V
supply that is boosted above the input voltage using a bootstrap
circuit. This floating 5 V supply is used for the upper (main)
MOSFET gate drive. Logic-level threshold MOSFETs must be
used for both the main and synchronous switches.
Maximum output current (IMAX) determines the RDS(ON)
requirement for the two power MOSFETs. When the ADP3026
is operating in continuous mode, the simplifying assumption
can be made that one of the two MOSFETs is always conducting
the load current. The duty cycles for the MOSFETs are given by
Upper MOSFET Duty Cycle =
V OUT
V IN
(10)
Lower MOSFET Duty Cycle =
V IN − V OUT
V IN
(11)
Maximum MOSFET power dissipation occurs at maximum
output current, and is calculated as follows:
Upper MOSFET:
P D (Upper ) =
(14)
Lower MOSFET:
P D (Lower ) =
V IN − V OUT
× I MAX 2 × R DS(ON ) × (1 + α∆T ) (15)
V IN
The Schottky diode, D1 in Figure 15, conducts only during the
dead time between conduction of the two power MOSFETs.
D1’s purpose is to prevent the body diode of the lower Nchannel MOSFET from turning on and storing charge during
the dead time, which could cost as much as 1% in efficiency. D1
should be selected for a forward voltage of less than 0.5 V when
conducting IMAX. Recommended transistors for upper and lower
MOSFETs are given in Table 9.
Maximum Output
Vishay/Siliconix
Upper MOSFET:
V IN × P D
V OUT × I MAX 2 × (1 × α∆T )
V OUT
× I MAX 2 × RDS(ON ) × (1 + α∆T )
V IN
Table 9. Recommended MOSFETs
From the duty cycle, the required minimum RDS(ON) for each
MOSFET can be derived by the following equations:
R DS (ON ) (Upper ) =
4A
TOKIN Multilayer
Ceramic Cap, 2 × 22 µF/25 V
P/N:C55Y5U1E226Z
TAIYO YUDEN INC.
Ceramic Caps, Y5V Series 10 µF/25 V
P/N: TMK432BJ106KM
SANYO POSCAP TPC
Series, 2 × 68 µF/10 V
SANYO POSCAP TPC
Series,2 × 68 µF/10 V
(12)
International
Rectifier
2A
Si4412DY,
28 mΩ
IRF7805,
11 mΩ
4A
Si4410DY,
13.5 mΩ
IRF7811,
8.9 mΩ
IRF7805,
11 mΩ
10 A
Si4874DY,
7.5 mΩ
IRFBA3803,
5.5 mΩ
IRF7809,
7.5 mΩ
Lower MOSFET:
V IN × P D
RDS (ON ) (Lower ) =
(V IN − V OUT ) × I MAX 2 × (1 + α∆T )
where PD is the allowable power dissipation and α is the
temperature dependency of RDS(ON). PD is determined by
efficiency and/or thermal requirements (see the Efficiency
Enhancement section). (1 + α∆T) is generally given for a
MOSFET in the form of a normalized RDS(ON) versus
temperature curve, but α = 0.007/°C can be used as an
approximation for low voltage MOSFETs.
Soft Start
(13)
The soft start time of each switching regulator is programmed
by connecting a soft start capacitor to the corresponding soft
start pin (SS3 or SS5). The time it takes each regulator to ramp
up to its full duty ratio depends proportionally on the values of
the soft start capacitors. The charging current is 2.5 µA ±20%.
The capacitor value to set a given soft start time, tSS, is given by
C SS = 2.5 µA
Rev. 0 | Page 14 of 20
(t SS(ms))
(pF)
1.8 V
(16)
ADP3026
Efficiency Enhancement
Feedback Loop Compensation
The efficiency of each switching regulator is inversely
proportional to the losses during the switching conversion. The
main factors to consider when attempting to maximize
efficiency are
The ADP3026 uses voltage mode control to stabilize the
switching controller outputs. Figure 16 shows the voltage mode
control loop for one of the buck switching regulators. The
internal reference voltage VREF is applied to the positive input of
the internal error amplifier. The other input of the error
amplifier is EAN, which is internally connected to the feedback
sensing pin FB via an internal resistor. The error amplifier
creates the closed-loop voltage level for the pulse-width
modulator that drives the external power MOSFETs. The output
LC filter smoothes the pulse-width modulated input voltage to a
dc output voltage.
1.
Resistive losses, which include the RDS(ON) of upper and
lower MOSFETs, trace resistances, and output equivalent
series resistance.
These losses contribute a major part of the overall power
loss in low voltage battery-powered applications. However,
trying to reduce these resistive losses by using multiple
MOSFETs and thick traces may lead to lower efficiency
and higher price. This is due to the trade-off between
reduced resistive loss and increased gate drive loss that
must be considered when optimizing efficiency.
VIN
ADP3026
PWM
COMPARATOR
DRVH
L1
VRAMP
2.
VOUT
Switching losses due to the limited time of switching
transitions.
COUT
DRVL
C2
This occurs due to the gate drive losses of both upper and
lower MOSFETs, and switching node capacitive losses, as
well as through hysteresis and eddy current losses in power
choke. Input and output capacitor ripple current losses
should also be considered as switching losses. These losses
are input voltage dependent and can be estimated as
follows:
P SWLOSS = 2.5 × V IN
1.85
× I MAX × C SN × f
R2 C1
C3
EAN
R1
FB
R3
02950-016
REF
Figure 16. Buck Regulator Voltage Control Loop
(17)
where CSN is the overall capacitance of the switching node
related to loss.
3.
PARASITIC
ESR
EAO
Supply current of the switching controller (independent of
the input current redirected to supply the MOSFET’s
gates).
This is a very small portion of the overall loss, but it does
increase with input voltage.
The pulse-width modulator transfer function is VOUT/VEAOUT,
where VEAOUT is the output voltage of the error amplifier. That
function is dominated by the impedance of the output filter
with its double-pole resonance frequency (fLC), a single zero at
the output capacitor (fESR), and the dc gain of the modulator, and
is equal to the input voltage divided by the peak ramp height
(VRAMP), which is equal to 1.2 V when VIN = 12 V.
Transient Response Considerations
Both stability and regulator loop response can be checked by
looking at the load transient response. Switching regulators take
several cycles to respond to a step in output load current. When
a load step occurs, output voltage shifts by an amount equal to
the current step multiplied by the total ESR of the summed
output capacitor array. Output overshoot or ringing during the
recovery time (in both directions of the current step change)
indicates poor regulation stability. The external feedback
compensation components shown in Figure 16 provide
adequate compensation for most applications.
f LC =
1
2 π × L F × C OUT
(18)
F ESR =
1
2π × ESR × COUT
(19)
The compensation network consists of the internal error
amplifier and two external impedance networks, ZIN and ZFB.
Once the application and the output filter capacitance and ESR
are chosen, the specific component values of the external
impedance networks, ZIN and ZFB, can be determined. There are
two design criteria for achieving stable switching regulator
behavior within the line and load range. One is the maximum
bandwidth of the loop, which affects fast transient response, if
needed; the other is the minimum accepted by the design phase
margin.
Rev. 0 | Page 15 of 20
ADP3026
The phase margin is the difference between the closed-loop
phase and 180°. Recommended phase margin is 45° to 60° for
most applications.
The equations for calculating the compensation poles and zeros
are
f P1
1
2π × R 2 ×
f P2 =
C1 × C2
C1 + C 2
1
2π × R 3 × C 3
1
f Z1 =
2 π × R 2 × C1
f Z2 =
1
2π × (R1 + R3) × C 3
2.
Whenever high currents must be routed between PCB
layers, use vias liberally to create several parallel current
paths so that the resistance and inductance introduced by
these current paths is minimized and the via current rating
is not exceeded.
3.
Minimize overlapping of the power and ground planes as
much as possible. It is generally easiest (although not
necessary) to have the power and signal ground planes on
the same PCB layer. Connect the planes together nearest to
the first input capacitor where the input ground current
flows from the converter back to the battery.
4.
If critical signal lines (including the voltage and current
sense lines of the ADP3026) must cross through power
circuitry, place a signal ground plane between those signal
lines and the traces of the power circuitry. This serves as a
shield to minimize noise injection into the signals at the
expense of making signal ground a bit noisier.
5.
Connect the PGND pin of the ADP3026 first to a ceramic
bypass capacitor on the VIN pin, and then into the power
ground plane using the shortest possible trace. However, do
not route the power ground plane under other signal
components, including the ADP3026 itself. If necessary,
follow the preceding guideline to use the signal plane as a
shield between the power ground plane and the signal
circuitry.
6.
Connect the AGND pin of the ADP3026 first to the REF
capacitor, and then into the signal ground plane. In cases
where no signal ground plane can be used, use short
interconnections to other signal ground circuitry in the
power converter.
7.
Connect the output capacitors of the power converter to
the signal ground plane even though power current flows
in the ground of these capacitors. It is advisable to avoid
critical ground connections (e.g., the signal circuitry of the
power converter) in the signal ground plane between the
input and output capacitors. It is also advisable to keep the
planar interconnection path short (i.e., have input and
output capacitors close together).
8.
Connect the output capacitors as close as possible to the
load (or connector) that receives the power. If the load is
distributed, also distribute the capacitors, and generally in
proportion to where the load tends to be more dynamic.
9.
Absolutely avoid crossing any signal lines over the
switching power path loop, as described in the Power
Circuitry section.
(20)
(21)
(22)
(23)
The value of the internal resistor R1 is 89 kΩ for the 3.3 V
switching regulator, and 150 kΩ for the 5 V switching regulator.
Compensation Loop Design and Test Method
1.
Choose the gain (R2/R1) for the desired bandwidth.
2.
Place fZ1 20% to 30% below fLC.
3.
Place fZ2 20% to 30% above fLC.
4.
Place fP1 at fESR, and check the output capacitor for worstcase ESR tolerances.
5.
Place fP2 at 40% to 60% of the oscillator frequency.
6.
Estimate phase margins in full frequency range (zero
frequency to zero gain crossing frequency).
7.
Apply the designed compensation and test the transient
response under a moderate step load change (30% to 60%)
and various input voltages. Monitor the output voltage via
the oscilloscope. The voltage overshoot or undershoot
should be within 1% to 3% of the nominal output, without
ringing and abnormal oscillation.
LAYOUT CONSIDERATIONS
The following guidelines are recommended for optimal
performance of a switching regulator in a portable PC system.
General Recommendations
1.
For best results, a 4-layer (minimum) PCB is
recommended. This allows the needed versatility for
control circuitry interconnections with optimal placement,
a signal ground plane, power planes for both power ground
and the input power, and wide interconnection traces in
the rest of the power delivery current paths. Each square
unit of 1 ounce copper trace has a resistance of ~0.53 mΩ
at room temperature.
Rev. 0 | Page 16 of 20
ADP3026
Power Circuitry
10. Route the switching power path on the PCB to encompass
the smallest possible area in order to minimize radiated
switching noise energy (i.e., EMI). Failure to take proper
precautions often results in EMI problems for the entire PC
system as well as noise related operational problems in the
power converter control circuitry. The switching power
path is the loop formed by the current path through the
input capacitors, the two FETs, and the power Schottky
diode, if used, including all interconnecting PCB traces and
planes. The use of short and wide interconnection traces is
especially critical in this path for two reasons: it minimizes
the inductance in the switching loop, which causes high
energy ringing, and it accommodates the high current
demand with minimal voltage loss.
11. A power Schottky diode (1 A ~ 2 A dc rating) placed from
the lower FET’s source (anode) to drain (cathode) helps to
minimize switching power dissipation in the upper FET. In
the absence of an effective Schottky diode, this dissipation
occurs through the following sequence of switching events.
The lower FET turns off in advance of the upper FET
turning on (necessary to prevent cross-conduction). The
circulating current in the power converter, no longer
finding a path for current through the channel of the lower
FET, draws current through the inherent body-drain diode
of the FET. The upper FET turns on, and the reverse
recovery characteristic of the lower FET’s body-drain
diode prevents the drain voltage from being pulled high
quickly.
The upper FET then conducts very large current while it
momentarily has a high voltage forced across it, which
translates into added power dissipation in the upper FET.
The Schottky diode minimizes this problem by carrying a
majority of the circulating current when the lower FET is
turned off, and by virtue of its essentially nonexistent
reverse recovery time.
12. Whenever a power-dissipating component (e.g., a power
MOSFET) is soldered to a PCB, liberally use vias, both
directly on the mounting pad and immediately
surrounding it. Two important reasons for this are
improved current rating through the vias (if it is a current
path) and improved thermal performance, especially if the
vias are extended to the opposite side of the PCB where a
plane can more readily transfer the heat to the air.
13. Route the output power path, though not as critical as the
switching power path, to encompass a small area. The
output power path is formed by the current path through
the inductor, the output capacitors, and back to the input
capacitors.
14. Extend the power ground plane fully under all the power
components except the output capacitors for best EMI
containment. These are the input capacitors, the power
MOSFETs and Schottky diode, the inductor, and any
snubbing elements that might be added to dampen ringing.
Avoid extending the power ground under any other
circuitry or signal lines, including the voltage and current
sense lines.
Signal Circuitry
15. Kelvin connect the CS and SW traces to the upper
MOSFET drain and source so that the additional voltage
drop due to current flow on the PCB at the current sense
comparator connections does not affect the sensed voltage.
It is desirable to have the ADP3026 close to the output
capacitor bank and not in the output power path, so that
any voltage drop between the output capacitors and the
AGND pin is minimized, and voltage regulation is not
compromised.
Rev. 0 | Page 17 of 20
ADP3026
OUTLINE DIMENSIONS
9.80
9.70
9.60
28
15
4.50
4.40
4.30
6.40 BSC
1
14
PIN 1
0.65
BSC
0.15
0.05
COPLANARITY
0.10
0.30
0.19
1.20 MAX
SEATING
PLANE
0.20
0.09
8°
0°
0.75
0.60
0.45
COMPLIANT TO JEDEC STANDARDS MO-153AE
Figure 17. 28-Lead Thin Shrink Small Outline Package [TSSOP]
(RU-28)
Dimensions shown in inches and (millimeters)
ORDERING GUIDE
Model
1
ADP3026JRUZ-REEL
1
Temperature Range
Package Description
Package Option
0°C to 70°C
Thin Shrink Small Outline (TSSOP)
RU-28
Z = Pb-free part.
Rev. 0 | Page 18 of 20
ADP3026
NOTES
Rev. 0 | Page 19 of 20
ADP3026
NOTES
© 2004 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D02950–0–10/04(0)
Rev. 0 | Page 20 of 20
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