FEATURES
TYPICAL APPLICATION CIRCUIT
Boost regulator with maximum power point tracking (MPPT)
with dynamic sensing or no sensing mode
Hysteresis mode for best ultralight load efficiency
Operating quiescent current of SYS pin (VIN > VCBP ≥ VMINOP): 510 nA
Sleeping quiescent current of SYS pin (VCBP < VMINOP): 390 nA
Input voltage operating range: 0.08 V to 3.3 V
Fast cold start from 380 mV (typical) with charge pump
Programmable shutdown point on MINOP pin based on the
input open circuit voltage (OCV)
150 mA regulated output from 1.5 V to 3.6 V
Battery terminal charging threshold (2.2 V to 5.2 V) to
support charging storage elements
Optional BACK_UP power path management
Radio frequency (RF) transmission conducive to shutting
down the switcher temporarily via microcontroller unit
(MCU) communication
APPLICATIONS
Photovoltaic (PV) cell energy harvesting
Thermoelectric generators (TEGs) energy harvesting
Industrial monitoring
Self powered wireless sensor devices
Portable and wearable devices with energy harvesting
ADP5091
REG_D0
FROM MCU
LLD
TO MCU
REG_OUT
REG_D1
VID
HYSTERESIS
REGULATOR
AND LDO
PIN
REG_FB
PGOOD
TO MCU
SW
COLD START
CHARGE PUMP
VIN
MPPT
CBP
SYS
BAT
MPPT
BOOST
CONTROL REGULATOR
SYSTEM
LOAD
+ RECHARGEABLE
BATTERY OR
–
SUPERCAP
REF
MINOP
FROM MCU
CHARGE CONTROL
AND
POWER PATH
MANAGEMENT
SETSD
SETPG
SETHYST
DIS_SW
SETBK
BACK_UP
OPTIONAL +
PRIMARY –
BATTERY
TERM
AGND PGND
14145-001
Data Sheet
Ultralow Power Energy Harvester PMUs
with MPPT and Charge Management
ADP5091/ADP5092
Figure 1.
GENERAL DESCRIPTION
The ADP5091/ADP5092 are intelligent, integrated energy
harvesting, ultralow power management unit (PMU) solutions
that convert dc power from PV cells or TEGs. These devices charge
storage elements such as rechargeable Li-Ion batteries, thin film
batteries, super capacitors, or conventional capacitors, and
power up small electronic devices and battery free systems.
The ADP5091/ADP5092 provide efficient conversion of the
harvested limited power from a 6 µW to 600 mW range with
submicrowatt operation losses. With the internal cold start circuit,
the regulator can start operating at an input voltage as low as
380 mV. After cold startup, the regulator is functional at an
input voltage range of 0.08 V to 3.3 V. An additional 150 mA
regulated output can be programmed by an external resistor
divider or the VID pin.
The MPPT control keeps the input voltage ripple in a fixed range to
maintain stable dc-to-dc boost conversion. The dynamic sensing
mode and no sensing mode, both programming regulation points
of the input voltage, allow extraction of the highest possible energy
from the harvester. A programmable minimum operation
threshold enables boost shutdown during a low input condition.
Rev. A
As a low light indicator for a microprocessor, the LLD pin of the
ADP5091 is the MINOP comparator output. However, the
REG_GOOD flag of the ADP5092 monitors the REG_OUT
voltage. In addition, the DIS_SW pin can temporarily shut down
the boost regulator and is RF transmission friendly.
The charging control function of the ADP5091/ADP5092 protects
the rechargeable energy storage, which is achieved by monitoring
the battery voltage with the programmable charging termination
voltage and the shutdown discharging voltage. In addition, a
programmable PGOOD flag monitors the SYS voltage.
An optional primary cell battery can be connected and managed
by an integrated power path management control block that is
programmable to switch the power source from the energy
harvester, rechargeable battery, and primary cell battery.
The ADP5091/ADP5092 are available in a 24-lead LFCSP and
are rated for a −40°C to +125°C temperature range.
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Technical Support
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ADP5091/ADP5092
Data Sheet
TABLE OF CONTENTS
Features .............................................................................................. 1
Regulated Output Configuration ............................................. 17
Applications ....................................................................................... 1
REG_GOOD (ADP5092 Only) ................................................ 18
Typical Application Circuit ............................................................. 1
Energy Storage Charge Management ...................................... 18
General Description ......................................................................... 1
Backup Storage Path................................................................... 18
Revision History ............................................................................... 2
Backup and BAT Selection Threshold ..................................... 19
Detailed Functional Block Diagram .............................................. 3
Battery Overcharging Protection ............................................. 19
Specifications..................................................................................... 4
Battery Discharging Protection ................................................ 19
Regulated Output Specifications ................................................ 6
Power Good (PGOOD) ............................................................. 20
Absolute Maximum Ratings ............................................................ 7
Power Path Working Flow......................................................... 20
Thermal Resistance ...................................................................... 7
Current-Limit and Short-Circuit Protection.............................. 20
ESD Caution .................................................................................. 7
Thermal Shutdown .................................................................... 21
Pin Configurations and Function Descriptions ........................... 8
Applications Information .............................................................. 23
Typical Performance Characteristics ........................................... 10
Energy Harvester Selection ....................................................... 23
Theory of Operation ...................................................................... 16
Energy Storage Element Selection ........................................... 23
Fast Cold Start-Up Circuit (VSYS < VSYS_TH, VIN > VIN_COLD) ... 16
Inductor Selection ...................................................................... 23
Main Boost Regulator (VBAT_TERM > VSYS > VSYS_TH) ..................... 16
Capacitor Selection .................................................................... 24
VIN Open Circuit and MPPT .................................................. 16
Layout and Assembly Considerations ..................................... 24
Minimum Operation Threshold Function ............................. 17
Typical Application Circuits ..................................................... 25
Disabling Boost ........................................................................... 17
Factory Programmable Options ................................................... 27
Regulated Output Working Mode ............................................ 17
Outline Dimensions ....................................................................... 28
REG_D0 and REG_D1 .............................................................. 17
Ordering Guide .......................................................................... 28
REVISION HISTORY
5/2017—Rev. 0 to Rev. A
Changes to Figure 2 .......................................................................... 3
Changes to Figure 7, Figure 10, Figure 7 Caption, and Figure 10
Caption ............................................................................................. 10
Changes to Figure 11 and Figure 11 Caption ............................. 11
Changed CP-24-10 to CP-24-14 .................................. Throughout
Updated Outline Dimensions ....................................................... 28
Changes to Ordering Guide .......................................................... 28
7/2016—Revision 0: Initial Version
Rev. A | Page 2 of 28
Data Sheet
ADP5091/ADP5092
DETAILED FUNCTIONAL BLOCK DIAGRAM
ADP5091/ADP5092
SYS
LDO
CSYS
REG_SWITCHES
RSYS
BACK_UP
+
REG_OUT
–
REG_FB
REG_D0
REG_D1
BACK_UP
SWITCHES
HYSTERESIS
REGULATOR
AND LDO
SYS SWITCH
VID
PHOTOVOLTAIC
CELL
L
BK
BAT SWITCHES
BAT
SW
+
SD
HS
+
–
CIN
BAT
VIN
COLD START
CHARGE PUMP
LS
BK
REF
SYS
ROC2
MPPT
MPPT
CONTROLLER
TERM_REF
ROC1
EN_BST
CBP
BOOST
CONTROLLER
SETSD
SD
CHARGE
CONTROL
AND
POWER PATH
MANAGEMENT
PGOOD
PG
MINOP
SETPG
PG
SETHYST
DIS_SW
PG
CLK
BK
VINT_REF SETBK
LLD (ADP5091)
TERM_REF
REG_GOOD (ADP5092)
BIAS REFERENCE
AND OSCILLATOR
VREF
TERM
CONTROL
TERM
2R
CLK
R
PGND
AGND
BAT
Figure 2. Detailed Functional Block Diagram
Rev. A | Page 3 of 28
14145-040
–
BACK_UP
CONTROL
ADP5091/ADP5092
Data Sheet
SPECIFICATIONS
Voltage input (VIN) = 1.2 V, VSYS = VBAT = 3 V, TJ = −40°C to +125°C for minimum/maximum specifications, and TA = 25°C for typical
specifications, unless otherwise noted. External components include the following: inductance (L) = 22 µH, input capacitance (CIN) = 4.7 µF,
and CSYS = 4.7 µF.
Table 1.
Parameter
Symbol
Test Conditions/Comments
QUIESCENT CURRENT
Operating Quiescent Current of SYS Pin
(VIN > VCBP ≥ VMINOP)
IQ_SYS
IIQ_SLEEP_SYS
Sleeping Quiescent Current of SYS Pin
(VCBP < VMINOP)
COLD START CIRCUIT
Minimum Input Voltage for Cold Start
Minimum Input Power for Cold Start
End of Cold Start Operation
Threshold
Hysteresis
BOOST REGULATOR
Input Voltage Operating Range
Input Power Operating Range
Start Charging BAT Threshold on SYS
Start Charging BAT Hysteresis on SYS
Input Peak Current
Low-Side Switch On Resistance
High-Side Switch On Resistance
SYS Switch On Resistance
DIS_SW Voltage
High
Low
DIS_SW Delay
VIN CONTROL AND MINOP
VIN Open Circuit Voltage
Default Sampling Cycle
Sampling Time
MINOP Bias Current
MINOP Operation Voltage Threshold
of Dynamic MPPT Sensing Mode
MPPT Bias Current of MPPT No
Sensing Mode
LLD (ADP5091 Only)
Pull-Up Resistor
Pull-Down Resistor
High Voltage
Leakage Current at CBP Pin
VIN_COLD
PIN_COLD
Typ
Max
Unit
REG_D0 = low, REG_D1 = low
510
1000
nA
REG_D0 = high, REG_D1 = low
REG_D0 = low, REG_D1 = high
REG_D0 = high, REG_D1 = high
REG_D0 = low, REG_D1 = low
650
750
760
390
1150
1290
1300
880
nA
nA
nA
nA
VSYS = 0 V, 0°C < TA < 85°C
380
6
500
mV
µW
1.87
95
2.00
V
mV
3.3
600
2.35
V
mW
V
mV
mA
mA
Ω
Ω
Ω
VSYS_TH
VSYS_HYS
VIN
PIN
VSYS_CHG
VSYS_CHG_HYS
IIN_PEAK
RLS_DS_ON
RHS_DS_ON
RSYS_DS_ON
1.73
Cold start completed
Cold start completed, VIN = 3 V
0.08
2.00
Factory trim, 1 bit, Option 0
Option 1
Pin to pin measurement
Pin to pin measurement
VDIS_SW_HIGH
VDIS_SW_LOW
tDIS_SW_DELAY
tOCV_CYCLE
Min
2.19
150
200
300
0.44
0.85
0.32
250
0.6
1.2
0.70
1
1
V
V
µs
16
sec
0.5
Factory trim, 2 bit (4 sec, 8 sec, 16 sec,
32 sec)
tOCV_SAMPL
IMINOP
VMINOP_DSM
1.58
256
2.00
IMPPT
1.7
VLLD_IH
ICBP_LEAK
Rev. A | Page 4 of 28
2.45
1.5
ms
µA
V
2.0
2.3
µA
12
12
VREG_OUT
10
17
17
kΩ
kΩ
V
pA
2000
Data Sheet
Parameter
ENERGY STORAGE MANAGEMENT
Internal Reference Voltage
Battery Stop Discharging
Threshold
Hysteresis Resistor
Battery Terminal Charging
Threshold
Hysteresis
PGOOD Rising Threshold at SYS Pin
PGOOD Pull-Up Resistor
PGOOD Pull-Down Resistor
PGOOD High Voltage
Battery Switches On Resistance
Battery Source Current
Leakage Current at BAT Pin
BACK_UP POWER PATH
Turning Off BACK_UP Switch
Threshold on BAT
Hysteresis Resistor
BACK_UP Switches On Resistance
BACK_UP and BAT Comparator
Offset
Hysteresis
BACK_UP Current Capability
Leakage Current at BACK_UP Pin
THERMAL SHUTDOWN
Threshold
Hysteresis
ADP5091/ADP5092
Symbol
Min
Typ
Max
Unit
VINT_REF
0.955
1.011
1.067
V
VSETSD
RSETSD_HYS
2.0
80
115
VBAT_TERM
160
V
kΩ
VBAT_TERM
VBAT_TERM_HYS
VSYS_PG
2.2
5.2
3.1
VBAT_TERM
17.0
17.0
V
%
V
kΩ
kΩ
V
Ω
A
nA
nA
VPGOOD_HIGH
RBAT_SW_ON
IBAT
IBAT_LEAK
Test Conditions/Comments
3
VSETSD
Pin to pin measurement
11.6
11.6
VSYS
0.59
VBAT = 2 V, VSETSD = 2.2 V, VSYS = 2 V
VBAT = 3.3 V, VSETSD = 2.2 V, VSYS = 0 V
22
3.5
0.85
1
50
35
115
0.85
VBAT_TERM
160
1.20
V
kΩ
Ω
271
108
mV
mV
µA
nA
VSETBK
RSETBK_HYS
2.0
80
VSYS ≥ VSYS_TH
VBKP_OFFSET
VBAT_HYS
IBKP
IBKP_LEAK
TSHDN
THYS
158
68
VSYS < VSYS_TH
VBACK_UP = VSYS = VBAT = 3 V
VSYS ≥ VSYS_TH
Rev. A | Page 5 of 28
190
75
250
16
142
15
40
°C
°C
ADP5091/ADP5092
Data Sheet
REGULATED OUTPUT SPECIFICATIONS
VIN = 1.2 V, VSYS = VBAT = 3 V, VREG_OUT = 2 V, L = 22 µH, CIN = 4.7 µF, CSYS = 4.7 µF, CREG_OUT = 4.7 µF, TJ = −40°C to +125°C for
minimum/maximum specifications, and TA = 25°C for typical specifications, unless otherwise noted.
Table 2.
Parameter
REGULATED OUTPUT
Output Options by VID Control
Rating Current
REG_OUT Pull-Down Resistance
REG_OUT IN BOOST MODE
REG_OUT Wake Threshold
Symbol
Test Conditions/Comments
VREG_OUT
IREG_OUT
RREG_OUT
VREG_OUT = 1.5 V to 3.6 V
REG_OUT Wake Threshold
Hysteresis
Adjustable REG_OUT Wake
Threshold
Adjustable REG_OUT Sleep
Threshold
High-Side Switches On Resistance
Current-Limit Threshold of Boost
Mode
REG_OUT IN LOW DROPOUT (LDO)
MODE
REG_OUT Accuracy
Adjustable REG_OUT Accuracy
VREG_WAKE_HYS
REG_OUT Dropout
Current-Limit Threshold of LDO
Mode
Output Noise
Power Supply Rejection Ratio
REG_D0 and REG_D1
Input Logic
High
Low
Input Leakage Current
REG_GOOD (ADP5092 ONLY)
Rising Threshold
Hysteresis
Pull-Up Resistor
Pull-Down Resistor
High Voltage
Min
Typ
Max
Unit
3.6
V
mA
Ω
1.027 ×
VREG_OUT
1
1.048 ×
VREG_OUT
V
1.5
VREG_WAKE
150
235
1.008 ×
VREG_OUT
%
VADJ_REG_WAKE
1.008
1.028
1.048
V
VADJ_REG_SLEEP
1.018
1.038
1.058
V
1.63
100
2.15
155
Ω
mA
+3.5
1.028
1.045
%
V
V
mV
mA
RBST_DS_ON
IREG_BST_LIM
VREG_LDO
VREG_LDO_ADJ
VREG_DROP
IREG_LIM
OUTNOISE
PSRR
0 µA < IOUT < 150 mA, VSYS = (VREG_OUT + 0.5 V)
IOUT = 1 mA
0 µA < IOUT < 150 mA, VSYS = (VREG_OUT + 0.5 V)
IOUT = 150 mA
VSYS ≥ VSYS_TH
−3.5
0.999
0.985
200
10 Hz to 100 kHz
100 Hz
1 kHz
1.015
1.015
200
260
700
60
40
VREG_DX_IH
VREG_DX_IL
IREG_DX_LEAK
1.2
VREG_GOOD
VREG_GOOD_HYS
89.5
µV rms
dB
dB
0.4
20
VREG_GOOD_IH
Rev. A | Page 6 of 28
92.5
2
11.6
11.6
VREG_OUT
95.7
17
17
V
V
nA
%
%
kΩ
kΩ
V
Data Sheet
ADP5091/ADP5092
ABSOLUTE MAXIMUM RATINGS
THERMAL RESISTANCE
Table 3.
Parameter
VIN, MPPT, CBP, MINOP
DIS_SW, TERM, SETPG, SETSD, SETBK,
PGOOD, SETHYST, REF, REG_D0, VID,
REG_D1, LLD, REG_GOOD to AGND
SW, SYS, BAT, BACK_UP, REG_OUT, REG_FB
to PGND
PGND to AGND
Rating
−0.3 V to +3.6 V
−0.3 V to +6.0 V
−0.3 V to +6.0 V
−0.3 V to +0.3 V
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
θJA is specified for the worst case conditions, that is, a device
soldered in a circuit board for surface-mount packages.
Table 4.
Package Type
24-Lead LFCSP
ESD CAUTION
Rev. A | Page 7 of 28
θJA
58.7
θJC
36
Unit
°C/W
ADP5091/ADP5092
Data Sheet
SETPG 5
20 VID
19 PGOOD
14 REG_OUT
13 SW
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO AGND.
14145-003
AGND 7
14145-002
LLD 11
NOTES
1. THE EXPOSED PAD MUST BE CONNECTED TO AGND.
16 SYS
15 REG_FB
SETHYST 6
PGND 12
VIN 10
MPPT 9
CBP 8
22 DIS_SW
TOP VIEW
(Not to Scale)
13 SW
AGND 7
21 MINOP
24 REG_D0
ADP5092
TERM 4
14 REG_OUT
SETHYST 6
23 REG_D1
SETBK 3
PGND 12
SETPG 5
16 SYS
15 REG_FB
17 BAT
REG_GOOD 11
TOP VIEW
(Not to Scale)
SETSD 2
VIN 10
ADP5091
TERM 4
17 BAT
MPPT 9
SETBK 3
18 BACK_UP
REF 1
18 BACK_UP
REF 1
SETSD 2
CBP 8
20 VID
19 PGOOD
22 DIS_SW
21 MINOP
24 REG_D0
23 REG_D1
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
Figure 4. ADP5092 Pin Configuration
Figure 3. ADP5091 Pin Configuration
Table 5. Pin Function Descriptions
Pin No. 1
ADP5091 ADP5092
1
1
2
2
Mnemonic
REF
SETSD
3
3
SETBK
4
4
TERM
5
6
5
6
SETPG
SETHYST
7
8
7
8
AGND
CBP
9
9
MPPT
10
10
VIN
11
N/A
LLD
N/A
12
13
11
12
13
REG_GOOD
PGND
SW
14
15
14
15
REG_OUT
REG_FB
16
16
SYS
17
17
BAT
18
18
BACK_UP
Description
Internal Voltage Reference Monitoring Node for the SETSD, SETPG, SETBK, and TERM Pins.
Shutdown Setting. The SETSD pin sets the shutdown discharging voltage based on the BAT pin
voltage level.
BACK_UP Disabled Threshold Monitoring BAT Voltage Setting. Connect the SETBK pin to the AGND
pin without the BACK_UP storage element.
Termination Charging Voltage. This pin sets the termination charging voltage based on the BAT pin
voltage level.
Power-Good Rising Threshold Monitoring SYS Node Voltage Level Setting.
PGOOD Falling Hysteresis Setting. Connect a resistor between SETPG and SETHYST to program the
PGOOD falling hysteresis.
Analog Ground.
Capacitor Bypass. This pin samples and holds the maximum power point level. Connect a 10 nF
capacitor from the CBP pin to the AGND pin. When the MPPT pin is disabled, tie the CBP pin to an
external reference that is lower than the VIN pin.
Maximum Power Point Tracking. This pin sets the maximum power point ratio for the different
energy harvesters with a resistor divider. In no sensing mode, place a resistor through AGND to set
the MPPT voltage. The typical current value is 2.0 µA.
Input Supply from Energy Harvester Source. Connect at least a 10 µF capacitor as close as possible
between VIN and PGND.
Low Light Density Indicator to Microcontroller for the ADP5091. LLD pulls high at the MINOP voltage
higher than the CBP voltage.
Regulated Output Power Good for the ADP5092.
Power Ground.
Switching Node for the Inductive Boost Regulator with a Connection to an External Inductor.
Connect a 22 µH inductor between SW and VIN.
Regulated Output. Connect at least a 4.7 µF capacitor as close as possible between REG_OUT and PGND.
Regulated Output Feedback Voltage Sense Input. The fixed output connects this pin to REG_OUT.
The adjustable output connects this pin to a resistor divider from REG_OUT.
Output Supply to System Load. Connect at least a 4.7 µF capacitor as close as possible between SYS
and PGND.
SYS Output Supply Storage. This pin places the rechargeable battery or super capacitor as a storage
for the SYS output supply.
Optional Input Supply from the Backup Primary Battery Cell.
Rev. A | Page 8 of 28
Data Sheet
ADP5091/ADP5092
Pin No. 1
ADP5091 ADP5092
19
19
Mnemonic
PGOOD
20
20
VID
21
21
MINOP
22
23
24
22
23
24
DIS_SW
REG_D1
REG_D0
EPAD
1
Description
Output Signal to Microcontroller. This pin maintains a pulled high level when SYS is higher than the
SETPG threshold.
Voltage Configuration Pin for REG_OUT. This pin sets up to eight different regulated outputs tied
low through a resistor to AGND. The output configuration details are in Table 7.
Minimum Operating Power. Place a resistor on MINOP to set the minimum operating input voltage
level. The boost regulator starts switching when the CBP voltage exceeds the MINOP voltage. When
the MINOP pin is floating, the IC operates in no sensing mode with a fixed MPPT level. Connect this
pin through AGND to disable the MINOP function.
Control Signal from Microcontroller or RF Transceiver to Stop Switching Boost Charger.
Regulated Output Working Mode Set D1. Enable LDO mode by pulling this pin high.
Regulated Output Working Mode Set D0. Enable boost mode by pulling this pin high.
Exposed Pad. The exposed pad must be connected to AGND.
N/A means not applicable.
Rev. A | Page 9 of 28
ADP5091/ADP5092
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
VBAT_TERM = 3.5 V, VSYS_PG = 2.8 V, VSETSD = 2.4 V, MPPT (OCV) = 80%, L = 22 μH, CIN = 10 μF, CSYS = 4.7 μF, CREG_OUT = 10 μF, CCBP = 10 nF.
90
100
80
90
80
50
40
30
20
0
0.5
1.0
1.5
2.0
50
2.5
SYS = 2V
SYS = 3V
SYS = 5V
30
20
3.0
0
0.5
1.0
100
90
90
80
3.0
70
60
50
40
0
0.5
1.0
1.5
2.0
50
40
30
20
2.5
SYS = 2V
SYS = 3V
SYS = 5V
10
14145-005
SYS = 2V
SYS = 3V
SYS = 5V
30
60
0
0.01
3.0
0.10
Figure 9. Efficiency vs. Input Current, VIN = 0.2 V
Figure 6. Efficiency vs. Input Voltage, IIN = 10 mA
90
80
80
70
70
EFFICIENCY (%)
90
60
SYS = 2V
SYS = 3V
SYS = 5V
60
30
30
1
10
INPUT VOLTAGE (V)
100
14145-100
40
0.1
Figure 7. Efficiency vs. Input Voltage, VIN = 0.5 V
SYS = 2V
SYS = 3V
SYS = 5V
50
40
20
0.01
10
INPUT CURRENT (mA)
INPUT VOLTAGE (V)
50
1
14145-008
EFFICIENCY (%)
EFFICIENCY (%)
2.5
70
80
EFFICIENCY (%)
2.0
Figure 8. Efficiency vs. Input Voltage, IIN = 100 μA
Figure 5. Efficiency vs. Input Voltage, IIN = 10 μA
20
1.5
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
20
0.01
0.1
1
10
INPUT VOLTAGE (V)
Figure 10. Efficiency vs. Input Voltage, VIN = 1 V
Rev. A | Page 10 of 28
100
14145-101
0
60
40
SYS = 2V
SYS = 3V
SYS = 5V
10
70
14145-007
EFFICIENCY (%)
60
14145-004
EFFICIENCY (%)
70
Data Sheet
ADP5091/ADP5092
100
100
90
95
80
90
EFFICIENCY (%)
EFFICIENCY (%)
70
85
80
75
60
50
40
30
SYS = 3V
SYS = 5V
20
65
0.1
1
10
0
.05
14145-102
60
0.01
100
INPUT VOLTAGE (V)
0.5
5
50
INPUT CURRENT (mA)
Figure 14. Efficiency vs. Input Current, VIN = 0.5 V, VREG_OUT = 2 V,
IREG_OUT = 10 µA
Figure 11. Efficiency vs. Input Voltage, VIN = 2 V
1400
100
90
1200
70
60
50
40
30
1000
800
600
400
TA = –40°C
TA = +25°C
TA = +85°C
TA = +125°C
20
200
0
.02
0.2
2
14145-011
SYS = 3V
SYS = 5V
10
0
2.0
20
2.5
3.0
3.5
4.0
4.5
14145-014
QUIESCENT CURRENT (nA)
80
EFFICIENCY (%)
SYS = 3V
SYS = 5V
10
14145-013
70
5.0
SYS VOLTAGE (V)
INPUT CURRENT (mA)
Figure 12. Efficiency vs. Input Current, VIN = 1 V, VREG_OUT = 2 V, IREG_OUT = 10 µA
Figure 15. Quiescent Current vs. SYS Voltage, VMINOP ≤ VCBP
1600
1200
1400
QUIESCENT CURRENT (nA)
1000
800
600
TA = –40°C
TA = +25°C
TA = +85°C
TA = +125°C
200
0
2.0
2.5
3.0
3.5
4.0
4.5
TA = –40°C
TA = +25°C
TA = +85°C
TA = +125°C
800
600
400
200
5.0
SYS VOLTAGE (V)
0
2.0
14145-015
400
14145-012
QUIESCENT CURRENT (nA)
1000
1200
2.5
3.0
3.5
4.0
4.5
SYS VOLTAGE (V)
Figure 13. Quiescent Current vs. SYS Voltage, VREG_D0 = VREG_D1 = VSYS, VMINOP ≤ VCBP
Rev. A | Page 11 of 28
Figure 16. Quiescent Current vs. SYS Voltage, VMINOP > VCBP
5.0
ADP5091/ADP5092
Data Sheet
60
TA = –40°C
TA = +25°C
TA = +85°C
TA = +125°C
TA = –40°C
TA = +25°C
TA = +85°C
TA = +125°C
50
BAT LEAKAGE CURRENT (nA)
100
80
60
40
40
30
20
10
0
2.0
2.4
2.8
3.2
3.6
4.0
4.4
4.8
5.2
0
2.0
14145-019
20
14145-016
BACK_UP LEAKAGE CURRENT (nA)
120
2.4
2.8
Figure 17. BACK_UP Leakage Current vs. BACK_UP Voltage
1
3.2
3.6
4.0
4.4
4.8
5.2
BAT VOLTAGE (V)
BACK_UP VOLTAGE (V)
Figure 20. BAT Leakage Current vs. BAT Voltage
VIN
VIN
1
BAT
SYS
BAT
SYS
2
SW
4
14145-017
4
CH1 1.00V BW CH2 1.00V BW
CH3 1.00V BW CH4 2.00V BW
M40.0ms
A CH2
SW
14145-020
2
CH1 1.00V BW CH2 1.00V BW
CH3 1.00V BW CH4 2.00V BW
1.00V
Figure 18. Startup with 100 µF Battery, VBAT > VSETSD
M100ms
A CH2
1.00V
Figure 21. Startup with Empty 100 µF Capacitor
VIN
VIN
1
CH3: BAT (AC)
3
1
SYS
CH2: SYS (AC)
BAT
3
SW
PGOOD
CH1 1.00V BW CH2 50.0mV BW M20.0ms A CH3
CH3 50.0mV BW CH4 2.00V BW
T 80.0000µs
14145-021
4
14145-018
4
CH1 500mV BW CH2 1.00V BW
CH3 1.00V BW CH4 2.00V BW
5.00mV
Figure 19. Output Ripple of TERM Function with 100 µA Load
M40.0ms
A CH4
Figure 22. PGOOD Function Waveform
Rev. A | Page 12 of 28
1.00V
Data Sheet
ADP5091/ADP5092
VIN
1
BAT
VIN
1
BACK_UP
BAT
SYS
3
SW
SYS
CH1 500mV BW CH2 1.00V BW
CH3 1.00V BW CH4 2.00V BW
M10.0ms
A CH2
T –80.0000µs
14145-025
3
14145-022
4
CH1 500mV BW CH2 1.00V BW
CH3 1.00V BW CH4 1.00V BW
2.00V
Figure 23. Battery Protection Function Waveform
M2.00s
A CH2
2.12V
Figure 26. BACK_UP Function, VBAT < VSETBK, VBACK_UP < VBAT
VIN
VIN
1
1
BAT
BACK_UP
BAT
BACK_UP
CH2: SYS
SYS
CH1 500mV BW CH2 1.00V BW
CH3 1.00V BW CH4 2.00V BW
M2.00s
A CH2
14145-026
3
14145-023
3
4
CH1 500mV BW CH2 1.00V BW
CH3 1.00V BW CH4 1.00V BW
2.12V
Figure 24. Backup Function, VBAT < VSETBK, VBACK_UP > VBAT
M2.00s
A CH2
2.12V
Figure 27. BACK_UP Function, VBAT > VSETBK, VBACK_UP > VBAT
VIN
VIN
SYS
SYS
1
1
BAT
DIS_SW
3
3
SW
2
CH1 500mV BW CH2 2.00V BW
CH3 2.00V BW CH4 2.00V BW
M40.0µs
A CH4
T 996.400µs
2.00V
14145-027
4
14145-024
4
SW
CH1 500mV
CH3 2.00V
Figure 25. Main Boost Pulse Frequency Modulation (PFM) Waveform with
200 µA Load
Rev. A | Page 13 of 28
CH2 1.00V
CH4 1.00V
M100ms
A CH1
Figure 28. DIS_SW Function Waveform
880mV
ADP5091/ADP5092
Data Sheet
VIN
VIN
SYS
1
1
SYS
BAT
2
3
3
4
14145-028
2
CH1 500mV BW CH2 1.00V BW
CH3 1.00V BW CH4 2.00V BW
M4.00s
A CH2
BAT
SW
14145-031
SW
CH1 500mV BW CH2 2.00V B
W
CH3 2.00V BW CH4 5.00V BW
2.12V
Figure 29. MPPT No Sensing Mode, RMPPT = 400 kΩ
M4.00s
A CH2
2.04V
Figure 32. MPPT Dynamic Sensing Mode
VIN
SYS
VIN
LLD
1
1
MINOP
MINOP
2
3
2
SW
SW
CH1 500mV BW CH2 1.00V B
W
CH3 500mV BW CH4 2.00V BW
M100ms
A CH1
14145-032
4
14145-029
4
CH1 500mV BW CH2 1.00V B
W
CH3 500mV BW CH4 2.00V BW
780mV
Figure 30. MINOP Function
M400ms
A CH1
780mV
Figure 33. LLD Function
VIN
SYS
VIN
1
1
REG_OUT (AC)
3
SYS
REG_OUT
BAT
4
4
CH1 500mV BW CH2 1.00V B
W
CH3 1.00V BW CH4 2.00V BW
M400ms
A CH4
SW
14145-033
2
14145-030
3
CH1 500mV BW
CH2 1.00V BW
CH3 20.0mV BW CH4 2.00V BW
220mV
Figure 31. REG_OUT Start (Hybrid Mode)
M400µs
A CH3
T 0.0000s
Figure 34. REG_OUT Ripple (Boost Mode)
Rev. A | Page 14 of 28
2.00V
Data Sheet
ADP5091/ADP5092
SYS
REG_OUT (AC)
1
VIN
3
1
REG_OUT
4
2
REG_GOOD
14145-033
14145-037
LOAD CURRENT
2
CH1 500mV
CH3 1.00V
CH2 2.00V
CH4 2.00V
M200ms
A CH2
CH1 50.0mV
1.68V
Figure 35. REG_GOOD Function
B
W
A CH2
CH2 10.0mAΩ BW
T 0.0000s
M1.00ms
–129mA
Figure 38. REG_OUT Load Transient (Hybrid), IREG_OUT from 10 µA to 10 mA
1200
REG_OUT RMS NOISE (µV)
1000
REG_OUT (AC)
1
2
800
600
ILOAD
ILOAD
ILOAD
ILOAD
400
= 0mA
= 1mA
= 10mA
= 150mA
LOAD CURRENT
CH1 50.0mV
B
W
CH2 50.0mAΩ BW
A CH1
T 0.0000s
M1.00µs
0
10
–36.0mV
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 36. REG_OUT Load Transient (LDO), IREG_OUT from 10 µA to 50 mA
Figure 39. REG_OUT RMS Noise vs. Frequency
1
0
ILOAD
ILOAD
ILOAD
ILOAD
100m
10m
= 0mA
= 1mA
= 10mA
= 150mA
–10
ILOAD
ILOAD
ILOAD
ILOAD
–20
1m
PSRR (dB)
100µ
10µ
1µ
=
=
=
=
0mA
1mA
10mA
150mA
–30
–40
–50
100n
–60
10n
1n
100p
10
100
1k
10k
100k
FREQUENCY (Hz)
1M
10M
–70
–80
10
14145-039
14145-036
REG_OUT NOISE DENSITY (µV/Hz)
14145-038
14145-035
200
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
Figure 37. REG_OUT Noise Density vs. Frequency at Various Current Loads (ILOAD)
Rev. A | Page 15 of 28
Figure 40. Power Supply Rejection Ratio (PSRR) vs. Frequency
ADP5091/ADP5092
Data Sheet
THEORY OF OPERATION
The ADP5091/ADP5092 are intelligent, integrated energy
harvesting, ultralow power management solutions that include
a cold start-up circuit, one synchronous main boost controller,
and one regulated output hybrid controller with integrated
switches, a charging controller with integrated switches, and
backup power path switches. The main boost controller converts
maximum power from low voltage, high impedance dc sources,
such as PV cells, TEGs, and piezoelectric modules, to store energy
in a rechargeable battery or capacitor with storage protection
and provides power to the load. Another regulated output with
automatic hysteresis boost/LDO mode, or pure LDO mode, is
optimized to provide high efficiency across low output currents
(10 μA), see Figure 14) to high currents of 200 mA. The ADP5091/
ADP5092 can also control an additional power path from a
primary battery cell to the system. An external signal can
temporarily stop the two boost circuits to prevent interference
with RF transmission.
FAST COLD START-UP CIRCUIT (VSYS < VSYS_TH,
VIN > VIN_COLD)
The fast cold start-up circuit extracts energy available at the
VIN pin and charges only the capacitors at the SYS pin up to
VSYS_TH above which the main boost regulator and charge controller
start working. The efficient boost regulator charges storage
elements on the BAT pin when the SYS voltage is more than
the internal BAT charging threshold (VSYS_CHG). When the SYS
voltage is less than the internal BAT charging threshold with a
hysteresis, it stops charging the BAT pin and restarts charging
the SYS pin to ensure that it does not enter cold startup. Figure 41
shows the fast cold start-up sequence.
The cold start-up circuit is required when the VIN pin is more
than the minimum input voltage for the cold start (VIN_COLD),
and the energy storage voltage at the SYS pin is less than the end
of the cold start operation threshold (VSYS_TH). To complete the
cold startup, the energy harvester must supply sufficient power
(see the Energy Harvester Selection section). The cold startup,
with much lower efficiency compared to the main boost regulator,
achieves a short start-up time, creating a low shutdown current
from the system load enabled by the PGOOD signal. To bypass
the cold startup, place a primary battery at the BACK_UP pin
(see the Backup Storage Path section).
MAIN BOOST REGULATOR (VBAT_TERM > VSYS > VSYS_TH)
The switching mode synchronous boost regulator, with an external
inductor connected between the VIN and the SW pins, operates
in pulse frequency modulation (PFM) mode, transferring energy
stored in the input capacitor to the energy storage connected to
the BAT pin. The MPPT control loop regulates the VIN voltage
at the level sampled at the MPPT pin and stored at the capacitor
through the CBP and the AGND pins. To maintain the high
efficiency of the regulator across a wide input power range, the
current sense circuitry employs an internal dither peak current
limit to control the inductor current.
The main boost regulator operation reaches an asynchronous
mode via the energy storage controller if the BAT pin voltage is
less than the battery terminal charging threshold programmed at
the SETSD pin, or stops switching if the BAT pin voltage is
more than the battery overcharging threshold programmed at
the TERM pin. The boost regulator disables when the voltage
on the CBP pin decreases to the threshold set by the resistor at
the MINOP pin. In addition, the boost is periodically stopped
by an open voltage sampling circuit and can also be temporary
disabled by driving the DIS_SW pin high.
VIN OPEN CIRCUIT AND MPPT
By floating the MINOP pin, the MPPT no sensing mode can
operate on a fixed MPPT voltage. The MPPT pin, with a 2.0 μA
(typical) bias current through a resistor, sets the MPPT voltage,
which is the boost input regulation reference.
When the MINOP pin voltage is set lower than VMINOP_DSM
through a resistor to AGND, the ADP5091/ADP5092 operate in
MPPT dynamic sensing mode. The boost input regulation
reference is the open circuit voltage at the VIN pin scaled to a ratio
programmed by the resistor divider at the MPPT pin. To keep
the VIN voltage operating at the maximum power points available
from the energy harvester at the input of the ADP5091/ADP5092,
periodically sample the MPPT voltage and store it in the capacitor
connected to the CBP pin. The reference voltage refreshes every
16 sec (default value) by periodically disabling the boost regulator
for 256 ms (default value) and by sampling the ratio of the open
circuit voltage when the BAT voltage level exceeds the SETSD
rising threshold. The factory bit can program the sampling
cycle. Set the reference voltage by
ROC1
VMPPT VIN Open Circuit
R R
OC1 OC2
VSETSD
VSYS_CHG
VSYS_CHG_HYS
0V
where:
VIN (Open Circuit) is the input open circuit voltage (VIN_OCV) of
the input voltage.
See Figure 2 for ROC1 and ROC2.
FAST
COLD
START
SYS
LOW
EFFICIENCY
BAT
HIGH EFFICIENCY
14145-041
VSYS_TH
(1)
Figure 41. Fast Cold Start-Up Sequence
Rev. A | Page 16 of 28
Data Sheet
ADP5091/ADP5092
The typical MPPT ratio depends on the type of harvester. For
example, it is 0.7 to 0.85 for PV cells, and 0.5 for TEGs. The
sampling OCV rate is adjustable depending on the previously
sampled OCV level. To disable the MPPT function, leave the
MPPT pin floating and set the CBP pin to an external voltage
reference lower than the VIN voltage.
MINIMUM OPERATION THRESHOLD FUNCTION
By setting the MINOP pin voltage lower than the MINOP
operation voltage range of the dynamic MPPT sensing mode
(VMINOP_DSM) through a resistor to AGND, the minimum operation
threshold function can disable the main boost regulator to prevent
discharging the storage element when the energy generated by the
harvester is less than the system consumption. When the voltage
of the CBP pin decreases to the threshold set by the resistor at
the MINOP pin, the boost regulator stops switching. The
typical MINOP bias current is 2.00 µA. The minimum operation
threshold function disables the MPPT function to achieve the
sleeping quiescent current of 390 nA (typical). Disable this
function by connecting the MINOP pin to the AGND pin.
The low light density (LLD) indicator (ADP5091 only) is the
MINOP comparator output that signals the microprocessor to
calculate the cycle with insufficient input energy in a certain
period.
DISABLING BOOST
For noise or electromagnetic interference (EMI) sensitive
applications, pull the DIS_SW pin high to stop the boost
switcher temporarily to prevent interference with RF circuits.
Pull the DIS_SW pin low to resume the boost switching. The
transition delay is 1 µs (typical).
In LDO mode, the output generates power from the SYS pin
with at least a small 4.7 µF ceramic output capacitor. Using new
innovative design techniques, the LDO provides ultralow quiescent
current and superior transient performance for digital and RF
applications, and supports noise sensitive applications.
In hybrid mode, the VIN and SYS pins both extract energy to
the REG_OUT pin. When the load power is lower than the input
power, the regulator exits LDO mode and obtains the energy
only from the input side.
REG_D0 AND REG_D1
The REG_D0 and REG_D1 pins allow flexible configuration of
the working mode of the regulated output. Table 6 details the
working mode configuration set by these two pins.
Table 6. Regulated Output Working Mode Configuration
Working Mode
Boost Disable
Boost Enable
LDO Disable
LDO Enable
REG_D0
Low
High
Not applicable
Not applicable
REG_D1
Not applicable
Not applicable
Low
High
REGULATED OUTPUT CONFIGURATION
The 150 mA regulated output of the ADP5091/ADP5092 is
available in eight fixed output voltage options ranging from
1.5 V to 3.6 V by connecting one resistor through the VID pin
to the AGND pin. Table 7 shows the output voltage options set by
the VID pin.
Table 7. Output Voltage Options Set by the VID Pin
The 150 mA regulated output of the ADP5091/ADP5092 not
only operates in the hysteresis boost mode or the LDO mode
but also operates in the hybrid mode in which the regulator can
smoothly transition between these two modes automatically.
After the BAT voltage exceeds the SETSD threshold or the SYS
voltage is greater than SETPG threshold, the regulator can be
enabled.
VID Configuration
Short to Ground
Floating
RVID = 7 kΩ
RVID = 14 kΩ
RVID = 27.7 kΩ
RVID = 55.6 kΩ
RVID = 111 kΩ
RVID = 221 kΩ
RVID = 442 kΩ
In hysteresis boost mode, the boost regulator in the ADP5091/
ADP5092 charges the output voltage slightly higher than its
preset output voltage. When the output voltage increases until
the output sense signal exceeds the hysteresis comparator upper
threshold (the sleep threshold), the regulator enters sleep mode. In
sleep mode, to allow a low quiescent current as well as high
efficiency performance, the low-side and high-side switches
and a majority of the circuitry are disabled.
The external resistor divider or the VID pin can program the
regulated output. The ratio of the two external resistors sets the
adjustable output voltage range of 1.5 V to 3.6 V, as shown in
Figure 47. The device acts as a servo to the output to maintain
the voltage at the REG_FB pin at 1.0 V referenced to ground.
The current in R1 is then equal to 1.0 V/R2, and the current in
R1 is the current in R2 plus the REG_FB pin bias current.
Calculate the output voltage by
REGULATED OUTPUT WORKING MODE
During sleep mode, the output capacitor supplies the energy into
the load, the output voltage decreases until it falls below the
hysteresis comparator lower threshold (the wake threshold),
and the boost regulator wakes up and generates the pulse-width
modulation (PWM) pulses to charge the output again. The
hysteresis mode allows the regulator to act as the keep alive
power supply.
Output Voltage Set by the VID Pin
Programmed with external resistors
VOUT = 2.5 V
VOUT = 1.5 V
VOUT = 1.8 V
VOUT = 3.6 V
VOUT = 3.3 V
VOUT = 2.0 V
VOUT = 3.0 V
VOUT = 2.8 V
VOUT = 1.02 V × (1 + R1/R2)
(2)
where:
VOUT = VREG_OUT.
See Figure 47 for R1 and R2.
To minimize quiescent current, it is recommended to use large
resistance values for R1 and R2.
Rev. A | Page 17 of 28
ADP5091/ADP5092
Data Sheet
REG_GOOD (ADP5092 ONLY)
BACKUP STORAGE PATH
A logic high on the REG_GOOD pin indicates that the REG_OUT
voltage is above 92.5% (typical) of its nominal output for a delay
time greater than approximately 2 ms. The logic high level on
REG_GOOD is equal to the REG_OUT voltage, and the logic low
level is ground. When the REG_OUT voltage falls below a 2%
hysteresis (typical) of the rising threshold, the REG_GOOD pin
goes low. The logic high level has about 11.6 kΩ internally in
series to limit the available current.
The ADP5091/ADP5092 provide an optional backup storage
energy path, an integrated backup controller, and two back to
back power switches between the BACK_UP pin and the SYS
pin. When the system operates at a condition where the harvested
and stored energy is periodically insufficient, attach a backup
energy storage element to the BACK_UP pin.
ENERGY STORAGE CHARGE MANAGEMENT
Energy storage is connected to the BAT pin. The storage can be
a rechargeable battery, super capacitor, or 100 µF or larger
capacitor. The energy storage controller manages the charging
and discharging operations, monitors the SYS pin voltage, and
asserts the PGOOD signal high when it is above the threshold
programmed at the SETPG pin.
When the BAT pin voltage exceeds the battery terminal charging
threshold programmed at the TERM pin, the boost operation
terminates to prevent battery overcharging. The battery terminal
charging threshold is programmable from 2.2 V to 5.2 V. When
the BAT voltage drops below the battery stop charging threshold
level programmed at the SETSD pin, the switches between the
BAT pin and the SYS pin are turned off to prevent a deep, destructive battery discharge, and the boost operates in asynchronous
mode. Although there is no current limit at the SYS and the
BAT pins, it is recommended to limit the system load current
to lower than 1000 mA. The large system load current generates a
droop between the SYS pin and the rechargeable battery at the
BAT pin, with consideration given to the resistance of the SYS
switch, the BAT switch, and the rechargeable battery internal
resistance.
The backup controller enables when the SYS voltage exceeds the
end of the cold start operation threshold (VSYS_TH). Before the BAT
voltage lowers the SETBK threshold, the backup switches turn
off. While the BAT voltage is less than the SETBK threshold, the
switches status depends on the voltage level of the BACK_UP pin
and the BAT pin. The internal BACK_UP_Mx and BACK_UP
control circuit automatically determine the BACK_UP switches
(BACK_UP_M1 and BACK_UP_M2) on/off status and selects
the high voltage terminal as the power source of SYS. The 190 mV
(typical) comparator input offset of the BAT pin prevents the
input source and the BAT pin from charging the BACK_UP pin
(see Figure 44).
In addition, the backup storage element can bypass the cold
startup with inrush current protection circuitry. Nevertheless,
the current capability is only 250 µA (typical) when plugging in
the backup battery before completing the cold start. It is recommended to restrict the system load current from the SYS pin to
ensure that the power path can enter normal operation status.
Table 9 explains the power path working state. For long-term
store mode, disconnect the backup storage element and then
discharge SYS to ground.
When no input source is attached, discharge the SYS pin to
ground before attaching a storage element to the BAT pin.
After hot plugging a charged storage element, release the SYS pin
because a SYS voltage that is less than the end of the cold start
operation threshold (VSYS_TH) results in the BAT switch remaining
off to protect the storage element until the SYS voltage reaches
VSYS_TH. The BAT switches remaining off can also be described
as store mode, a state with the lowest leakage (3.5 nA typical)
that allows a long store period without discharging the storage
element on BAT.
Rev. A | Page 18 of 28
Data Sheet
ADP5091/ADP5092
BACKUP AND BAT SELECTION THRESHOLD
BATTERY OVERCHARGING PROTECTION
To determine when to enable the BACK_UP function, the switch
threshold on the BAT pin must be set by using external resistors at
SETBK pin. When the BAT voltage is lower than the SETBK
threshold, the internal BACK_UP_Mx control circuit automatically
selects the high voltage terminal as the SYS power source. Figure 42
shows the VSETBK falling threshold voltage given by Equation 3.
To prevent rechargeable batteries from being overcharged and
damaged, the battery terminal charging threshold (VBAT_TERM) must
be set by using external resistors. Figure 42 shows the VBAT_TERM
rising threshold voltage given by Equation 6.
VSETBK
R
VINT _ REF 1 BK1
RBK2
(3)
RSETBK_HYS
RTERM1 + RTERM2 ≥ 6 MΩ
(4)
RE
where RE is the equivalent resistor of the four external
configuration resistor dividers.
Considering the quiescent current consumption, the sum of the
resistors that comprise the resistor divider (RSETBK_HYS, RBK1, and
RBK2) must be greater than 6 MΩ, that is,
RSETBK_HYS + RBK1 + RBK2 > 6 MΩ
The battery terminal charging threshold is given by VBAT_TERM_HYS,
which is internally set to the battery terminal charging threshold
minus an internal hysteresis voltage denoted by VBAT_TERM_HYS.
When the voltage at the battery exceeds the VBAT_TERM threshold,
the main boost regulator disables. The main boost starts again
when the battery voltage falls below the VBAT_TERM_HYS level. When
input energy is excessive, the VBAT pin voltage ripples between
the VBAT_TERM and the VBAT_TERM_HYS levels.
(5)
To prevent rechargeable batteries from being deeply discharged
and damaged, the battery stop discharging threshold (VSETSD)
must be set by using external resistors. Figure 42 shows the
VSETSD falling threshold voltage given by Equation 8.
R
VSETSD V INT _ REF 1 SD1
R
SD2
TERM_REF
BK
RSETBK_HYS
REF
SD
VSETSD_HYS VSETSD
BAT
RSD1
RSETSD_HYS
RPG1
RBK1
RTERM1
SD
PG
PGOOD
PG
PG
SETBK
TERM
RSD2
RPG2
RBK2
RTERM2
R
BAT
14145-042
2R
TERM
CONTROL
(10)
The equivalent resistor of the three external configuration
resistor dividers (RE) is equivalent to the paralleling value of the
three resistor dividers.
RPG_HYST
SETHYST
(9)
RE
RSETSD_HYS + RSD1 + RSD2 ≥ 6 MΩ
SETPG
PG
VINT_REF
RSETSD_HYS
Considering the quiescent current consumption, the sum of the
resistors that comprise the resistor divider (RSETSD_HYS, RSD1, and
RSD2) must be more than 6 MΩ, that is,
SETSD
TERM_REF
(8)
The ADP5091/ADP5092 have an internal resistor, RSETSD_HYS =
115 kΩ (typical), to program the hysteresis, given by Equation 9.
BAT
TRM
(7)
BATTERY DISCHARGING PROTECTION
The equivalent resistor of the four external configuration resistor
dividers (RE) is equivalent to the paralleling value of the three
resistor dividers.
BK
(6)
Considering the quiescent current consumption, the sum of the
resistors must be more than 6 MΩ, that is,
The ADP5091/ADP5092 have an internal resistor, RSETBK_HYS =
115 kΩ (typical), to program the hysteresis, given by
Equation 4.
VSETBK_HYS VSETBK
R
3
VBAT_TERM VINT _ REF 1 TERM1
2
RTERM2
Figure 42. ADP5091/ADP5092 Program Paramater Setting
Rev. A | Page 19 of 28
ADP5091/ADP5092
Data Sheet
POWER GOOD (PGOOD)
POWER PATH WORKING FLOW
The ADP5091/ADP5092 allow users to set a programmable
PGOOD voltage threshold, which indicates that the SYS voltage
is at an acceptable level. It must be set by using external resistors.
Figure 42 shows the VSETPG falling threshold voltage given by
Equation 11.
Figure 44 shows the power switches structure when the backup
primary battery is used. During the cold start, when a primary
battery connects to the BACK_UP pin, the S1 switch turns on.
The primary battery with the Diode D1 forward voltage drop
can be the SYS power source.
RPG1
VSETPG _ FALLING = VINT _ REF 1 +
R +R
PG2
PG _ HYST
(11)
The SETHYST pin can program the hysteresis with an external
resistor (RPG_HYST) given by Equation 12.
R + RPG _ HYST
VSETPG _ RISING = VINT _ REF 1 + PG1
RPG2
(12)
Considering the quiescent current consumption, the sum of the
resistors that comprise the power-good resistor divider
(RPG_HYST, RPG1, and RPG2) must be more than 6 MΩ, that is,
After completing the cold start, if the BAT voltage is above the
SETBK falling threshold, the BACK_UP switches remain off.
When the BAT voltage is lower than the SETBK falling threshold,
the backup control automatically selects the high voltage terminal
as the SYS power source as long as the SYS voltage is more than
VSYS_CHG. The backup control also prevents the BACK_UP
primary battery from charging the BAT pin. Meanwhile, the BAT
offset of the comparator prevents the input source from
charging the BACK_UP primary battery. Table 9 shows the
power path of the working state.
S1
D1
RPG_HYST + RPG1 + RPG2 ≥ 6 MΩ
MAXIMUM DEVICE
RATING VOLTAGE
TURN OFF MAIN BOOST
MAIN BOOST
CHARGER OFF
VBAT_TERM
VBAT_TERM_HYS
INCREASING SYS VOLTAGE
PGOOD BECOMES HIGH
VSETPG_RISING
VSETPG_FALLING
MAIN BOOST IN
SYNCHRONOUS MODE
TURN ON SWITCH BETWEEN
BSTO AND BAT
MAIN BOOST
CHARGER ON
SYS
SYS SWITCH
VSETSD
CHARGING BATTERY
VSYS_CHG_HYS
TURN ON MAIN BOOST IN
ASYNCHRONOUS MODE
VSYS_TH
ENABLE CHIP
0V
BAT_M1
HS
BAT_M2
BSTO
BAT
+
GATE
DRIVER
GATE DRIVER
14145-044
–
LS
Figure 44. ADP5091/ADP5092 Power Switches Structure
CURRENT-LIMIT AND SHORT-CIRCUIT PROTECTION
The boost regulator and regulated output in hysteresis boost mode
in the ADP5091/ADP5092 includes current-limit protection
circuitry to limit the amount of positive current flowing through
the low-side boost switch. The boost regulator current-limit
protection circuitry is a cycle-by-cycle, three-level peak currentlimit protection with a third level of 200 mA (typical), and the
regulated output current-limit protection circuitry is 100 mA
(typical). In LDO mode, the current-limit protection is designed
to limit the current when the output load reaches 260 mA
(typical). When the output load exceeds 260 mA, the output
voltage reduces to maintain a constant current limit.
COLD STARTUP
14145-043
VSYS_TH
SW
Although there is no current limit at the SYS and the BAT pins,
it is recommended to limit the system load current to lower
than 1000 mA. The total resistance of the SYS switch and the
BAT switch (1.03 Ω, typical) generates a voltage drop when the
system load sinks a large current from BAT. It is also necessary
to consider the internal resistance of the storage elements
connected to the BAT pin.
VSETSD_HYS
VSYS_CHG
–
BACK_UP_M2
For the best operation of the system, use PGOOD to enable the
system load or to turn on an ultralow power load switch or to
drive an external positive channel field effect transistor (PFET)
between SYS and the system load via an inverter to determine
when the system load can be connected or removed (see Figure 48).
Table 8 shows programming threshold resistor examples
corresponding to various voltages with a 10 MΩ resistor divider.
Figure 43 shows various threshold voltages states.
BACK_UP
+
BACK_UP_M1
The logic high level on PGOOD is equal to the SYS voltage and
the logic low level is ground. The logic high level has approximately
11.6 kΩ (typical) internally in series to limit the available current.
The VSETPG_FALLING threshold must be greater than the VSETSD
threshold.
Figure 43. ADP5091/ADP5092 Various Threshold Voltages States (See
Equation 8 and Equation 9)
Rev. A | Page 20 of 28
Data Sheet
ADP5091/ADP5092
THERMAL SHUTDOWN
In the event that the ADP5091/ADP5092 junction temperature
rises above 142°C, the thermal shutdown circuit turns off the
switch between the BAT pin and the SYS pin to prevent the
damage of the energy storage at a high ambient temperature. In
addition, the boost operation terminates. A 15°C hysteresis is
included, allowing the ADP5091/ADP5092 to return to operation
when the on-chip temperature drops to less than 127°C. When
exiting thermal shutdown, the boost and the energy storage
controller resume their functions.
Table 8. Programming Threshold Resistors (See Figure 42)
Voltage Threshold (V)
2
2.1
2.2
2.3
2.4
2.5
2.6
2.7
2.8
2.9
3
3.1
3.2
3.3
3.4
3.5
3.6
3.7
3.8
3.9
4
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
4.9
5
5.1
5.2
RBK1, RSD1, and RPG1 (MΩ)
5
5.23
5.49
5.62
5.9
6.04
6.19
6.34
6.49
6.6
6.65
6.8
6.81
6.98
6.98
7.15
7.15
7.32
7.32
7.5
7.5
7.5
7.68
7.68
7.68
7.87
7.87
7.87
7.87
7.87
8.06
8.06
8.06
RBK2, RSD2, and RPG2 (MΩ)
5
4.75
4.53
4.32
4.12
4
3.83
3.74
3.57
3.48
3.32
3.24
3.09
3.01
2.94
2.87
2.8
2.7
2.61
2.55
2.5
2.43
2.37
2.32
2.26
2.21
2.15
2.15
2.1
2.05
2
1.96
1.91
Rev. A | Page 21 of 28
RTERM1 (MΩ)
Not applicable
Not applicable
3.2
3.48
3.74
4
4.22
4.42
4.64
4.87
5
5.11
5.36
5.49
5.6
5.76
5.9
5.9
6.04
6.19
6.2
6.34
6.49
6.49
6.6
6.65
6.8
6.81
6.81
6.98
6.98
6.98
7.15
RTERM2 (MΩ)
Not applicable
Not applicable
6.81
6.49
6.2
6.04
5.76
5.6
5.36
5.23
5
4.87
4.7
4.53
4.42
4.3
4.12
4.02
3.92
3.83
3.74
3.65
3.57
3.48
3.4
3.32
3.24
3.2
3.09
3.09
3
2.94
2.87
ADP5091/ADP5092
Data Sheet
Table 9. Power Path Working State (See Figure 44)
Backup Battery
Without
With
1
Power Condition 1
VSYS_CHG > VSYS > VSYS_TH,
VSETSD > VBAT
VSYS > VSYS_CHG, VSETSD > VBAT
VBAT_TERM > VBAT = VSYS > VSETSD
VSYS > VSYS_TH, VBAT > VBAT_TERM
VSYS_CHG > VSYS > VSYS_TH,
VSETSD > VBAT
VSYS > VSYS_CHG, VSETSD > VBAT,
VBACK_UP > VBAT
VSYS > VSYS_TH, VBAT > VSETSD,
VBAT > VSETBK
VSYS > VSYS_TH, VBAT > VSETSD,
VBAT < VSETBK, VBACK_UP > VBAT
VSYS < VSYS_TH
Main Boost
Asynchronous
BAT_M1
Off
BAT_M2
Off
SYS Switch
On
BACK_UP_M1
Off
BACK_UP_M2
Off
Asynchronous
Synchronous
Disabled
Asynchronous
On
On
On
Off
Off
On
On
Off
On
On
On
On
Off
Off
Off
Off
Off
Off
Off
Off
Asynchronous
On
Off
Off
On
On
Synchronous
On
On
On
Off
Off
Synchronous
On
On
Off
On
On
Disabled
Off
Off
On
Off
Off
VBACK_UP is the voltage on the BACK_UP pin, and VSETBK is the threshold of the SETBK pin.
Rev. A | Page 22 of 28
Data Sheet
ADP5091/ADP5092
APPLICATIONS INFORMATION
The ADP5091/ADP5092 extract the energy from the VIN pin
to charge the SYS and the BAT pins. This process occurs in
three stages: cold start, asynchronous boost, and synchronous
boost. This section describes the procedures for selecting the
external components to maintain the energy transmission
system with the layout and assembly considerations.
Table 10. Recommended Solar Cells
Vendor
Alta Devices
Fujikura
Gcell
ElectricFilm
ENERGY HARVESTER SELECTION
ENERGY STORAGE ELEMENT SELECTION
The energy harvester input source must provide a minimum level
of power for cold start, asynchronous boost, and synchronous
boost. To estimate the minimum input power required to
complete the cold start using the following equation:
VIN × IIN × ηCOLD > VSYS_TH × ISYS_LOAD
To protect the storage element from overcharging or overdischarging, the storage element must be connected to the BAT pin
and the system load tied to the SYS pin. The ADP5091/ADP5092
support many types of storage elements, such as rechargeable
batteries, super capacitors, and conventional capacitors. A
storage element with a 100 µF equivalent capacitance is required
to filter the pulse currents of the PFM switching converter. The
storage element capacity must provide the entire system load
when the input source is no longer generating power.
(13)
where:
VIN is clamped to VIN_COLD = 380 mV (typical), which indicates
the minimum input voltage for cold start.
IIN is the input current.
ηCOLD is the cold start efficiency, which is about 5% to 7%.
(VSYS_TH is the end of cold start operation.
ISYS_LOAD is the system load current of the SYS pin. Minimizing
the system load accelerates the cold start. Programming the
PGOOD threshold to enable the system load current is
recommended.
If there is a high pulse current or the storage element has
significant impedance, it may be necessary to increase the SYS
capacitor from the 4.7 µF minimum, or add additional capacitance
to the BAT pin to prevent a droop in the SYS voltage. Note that
increasing the SYS capacitor causes the boost regulator to operate
in the less efficient cold start stage for a longer period at startup.
If the application is unable to accept the longer cold start time,
place the additional capacitor parallel to the storage element. See
the Capacitor Selection section for more information.
After the ADP5091/ADP5092 complete the cold start, the MPPT
function enables. To meet the average system load current, the
input source must provide the boost regulator with enough power
to fully charge the storage element while the system is in low
power or sleep mode. To estimate the power required by the
system, use the following equation:
VIN × IIN × ηBOOST > VBAT_TERM × (ISTR_LEAK + ISYS_LOAD)
Device Type
GaAs
Dye sensitized solar cell
Dye sensitized solar cell
Dye sensitized solar cell
INDUCTOR SELECTION
The boost regulator needs an appropriate inductor for proper
operation. The inductor saturation current must be at least 30%
higher than the expected peak inductor currents, as well as a
low series resistance (DCR) to maintain high efficiency. The
boost regulator internal control circuitry is designed to optimize
the efficiency and control the switching behavior with a nominal
inductance of 22 µH ± 20%. Table 11 lists some of the
recommended inductors.
(14)
where:
VIN is regulated to the MPPT pin voltage (MPPT ratio × OCV).
IIN is the input current.
ηBOOST is the boost regulator efficiency. See Figure 5 through
Figure 12 in the Typical Performance Characteristics section for
more information.
VBAT_TERM is the battery terminal charging threshold (see Table 1).
ISTR_LEAK is the storage element leakage current at the BAT pin.
ISYS_LOAD is the average system load current of the SYS pin.
Table 11. Recommended Inductors
Vendor
Würth Elektronik
Coilcraft
1
2
Device No.
74437324220
744042220
LPS4018-223M
L (µH)
22
22
22
ISAT is the dc current that causes the 20% inductance drop from its value without current.
IRMS is the current that causes a 20°C rise from a 25°C ambient temperature.
Rev. A | Page 23 of 28
ISAT (A)1
2
0.6
0.8
IRMS (A)2
1
0.88
0.65
DCR (mΩ)
470
255
360
ADP5091/ADP5092
Data Sheet
CAPACITOR SELECTION
influences the effectiveness of MPPT. When the IC junction
temperature exceeds 85°C, a larger capacitance is beneficial to
the effectiveness of MPPT, and for a higher CPB pin leakage
current. It is recommended to keep the same RC time constant
of the MPPT resistors and CBP capacitor (up to 22 µF) as shown
in the typical application circuit in Figure 45. Considering the
time constant of the MPPT resistor divide and the CBP capacitor, a
low leakage X7R or C0G 10 nF ceramic capacitor is recommended.
Low leakage capacitors are required for ultralow power
applications that are sensitive to the leakage current. Any
leakage from the capacitors reduces efficiency, increases the
quiescent current, and degrades the MPPT effectiveness.
Input Capacitor
A capacitor (CIN) connected to the VIN pin and the PGND pin
stores energy from the input source. For the energy harvester,
capacitive behavior dominates the source impedance. Scale the
input capacitor according to the value of the output capacitance
of the energy harvester; a minimum of 10 µF is recommended.
For the primary battery application, a larger capacitance helps
to reduce the input voltage ripple and keeps the source current
stable to extend the battery life.
SYS Capacitor
The ADP5091/ADP5092 require two capacitors to be connected
between the SYS pin and the PGND pin. Connect a low ESR
ceramic capacitor of at least 4.7 µF parallel to a high frequency,
0.1 µF bypass capacitor. Connect the bypass capacitor as close as
possible between SYS and PGND.
REG_OUT Capacitor
The ADP5091/ADP5092 regulated output is designed for
operation with small, space-saving ceramic capacitors but
functions with the most commonly used capacitors as long as
care is taken with regard to the effective series resistance (ESR)
value. The ESR of the output capacitor affects stability of the
LDO control loop. A minimum capacitance of 4.7 µF with an
ESR of 1 Ω or less is recommended to ensure stability of the
regulated output. Transient response to changes in load current
is also affected by output capacitance. Using a larger value of
output capacitance improves the transient response of the
regulated output to large changes in load current.
CBP Capacitor
The operation of the MPPT pin depends on the sampled value
of the OCV. The voltage stored on the CBP capacitor regulates
to the VIN pin. This capacitor is sensitive to leakage because the
holding period is around 16 sec. As the capacitor voltage drops
due to leakage, the VIN regulation voltage also drops and
LAYOUT AND ASSEMBLY CONSIDERATIONS
Carefully consider the printed circuit board (PCB) layout
during the design of the switching power supply, especially at
high peak currents and high switching frequency. Therefore, it
is recommended to use wide and short traces for the main power
path and the power ground paths. Place the input capacitors,
output capacitors, inductor, and storage elements as close as
possible to the IC. It is most important for the boost regulator to
minimize the power path from output to ground. Therefore,
place the output capacitor as close as possible between the SYS
pin and the PGND pin. Keep a minimum power path from the
input capacitor to the inductor from the VIN pin to the PGND
pin. Place the input capacitor as close as possible between the
VIN pin and the PGND pin, and place the inductor close to the
VIN pin and the SW pin. It is best to use vias and bottom traces
for connecting the inductors to their respective pins. To minimize
noise pickup by the high impedance threshold setting nodes
(REF, TERM, SETBK, SETSD, and SETPG), place the external
resistors close to the IC with short traces.
The CBP capacitor must hold the MPPT voltage for 16 sec,
because any leakage can degrade the MPPT effectiveness. During
board assembly and cleaning, contaminants such as solder flux
and residue may form parasitic resistance to ground, especially
in humid environments with fast airflow. Contamination can
significantly degrade the voltage regulation and change threshold
levels set by the external resistors. Therefore, it is recommended
that no ground planes be poured near the CBP capacitor or the
threshold setting resistors. In addition, carefully clean the boards. If
possible, clean ionic contamination with deionized water for the
CBP capacitor and the threshold setting resistors.
Rev. A | Page 24 of 28
Data Sheet
ADP5091/ADP5092
TYPICAL APPLICATION CIRCUITS
VID
LLD
111kΩ
2V
REG_OUT
FROM MCU
22µH
SOLAR
HARVESTER
TO MCU
REG_D0
REG_FB
REG_D1
PGOOD
SENSOR
10µF
SYS
SW
4.7µF
VIN
10µF
4.7MΩ
BAT
+
MPPT
18MΩ
–
CBP
10nF
PA-5R0H224
0.22F
ADP5091
MCU
(ALWAYS ON)
REF
SETSD
BACK_UP
CR2032
3V
225mAh
+
SETPG
DIS_SW
–
MINOP
ADF7024
SETHYST
(Rx/Tx)
SETBK
150kΩ
TERM
PGND
14145-045
AGND
Figure 45. ADP5091-Based Energy Harvester Wireless Sensor Application with PV Cell as the Harvesting Energy Source (Trony 0.7 V, 60 μA, Alta Devices 0.72 V, 42 μA,
Gcell 1.1 V, 100 μA), Cooper Bussmann Super Capacitor PA-5R0H224 as the Harvested Energy Storage, and Panasonic Primary Li-Ion Coin Cell CR2032 as the Backup
Battery
VID
LLD
111kΩ
FROM MCU
THERMOELECTRIC
GENERATOR
TO MCU
2V
REG_OUT
22µH
REG_D0
REG_FB
REG_D1
PGOOD
10µF
SYS
SW
+
4.7µF
VIN
10µF
BAT
MPPT
250kΩ
+
–
CBP
10nF
PA-5R0H224
0.22F
ADP5091
REF
SETSD
BACK_UP
CR2032
3V
225mAh
+
–
SETPG
DIS_SW
MINOP
SETHYST
SETBK
TERM
PGND
14145-046
AGND
Figure 46. ADP5091-Based Energy Harvester Circuit with a Thermoelectric Generator as the Harvesting Energy Source, Cooper Bussmann Super Capacitor
PA-5R0H224 as the Harvested Energy Storage, and Panasonic Primary Li-Ion Coin Cell CR2032 as the Backup Battery
Rev. A | Page 25 of 28
ADP5091/ADP5092
Data Sheet
LLD
VID
REG_OUT
REG_D0
FROM MCU
REG_FB
REG_D1
PIEZOELECTRIC
HARVESTER
TO MCU
2V
R1 10MΩ
10µF
R2 10MΩ
PGOOD
22µH
SYS
SW
4.7µF
VIN
10MΩ
BAT
10µF
+
MPPT
10MΩ
–
CBP
10nF
PA-5R0H224
0.22F
ADP5091
REF
SETSD
BACK_UP
CR2032
3V
225mAh
+
SETPG
DIS_SW
–
MINOP
SETHYST
200kΩ
SETBK
TERM
PGND
14145-047
AGND
Figure 47. ADP5091-Based Energy Harvester Circuit with a Piezoelectric Generator as the Harvesting Energy Source, Cooper Bussmann Super Capacitor PA-5R0H224
as the Harvested Energy Storage, and Panasonic Primary Li-Ion Coin Cell CR2032 as the Backup Battery
VID
REG_GOOD
111kΩ
2V
REG_OUT
1µF
REG_D0
FROM MCU
REG_FB
REG_D1
SYSTEM
LOAD
SYS
22µH
4.7µF
SW
TRANSFORMER
SYS
VIN
PGOOD
6.34MΩ
AC
10µF
BAT
MPPT
14.7MΩ
+
–
CBP
10nF
PA-5R0H224
0.22F
ADP5092
REF
SETSD
BACK_UP
CR2032
3V
225mAh
+
SETPG
DIS_SW
–
MINOP
SETHYST
20kΩ
SETBK
TERM
PGND
14145-048
AGND
Figure 48. ADP5092 AC Input Source and PGOOD Function Determines the Time to Enable the System Load
Rev. A | Page 26 of 28
Data Sheet
ADP5091/ADP5092
FACTORY PROGRAMMABLE OPTIONS
To order a device with options other than the default options,
contact a local Analog Devices, Inc., sales or distribution
representative.
Table 12. Input Current-Limit Options
Option
Option 0
Option 1
Description
200 mA (default)
300 mA
Table 13. VIN Open Circuit Voltage Sampling Cycle Options
Option
Option 0
Option 1
Option 2
Option 3
Rev. A | Page 27 of 28
Description
4 sec
8 sec
16 sec (default)
32 sec
ADP5091/ADP5092
Data Sheet
OUTLINE DIMENSIONS
DETAIL A
(JEDEC 95)
4.10
4.00 SQ
3.90
1
0.50
BSC
2.44
2.30 SQ
2.16
EXPOSED
PAD
13
TOP VIEW
0.80
0.75
0.70
0.50
0.40
0.30
6
12
7
BOTTOM VIEW
0.05 MAX
0.02 NOM
COPLANARITY
0.08
0.203 REF
PKG-003994/5111
SEATING
PLANE
PIN 1
INDIC ATOR AREA OPTIONS
(SEE DETAIL A)
24
19
18
0.20 MIN
FOR PROPER CONNECTION OF
THE EXPOSED PAD, REFER TO
THE PIN CONFIGURATION AND
FUNCTION DESCRIPTIONS
SECTION OF THIS DATA SHEET.
COMPLIANT TO JEDEC STANDARDS MO-220-WGGD-8
03-09-2017-B
PIN 1
INDICATOR
0.30
0.25
0.20
Figure 49. 24-Lead Lead Frame Chip Scale Package [LFCSP]
4 mm × 4 mm Body and 0.75 mm Package Height
(CP-24-14)
Dimensions shown in millimeters
ORDERING GUIDE
Model1
ADP5091ACPZ-1-R7
Temperature Range
−40°C to + 125°C
ADP5091ACPZ-2-R7
−40°C to + 125°C
ADP5092ACPZ-1-R7
−40°C to + 125°C
ADP5091-1-EVALZ
ADP5091-2-EVALZ
ADP5092-1-EVALZ
1
Package Description
24-Lead Lead Frame Chip Scale Package [LFCSP], 200 mA Input
Peak Current
24-Lead Lead Frame Chip Scale Package [LFCSP], 300 mA Input
Peak Current
24-Lead Lead Frame Chip Scale Package [LFCSP], 200 mA Input
Peak Current
Evaluation Board
Evaluation Board with Solar Harvester and Super Capacitor
Evaluation Board
Z = RoHS Compliant Part.
©2016–2017 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D14145-0-5/17(A)
Rev. A | Page 28 of 28
Package Option
CP-24-14
CP-24-14
CP-24-14
工商网监
湘ICP备2023018690号
