ADUM4121-1TRIZ-EP

High Voltage, Isolated Gate Driver with Internal Miller Clamp, 2.3 A Output ADuM4121-1-EP Enhanced Product FEATURES GENERAL DESCRIPTION 2.3 A peak output current (typical) 2.5 V to 6.5 V input 7.5 V to 35 V output Undervoltage lockout (UVLO) at 2.5 V VDD1 and 7.5 V VDD2 Precise timing characteristics 53 ns maximum isolator and driver propagation delay CMOS input logic levels High common-mode transient immunity: >150 kV/µs High junction temperature operation: 125°C Default low output Internal Miller clamp Safety and regulatory approvals (pending) UL recognition per UL 1577 5 kV rms for 1-minute withstand CSA Component Acceptance Notice 5A VDE certificate of conformity (pending) DIN V VDE V 0884-10 (VDE V 0884-10): 2006-12 VIORM = 849 V peak Wide-body, 8-lead SOIC The ADuM4121-1-EP1 is a 2.3 A isolated, single-channel driver that employ Analog Devices, Inc., iCoupler® technology to provide precision isolation. The ADuM4121-1-EP provides 5 kV rms isolation in the wide-body, 8-lead SOIC package. Combining high speed CMOS and monolithic transformer technology, this isolation component provides outstanding performance characteristics superior to alternatives such as the combination of pulse transformers and gate drivers. The ADuM4121-1-EP operates with an input supply ranging from 2.5 V to 6.5 V, providing compatibility with lower voltage systems. In comparison to gate drivers that employ high voltage level translation methodologies, the ADuM4121-1-EP offers the benefit of true, galvanic isolation between the input and the output. The ADuM4121-1-EP includes an internal Miller clamp that activates at 2 V on the falling edge of the gate drive output, supplying the driven gate with a lower impedance path to reduce the chance of Miller capacitance induced turn on. The ADuM4121-1-EP provides reliable control over the switching characteristics of insulated gate bipolar transistor (IGBT)/metal oxide semiconductor field effect transistor (MOSFET) configurations over a wide range of switching voltages. ENHANCED PRODUCT FEATURES Supports defense and aerospace applications (AQEC standard) Military temperature range (−55°C to +125°C) Controlled manufacturing baseline 1 assembly/test site 1 fabrication site Product change notification Qualification data available on request Additional application and technical information can be found in the ADuM4121-1 data sheet. APPLICATIONS Missiles and munitions Avionics Unmanned systems Isolated IGBT/MOSFET gate drives FUNCTIONAL BLOCK DIAGRAM VDD1 1 ADuM4121-1-EP UVLO 8 VDD2 DECODE AND LOGIC ENCODE VI+ 2 TSD 7 VOUT VI– 3 6 CLAMP GND1 4 5 GND2 UVLO 17322-001 2V Figure 1. Protected by U.S. Patents 5,952,849; 6,873,065; and 7,075,329. Other patents pending. Rev. 0 Document Feedback 1 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2019 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com ADuM4121-1-EP Enhanced Product TABLE OF CONTENTS Features .............................................................................................. 1 Enhanced Product Features ............................................................ 1 DIN V VDE V 0884-10 (VDE V 0884-10) Insulation Characteristics ...............................................................................5 Applications ....................................................................................... 1 Recommended Operating Conditions .......................................5 General Description ......................................................................... 1 Absolute Maximum Ratings ............................................................6 Functional Block Diagram .............................................................. 1 Thermal Resistance .......................................................................6 Revision History ............................................................................... 2 ESD Caution...................................................................................6 Specifications..................................................................................... 3 Pin Configuration and Function Descriptions..............................7 Electrical Characteristics ............................................................. 3 Typical Performance Characteristics ..............................................8 Regulatory Information ............................................................... 4 Outline Dimensions ..........................................................................9 Package Characteristics ............................................................... 4 Ordering Guide .............................................................................9 Insulation and Safety Related Specifications ............................ 5 REVISION HISTORY 1/2019—Revision 0: Initial Version Rev. 0| Page 2 of 9 Enhanced Product ADuM4121-1-EP SPECIFICATIONS ELECTRICAL CHARACTERISTICS Low-side voltages referenced to GND1. High side voltages referenced to GND2; 2.5 V ≤ VDD1 ≤ 6.5 V; 7.5 V ≤ VDD2 ≤ 35 V, TJ = −55°C to +125°C. All minimum/maximum specifications apply over the entire recommended operating range, unless otherwise noted. All typical specifications are at TJ = 25°C, VDD1 = 5.0 V, VDD2 = 15 V. Table 1. Parameter DC SPECIFICATIONS High Side Power Supply VDD2 Input Voltage VDD2 Input Current, Quiescent Logic Supply VDD1 Input Voltage Input Current Logic Inputs (VI+, VI−) Input Current Input Voltage Logic High Logic Low UVLO VDD1 Positive Going Threshold Negative Going Threshold Hysteresis VDD2 Positive Going Threshold Negative Going Threshold Hysteresis Internal NMOS Gate Resistance Internal PMOS Gate Resistance Internal Miller Clamp Resistance Miller Clamp Voltage Threshold Peak Current SWITCHING SPECIFICATIONS Pulse Width Propagation Delay Rising Edge2 Falling Edge2 Skew3 Falling Edge4 Rising Edge5 Pulse Width Distortion Output Rise/Fall Time (10% to 90%) Symbol Min VDD2 IDD2(Q) 7.5 VDD1 IDD1 2.5 II+, II− −1 VIH 0.7 × VDD1 3.5 Typ Max Unit 2.3 35 2.7 V mA 3.6 6.5 5 V mA 0.01 +1 µA 0.3 × VDD1 1.5 V V V V VIL VVDD1UV+ VVDD1UV− VVDD1UVH VVDD2UV+ VVDD2UV− VVDD2UVH RDSON_N 2.3 6.9 RDSON_P Test Conditions/Comments VI+ = high, VI− = low 2.5 V ≤ VDD1 ≤ 5 V VDD1 > 5 V 2.5 V ≤ VDD1 ≤ 5 V VDD1 > 5 V 2.45 2.35 0.1 2.5 V V V 7.3 7.1 0.2 0.6 0.6 0.8 0.8 0.8 2 2.3 7.5 V V V Ω Ω Ω Ω Ω V A Tested at 250 mA, VDD2 = 15 V Tested at 1 A, VDD2 = 15 V Tested at 250 mA, VDD2 = 15 V Tested at 1 A, VDD2 = 15 V Tested at 200 mA, VDD2 = 15 V Referenced to GND2, VDD2 = 15 V VDD2 = 12 V, 4 Ω gate resistance ns CL = 2 nF, VDD2 = 15 V, RGON1 = RGOFF1 = 5 Ω ns ns ns ns ns ns ns CL = 2 nF, VDD2 = 15 V, RGON = RGOFF = 5 Ω CL = 2 nF, VDD2 = 15 V, RGON = RGOFF = 5 Ω CL = 2 nF, VDD2 = 15 V, RGON = RGOFF = 5 Ω CL = 2 nF, VDD2 = 15 V, RGON = RGOFF = 5 Ω CL = 2 nF, VDD2 = 15 V, RGON = RGOFF = 5 Ω CL = 2 nF, VDD2 = 15 V, RGON = RGOFF = 5 Ω CL = 2 nF, VDD2 = 15 V, RGON = RGOFF = 5 Ω RDSON_MILLER VCLP_TH IPK 1.75 PW 50 tDLH tDHL tPSK tPSKHL tPSKLH tPWD tR/tF 22 30 32 38 11 7 18 Rev. 0 | Page 3 of 9 1.6 1.6 1.8 1.8 2 2.25 42 53 22 12 15 13 26 ADuM4121-1-EP Enhanced Product Parameter Common-Mode Transient Immunity (CMTI) Static CMTI6 Dynamic CMTI7 Symbol |CM| Min Typ Max 150 150 Unit Test Conditions/Comments kV/µs kV/µs VCM = 1500 V VCM = 1500 V RGON and RGOFF are the external gate resistors in the test. tDLH propagation delay is measured from the time of the input rising logic high threshold, VIH, to the output rising 10% threshold of the VOUT signal. tDHL propagation delay is measured from the input falling logic low threshold, VIL, to the output falling 90% threshold of the VOx signal. See the ADuM4121-1 data sheet for waveforms of the propagation delay parameters. 3 tPSK is the magnitude of the worst case difference in tDLH and/or tDHL that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. See the ADuM4121-1 data sheet for waveforms of the propagation delay parameters. 4 tPSKHL is the magnitude of the worst case difference in tDHL that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. See the ADuM4121-1 data sheet for waveforms of the propagation delay parameters. 5 tPSKLH is the magnitude of the worst case difference in tDLH that is measured between units at the same operating temperature, supply voltages, and output load within the recommended operating conditions. See the ADuM4121-1 data sheet for waveforms of the propagation delay parameters. 6 Static common-mode transient immunity (CMTI) is defined as the largest dv/dt between GND1 and GND2, with inputs held either high or low, such that the output voltage remains either above 0.8 × VDD2 for output high or 0.8 V for output low. Operation with transients above recommended levels can cause momentary data upsets. 7 Dynamic common-mode transient immunity (CMTI) is defined as the largest dv/dt between GND1 and GND2 with the switching edge coincident with the transient test pulse. Operation with transients above the recommended levels can cause momentary data upsets. 1 2 REGULATORY INFORMATION The ADuM4121-1-EP is pending approval by the organizations listed in Table 2. Table 2. UL (Pending) UL1577 Component Recognition Program Single Protection, 5000 V rms Isolation Voltage File E214100 CSA (Pending) Approved under CSA Component Acceptance Notice 5A CSA 60950-1-07+A1+A2 and IEC 60950-1, second edition, +A1+A2: Basic insulation at 800 V rms (1131 V peak) Reinforced insulation at 400 V rms (565 V peak) IEC 60601-1 Edition 3.1: Basic insulation (1 means of patient protection (MOPP)), 500 V rms (707 V peak) Reinforced insulation (2 MOPP), 250 V rms (1414 V peak) CSA 61010-1-12 and IEC 61010-1 third edition Basic insulation at: 600 V rms mains, 800 V secondary (1089 V peak) Reinforced insulation at: 300 V rms mains, 400 V secondary (565 V peak) File 205078 VDE (Pending) DIN V VDE V 0884-10 (VDE V 0884-10):2006-12 Reinforced insulation, 849 V peak, VIOSM = 10 kV peak Basic insulation 849 V peak, VIOSM = 16 kV peak CQC (Pending) Certified under CQC11471543-2012 GB4943.1-2011 File 2471900-4880-0001 File (pending) Basic insulation at 800 V rms (1131 V peak) Reinforced insulation at 400 V rms (565 V peak) PACKAGE CHARACTERISTICS Table 3. Parameter Resistance (Input Side to High-Side Output)1 Capacitance (Input Side to High-Side Output)1 Input Capacitance 1 Symbol RI-O CI-O CI Min Typ 1012 2.0 4.0 The device is considered a two-terminal device: Pin 1 through Pin 4 are shorted together, and Pin 5 through Pin 8 are shorted together. Rev. 0| Page 4 of 9 Max Unit Ω pF pF Enhanced Product ADuM4121-1-EP INSULATION AND SAFETY RELATED SPECIFICATIONS Table 4. Parameter Rated Dielectric Insulation Voltage Minimum External Air Gap (Clearance) Symbol L(I01) Value 5000 8 min Unit V rms mm Minimum External Tracking (Creepage) L(I02) 8 min mm Minimum Clearance in the Plane of the Printed Circuit Board (PCB Clearance) Minimum Internal Gap (Internal Clearance) Tracking Resistance (Comparative Tracking Index) Isolation Group L (PCB) 8.3 min mm CTI 25.5 min >400 II µm V Conditions 1-minute duration Measured from input terminals to output terminals, shortest distance through air Measured from input terminals to output terminals, shortest distance path along body Measured from input terminals to output terminals, shortest distance through air, line of sight, in the PCB mounting plane Minimum distance through insulation DIN IEC 112/VDE 0303 Part 3 Material Group (DIN VDE 0110, 1/89, Table 1) DIN V VDE V 0884-10 (VDE V 0884-10) INSULATION CHARACTERISTICS This isolator is suitable for reinforced isolation only within the safety limit data. Maintenance of the safety data is ensured by protective circuits. Table 5. VDE Characteristics Description Installation Classification per DIN VDE 0110 For Rated Mains Voltage ≤ 600 V rms Climatic Classification Pollution Degree per DIN VDE 0110, Table 1 Maximum Working Insulation Voltage Input to Output Test Voltage, Method B1 SAFE LIMITING POWER (W) Input to Output Test Voltage, Method A After Environmental Tests Subgroup 1 After Input and/or Safety Test Subgroup 2 and Subgroup 3 Highest Allowable Overvoltage Surge Isolation Voltage Basic Surge Isolation Voltage Reinforced Safety Limiting Values Maximum Junction Temperature Safety Total Dissipated Power Insulation Resistance at TS Test Conditions/Comments VIORM × 1.875 = Vpd (m), 100% production test, tini = tm = 1 sec, partial discharge < 5 pC VIORM × 1.5 = Vpd (m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC VIORM × 1.2 = Vpd (m), tini = 60 sec, tm = 10 sec, partial discharge < 5 pC VPEAK = 16 kV, 1.2 µs rise time, 50 µs, 50% fall time VPEAK = 16 kV, 1.2 µs rise time, 50 µs, 50% fall time Maximum value allowed in the event of a failure (see Figure 2) VIO = 500 V Symbol Characteristic Unit VIORM Vpd (m) I to IV 40/105/21 2 849 1592 V peak V peak Vpd (m) Vpd (m) 1274 1019 V peak V peak VIOTM VIOSM VIOSM 7000 16,000 10,000 V peak V peak V peak TS PS RS 150 1.2 >109 °C W Ω 1.4 RECOMMENDED OPERATING CONDITIONS 1.2 Table 6. Parameter Operating Temperature Range (TJ) Supply Voltages VDD1 to GND1 VDD2 to GND2 1.0 0.8 0.6 0.4 0 0 50 100 150 AMBIENT TEMPERATURE (°C) 200 14967-002 0.2 Figure 2. Thermal Derating Curve, Dependence of Safety Limiting Values on Ambient Temperature, per DIN V VDE V 0884-10 Rev. 0 | Page 5 of 9 Value −55°C to +125°C 2.5 V to 6.5 V 7.5 V to 35 V ADuM4121-1-EP Enhanced Product ABSOLUTE MAXIMUM RATINGS Ambient temperature = 25°C, unless otherwise noted. THERMAL RESISTANCE Table 7. Thermal performance is directly linked to printed circuit board (PCB) design and operating environment. Careful attention to PCB thermal design is required. Parameter Storage Temperature Range (TST) Junction Operating Temperature Range (TJ) Supply Voltages VDD1 to GND1 VDD2 to GND2 Input Voltages VI+, VI−1 VCLAMP2 Output Voltages VOUT2 Common-Mode Transients (|CM|)3 Rating −55°C to +150°C −55°C to +125°C θJA is the natural convection junction to ambient thermal resistance measured in a one cubic foot sealed enclosure. −0.3 V to +7 V −0.3 V to +40 V Table 8. Thermal Resistance −0.3 V to +7 V −0.3 V to VDD2 + 0.3 V −0.3 V to VDD2 + 0.3 V −200 kV/µs to +200 kV/µs Package Type RI-8-11 1 θJA 104.2 Unit °C/W Test Condition 1: thermal impedance simulated values are based on a 4-layer PCB. ESD CAUTION Rating assumes VDD1 is above 2.5 V. VI+ and VI− are rated up to 6.5 V when VDD1 is unpowered. Referenced to GND2, maximum of 40 V. 3 |CM| refers to common-mode transients across the insulation barrier. Common-mode transients exceeding the absolute maximum rating can cause latch-up or permanent damage. 1 2 Stresses at or above those listed under Absolute Maximum Ratings may cause permanent damage to the product. This is a stress rating only; functional operation of the product at these or any other conditions above those indicated in the operational section of this specification is not implied. Operation beyond the maximum operating conditions for extended periods may affect product reliability. Table 9. Maximum Continuous Working Voltage1 Parameter AC Voltage Bipolar Waveform Basic Insulation Reinforced Insulation Unipolar Waveform Basic Insulation Reinforced Insulation DC Voltage Basic Insulation Reinforced Insulation 1 Rating Unit Constraint 849 789 V peak V peak 50-year minimum insulation lifetime Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1 1698 849 V peak V peak 50-year minimum insulation lifetime 50-year minimum insulation lifetime 1118 558 V peak V peak Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1 Lifetime limited by package creepage maximum approved working voltage per IEC 60950-1 Maximum continuous working voltage refers to continuous voltage magnitude imposed across the isolation barrier. See the ADuM4121-1 data sheet for more details. Table 10. Truth Table VI− Don’t care Low High Don’t care Don’t care 1 VI+ Low High Don’t care Don’t care Don’t care VDD1 State Powered Powered Powered Unpowered Powered The output is low, but not actively driven because the device is not powered. Rev. 0| Page 6 of 9 VDD2 State Powered Powered Powered Powered Unpowered VOUT Output Low High Low Low Low1 Enhanced Product ADuM4121-1-EP PIN CONFIGURATION AND FUNCTION DESCRIPTIONS ADuM4121-1-EP VDD1 1 8 VI+ 2 7 VOUT VI– 3 6 CLAMP GND1 4 5 GND2 17322-003 TOP VIEW (Not to Scale) VDD2 Figure 3. Pin Configuration Table 11. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 Mnemonic VDD1 V I+ V I− GND1 GND2 CLAMP VOUT VDD2 Description Supply Voltage for Isolator Side 1. Noninverting Gate Drive Logic Input. Inverting Gate Drive Logic Input. Ground 1. This pin is the ground reference for Isolator Side 1. Ground 2. This pin is the ground reference for Isolator Side 2. Miller Clamp and Gate Voltage Sense. Connect this pin directly to the gate being driven. Gate Drive Output. Connect this pin to the gate being driven through an external series resistor. Supply Voltage for Isolator Side 2. Rev. 0 | Page 7 of 9 ADuM4121-1-EP Enhanced Product TYPICAL PERFORMANCE CHARACTERISTICS 1.2 tDHL tDLH PMOS NMOS 1.0 40 0.8 30 0.6 20 0.4 10 0.2 0 –55 –35 –15 5 25 45 65 85 105 TEMPERATURE (°C) 125 0 –55 –35 –15 5 25 45 65 85 105 125 TEMPERATURE (°C) Figure 4. Propagation Delay vs. Temperature, 2 nF Load Figure 5. Output Resistance (RDSON) vs. Temperature, VDD2 = 15 V Rev. 0| Page 8 of 9 17322-005 RDSON (Ω) 50 17322-004 PROPAGATION DELAY (ns) 60 Enhanced Product ADuM4121-1-EP OUTLINE DIMENSIONS 6.05 5.85 5.65 8 5 7.60 7.50 7.40 10.51 10.31 10.11 4 2.45 2.35 2.25 0.30 0.20 0.10 COPLANARITY 0.10 2.65 2.50 2.35 1.27 BSC 0.51 0.41 0.31 0.75 0.50 0.25 1.04 BSC SEATING PLANE 45° 0.75 0.58 0.40 8° 0° 0.33 0.27 0.20 09-17-2014-B PIN 1 MARK 1 Figure 6. 8-Lead Standard Small Outline Package, with Increased Creepage [SOIC_IC] Wide Body (RI-8-1) Dimensions shown in millimeters ORDERING GUIDE Model1 ADUM4121-1TRIZ-EP No. of Channels 1 Output Peak Current (A) 2 Thermal Shutdown No Minimum Output Voltage (V) 7.5 ADUM4121-1TRIZ-EPR 1 2 No 7.5 1 Z = RoHS Compliant Part. ©2019 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D17322-0-1/19(0) Rev. 0 | Page 9 of 9 Temperature Range −55°C to +125°C −55°C to +125°C Package Description 8-Lead SOIC_IC Package Option RI-8-1 8-Lead SOIC_IC RI-8-1